WO2013029441A1 - 一种时钟同步方法及装置 - Google Patents
一种时钟同步方法及装置 Download PDFInfo
- Publication number
- WO2013029441A1 WO2013029441A1 PCT/CN2012/078883 CN2012078883W WO2013029441A1 WO 2013029441 A1 WO2013029441 A1 WO 2013029441A1 CN 2012078883 W CN2012078883 W CN 2012078883W WO 2013029441 A1 WO2013029441 A1 WO 2013029441A1
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- WO
- WIPO (PCT)
- Prior art keywords
- clock source
- candidate
- clock
- primary
- source device
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
Definitions
- the present invention relates to a 1588 clock synchronization protocol, and more particularly to a clock synchronization method and apparatus. Background technique
- Precision Time Protocol (PTP) IEEESTD1588 is one of the most important technologies in the field of time and frequency synchronization control.
- the 1588 protocol specifies that the slave clock device simultaneously records several valid clock source devices as alternate clock sources. The best one of the preferred clock sources is selected as the primary clock source of the current system by using the best master clock algorithm (BMC).
- BMC master clock algorithm
- the slave clock device interacts with the preferred clock source to calculate the time and frequency deviation. Correct the time and frequency of the slave clock device.
- switch to the secondary priority source calculated by the BMC algorithm in the alternate clock source and then restart the protocol interaction to perform calculation and synchronization.
- the technical problem to be solved by the embodiments of the present invention is to provide a clock synchronization method and device, which can accurately track a new alternate clock source immediately when the current primary clock source fails.
- the embodiment of the present invention provides a clock synchronization method, including: the slave clock device simultaneously performs protocol packet interaction with multiple candidate clock source devices, according to the multiple candidate clock source devices. The interaction of the protocol packets, respectively calculating the time and frequency deviation from each of the candidate clock source devices, and performing locking with the plurality of candidate clock source devices;
- the slave clock device selects a master clock source from the plurality of candidate clock source devices, and corrects its own time and frequency with a time and frequency offset from the master clock source.
- the selecting, by the slave clock device, the primary clock source from the multiple candidate clock source devices includes:
- the slave clock device When the slave clock device does not lock any one of the plurality of clock source devices, select the clock source device with the highest priority from the plurality of clock source devices as the primary clock source.
- the method further includes:
- the slave clock device When the slave clock device locks a clock source device and finds an alternate clock source device with a higher priority, selects the higher priority candidate clock source device as the primary clock source; or waits After locking with the higher priority clock source device, the higher priority clock source device is used as the primary clock source.
- the method further includes:
- the slave clock device locks a clock source device and finds an alternate clock source device having a lower priority than the master clock source, calculating a time and frequency deviation from the found candidate clock source device, Locking with the discovered alternate clock source device.
- the method further includes:
- the slave clock device finds that the primary clock source fails, selects a second highest priority candidate clock source device from the plurality of candidate clock source devices, and selects a secondary high priority candidate clock source When the device is locked, the secondary high priority alternate clock source device is used as the primary clock source.
- the method further includes:
- the slave clock device finds that the primary clock source fails, selects a second highest priority candidate clock source device from the plurality of candidate clock source devices, and the slave clock device is in the second highest priority
- an embodiment of the present invention further provides a clock synchronization apparatus, including: a text interaction unit, a deviation calculation unit, a main clock source selection unit, and a time ⁇ positive unit, where:
- the packet interaction unit is configured to perform protocol packet interaction with a plurality of candidate clock source devices;
- the deviation calculation unit is configured to be configured according to the packet interaction unit and the plurality of candidate clock source devices Interacting with the protocol packets, respectively calculating a time and frequency deviation from each of the candidate clock source devices, and performing locking with the plurality of candidate clock source devices;
- the primary clock source selection unit is configured to select an active clock source from the plurality of candidate clock source devices
- the time correction unit is configured to adopt a time and frequency deviation from the primary clock source, a time and a frequency.
- the primary clock source selection unit selects the clock source device with the highest priority from the plurality of clock source devices when the deviation calculation unit does not lock any one of the plurality of clock source devices As the primary clock source.
- the primary clock source selection unit selects the higher priority when the offset calculation unit has locked an candidate clock source device and finds a higher priority candidate clock source device.
- the alternate clock source device is used as the primary clock source; or after waiting for the higher priority alternate clock source device to be locked, the higher priority alternate clock source device is used as the primary clock source.
- the primary clock source selection unit calculates and works when the offset calculation unit has locked an alternate clock source device and finds an alternate clock source device having a lower priority than the primary clock source.
- the time and frequency deviation of the discovered clock source device is locked with the discovered clock source device.
- the primary clock source selection unit selects a second highest priority candidate clock source device from the plurality of candidate clock source devices when the primary clock source is found to be invalid, When the priority clock source device is not locked, select the highest priority candidate clock source device among the locked candidate clock source devices as the primary clock source; or, the second highest priority candidate clock The source device acts as the primary clock source; when the secondary clock source device with the second highest priority is locked, The second highest priority alternate clock source device acts as the primary clock source.
- the embodiment of the present invention starts to lock immediately after discovering the candidate clock source device, instead of waiting for the switch to start locking the candidate clock source device, so that the slave clock device simultaneously locks the multiple candidate clock source devices, Correcting the time and frequency of the device by using the time and frequency deviation from the preferred clock source.
- the clock source device is switched, it is switched to the candidate clock source device that has been locked as much as possible.
- the embodiment of the present invention not only shortens the switching. Time, and can ensure the synchronization accuracy of time and frequency during the switching to the greatest extent, speed up the switching speed of the clock source device, and improve the switching performance.
- FIG. 1 is a schematic diagram of synchronization of a master-slave clock device in the prior art
- FIG. 2 is a schematic diagram of synchronization of a master-slave clock device according to a preferred embodiment of the present invention
- FIG. 3 is a flow chart showing an alternative clock source joining in a clock synchronization method according to a preferred embodiment of the present invention
- FIG. 4 is a flowchart of performing a failover of a primary clock source in a clock synchronization method according to a preferred embodiment of the present invention
- FIG. 5 is a block diagram of a clock synchronizing apparatus in accordance with a preferred embodiment of the present invention. Preferred embodiment of the invention
- the slave clock device simultaneously performs protocol packet exchange with multiple candidate clock source devices, and simultaneously calculates PDV (network delay jitter) of the link of the multiple candidate clock source devices, and further calculates and selects multiple candidate clocks. Time and frequency deviation of the source device. When a clock source switch occurs, the time and frequency deviation of the new link is used to correct the time and frequency of the slave clock device.
- PDV network delay jitter
- Step 1 When a new alternate clock source device is discovered from the clock device, a link with the alternate clock source device is established and maintained from the clock device, protocol communication is performed, the PDV is calculated, and the candidate clock source device is further calculated. Time and frequency offsets to establish linkages with multiple alternate clock source devices and calculate time and frequency offsets for locking with multiple alternate clock sources; Step 2: When the slave clock device does not currently lock any clock source device, the slave clock device selects the candidate clock source device with the highest priority as the primary clock source, and uses the time and frequency deviation from the master clock source. Time and frequency;
- Step 3 When the slave clock device has locked an alternate clock source device, and the new candidate clock source device is not as high as the current primary clock source, the time and frequency deviation of the new clock source device is also calculated. Without switching;
- Step 4 When the slave clock device has locked an alternate clock source device, and the new alternate clock source device has a higher priority, the user may choose to switch immediately or temporarily not to switch, waiting for the new higher The priority clock source device is locked and then switched;
- Step 5 When the current primary clock source device fails, if the secondary high priority candidate clock source is already locked, the slave clock device immediately switches to the preferred clock source device, and uses the time and frequency of the clock source device. The time and frequency of the deviation itself;
- Step 6 When the current primary clock source device fails, if the secondary high priority candidate clock source is not locked, you can choose to switch to the unlocked second highest priority clock source device or switch to the current one according to user settings. The highest priority of the locked alternate clock source devices;
- the user can also be allowed to perform the clock source device switching at any time by manual operation or directly specify the main clock source regardless of the lock status.
- the implementation process of the clock synchronization method of the present embodiment on a network having two backup clock sources will be described below with reference to the accompanying drawings.
- the 1588 slave clock device discovers 1588 clock source 1, source 2, and source 3.
- the slave clock device determines which clock source to use as the primary clock source according to the BMC algorithm.
- Other clock source devices automatically become the alternate clock source. If the priority of 1588 clock source 1 is the highest, the slave clock device selects source 1 as the primary clock. Only source 1 is locked after the source. When source 1 fails, the one with the higher priority among the alternate sources is locked.
- the process of relocking takes a while and performs poorly in the short term.
- the messages related to the interaction include protocol (advertise), synchronization (Sync), delay request (Delay_req), delay response (Delay_resp) and other protocol messages.
- the preferred embodiment of the present invention performs the following steps when adding a new clock source to the network:
- Step 301 1588 detects the clock source 1 from the clock device, starts to lock the clock source 1, and outputs the time and frequency of the clock source 1;
- Step 302 1588 discovers the clock source 2 from the clock device, starts to lock the clock source 2, and does not switch the output;
- Step 303 The clock source device determines whether the priority of the clock source 2 is greater than the priority of the source 1. If the value is less than , step 304 is performed; if not, step 305 is performed;
- Step 304 Continue to output the time and frequency of the source 1 from the clock device, do not switch, calculate the time and frequency deviation from the clock source 2, and end;
- Step 305 The clock device determines whether the clock source 1 is locked, if not, executing step 306; if it is locked, executing step 307;
- Step 306 The time and frequency of switching from the clock device to the output clock source 2 are ended.
- Step 307 It is determined from the clock device whether the user sets the priority to use the locked clock source. If the user sets the priority to use the locked clock source, step 308 is performed; The user does not set the priority to use the locked clock source, and step 309 is performed;
- Step 308 The slave clock device does not temporarily switch, waiting for the clock source 2 to lock and then switch to the output clock source 2 time and frequency;
- Step 309 Immediately switch the time and frequency of the output clock source 2 link from the clock device.
- the 1588 slave clock device can correctly perform the join switch operation.
- Step 402 1588, when the clock device finds that the clock source 1 is invalid, it determines whether the clock source 2 is locked.
- Step 403 If the clock source 2 is locked, switch the time and frequency of the output source 2; Step 404: If the clock source 2 is not locked, determine whether the user sets the priority to use the locked clock source;
- Step 405 If the user does not set the priority use lock clock source, switch to the time and frequency of the output clock source 2;
- Step 407 If the clock source 3 is locked, switch the output clock source 3 time and frequency; Step 408: If the clock source 3 is not locked, then there is no other locked clock source, then switch to the highest priority valid clock source, That is, the time and frequency of the clock source 2 are output.
- the source selection is made.
- the 1588 slave clock device can correctly perform the failover operation.
- FIG. 5 is a diagram showing a clock synchronization apparatus according to a preferred embodiment of the present invention, including: a message interaction unit, a deviation calculation unit, a main clock source selection unit, and a time correction unit, wherein:
- the packet interaction unit is configured to perform protocol packet exchange with multiple candidate clock source devices.
- the deviation calculation unit is configured to calculate according to the interaction between the packet interaction unit and the protocol packets of the multiple candidate clock source devices. Locking with multiple candidate clock source devices with time and frequency deviation from each alternate clock source device;
- a primary clock source selection unit configured to select a primary clock source from a plurality of candidate clock source devices
- a time correction unit configured to use a time and frequency deviation correction time from the primary clock source Frequency.
- the main clock source selection unit calculates the time and time of the found clock source device when the deviation calculation unit has locked a clock source device and finds an alternative clock source device having a lower priority than the main clock source. Frequency deviation, performing a lock with the discovered clock source device.
- the primary clock source selection unit selects the second highest priority candidate clock source device from the plurality of candidate clock source devices when the primary clock source fails, and is not locked with the second highest priority candidate clock source device.
- the candidate clock source device with the highest priority is selected as the primary clock source
- the second highest priority device is selected when the secondary clock source device with the second highest priority is locked. Select the clock source device as the primary clock source; or use the second highest priority alternate clock source device as the primary clock source.
- modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
- the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module.
- the invention is not limited to any particular combination of hardware and software.
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP12827400.8A EP2738971B1 (en) | 2011-09-01 | 2012-07-19 | Method and device for clock synchronization |
RU2014112233/07A RU2583847C2 (ru) | 2011-09-01 | 2012-07-19 | Способ и устройство для синхронизации часов |
BR112014004559A BR112014004559A2 (pt) | 2011-09-01 | 2012-07-19 | método e dispositivo para sincronização de relógio |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110256492.7A CN102291232B (zh) | 2011-09-01 | 2011-09-01 | 一种时钟同步方法及装置 |
CN201110256492.7 | 2011-09-01 |
Publications (1)
Publication Number | Publication Date |
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WO2013029441A1 true WO2013029441A1 (zh) | 2013-03-07 |
Family
ID=45337357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2012/078883 WO2013029441A1 (zh) | 2011-09-01 | 2012-07-19 | 一种时钟同步方法及装置 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP2738971B1 (zh) |
CN (1) | CN102291232B (zh) |
BR (1) | BR112014004559A2 (zh) |
RU (1) | RU2583847C2 (zh) |
WO (1) | WO2013029441A1 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102291232B (zh) * | 2011-09-01 | 2017-04-12 | 中兴通讯股份有限公司 | 一种时钟同步方法及装置 |
CN102752065B (zh) * | 2012-06-29 | 2015-09-09 | 华为技术有限公司 | 一种时间同步方法及系统 |
CN102983960A (zh) * | 2012-12-06 | 2013-03-20 | 盛科网络(苏州)有限公司 | Ptp中实现快速同步切换的方法及装置 |
CN105024798A (zh) * | 2014-04-28 | 2015-11-04 | 中兴通讯股份有限公司 | 一种时间同步的方法及装置 |
CN104052565B (zh) * | 2014-06-26 | 2017-01-25 | 青岛海信移动通信技术股份有限公司 | 一种时间同步方法和通信终端 |
CN104579534B (zh) * | 2014-12-31 | 2017-10-10 | 北京东土科技股份有限公司 | 一种sdh网络中的时钟同步方法及系统 |
CN105515752B (zh) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | 一种消除网络时钟偏差的数据同步方法 |
CN106911414A (zh) * | 2015-12-22 | 2017-06-30 | 中兴通讯股份有限公司 | 时钟同步方法和装置 |
CN105577311A (zh) * | 2015-12-25 | 2016-05-11 | 中国南方电网有限责任公司电网技术研究中心 | 被授时设备1588自适应对时方法与系统 |
CN106936529B (zh) * | 2017-02-28 | 2018-12-07 | 南方电网科学研究院有限责任公司 | 用于并行冗余协议网络中的时钟输出控制方法和系统 |
CN107070579A (zh) * | 2017-05-16 | 2017-08-18 | 中国船舶重工集团公司第七0九研究所 | 三级时间服务器控制与容错方法 |
CN107342831B (zh) * | 2017-06-07 | 2019-02-26 | 北京东土军悦科技有限公司 | 一种主定时源确定方法及装置 |
JP7301689B2 (ja) * | 2019-09-13 | 2023-07-03 | 株式会社東芝 | Ptpメッセージ選択方法およびプログラム、ならびにptpスレーブ装置 |
TWI748902B (zh) * | 2020-05-19 | 2021-12-01 | 瑞昱半導體股份有限公司 | 用於無縫精確時間協定的控制方法以及時間感知橋接裝置 |
CN112867132B (zh) * | 2020-12-27 | 2022-07-15 | 卡斯柯信号有限公司 | 一种基于ptp的多链路时延抖动优化方法及装置 |
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CN101686093A (zh) * | 2008-09-28 | 2010-03-31 | 大唐移动通信设备有限公司 | 传输网时钟同步的方法、设备及系统 |
US20100098111A1 (en) * | 2008-10-21 | 2010-04-22 | Huawei Technologies Co., Ltd. | Method and system for precise-clock synchronization, and device for precise-clock frequency/time synchronization |
US20100150288A1 (en) * | 2008-12-17 | 2010-06-17 | Miao Zhu | Synchronization of Low Noise Local Oscillator using Network Connection |
CN102123024A (zh) * | 2011-03-17 | 2011-07-13 | 中兴通讯股份有限公司 | 一种时钟源设备切换选择方法、系统及装置 |
CN102291232A (zh) * | 2011-09-01 | 2011-12-21 | 中兴通讯股份有限公司 | 一种时钟同步方法及装置 |
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RU2133489C1 (ru) * | 1997-07-09 | 1999-07-20 | Акционерное общество закрытого типа Фирма "Котлин" | Система формирования временных поправок по сигналам спутниковой радионавигационной системы к шкалам времени пространственно разнесенных пунктов |
US20100254225A1 (en) * | 2009-04-03 | 2010-10-07 | Schweitzer Iii Edmund O | Fault tolerant time synchronization |
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2011
- 2011-09-01 CN CN201110256492.7A patent/CN102291232B/zh not_active Expired - Fee Related
-
2012
- 2012-07-19 EP EP12827400.8A patent/EP2738971B1/en not_active Not-in-force
- 2012-07-19 BR BR112014004559A patent/BR112014004559A2/pt not_active Application Discontinuation
- 2012-07-19 WO PCT/CN2012/078883 patent/WO2013029441A1/zh active Application Filing
- 2012-07-19 RU RU2014112233/07A patent/RU2583847C2/ru not_active IP Right Cessation
Patent Citations (5)
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CN101686093A (zh) * | 2008-09-28 | 2010-03-31 | 大唐移动通信设备有限公司 | 传输网时钟同步的方法、设备及系统 |
US20100098111A1 (en) * | 2008-10-21 | 2010-04-22 | Huawei Technologies Co., Ltd. | Method and system for precise-clock synchronization, and device for precise-clock frequency/time synchronization |
US20100150288A1 (en) * | 2008-12-17 | 2010-06-17 | Miao Zhu | Synchronization of Low Noise Local Oscillator using Network Connection |
CN102123024A (zh) * | 2011-03-17 | 2011-07-13 | 中兴通讯股份有限公司 | 一种时钟源设备切换选择方法、系统及装置 |
CN102291232A (zh) * | 2011-09-01 | 2011-12-21 | 中兴通讯股份有限公司 | 一种时钟同步方法及装置 |
Also Published As
Publication number | Publication date |
---|---|
RU2583847C2 (ru) | 2016-05-10 |
BR112014004559A2 (pt) | 2017-06-13 |
EP2738971A4 (en) | 2015-01-28 |
RU2014112233A (ru) | 2015-10-10 |
EP2738971A1 (en) | 2014-06-04 |
CN102291232A (zh) | 2011-12-21 |
CN102291232B (zh) | 2017-04-12 |
EP2738971B1 (en) | 2016-09-21 |
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