WO2013027739A1

WO2013027739A1 - Deterioration diagnostic circuit and deterioration diagnostic method

Info

Publication number: WO2013027739A1
Application number: PCT/JP2012/071109
Authority: WO
Inventors: 永典實吉
Original assignee: 日本電気株式会社
Priority date: 2011-08-24
Filing date: 2012-08-15
Publication date: 2013-02-28
Also published as: JPWO2013027739A1

Abstract

In order to more accurately measure a deterioration state of a semiconductor integrated circuit by means of a simpler configuration, a deterioration diagnostic circuit of the present invention is provided with: a block to be tested, which includes a first circuit to be subjected to deterioration diagnosis; a reference block, which includes a second circuit that is provided with a configuration identical to that of the first circuit; a determining means, which determines whether elements constituting the block to be tested are deteriorated or not by comparing characteristics of first signals, which are outputted from the block to be tested in the cases where signals indicating measurement mode are inputted, with characteristics of second signals outputted from the reference block; and a control means, which outputs, to the determining means, the signals that indicate the measurement mode.

Description

Deterioration diagnosis circuit and deterioration diagnosis method

The present invention relates to a deterioration diagnosis circuit and a deterioration diagnosis method for a semiconductor integrated circuit.

The characteristics of a semiconductor integrated circuit deteriorate due to factors such as use after manufacture and environmental conditions. When the deterioration of the semiconductor integrated circuit proceeds more than a certain level, the semiconductor integrated circuit is determined to be defective. However, when it is determined that the semiconductor integrated circuit is defective, it is generally difficult to determine whether the cause of the failure is due to lifetime (ie, reasonable deterioration due to aging deterioration) or accidental failure. It is.
Therefore, knowing the degree of progress of deterioration of the semiconductor integrated circuit after shipment is extremely important for identifying the true cause of the failure of the semiconductor integrated circuit. By knowing the progress of deterioration of the semiconductor integrated circuit, it is possible to easily feed back the progress of deterioration when an unexpected failure or unexpected deterioration is observed to the design of the semiconductor integrated circuit. Further, by acquiring and analyzing log information of the degree of progress of deterioration and predicting an appropriate replacement time of the semiconductor integrated circuit, it can be used for setting an optimal maintenance time of the semiconductor integrated circuit.
It is desirable that the information on the degree of progress of deterioration of the semiconductor integrated circuit can be output to the outside of the semiconductor integrated circuit without using an external measuring instrument, and further stored. As a means for that purpose, a technique is known in which a ring oscillator is configured in a semiconductor integrated circuit, and the degree of deterioration of the semiconductor integrated circuit is calculated by measuring changes in the oscillation frequency.
Non-Patent Document 1 discloses a configuration in which the resolution of the deterioration degree in the practical range is improved and the measurement time is shortened by using two CMOS (Complementary Metal Oxide Semiconductor) ring oscillators. Specifically, Non-Patent Document 1 describes a configuration in which the ratio of the oscillation frequency is measured using two ring oscillators.
Patent Document 1 discloses a configuration for measuring deterioration of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) using two CMOS ring oscillators. The semiconductor integrated circuit described in Patent Document 1 includes two ring oscillators, and is connected so that a part of its own circuit is branched and replaced with a part of the other circuit when measuring deterioration. Then, by comparing the output phases of the own circuit and the other circuit, a change in the delay amount of the signal due to the deterioration of the circuit characteristics is detected.
Patent Document 2 discloses a configuration for determining whether or not a circuit has failed depending on whether the signal propagation time of the degradation diagnosis target circuit is earlier or later than the reference value. The deterioration diagnosis circuit described in Patent Document 2 performs circuit deterioration diagnosis using only the deterioration diagnosis circuit.
Further, Patent Document 3 discloses a configuration for detecting aged deterioration of a signal delay path. The semiconductor integrated circuit device described in Patent Document 3 writes a comparison result of delay amounts of different delay paths to a memory before shipment, performs the same measurement after shipment, and changes to a delay path if the magnitude relationship of the delay amounts differs. Judge that a failure has occurred.

JP 2010-087275 A JP 2008-147245 A JP 2010-287860 A

In the method described in Non-Patent Document 1 for determining the degree of deterioration of a semiconductor integrated circuit using a change in the oscillation frequency of a ring oscillator, the measured oscillation frequency varies greatly under the influence of the environment. There is a problem. The influence of the environment on the oscillation frequency includes, for example, fluctuations in the chip temperature and power supply voltage of the semiconductor integrated circuit. Non-Patent Document 1 alleviates the influence of the environment to some extent by measuring the ratio of the oscillation frequencies using two ring oscillators. However, the configuration of Non-Patent Document 1 generates a signal having a difference frequency between two ring oscillators in order to measure a change in oscillation frequency. For this reason, the configuration of Non-Patent Document 1 has a problem that the circuit configuration becomes complicated.
In addition, the semiconductor integrated circuit described in Patent Document 1 compares the delay using only a part of its own circuit and the other circuit. For this reason, the configuration described in Patent Document 1 has a problem that an accurate characteristic deterioration amount based on the delay deterioration amount of the entire ring oscillator cannot be obtained.
Furthermore, since the deterioration diagnosis circuit described in Patent Document 2 performs deterioration diagnosis without using the signal of the actual circuit, the result of the deterioration diagnosis may not match the state of the actual circuit. In addition, the deterioration diagnosis circuit described in Patent Document 2 has a problem that it requires generation of a highly accurate reference signal for deterioration diagnosis and complicated setting.
Furthermore, the semiconductor integrated circuit device described in Patent Document 3 needs to measure a delay value and record the value in a nonvolatile memory before shipment. For this reason, the semiconductor integrated circuit device described in Patent Document 3 has a problem in that the cost increases due to the use of expensive components such as a memory and an increase in manufacturing procedures.
An object of the present invention is to provide a technique for solving the problem of more accurately measuring the state of deterioration of a semiconductor integrated circuit with a simple configuration.

The deterioration diagnosis circuit of the present invention includes a test block including a first circuit to be subjected to deterioration diagnosis, a reference block including a second circuit having the same configuration as the first circuit, and a measurement mode. Deterioration of the elements constituting the test block by comparing the characteristics of the first signal output from the test block with the characteristics of the second signal output from the reference block when the signal shown in FIG. Determination means for determining the presence or absence of the control, and control means for outputting a signal indicating the measurement mode to the determination means.
The degradation diagnosis method of the present invention is characterized in that when a signal indicating a measurement mode is input, the characteristics of the first signal output from the test block including the first circuit to be diagnosed for degradation and the first By comparing the characteristics of the second signal output from the reference block including the second circuit having the same configuration as the circuit, the presence or absence of deterioration of the elements constituting the test block is determined.

The present invention makes it possible to more accurately measure the state of degradation of a semiconductor integrated circuit with a simple configuration.

It is a figure which shows the structure of the deterioration diagnostic circuit of 1st Embodiment. It is a figure which shows the structure of the modification of the deterioration diagnostic circuit of 1st Embodiment. It is a figure which shows the structure of the deterioration diagnostic circuit of 2nd Embodiment. It is a figure which shows the structure of the deterioration diagnostic circuit of 3rd Embodiment. It is a figure which shows the logic of the input-output signal to DFF and the output signal of EX-OR in 2nd Embodiment.

Next, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing a configuration of a deterioration diagnosis circuit according to the first embodiment of the present invention.
As shown in FIG. 1, the deterioration diagnosis circuit 100 includes a deterioration diagnosis block 101 and a control means 105. The deterioration diagnosis block 101 includes a test block 102, a reference block 103, and a determination unit 104.
As a result of the stress applied to the test block 102, when the semiconductor integrated circuit constituting the circuit of the test block is deteriorated, a delay which is a kind of characteristic of the logic gate constituting the semiconductor integrated circuit may increase. . As will be described later, there is a difference in the amount of stress between the test block 102 and the reference block 103. The amount of stress is, for example, the intensity of stress or the length of a period during which stress is applied. Therefore, there is a difference in the degree of deterioration (deterioration degree) between the test block 102 and the reference block 103. Accordingly, the delay of the semiconductor integrated circuit in the test block 102 causes a larger delay in the logic gate than in the reference block 103. As a result, the signal output from the test block 102 is gradually delayed with respect to the signal output from the reference block 103. The determination unit 104 detects this delay and determines the deterioration state of the test block 102.
The determination unit 104 has two operation states, a standby mode and a measurement mode. The standby mode is a state in which the deterioration diagnosis block 101 does not measure the deterioration of the test block 102. The measurement mode is a state in which the deterioration diagnosis block 101 measures the deterioration of the test block 102.
The test block includes a first circuit to be subjected to deterioration diagnosis. The reference block includes a second circuit having the same configuration as the first circuit. The test block 102 and the reference block 103 output the first signal and the second signal to the determination unit 104, respectively. The control unit 105 outputs a signal indicating the standby mode or the measurement mode to the determination unit 104.
The determination unit 104 performs the following operation when the signal input from the control unit 105 indicates the measurement mode. That is, in the measurement mode, the determination unit 104 compares the first signal input from the test block 102 and the second signal input from the reference block 103, and degrades the elements constituting the test block 102. The presence or absence of is determined.
It is possible to apply stress to the test block 102 and the reference block 103 to advance the deterioration of each semiconductor integrated circuit. The stress can be applied by whether or not the power supply voltage is applied, the power supply voltage is changed, the ambient temperature is changed, the operating frequency is changed, the circuit load is changed, and the like. However, the types of stress are not limited to these. Any stress that affects the life of the semiconductor integrated circuit may be applied to one or both of the test block 102 and the reference block 103.
A plurality of types of stress may be simultaneously applied to the test block 102 and the reference block 103. At this time, it is preferable that the type and strength of the applied stress be different between the test block 102 and the reference block 103.
For example, in the standby mode, the test block 102 is set to a state in which deterioration is advanced by applying stress, and the power is not applied by connecting the power supply terminal of the semiconductor integrated circuit of the reference block 103 to the ground potential. That is, it is good also as a state which deterioration does not advance. Alternatively, stress may be applied to both the test block 102 and the reference block 103 even in the standby state, and a difference may be provided in the operating conditions such as temperature and operating frequency. Note that the positions of the test block 102 and the reference block 103 may be interchanged.
On the other hand, in the measurement mode, the determination unit 104 compares the timings of the two signals, the output of the test block 102 and the output of the reference block 103, and obtains the difference.
As a specific configuration, the test block 102 and the reference block 103 may include an oscillation circuit, and the output of the oscillation circuit may be output to the determination unit 104.
The determination unit 104 compares the characteristics of the signals output from the test block 102 and the reference block 103 and determines the deterioration state of the test block 102. If the test block 102 and the reference block 103 are provided with an oscillation circuit, the oscillation frequency or the signal phase may be used as the signal characteristics.
FIG. 2 is a diagram illustrating a configuration of a modified example of the deterioration diagnosis circuit of the first embodiment. The deterioration diagnosis block 106 shown in FIG. 2 includes a characteristic adjustment unit 107 between the test block 102 and the determination unit 104. The characteristic adjusting unit 107 adjusts the characteristic of the signal output from the test block 102 and inputs it to the determining unit 104. The output of the determination unit 104 is input to the characteristic adjustment unit 107. The characteristic adjustment unit 107 adjusts the output characteristic (for example, delay time) of the test block 102 so that the difference between the characteristic of the test block 102 and the characteristic of the reference block 102 is not detected in the output of the determination unit 104. The determination unit 104 may have a function of instructing the characteristic adjustment unit 107 whether or not to adjust the characteristic of the signal input to the characteristic adjustment unit 107. In the modification of the first embodiment shown in FIG. 2, the characteristic adjustment amount performed by the characteristic adjustment unit 107 can be the deterioration amount of the test block 102.
The characteristic adjustment unit 107 may be disposed between the reference block 103 and the determination unit 104. Also in this case, the characteristic adjustment amount of the characteristic adjustment unit 107 in a state where the difference between the characteristic of the test block 102 and the characteristic of the reference block 103 is not detected in the output of the determination unit 104 is set as the deterioration amount of the test block 102. it can. Further, the characteristic adjusting means 107 may be provided both between the test block 102 and the determination means 104 and between the reference block 103 and the determination means 104. In this case, the difference between the characteristic adjustment amounts of the two characteristic adjustment means 107 in a state where the difference between the characteristic of the test block 102 and the characteristic of the reference block 103 is not detected in the output of the determination means 104 is the deterioration of the test block 102. It can be an amount. In addition, in the modification of the first embodiment, the deterioration diagnosis block 106 may have a function of outputting the characteristic adjustment amount of the characteristic adjustment unit 107 to the outside.
Here, when the characteristic of the test block 102 is equal to the characteristic of the reference block 103 without the characteristic adjustment unit 107 adjusting the characteristic of the signal, the deterioration diagnosis block 106 determines that the determination unit 104 determines the test block 102. It may be determined that is not deteriorated. In this case, the determination unit 104 does not need to instruct the characteristic adjustment unit 107 to adjust the signal characteristic. Therefore, the determination unit 104 may determine that the test block 102 has not deteriorated because an instruction to adjust the characteristic of the signal to the characteristic adjustment unit 107 is unnecessary.
When the deterioration diagnosis circuit is in the standby mode, the operation states of the test block and the reference block can be arbitrarily set. For example, the test block may be operated even in the standby mode, and the reference block may be stopped.
Furthermore, the above-mentioned “characteristic” is a predetermined observable electric characteristic provided for signals output from the test block 102 and the reference block 103, and can be used for deterioration diagnosis of a semiconductor integrated circuit. Anything is acceptable. Therefore, “characteristics” include the output voltage, output current, voltage amplitude, current amplitude, and the ability to drive the load with respect to the phase, change timing, frequency, and signal magnitude aspects of the time aspect of the signal. included.
In the present embodiment, the occurrence of deterioration is diagnosed by detecting the difference in “characteristic” as described above. Therefore, a specific method for detecting a difference in characteristics is not limited. For example, the determination unit 104 may include a phase comparator for detection of a signal phase, change timing, and frequency difference. The determination means 104 may include a voltage comparator for detecting a difference in signal voltage. Further, the difference between the currents of the signals output from the test block 102 and the reference block 103 may be obtained, for example, from the difference between the voltages generated by the respective signals in the resistor. Furthermore, the ability of a signal to drive a load may be obtained from, for example, the amount of change in voltage or current generated in the signal when a predetermined load is connected to the signal.
The first embodiment described above measures the deterioration state of a semiconductor integrated circuit with a simple configuration. By controlling the measurement of the deterioration diagnosis block including two blocks, the same applies to the test block 102 and the reference block 103 even when receiving environmental fluctuations (for example, power supply voltage and ambient temperature) during measurement. By calculating the difference in delay time after giving environmental fluctuations, it becomes possible to offset the influence of environmental fluctuations.
In addition, a phenomenon called BTI (Bias Temperature Instability) is known in which a deterioration state of an element is recovered when stress applied to the circuit element is removed. If the stress applied to the circuit element in the measurement mode is different from the stress of the circuit element in the standby mode, the deterioration state may be erroneously determined by the BTI. In the deterioration diagnosis circuit of the first embodiment, in the measurement mode, the determination unit 104 determines the deterioration state based on signals output from the test block 102 and the reference block 103. As described above, the test block 102 may operate even in the standby mode in which the control unit 105 does not output a signal indicating the measurement mode. In the standby mode, the reference block 103 may stop operating. By such an operation, the deterioration diagnosis circuit 100 according to the first embodiment can continuously shift from the standby state to the measurement state while maintaining a state in which the test block 102 is stressed. For this reason, the deterioration diagnosis circuit of the first embodiment also has an effect of reducing the possibility that the deterioration amount is erroneously determined due to the influence of BTI.
(Second Embodiment)
FIG. 3 is a diagram illustrating a configuration of a deterioration diagnosis circuit according to the second embodiment. The deterioration diagnosis circuit 200 shown in FIG. 3 includes a deterioration diagnosis block 220 and a control unit 211. The deterioration diagnosis block 220 includes a test block 201, a reference block 202, and a determination unit 203. It should be noted that elements and explanations that are not necessary for the description of the operation are omitted as appropriate, and the configuration shown in FIG. 3 is not limited to the only configuration that can achieve the object of the present invention.
The test block 201 and the reference block 202 shown in FIG. 3 are composed of logic gates. In the second embodiment, the test block 201 is configured as a ring oscillator in which the outputs of N NAND (not AND)

gates

2011, 2012,. The potentials of input terminals (not shown) of the

NAND gates

2011, 2012,... 201N are fixed to the “H” level. Accordingly, each of the NAND gates 2011,... 201N operates as an inverter. However, a NOR (not OR) gate or another type of logic gate may be used as the logic gate. The number of stages of logic gates is not particularly limited as long as the oscillation conditions of the ring oscillator are satisfied. However, the smaller the number of logic gates, the smaller the area of the deterioration diagnosis circuit.
Similar to the test block 201, the reference block 202 includes a ring oscillator including

N NAND gates

2021, 2022,... 202N. Here, the output of the frequency divider 204 is inverted and input to the input of the NAND gate 2021 that does not constitute a loop. In addition, the potentials of input terminals (not shown) of the NAND gates 2022,... 202N are fixed to the “H” level. Therefore, NAND gates 2022,... 202N each operate as an inverter.
The determination unit 203 includes a frequency divider 204, a DFF (D-flop flop) group 205, a switch group 206, an EXOR (exclusive-OR) group 207, an inverter group 212, and a deterioration amount calculation unit 214.
The frequency divider 204 divides a signal input from any one of the branch points between the logic gates included in the test block 201 (hereinafter, referred to as “node”), and thereby the DFF group 205 and the reference block 202. Are output to the NAND gate 2021.
The switch group 206 includes N switches 2061, 2062,... 206N, and inputs the output of one node selected from the nodes of the reference block 202 to the inverter group 212. That is, only one of the switches 2061 to 206N is turned ON (short circuit) at the same time.
The inverter group 212 includes three NAND gates 2121 to 2123 connected in series. The potentials of input terminals (not shown) of the NAND gates 2121 to 2123 are fixed to the “H” level. Accordingly, the NAND gates 2121 to 2123 each operate as an inverter. The inverter group 212 inverts the signal from the node selected by the switch group 206 every time it passes through the NAND gates 2121 to 2123. Outputs from the NAND gates 2121 to 2123 are input to the DFF group 205.
The DFF group 205 includes DFFs 2051 to 2053. The DFFs 2051 to 2053 hold the signals respectively input from the NAND gates 2121 to 2123 at the rising edge from the frequency divider 204. The EXOR group 207 includes

EXOR gates

2071 and 2072. The EXOR gate 2071 performs an exclusive OR operation on the outputs of the

DFFs

2051 and 2052 and outputs the result as an output 208 to the deterioration amount calculation means 214. The EXOR gate 2072 performs an exclusive OR operation on the outputs of the

DFFs

2052 and 2053 and outputs the result to the deterioration amount calculation unit 214 as an output 209.
The deterioration amount calculation unit 214 calculates the deterioration amount of the test block 201 based on the

outputs

208 and 209. A specific method for calculating the deterioration amount in the deterioration amount calculating unit 214 will be described later.
A switch 213 connects and disconnects the node of the test block 201 and the frequency divider 204. The switch 213 is controlled by a control signal 210 output from the control unit 211. The control signal 210 can connect or disconnect between the node of the test block 201 and the frequency divider 204.
In the second embodiment, a state in which the deterioration state is not measured is referred to as a standby mode, and a state in which the deterioration state is measured is referred to as a measurement mode. Hereinafter, operations in the standby mode and the measurement mode will be described. Obviously, the operations described below are examples and are not the only operations that can achieve the objectives of the present invention.
In the standby mode, the control unit 211 outputs a control signal 210 so that the switch 213 disconnects the test block 201 and the frequency divider 204. Then, the test block 201 self-oscillates as a ring oscillator. Here, the test block 201 may be configured so that the operating condition of the ring oscillator can be controlled by an external control signal (not shown). The operation of the reference block 202 is the same as that of the test block 201. Due to the difference in stress (voltage, temperature, etc.) applied to the test block 201 and the reference block 202, the deterioration status of the test block 201 under different stress conditions can be evaluated.
In the measurement mode, a specific node of the test block 201 and the frequency divider 204 are connected by the control signal 210. Transition from the standby mode to the measurement mode is performed by outputting a control signal 210 so that the control unit 211 closes the switch 213. That is, the only difference in the circuit configuration between the standby mode and the measurement mode is whether the switch 213 is open or closed. Therefore, the deterioration diagnosis circuit 200 can shift from the standby mode to the measurement mode without changing the circuit configuration of each block while applying stress to the test block 201 and the reference block 202.
In the measurement mode, the signal of the node of the test block 201 is input to the frequency divider 204. The frequency divider 204 divides the signal input from the test block 201 by a predetermined frequency division ratio. As a result, the output of the frequency divider 204 alternately changes between the “H” level and the “L” level in a cycle corresponding to the frequency division ratio. For example, when the output signal level of the frequency divider 204 immediately before entering the measurement mode is “H”, the output of the frequency divider 204 subsequently changes in the order of “L” and “H”.
First, the operation when the output of the frequency divider 204 changes to “L” will be described. The output of the frequency divider 204 is inverted and input to the input of the NAND gate 2021. Therefore, when the output signal of the frequency divider 204 is “H”, the output of the NAND gate 2021 is fixed to “H”. When the output signal of the frequency divider 204 becomes “L”, the reference block 202 starts oscillating. At the same time, any one of the switches 2061 to 206N is selected. This selection procedure will be described later.
Next, when the number of signals corresponding to the frequency division ratio is input from the test block 201, the output of the frequency divider 204 changes to “H”. At this time, the output level of the node selected by the reference block 202 is held at the output of the DFF group 205. The output level held by the DFF group 205 is logically operated by the EXOR group 207 at the subsequent stage and output as an output 208 and an output 209.
Note that the oscillation operation of the reference block 202 stops when the output of the frequency divider 204 changes from “L” to “H”. Since the stop of the oscillation operation and the latching of the input data from the switch group 206 in the DFF group 205 are performed at the same time, the output signal of the DFF group 205 may be disturbed. A delay circuit may be provided between the frequency divider 204 and the reference block 202 so that the DFF group 205 can correctly latch the input signal when the output of the frequency divider 204 changes. Alternatively, a circuit that holds the signal output from the frequency divider 204 to the reference block 202 until the DFF group 205 latches the input may be provided. Alternatively, the oscillation start and stop of the reference block 202 may be controlled separately from the output of the frequency divider 204 using the control signal 210.
Hereinafter, a method for calculating the deterioration state in the deterioration amount calculating unit 214 will be described. Here, for the sake of simplicity, it is assumed that only the test block 201 is deteriorated. However, it is easily understood that the deterioration state can be relatively calculated even when the operating environment of at least one of the test block 201 and the reference block 202 is changed. Further, when the test block 201 and the reference block 202 are interchanged, the relative deterioration state can be calculated in the same manner.
The connection between the test block 201 and the frequency divider 204 is described based on the configuration of FIG. However, even when a ring oscillator having another configuration or another circuit capable of timing comparison with the reference block 202 is used, the delay amount of the signal output from the test block is measured by the same operation. The amount of deterioration of the test block can be obtained.
In the deterioration detection circuit 220 shown in FIG. 3, the interval at which the output of the frequency divider 204 changes when the test block 201 and the frequency divider 204 are used is expressed by the following equation (1).
(T + ΔT) × 2 × N × M (1)
Here, T is a delay amount per stage of the NAND gate of the test block 201, and ΔT is a delay amount that increases due to deterioration per stage of the NAND gate of the test block 201. N is the number of NAND gate stages of the test block 201, and M is the frequency division ratio of the frequency divider 204. That is, the value of Equation (1) is the total sum of delay amounts generated in the test block at intervals at which the output of the frequency divider 204 changes. Since the internal circuits of the NAND gates 2011 to 201N are the same, it is assumed that the increase in delay amount at the time of performance deterioration in the NAND gates 2011 to 201N is all equal.
On the other hand, the delay amount represented by the following expression (2) is obtained in the reference block 202 as well.
T × X (2)
Expression (2) is a delay amount output from the reference block 202 while the output of the frequency divider 204 changes.
Here, X is the total number of stages of NAND gates through which the signal in the reference block 202 has passed from the fall of the output of the frequency divider 204 to the next rise. In general, in order to measure X, the reference block 202 also requires a counter and a large amount of DFF. Therefore, in the second embodiment, in order to simplify and reduce the area of the deterioration detection circuit, the difference between the delay amount of the test block 201 and the delay amount of the reference block 202 is obtained without directly obtaining X by a counter or the like. Measuring. Therefore, the deterioration detection circuit 220 selects a node of the reference block 202 to be input to the DFF group at the start of the measurement mode. The specific procedure will be described below.
First, the switch group 206 selects a certain node until the output of the frequency divider 204 rises. Then, a node in which the levels of the output 208 and the output 209 at the time point when the output of the frequency divider 204 falls is searched for. That is, a node where the output 208 is “L” and the output 209 is “H” or the output 208 is “H” and the output 209 is “L” is searched. Here, the opening / closing control of the switch group 206 and the investigation of the levels of the

outputs

208 and 209 may be performed by the determination unit 203 or may be performed by another device under the control of the determination unit 203 from the outside.
FIG. 5 is a diagram illustrating signal timing in the second embodiment. In FIG. 5, the output of the frequency divider 204 is a signal obtained by dividing the output of the test block 201. Signals A to C and signals A ′ to C ′ indicate inputs and outputs of the DFFs 2051 to 2053, respectively. FIG. 5 shows a timing chart when one of the switches 2061 to 206N in which the output 208 is “L” and the output 209 is “H” is selected and closed at the start of the measurement mode.
The circuit configuration of the test block 201 and the reference block 202 as ring oscillators is the same. Therefore, when the test block 201 is not deteriorated as compared with the reference block 202, it is between the output of the frequency divider 201 and the signals (A to C) input from the reference block to the DFF group. The timing does not change ((a) of FIG. 5). However, when the deterioration of the test block 201 progresses and the delay of the output of the test block 202 increases, the rise timing of the frequency divider 204 is delayed with respect to the input signals (A to C) to the DFF group. . When the deterioration of the test block 201 progresses and the rising timing of the frequency divider 204 is delayed from t1 to t2 in FIG. 5, the output signal B ′ of the DFF 2052 is inverted. As a result, the

outputs

208 and 209 are inverted, and the output 208 becomes “H” and the output 209 becomes “L” ((b) in FIG. 5).
Since the NAND gates 2121 to 2123 are connected in series, the timing of the input signals A to C to the DFF group 205 is delayed by one NAND gate of the inverter group 212 in the order of A, B, and C. When the rise timing of the frequency divider 204 is delayed from t1 to t2 across the inversion time of the output signal B ′ of the DFF 2052, the delay amount from the fall of the frequency divider 204 to the rise is averaged. One NAND gate. In the test block 201, it is considered that the delay for one gate stage has increased due to deterioration. Here, the number of gate stages through which the signal in the test block 201 has passed is “2 × N × M”. Therefore, when the signals A ′ to C ′ and the

outputs

208 and 209 change from (a) to (b) in FIG. 5, the deterioration amount calculation unit 214 determines the deterioration amount per gate stage in the test block 201. Can be obtained as 1 / (2 × N × M).
Note that the determination unit 203 may select the node again by the switch group 206 after both the output 208 and the output 209 are inverted and the output 208 becomes “H” and the output 209 becomes “L”. For example, the determination unit 203 may shift the node selected in the reference block 202 backward by one in a state where the rising timing of the frequency divider 204 is delayed until t2 in FIG. Signals A to C when the node is shifted backward by one are indicated by broken lines in FIG. The relationship between the signals indicated by broken lines in FIG. 5 is that the signal B in FIG. 5 is a new signal A, and the signals obtained by sequentially inverting them are B and C. As a result, by shifting the node backward by one, the relationship between the rising timing of the frequency divider 204 and the input signals A to C to the DFF group 205 becomes the same as that at t1 in FIG.
As described above, after the output 208 and the output 209 are inverted, the node selected by the switch group 206 is shifted backward, whereby the output 208 can be set to “L” and the output 209 can be set to “H”. . Thereafter, when the deterioration of the test block 201 further proceeds and the output 208 becomes “H” and the output 209 becomes “L”, the deterioration amount calculating means 214 further proceeds with the deterioration by 2 / (2 × N XM) can be calculated.
Thereafter, by sequentially shifting the selected nodes backward in accordance with the delay of the rise timing of the frequency divider 204, the deterioration amount calculating unit 214 can calculate the deterioration state of the test block with a simple circuit configuration. .
In selecting a node, the timing at which the output 208 becomes “L” and the output 209 becomes “H” may be not only t1 in FIG. 5 but also t3. However, also in this case, when the rise timing of the frequency divider 204 is delayed from t3 to t4 due to the progress of performance deterioration of the test block 201, the output 208 is inverted to “H” and the output 209 is inverted to “L”. Then, the deterioration amount calculating means 214 can measure the deterioration amount of the test block 201 in the same procedure as described above.
That is, when the node is selected, the deterioration amount calculating means 214 is not limited to the test block whether the output 208 is “L” and the output 209 is “H” at t1 or t4 in FIG. The amount of degradation 201 can be calculated.
Thereafter, the deterioration amount calculating unit 214 can measure the progress of deterioration by sequentially shifting the nodes of the reference block 202 that inputs signals to the determining unit 203 backward. That is, the deterioration diagnosis circuit of the second embodiment measures the delay amount generated in the test block by comparing the output of the test block and the reference block without using a counter or a large number of DFFs. ing. As a result, the degradation diagnosis circuit of the second embodiment has an effect that the degradation state of the semiconductor integrated circuit can be measured more accurately with a simple circuit configuration.
Further, the deterioration diagnosis circuit of the second embodiment can continuously shift from the standby mode to the measurement mode by the control signal 210 without changing the circuit configuration of the test block 201 and the reference block 202. is there. For this reason, the deterioration diagnosis circuit of the second embodiment also has an effect of reducing the possibility that the deterioration amount is erroneously determined due to the influence of BTI.
In the second embodiment, as a modification, the determination unit 203 may include a characteristic adjustment unit as in the modification of the first embodiment. The characteristic adjusting unit adjusts the delay amount of the input signal so that the deterioration amount of the test block 201 approaches 0 in the deterioration amount calculating unit 214.
The characteristic adjustment means may be provided between at least one of the output of the test block 201 and the input of the frequency divider 204 and between the output of the frequency divider 204 and the input of the NAND gate 2021. In the modification of the second embodiment, the deterioration amount of the test block 201 is obtained based on the delay adjustment amount of the characteristic adjustment unit when the deterioration amount calculation unit 214 does not detect the deterioration of the test block 201. it can.
Furthermore, in the modification of the second embodiment, the determination unit 203 may have a function of outputting the characteristic adjustment amount of the characteristic adjustment unit to the outside.
(Third embodiment)
The configuration of the second embodiment shown in FIG. 3 is a configuration that compares the signals A to C delayed by one stage by the inverter group 212 with the rising timing of the frequency divider 204. That is, the resolution of the delay amount of the test block 201 to be detected is fixed to one gate.
In the third embodiment, a configuration in which a signal whose timing is compared with the output from the frequency divider 204 can be freely selected for each node will be described.
FIG. 4 is a diagram illustrating a configuration of a deterioration diagnosis circuit according to the third embodiment. The deterioration diagnosis circuit 300 shown in FIG. 4 includes a deterioration diagnosis block 320 and a control means 311. The deterioration diagnosis block 320 includes a test block 301, a reference block 302, and a determination unit 303. It should be noted that elements and descriptions unnecessary for the description of the operation are omitted as appropriate, and the configuration shown in FIG. 4 is clearly not limited to the only configuration that can achieve the object of the present invention. .
The test block 301 and the reference block 302 shown in FIG. 4 are composed of logic gates. The test block 301 is a ring oscillator composed of NAND gates 3011 to 301N, and the reference block 302 is a ring oscillator composed of NAND gates 3021 to 302N.
The determination unit 303 includes a frequency divider 304, a switch group 306, a DFF group 305, an EXOR group 307, and a deterioration amount calculation unit 314.
The frequency divider 304 divides a signal input from any node of the test block 301 and outputs the divided signal to the DFF group 305 and the NAND gate 3021 of the reference block 302. The switch group 306 branches each node of the reference block 302 into three and connects them to DFFs 3051 to 3052 constituting the DFF group 305.
The output of the DFF group 305 latches the output from the three nodes selected by the switch group 306 at the rise from the frequency divider 304. The EXOR group 307 performs two exclusive OR operations among the three outputs from the DFF group 305.

Outputs

308 and 309 are outputs of EXORs 3071 and 3072, respectively, and are output to the deterioration amount calculation means 314.
The deterioration amount calculation unit 314 calculates the deterioration amount of the test block 301 based on the

outputs

308 and 309. A specific method for calculating the deterioration amount in the deterioration amount calculating means 314 will be described later.
The switch group 306 includes three switches for each node of the reference block 302. In FIG. 4, switches 3061a to 3061c, 3062a to 3062c,... 306Na to 306Nc constitute a switch group 306. When a switch in the switch group 306 is closed (conducts), the output of the node is connected to any DFF in the DFF group 305.
For example, when the switch 3061a is closed, the output of the NAND gate 302N is input to the DFF 3051 through the signal line A. When the

switch

3062b or 3062c is closed, the output of the NAND gate 3021 is input to the

DFF

3052 or 3053 through the signal line B or C, respectively. The operation of each switch constituting the switch group 306 is the same for other nodes.
In the third embodiment, the switches 3061a and the like constituting the switch group 306 are individually controlled. With this configuration, the wiring of the signals A to C can be connected to any node of the reference block 302. That is, the delay amount between the signals A and B and the delay amount between the signals B and C can be set in units of the number of NAND gates. As a result, in the third embodiment, it is possible to change the resolution for detecting the change in the rise timing of the output of the frequency divider 204 described in FIG.
In the configuration described with reference to FIG. 3, in the inverter group 212, a signal input to the DFFs 2051 to 2053 is delayed by one gate. In FIG. 4, for example, the determination unit 303 can be configured so that a signal that causes a delay of one gate stage is input to the DFF group 305 by closing the switch 3061 a, the switch 3062 b, and the switch 3063 c.
Further, in the configuration shown in FIG. 4, for example, in addition to the switch 3061a, the switches 3064b and 3067c, which are not shown in the figure, are separated by 3 stages by a NAND gate, respectively, so that the DFF group 305 has a delay of 3 stages of NAND gates. The signal that caused the error is input. In this case, the delay between the change points of the signals A and B and B and C in FIG. 5 is the length of three NAND gates. Therefore, when the

outputs

308 and 309 are inverted, a delay corresponding to three stages of gates is generated in the test block 301.
At this time, the number of gate stages through which the signal in the test block 301 has passed is 2 × N × M, and it is considered that the delay in the three stages of gates has increased in the test block 301 due to deterioration. For this reason, the deterioration amount calculating means 314 can determine the deterioration amount per gate stage in the test block 301 as 3 / (2 × N × M).
Note that the oscillation operation of the reference block 302 stops when the output of the frequency divider 304 changes from “L” to “H”. Since the stop of the oscillation operation and the latching of the input data from the switch group 306 in the DFF group 305 are performed at the same time, the output signal of the DFF group 305 may be disturbed. A delay circuit may be provided between the frequency divider 304 and the reference block 302 so that the DEF group 305 can correctly latch the input signal when the output of the frequency divider 304 changes. Alternatively, a circuit that holds the signal output from the frequency divider 304 to the reference block 302 until the DFF group 305 latches the input may be provided. Alternatively, the oscillation start and stop of the reference block 302 may be controlled separately from the output of the frequency divider 304 using the control signal 310.
As described above, the degradation diagnosis circuit of the third embodiment also has the effect that the degradation state of the semiconductor integrated circuit can be measured with a simple circuit configuration, similarly to the degradation diagnosis circuit of the second embodiment.
In the third embodiment, by providing the switch group 306, the measurement unit (resolution) of the deterioration amount of the test block 301 to be measured can be changed. By increasing the measurement unit of the deterioration amount, it is possible to average the delay amount variation due to each NAND gate and the delay amount error due to noise.
Note that the deterioration diagnosis circuit of the third embodiment is in a standby mode by the control signal 310 without changing the circuit configuration of the test block 301 and the reference block 302, similarly to the deterioration diagnosis circuit of the second embodiment. It is possible to make a continuous transition from measurement mode to measurement mode. For this reason, the deterioration diagnosis circuit of the third embodiment also has an effect of reducing the influence of recovery of deterioration due to BTI.
In the third embodiment, as a modification, the determination unit 303 may include a characteristic adjustment unit as in the modification of the first embodiment. The characteristic adjustment unit adjusts the delay amount of the input signal so that the deterioration amount of the test block 301 approaches 0 in the deterioration amount calculation unit 314.
The characteristic adjustment means may be provided between at least one of the output of the test block 301 and the input of the frequency divider 304 and between the output of the frequency divider 304 and the input of the NAND gate 3021. In the modification of the third embodiment, the deterioration amount of the test block 301 is obtained based on the delay adjustment amount of the characteristic adjustment means when the deterioration amount calculation means 314 does not detect the deterioration of the test block 301. it can.
Furthermore, in the modification of the third embodiment, the determination unit 303 may have a function of outputting the characteristic adjustment amount of the characteristic adjustment unit to the outside.
The embodiment of the present invention has been described above with reference to the first to third embodiments. However, the form to which the present invention can be applied is not limited to the above-described embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and detailed description of the present invention within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2011-182438 for which it applied on August 24, 2011, and takes in those the indications of all here.
The embodiment of the present invention can be described as in the following supplementary notes 1 to 12, but is not limited thereto.
(Appendix 1)
A test block including a first circuit to be diagnosed for deterioration;
A reference block including a second circuit having the same configuration as the first circuit;
When the signal indicating the measurement mode is input, the first characteristic of the first signal output from the test block is compared with the second characteristic of the second signal output from the reference block. Determination means for determining the presence or absence of the deterioration of the elements constituting the test block,
Control means for outputting a signal indicating the measurement mode to the determination means;
A deterioration diagnosis circuit comprising:
(Appendix 2)
The deterioration diagnosis circuit according to appendix 1, wherein the first characteristic and the second characteristic are electrical characteristics that are changed as a result of the deterioration, which are included in the first signal and the second signal, respectively.
(Appendix 3)
The first characteristic and the second characteristic each include at least one of a phase, a change timing, a frequency, an output voltage, an output current, a voltage amplitude, a current amplitude, and an ability to drive a load. Degradation diagnostic circuit described.
(Appendix 4)
4. The deterioration diagnosis circuit according to any one of appendices 1 to 3, wherein the determination unit detects a difference between a characteristic of an element constituting the test block and a characteristic of an element constituting the reference block.
(Appendix 5)
When a signal indicating the measurement mode is input, at least one of the first signal and the second signal according to an instruction from the determination unit so that the first characteristic and the second characteristic are equal to each other. Provided with characteristic adjustment means for performing predetermined adjustment on one side
The determination means determines the presence or absence of the deterioration depending on the necessity of the instruction.
The deterioration diagnosis circuit according to any one of appendices 1 to 3.
(Appendix 6)
The deterioration diagnosis circuit according to appendix 5, wherein the determination unit outputs an adjustment amount necessary for performing the adjustment as a deterioration amount indicating the degree of deterioration.
(Appendix 7)
7. The deterioration diagnosis circuit according to any one of appendices 1 to 6, wherein one or both of the first circuit and the second circuit has a circulation configuration in which a signal is output at a predetermined timing.
(Appendix 8)
8. The deterioration diagnosis circuit according to any one of appendices 1 to 7, wherein one or both of the first circuit and the second circuit has a configuration in which logic gates are cyclically connected.
(Appendix 9)
The deterioration diagnosis circuit according to any one of appendices 1 to 8, wherein the determination unit compares a delay time of an element constituting the test block with a delay time of an element constituting the reference block.
(Appendix 10)
The determination means includes
A frequency divider that outputs a third signal obtained by dividing the first signal;
A latch circuit that latches a fourth signal and a fifth signal having different delay amounts with respect to the second signal by the third signal and outputs the latched signal, respectively;
An EXOR (exclusive-OR) circuit for obtaining an exclusive OR of the outputs of the latch circuit;
A deterioration amount calculating means for calculating the deterioration amount based on an output of the EXOR circuit;
A deterioration diagnosis circuit according to any one of appendices 1 to 9.
(Appendix 11)
The deterioration diagnosis circuit according to appendix 10, wherein the fourth signal and the fifth signal are generated by delaying the second signal.
(Appendix 12)
The fourth signal and the fifth signal are the second signal output from positions corresponding to the preceding stage and the succeeding stage in the propagation path of the predetermined signal of the reference block. Deterioration diagnosis circuit.
(Appendix 13)
The deterioration diagnosis circuit according to any one of appendices 1 to 12, wherein when the control means does not output a signal indicating the measurement mode, the test block operates and the reference block stops operating.
(Appendix 14)
14. The deterioration diagnosis circuit according to any one of appendices 1 to 13, wherein the test block and the reference block operate in an operating environment in which stresses applied to the test block and the reference block are different.
(Appendix 15)
The same configuration as the first circuit and the first characteristic of the first signal output from the test block including the first circuit to be subjected to deterioration diagnosis when a signal indicating the measurement mode is input The presence or absence of deterioration of the elements constituting the test block is determined by comparing the second characteristic of the second signal output from the reference block including the second circuit including:
Deterioration diagnosis method.

100, 200, 300 Deterioration diagnosis circuit 101 Degradation diagnosis block 102, 201, 301 Test block 103, 202, 302

Reference block

104, 203, 303 Judgment means 105, 211, 311 Control means 106 Degradation diagnosis block 107 Characteristic adjustment means 204, 304

Frequency divider

205, 305

DFF group

206, 306

Switch group

207, 307

EXOR group

208, 308

Output

209, 309 Output 210, 310

Control signal

213, 313 Switch 214, 314 Degradation amount calculation means 2011-201N, 2021 ~ 202N, 2121 ~ 2123 NAND gate 2051 ~ 2053, 3051 ~ 3053 D flip-flop 2061 ~ 206N Switch 3061a ~ 306Na, 3061b ~ 306Nb, 3061c ~

306Nc Switch

2071,2072,3071,3072 EXOR gate

Claims

A test block including a first circuit to be diagnosed for deterioration;
A reference block including a second circuit having the same configuration as the first circuit;
When the signal indicating the measurement mode is input, the first characteristic of the first signal output from the test block is compared with the second characteristic of the second signal output from the reference block. Determination means for determining the presence or absence of the deterioration of the elements constituting the test block,
Control means for outputting a signal indicating the measurement mode to the determination means;
A deterioration diagnosis circuit comprising:
2. The deterioration diagnosis circuit according to claim 1, wherein the first characteristic and the second characteristic are electrical characteristics that change as a result of the deterioration, which are included in the first signal and the second signal, respectively. .
When a signal indicating the measurement mode is input, at least one of the first signal and the second signal according to an instruction from the determination unit so that the first characteristic and the second characteristic are equal to each other. Provided with characteristic adjustment means for performing predetermined adjustment on one side
The determination means determines the presence or absence of the deterioration depending on the necessity of the instruction.
The deterioration diagnosis circuit according to claim 1 or 2.
The deterioration diagnosis circuit according to claim 3, wherein the determination unit outputs an adjustment amount necessary for performing the adjustment as a deterioration amount indicating the degree of deterioration.
The determination means includes
A frequency divider that outputs a third signal obtained by dividing the first signal;
A latch circuit that latches a fourth signal and a fifth signal having different delay amounts with respect to the second signal by the third signal and outputs the latched signal, respectively;
An EXOR (exclusive-OR) circuit for obtaining an exclusive OR of the outputs of the latch circuit;
A deterioration amount calculating means for calculating the deterioration amount based on an output of the EXOR circuit;
A deterioration diagnosis circuit according to claim 1, comprising:
The deterioration diagnosis circuit according to claim 5, wherein the fourth signal and the fifth signal are generated by delaying the second signal.
The said 4th signal and the said 5th signal are the said 2nd signal output from the position corresponded to the front | former stage and back | latter stage in the propagation path of a predetermined | prescribed signal of the said reference block. Deterioration diagnosis circuit.
8. The deterioration diagnosis circuit according to claim 1, wherein when the control means does not output a signal indicating the measurement mode, the test block operates and the reference block stops operating. .
The deterioration diagnosis circuit according to claim 1, wherein the test block and the reference block operate in an operating environment in which stresses applied to the test block and the reference block are different.
When a signal indicating a measurement mode is input, the first characteristic of the first signal output from the test block including the first circuit to be diagnosed for deterioration is the same as the first circuit. Deterioration diagnosis method for determining presence / absence of deterioration of elements constituting said test block by comparing with second characteristic of second signal output from reference block including second circuit having configuration .