JPH11351883A - Closed-loop optical interference angular velocity meter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a closed-loop light interference angular velocity meter in which a maximum output can be held without reducing the output signal even when an input angular velocity exceeding a maximum input angular velocity is input by a method wherein an integrator is constituted of a cumulative adder in which a set prescribed value or higher is not added cumulatively regarding an addition in the positive or negative direction. SOLUTION: The output of an adder 761 in a cumulative adder 76 compares a reference value +DR and a reference value -DR which are output by an integrator reference source 764 and an integrator reference source 765 in an integrator comparator 766 and an integrator comparator 767. At this time, when the output of the adder 761 becomes equal to the reference value +DR and the reference value -DR by the integrator reference sources 764, 765 or becomes large as an absolute value, an OR circuit 768 outputs a logical value of 1 to an output terminal S. The output of the logical value of 1 is supplied to a latch switch 763, and the switch 763 is opened. Since an update clock is not applied to a latch circuit 762, the output of the adder 761 holds an immediately previous value as it is, and both the reference value +DR and the reference value -DR by the integrator reference source 764 and the integrator reference source 765 are maintained until they become less than the absolute value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a closed loop optical interferometer, and more particularly, to a digital phase lamp optical interferometer in a closed loop optical interferometer.

[0002]

2. Description of the Related Art The whole of a closed-loop optical interference gyro will be described with reference to FIG. FIG. 2 is a diagram showing a closed-loop optical interference gyro employing a digital phase lamp as a feedback signal.
In FIG. 2, 1 is a light source, 2 is a directional coupler, 3 is a branching device, 4 is an optical fiber coil, 5 is a photodetector, 6 is an AD converter, 7 is a logic circuit, 8 is a phase modulation drive circuit, 9
Is a DA converter. Light emitted from the light source 1 is sent to the splitter 3 via the directional coupler 2 and split into two, one of which is incident on one fiber end of the optical fiber coil 4 as CW light, and is split into two. The other is CC
The light enters the other fiber end of the optical fiber coil 4 as W light. The CW light propagates clockwise in the optical fiber coil 4, exits through the other end of the fiber, and is sent back to the splitter 3. The CCW light also propagates counterclockwise in the optical fiber coil 4, exits through one of the fiber ends, and is sent back to the splitter 3. here,
When an angular velocity is input with respect to the central axis of the optical fiber coil 4, a phase difference is generated between the CW light and the CCW light based on the Sagnac effect. The CW light and the CCW light interfere with each other to generate interference fringes. This interference light is received by the light receiver 5 via the directional coupler 2, and the interference light intensity of the interference fringes is converted into an electric signal. Based on this electric signal, the angular velocity input around the central axis of the optical fiber coil 4 can be detected.

In the closed loop optical interference gyro, a feedback phase is applied to the CW light and the CCW light in such a direction as to cancel the Sagnac phase difference generated based on the input angular velocity. Zero phase control for constantly controlling the phase difference between them to zero is performed, and the input feedback is measured to detect the input angular velocity. As a result, the closed-loop optical interference gyro is hardly affected by fluctuations in the amount of light emitted from the light source, fluctuations in the transmission loss of the optical unit, and other fluctuations. 31 and 32
Denotes a phase modulator incorporated in the splitter 3, and applies a phase modulation signal to the phase modulator 31 to phase-modulate the CW light and the CCW light at one end of the optical fiber coil 4. On the other hand, a feedback phase signal is applied to the phase modulator 32 to always cancel the phase difference between the two lights at the other end of the optical fiber coil 4 to zero.

In the above description, a first phase modulator 31 is formed at one branch end of the splitter 3 and is driven by the phase modulation drive circuit 8, while the other is provided with a second phase modulator 31 at the other branch end. The phase modulator 32 is configured to be individually driven by a feedback signal source. However, the phase modulation driving circuit 8 and the feedback signal source are connected in series to drive the phase modulator in common. It can be configured. Then, both the first phase modulator 31 and the second phase modulator 32 can be configured at one branch end of the splitter 3 to drive both separately. The phase modulation drive circuit 8 is commonly connected to one of the electrodes forming the first phase modulator 31 and one of the electrodes forming the second phase modulator 32, and the first phase modulation is performed. Of the electrodes forming the modulator 31 and the second phase modulator 3
It is possible to adopt a configuration in which a feedback signal source is commonly connected to and driven by the other of the electrodes forming the second electrode 2. Further, the phase modulation drive circuit 8 and the feedback signal source are connected in series, so that one phase modulator 31 provided only at one branch end of the branch unit 3 can be driven.

Here, the closed-loop optical interference gyro measures the CW light and the CW that circularly propagate through the optical fiber coil 4.
Based on the type of signal that provides a feedback phase difference between the two CW lights, the CW light is classified into a serrodyne method and a digital phase ramp method. The digital phase ramp system uses a step-like sawtooth wave signal as a feedback signal, and is a system in which the width of one step matches the propagation time τ of light in an optical fiber coil.
The serrodyne method includes a linear serodine method of a linear sawtooth wave, and a digital sellin method of digitally generating a linear sawtooth wave signal by making the width of the step of the digital phase ramp method smaller than τ.

Referring to FIG. 4A, a rectangular wave phase modulation signal having a pulse width of τ time is applied to a phase modulator 31 disposed at one end of the optical fiber coil 4 and To both CW light and CCW light propagating
A phase difference of π / 2 (rad) is applied alternately. Referring to FIG. 3 as well, “region I” indicates a stationary state where the input angular velocity Ω is not applied, and “region II” indicates a state where the input angular velocity Ω is applied and a Sagnac phase difference ΔΦ _s is generated. Is shown.

[0007] Positive phase modulation Φ ₁ , Φ ₃ , Φ ₅ , Φ ₇ ...
.. corresponding to the interference outputs I ₁ , I ₃ , I ₅ , I ₇ ... To I _p , negative phase modulation Φ ₂ , Φ ₄ , Φ ₆ , Φ ₈ . The corresponding interference light outputs I ₂ , I ₄ , I ₆ , I ₈ ...
Then, the following equation is obtained. Obtained from _{Ip = P o (1 + sin} △ Φ s) / 2 ······ (1) In = P o (1-sin △ Φ s) / 2 ······ (2) photodetector 5 The signal is referred to as I ₁
A / D conversion corresponding to I ₂ , I ₃ ...
and data D _p corresponding to _p, the data D _n corresponding to I _n
Are sequentially subtracted, D _p , D _n and the subtraction value △ D are obtained from the equations (1) and (2) as follows: D _p = B + K _d sin △ Φ _s (3) D _n = B− K _d sin △ Φ _s (4) ΔD = D _p −D _n = 2 K _d sin △ Φ _s (5) B: offset bias, K _d : proportional It becomes a constant and can perform high-accuracy synchronous detection without being affected by offset bias.

The phase difference ΔΦ between the CW light and the CCW light cyclically propagating through the optical fiber coil 4 is expressed by the following equation, where Sagnac phase difference is ΔΦ _s and feedback phase difference is ΔΦ _f . △ Φ = △ Φ _s one △ Φ _f ············ (6) The phase modulator signal shown by the formula (5) 32
, The output of the synchronous detection circuit 72, that is, the input of the integrator 73, can be made zero. In this case, ΔΦ _s = ΔΦ _f ...・ ・ (7) holds.

In order to generate the feedback phase difference ΔΦ _f , a stair-stepped feedback phase signal having a step width of τ time is converted into a phase modulator 3 composed of an optical integrated circuit.
2 is achieved. When a digital phase ramp is applied to the phase modulator 32 disposed at the other end of the optical fiber coil 4, the CW light undergoes a phase shift indicated by a solid line in FIG. 4B, while the CCW light is indicated by a broken line. As described above, the phase shift before the light propagation time τ is received. The phase difference ΔΦ (= Φ _CW −Φ _CCW ) between the two lights is shown in FIG.
As shown in (c), the same amount of phase difference as the height of one step of the stairs occurs.

Further, the digital phase ramp is fly back by 2π (rad) when the digital phase ramp exceeds 2π (rad). Although the phase difference at this time is ΔΦ _f −2π, the output of the interference light becomes equal to the output of the interference light outside the flyback period due to the periodicity of the trigonometric function, and continuous closed loop control becomes possible. A method of reading angular velocity information will be described. The feedback phase difference ΔΦ _f, that is, the height of one step is shown in FIG.
From (b), ΔΦ _f = τΦ _R / T (8) where τ is the propagation time of light in the optical fiber (τ = nL /
C) n: Refractive index of optical fiber L: Optical fiber length C: Light speed T: Period of digital phase ramp Φ _R : Maximum phase shift of digital phase ramp (flyback amount, Φ _R = 2π) . On the other hand, the Sagnac phase difference ΔΦ _s is represented by ΔΦ _s = 8πAΩ / Cλ (9) where A: total area surrounded by the optical fiber λ: light source wavelength Ω: input angular velocity Is done.

From the equations (7) to (9), f = 1 / T = 4AΩ / nLλ (10) = 2RΩ / nL (for a circular coil having a radius R) (11) The input angular velocity Ω can be known by measuring the output frequency of the digital phase lamp.

FIG. 5 shows a digital phase ramp generating circuit.
FIG. 1 illustrates a conventional example (hereinafter, referred to as DPR74).
It is. 6 to 10 show signal patterns of DPR74.
FIG. The output of the first adder 741 of the DPR 74
The force S is equal to the reference value + D of the first reference source 743. _RIs equal to or
Otherwise, the first switch 745 closes and the second
Of the second reference source 744 by the adder 742 of
_RIs added to the output of the first adder 741. as a result,
The output S of the second adder 742 is
A reference value -D of the second reference source 744 is input to the input D3._RAnd add
(D_Three-D_R), And the plus shown in the first half of FIG.
A stepped ramp waveform in the direction is generated.

On the other hand, the output S of the first adder 741
If equal to or smaller the reference value -D _R of the reference source 744, a second adder 7 to the second switch 746 is closed
By 42 adds the reference value + D _R of the first reference source to the output of the first adder 741. As a result, the second adder 74
Second output S is the sum of the reference value + D _R of the first reference source 743 to the input D3 of the first adder 741 (D ₃ + D _R)
Thus, a stepwise ramp waveform in the minus direction shown in the second half of FIG. 6 is generated.

Here, as shown in FIG.
Is added to the input of the DPR 74 every τ time, and the reference value of the first reference source 743 or the second reference source 7
When it is greater than or equal to the absolute value of the reference value of 44, it flies back to form a continuous digital phase ramp. And the output of the optical interference gyro is at the time of flyback of the digital phase lamp,
The output of the positive pulse train of the first comparator 747 when the output of the first adder 741 is equal to the reference value of the first reference source or the reference value of the second reference source, or has increased as an absolute value. It is generated as the output of the optical interference gyro and
Is output as the output of the optical interference gyro. These pulse trains appear at the P pulse terminal and the negative pulse terminal according to the magnitude and polarity of the input angular velocity.

FIG. 6 shows the DPR 74 when + D _R / 4 and -D _R / 4 are applied as the input D ₃ of the DPR 74 of FIG.
2 shows an output waveform of the optical interference gyro and an output pulse train. In this case, the P-pulse terminal or the N-pulse terminal of FIG. 2 appears corresponding to the polarity of the DPR waveform, and these pulse intervals appear every 4τ hours. The value of more than the reference value D _R,
The maximum phase shift of light is 2mπ (m = 1, 2, 3,...)
• Data corresponding to the value of ()) is set. Normally, data corresponding to 2π (rad) or 4π (rad) is set as the phase shift of light.

FIG. 7 shows the input D of the DPR 74 in FIG.
_ThreeTo D_Three= + D_R/ 2 and + D _RDPR when
74 output waveform D4 and output of P-pulse terminal of gyro
Is shown. The output of the N-pulse terminal is not shown.
No. D_Three= + D_R/ 2, flyback every 2τ hours
And D_Three= + D_RFlyer every τ hours
A lock has occurred.

[0017] Since the update data DPR74 shown in Figure 5 is performed for each τ time, a maximum value of the input D ₃ = + D input condition of _R is the output waveform D4 of DPR74 flyback. Naturally, the output pulse train of the optical interference gyro also shows the maximum value. FIG. 8 shows that the input D ₃ of the DPR 74 of FIG.
The case than _R of D _R / 4 by the excess + 5D _R / 4, the DPR74 output waveform when followed by the input D ₃ + 5D decreased from _R / 4 to + D _R / 4 will be described. Flyback occurs every τ hours and the output waveform DPR74
4 is + D unless the logic circuit 7 is saturated and inverted.
It increases at a step height of _R / 4. On the way, at a point indicated by P, the input D ₃ is changed from + 5D _R / 4 to + D _R /
Lowering the 4, the output waveform of DPR74 is and for some time during the generated unwanted pulse trains indicated by reference numeral Q This gyro output error to the output of DPR74 immediately after switching back to the above D _R However, a pulse train as shown in the first half of FIG. 6 is generated.

FIG. 9 shows the same DPR as the range up to point P in FIG.
9 shows an input condition D3 and a DPR output waveform D4 corresponding to the input condition D3 when the MSB value of the logic circuit 7 is assumed to be infinite. That is, the output waveform D4 of the DPR 74
Increases infinitely and the output pulse train shows a maximum value. FIG. 10 is a diagram illustrating an output waveform D4 when the MSB value and the LSB value of the logic circuit 7 are finite. That is, the maximum value of the logic circuit 7 is not less + 2D _R, the minimum value of the logic circuit 7 is -2 D _R.

[0019] Incidentally, Table 1 describes an example of a code format of the logic circuit 7, and is used properly depending on the application. In any case, when the data value exceeds the MSB value or falls below the LSB value, the output of the logic circuit 7 is inverted. Accordingly, in DPR74 shown in FIG. 5, the period f ₁ output S in FIG. 10 of the first adder 741 is a sum of the input D ₃ of the output D ₄ of the latch circuit 749 is the output of DPR74 DPR74 ~ in f ₇ is a MSB value + exceeds 2D _R. As a result, the logic circuit 7
The output D ₄ of the latch circuit 749 is the output is inverted to the other values as shown in FIG. The output P-pulse and N-pulse of the optical interference gyro at this time are as shown in the figure, and the difference between the P-pulse and the N-pulse is every 4τ, the same as the output of the optical interference gyro shown in FIG. One P-pulse is obtained.

[0020] This means that, MSB value + D _R or LSB
The output of the optical interference gyro when the same input conditions as values -D _R represents a maximum value as an absolute value, the output of the optical interference gyro Increasing than this indicates that decreasing. FIG. 11 shows the relationship between the input angular velocity and the output of the optical interference gyro in this case.

[0021]

As described above, when the output of the conventional optical interference gyro is input exceeding the maximum input angular velocity, the output thereafter decreases and becomes twice as large as the maximum input angular velocity. The output becomes zero at the angular velocity. The maximum input angular velocity Ωmax of the optical interference gyro is usually expressed by the following equation.

Ωmax = 2mπ / K _S (m = 1, 2, 3,...) (1) K _S : Sagnac coefficient Here, the Sagnac coefficient K _S is the detection sensitivity of the optical interference gyro. However, if an attempt is made to improve the accuracy by increasing the value, it is not possible to design a large Ωmax, and the measurement range is reduced. Then, when the output of the optical interference gyro is input exceeding the maximum input angular velocity, the output decreases thereafter, that is, the output decreases despite the increase of the input, which is inherently a measuring instrument. It is not suitable for.

The present invention solves the above-mentioned problem that the integrator of the logic circuit is constituted by a cumulative adder, and the maximum output is maintained without decreasing the output signal even when the input angular velocity exceeds the maximum input angular velocity. An object of the present invention is to provide an optical interference gyro which has been eliminated.

[0024]

Means for Solving the Problems Claim 1 comprises a light source 1, a directional coupler 2 for receiving light from the light source 1, and a directional coupler 2 for receiving light via the directional coupler 2. A branching device 3 for branching is provided, and phase modulators 31 and 32 driven by a phase modulation signal and a feedback signal are provided at one or both branch ends of the branching device 3.
A directional coupler 2 having an optical fiber coil 4 having one end and the other end on which the split light is incident;
And a light receiver 5 for converting the light intensity of the interference light of the right-handed light and the left-handed light of the optical fiber coil 4 in the branching device 3 into an electric signal. The circuit 7 includes a synchronous detector 72 for synchronously detecting an electric signal detected by the light receiver 5, an integrator 73 for filtering an angular velocity signal output from the synchronous detector 72, and a digital signal for generating a feedback phase signal and an optical interference angular velocity meter output. A closed-loop optical interference gyro which comprises a phase ramp generating circuit 74 and further includes a phase modulation driving circuit 8 for generating a phase modulation signal, and always controls the phase difference of light at both ends of the optical fiber coil 4 to zero. The integrator 73 is a closed-loop optical interference gyro consisting of a cumulative adder that does not perform cumulative addition above a predetermined value set for addition in the positive or negative direction. Configuration was.

Claim 2: In the closed-loop optical interference gyro according to claim 1, the accumulator 76 has a first input terminal B to which the angular velocity signal output from the synchronous detector 72 is input. An adder 761 having
A latch circuit 762 having an input terminal connected to the output terminal S of the adder 761, and a latch switch 76 connected to an update clock input terminal of the latch circuit 762;
3 and the output terminal S of the latch circuit 762 is an adder 7
61 comprising a first integrator reference source 764 and a second integrator reference source 765 connected to a second input terminal A of
A first integrator comparator 766 having a first input terminal B connected to the integrator reference source 764 and a second input terminal A connected to the output terminal S of the adder 761; Input terminal B connected to the comparator reference source 765 and second input terminal A connected to the output terminal S of the adder 761
And a logical sum circuit 768 for calculating the logical sum of the outputs of the first integrator comparator 766 and the second integrator comparator 767. connect the output end to the switching terminal L of the latch switch 763, the state output of the adder 761 is large as or absolute value becomes equal to the reference value + D _R of the first integrator reference source 764, or the second are those which do not cumulatively added by switching the latch switch by the logic values from the oR circuit 768 in the state is larger as the reference value -D _R becomes equal to or absolute value of the integrator reference source 765,
A closed-loop optical interference gyro was constructed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining a cumulative adder constituting a main part of the present invention. FIG. 2 is a diagram illustrating the entire optical interference gyro. The synchronous detection circuit 72 of the logic circuit 7 detects the angular velocity signal D2 by demodulating the digital photoelectric conversion signal D1 obtained by AD-converting the photoelectric conversion signal obtained by the light receiver 5. The angular velocity signal D ₂ detected by the synchronous detection circuit 72 is added to the adder 7 of the accumulator 76.
The data D ₃ is input to the B input terminal 61 and is added to the data D ₃ latched in the latch circuit 762 by τ time ago in this adder. This addition output of the adder 761 is latched by the latch circuit 762 with the update clock after the next τ time.

In the logic circuit 7 according to the embodiment of the present invention, the value of the output D ₃ of the accumulator 76, which is the input of the DPR 74, is set to the reference value of the first integrator reference source 764 + D _R or the second integration. control without exceeding the value of the reference value -D _R vessels reference source 765 in absolute value. That is, first, the output of the adder 761, while being compared with the reference value + D _R to the output of the first integrator reference source 764 in the first integrator comparator 766, the second integrator comparator 767 It is compared with a reference value -D _R to the output of the second integrator reference source 765.

[0028] Here, if the output of the adder 761 becomes larger as or absolute value becomes equal to the reference value + D _R of the first integrator reference source 764, or the second integrator reference source 7
The OR circuit 768 outputs a logical value 1 to the output terminal S when it becomes equal to the reference value −D _{R of} 65 or as an absolute value. The output of the logical value 1 at the output terminal S of the OR circuit 768 is supplied to the latch switch 763, and this switch is opened. Since the update clock is not applied to the latch circuit 762 by releasing the latch switch 763, the output of the adder 761 is not updated and the previous value is held as it is. This state is a reference value -D _R of the reference value + D _R second integrator reference source 765 of the output of the adder 761 is first integrator reference source 764
It continues until both values fall below the absolute value.

In the above description, the logic circuit 7 includes the synchronous detection circuit 72 and the DPR 74 in addition to the integrator 73. However, the circuit portion to be configured as the logic circuit includes the integrator 73 and the DPR 74. It can be. In this case, the synchronous detection circuit 72 is configured as an analog circuit, and
And an AD converter 6. The circuit section to be configured as a logic circuit uses this as an integrator 73
It can only be. In this case, the DPR 74 is also configured as an analog circuit, and is connected to a stage subsequent to the DA converter 9.

In summary, the output D ₃ of the accumulator 76, that is, the input of the DPR 74, becomes saturated when the input angular velocity exceeds the maximum input angular velocity, and becomes an output proportional to the input angular velocity when the input angular velocity falls below the maximum input angular velocity. .

[0031]

Be as above, according to the present invention, the invention is a large as the reference value + D _R becomes equal to or absolute value of the integrator reference source 764 outputs the first adder 761 of accumulator 76 one state, or a second integrator reference source in the state is larger as the reference value -D _R become equal or the absolute value of 765, the output D ₃ of the cumulative adder 76, i.e. DPR
By providing a configuration in which the input of 74 is saturated, even when exceeding the maximum input angular velocity, the output pulse train of the optical interference gyro has an effect of maintaining the saturated state without decreasing, and the force angular velocity input is The inconvenience of the prior art, which is inherently undesirable as a measuring instrument in which the output pulse train decreases despite the increase, can be solved.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment.

FIG. 2 illustrates an optical interference gyro.

FIG. 3 is a view for explaining rectangular wave phase modulation and interference light output.

FIG. 4 is a view for explaining a relationship among a rectangular wave phase modulation signal, a feedback signal, and a feedback phase difference.

FIG. 5 is a diagram illustrating a digital phase ramp generation circuit.

FIG. 6 is a diagram illustrating input / output waveforms of a digital phase ramp generation circuit.

FIG. 7 is a diagram illustrating another input / output waveform of the digital phase ramp generation circuit.

FIG. 8 is a diagram illustrating still another input / output waveform of the digital phase ramp generation circuit.

FIG. 9 is a view for explaining input / output waveforms of the digital phase ramp generation circuit when the MSB is infinite.

FIG. 10 is a diagram illustrating input / output waveforms of a digital phase ramp generation circuit when the MSB is finite.

FIG. 11 is a diagram showing a relationship between an input angular velocity and a pulse output in a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 light source 2 directional coupler 3 splitter 31 phase modulator 32 phase modulator 4 optical fiber coil 5 optical receiver 6 AD converter 7 logic circuit 72 synchronous detection circuit 73 integrator 74 digital phase ramp generation circuit 741 first adder 742 second adder 743 first reference source 744 second reference source 745 first switch 746 second switch 747 first comparator 748 second comparator 749 latch circuit 76 accumulator 761 adder 762 Latch circuit 763 Latch switch 764 First integrator reference source 765 Second integrator reference source 766 First integrator comparator 767 Second integrator comparator 768 OR circuit 8 Phase modulation drive circuit 9 DA converter

Claims (2)

[Claims] 1. A light source, comprising: a directional coupler for receiving light from the light source; and a splitter for splitting light incident via the directional coupler into two, and one of the splitters. Alternatively, both branch ends have a phase modulator driven by a phase modulation signal and a feedback signal,
An optical fiber coil having one end and the other end on which the split light is incident is provided. The optical fiber coil is coupled to a directional coupler to cause interference between right-handed light and left-handed light of the optical fiber coil in the splitter. It has a light receiver for converting the light intensity of light into an electric signal, and a circuit for processing the electric signal output from the light receiver is a synchronous detector for synchronously detecting the electric signal detected by the light receiver and outputting from the synchronous detector. The optical fiber coil includes an integrator for filtering an angular velocity signal, a digital phase ramp generating circuit for generating a feedback phase signal and an optical interference gyro output, and a phase modulation driving circuit for generating a phase modulation signal. In a closed-loop optical interference gyro that constantly controls the phase difference of light at zero to zero, the integrator accumulates more than a predetermined value set for addition in the positive or negative direction. A closed-loop optical interference gyro characterized by a cumulative adder without product addition. 2. The closed loop optical interference angular velocity meter according to claim 1, wherein the accumulator includes an adder having a first input terminal to which an angular velocity signal output from the synchronous detector is input, A latch circuit having an input terminal connected to an output terminal of the adder; a latch switch connected to an update clock input terminal of the latch circuit; an output terminal of the latch circuit connected to a second input terminal of the adder And a first input terminal connected to the first integrator reference source and a second input terminal connected to the output terminal of the adder, comprising a first integrator reference source and a second integrator reference source. The first with
A second input terminal connected to the second integrator reference source and a second input terminal connected to the output terminal of the adder.
And a logical sum circuit for calculating the logical sum of the outputs of the first and second integrator comparators. The output terminal of the logical sum circuit is a switching terminal of a latch switch. The output of the adder is equal to the reference value of the first integrator reference source or is large in absolute value, or is equal to the reference value of the second integrator reference source or the absolute value The closed loop optical interference gyro, wherein the latch switch is switched by a logical value from the OR circuit and the cumulative addition is not performed in a large state.