WO2013023392A1 - 一种液晶面板驱动电路和使用该电路的液晶显示装置 - Google Patents

一种液晶面板驱动电路和使用该电路的液晶显示装置 Download PDF

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Publication number
WO2013023392A1
WO2013023392A1 PCT/CN2011/079350 CN2011079350W WO2013023392A1 WO 2013023392 A1 WO2013023392 A1 WO 2013023392A1 CN 2011079350 W CN2011079350 W CN 2011079350W WO 2013023392 A1 WO2013023392 A1 WO 2013023392A1
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WIPO (PCT)
Prior art keywords
liquid crystal
circuit
crystal panel
panel driving
driving circuit
Prior art date
Application number
PCT/CN2011/079350
Other languages
English (en)
French (fr)
Inventor
林柏伸
谭小平
张裕桦
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/263,897 priority Critical patent/US20130044085A1/en
Publication of WO2013023392A1 publication Critical patent/WO2013023392A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a liquid crystal panel driving circuit and a liquid crystal display device using the same.
  • chamfering circuits are widely used to reduce feed-through and line distortion.
  • a common liquid crystal driving circuit with a chamfering circuit including a data driving circuit and a scan driving line chamfering control circuit uses three MOSFETs as a switching component (field effect transistor).
  • the timing control circuit 2 controls the off signal timing off signal GV0FF high level
  • the switch PQ8 is turned on, and the DC module 1 generates a DC power source VGHP output for driving the thin film transistor (TFT) gate to the scan driver.
  • TFT thin film transistor
  • the prior art must use a plurality of large-sized resistors in parallel, and a large-area heat sink member is laid on the bottom of the resistor so that the heat energy is evenly dispersed without causing the resistor. burn.
  • this method will cause the temperature of the region to be high due to the tight arrangement of these resistors, which affects the performance and service life of the driving circuit.
  • the technical problem to be solved by the present invention is to provide a liquid crystal panel driving circuit having good heat dissipation performance and a liquid crystal display device using the same.
  • a liquid crystal panel driving circuit comprising a plurality of scanning chips, wherein the liquid crystal panel driving circuit further comprises a plurality of discharge resistors for load scanning chips corresponding to the respective scanning chips.
  • the discharge resistor is located between the input of the scan chip and ground.
  • the output end of the scan chip is formed with a parasitic capacitance.
  • the discharge resistor is a variable resistor with adjustable resistance. Since the parasitic capacitance of each open scan chip branch is different, only the slope of the turn-on voltage VGH matches the corresponding DC parasitic capacitance to achieve the best adjustment effect, and by adjusting the resistance of each branch discharge resistor, It is more convenient to adjust the slope of the branch opening voltage VGH, which is also beneficial to improve versatility.
  • variable resistor is a digitally controlled variable resistor
  • the liquid crystal panel driving circuit further includes a digital controller for controlling a digitally controlled variable resistance value change.
  • the digital control variable resistor can easily control the resistance value of the variable resistor through the digital signal, realize the automatic adjustment of the resistance value of the discharge resistor, and improve the intelligent level of the circuit.
  • the liquid crystal panel driving circuit further includes a digital memory connected to the digital controller, and the digital controller stores the received serial data and the serial clock signal in a digital memory, and stores the data according to the data.
  • the information in the digital memory adjusts the resistance of the digitally controlled variable resistor. This is a specific control method for digitally controlling the variable resistor using a digital memory.
  • each of the discharge resistors is integrated into its corresponding scan chip.
  • This scheme can improve the degree of circuit integration.
  • the calculated value is closest to the actual value, and the calculated value is closest to the actual value.
  • the calculation of the parasitic capacitance is related to the adjustment of the discharge resistance, which in turn affects the chamfer slope of the turn-on voltage VGH. The closer the parasitic capacitance is calculated to the actual value, the better the adjustment effect of the turn-on voltage VGH.
  • the liquid crystal panel driving circuit includes a DC module for providing power of the scanning chip, the liquid crystal panel driving circuit further includes a timing control circuit, a first switching circuit and a second switching circuit, and the first switching circuit Located between the output end of the DC module and the scan chip; the second switch circuit is located between the discharge resistor and the ground; the control end of the first switch circuit and the second switch circuit and the timing Control circuit coupling.
  • This is a specific form of the chamfering circuit in accordance with the present invention.
  • the discrete switching circuit is used to realize the function of the chamfering circuit, which can reduce the cost.
  • the structure design is clean, the number of components used is small, the occupied area of the PCB board is reduced, and the circuit operation reliability is high.
  • each of the second switching circuits is integrated into its corresponding scanning chip. It can improve circuit integration while cooling the wiring.
  • a voltage stabilizing circuit is further connected in series between the discharge resistor and the second switch circuit, and one end of the voltage stabilizing circuit is connected to the discharge resistor, and the other end is grounded through the second switch circuit.
  • the voltage regulator circuit can stabilize the voltage of VGH during discharge to ensure that the turn-on voltage VGH has sufficient voltage to drive the thin film transistor (TFT).
  • a liquid crystal display device comprising the above liquid crystal panel driving circuit.
  • the load resistance group of the turn-on voltage VGH is dispersed into a plurality of discharge resistors, the number of discharge resistors is matched with the number of the scan chips in cooperation with the respective scan chips, so that each discharge resistor only needs to be responsible for the load of the scan chip.
  • the discharge energy of each discharge resistor can be reduced, so it is not easy to generate overheating problems.
  • the discharge resistance can be dispersed in various positions, the layout of the drive circuit can be more flexible, and the dispersion of the discharge resistor can also make the heat dissipation uniform, avoiding local parts. The temperature is too high and affects the performance and service life of the circuit.
  • FIG. 1 is a block diagram of the prior art
  • FIG. 3 is a schematic block diagram of the present invention.
  • FIG. 4 is a block diagram of a liquid crystal panel using the present invention.
  • FIG. 5 is a schematic block diagram of a grounding circuit of a discharge resistor with a voltage stabilizing circuit according to the present invention
  • FIG. 6 is a schematic block diagram of the ground loop of the discharge resistor of the present invention integrated into the scan chip;
  • FIG. 7 is a schematic block diagram of the resistance value of the digital mode control resistor of the present invention.
  • the liquid crystal panel driving circuit in this embodiment includes a DC module 1 and a scan driving circuit 4 connected to the output end of the DC module 1.
  • the scan driving circuit 4 includes a plurality of scanning chips 7
  • the output terminals of the DC module 1 are respectively connected to each of the scanning chips 7 to form a plurality of branches, and the liquid crystal panel driving circuit further includes a plurality of discharge resistors for the load scanning chips corresponding to the respective scanning chips.
  • the discharge resistor is located between the input of the scan chip and ground.
  • the present invention may further include a first switching circuit 5 located between the output end of the DC module 1 and the scanning chip 7, and a second switching circuit 5 located between the discharge resistor 3 and the ground. between.
  • a timing control circuit 2 is generally included, and the timing control circuit 2 periodically alternately generates the on signal GVON and the off signal GVOFF according to the transmitted image frame signal.
  • the first switching circuit 5 When the closing signal GVOFF signal of the timing control circuit 2 is at a high level, the first switching circuit 5 is turned on, The second switch circuit 6 is closed, at which time the turn-on voltage VGH outputted by the first switch circuit 5 is equal to the DC power source VGHP; when the timing turn-on signal GVON signal of the timing control circuit 2 is at a high level, the first switch circuit 5 is turned off, the second switch The circuit 6 is turned on, at which time the turn-on voltage VGH is discharged to the ground through the discharge resistor 3, and the voltage is gradually pulled down to form a chamfering waveform.
  • the scan chip 7 loads the turn-on voltage VGH into the scan line for driving a thin film transistor (TFT).
  • TFT thin film transistor
  • the second switch circuit 6 can adopt components such as a relay, a triode, a field effect transistor, etc., which can realize conduction and shutdown control.
  • the present invention uses a field effect transistor as a second switch (hereinafter referred to as a switch QP) as an example.
  • the source of the switch QP is connected to the discharge resistor 3, the drain is grounded, and the gate is connected to the timing turn-on signal GVON signal of the timing control circuit 2.
  • the timing turn-on signal GVON When the timing turn-on signal GVON is high, the timing off signal GVOFF signal is low, At this time, the first switch circuit 5 is turned off, the switch QP is turned on, the turn-on voltage VGH is discharged through the discharge resistor 3, and the voltage is gradually decreased; when the timing turn-off signal GVOFF signal of the timing control circuit 2 is at a high level, the timing turn-on signal GVON signal is Low level, at this time, the first switch circuit 5 is turned on, the switch QP is turned off, the turn-on voltage VGH is stopped, and the voltage of the DC power source VGHP is restored.
  • the turn-on voltage VGH forms a chamfer wave as shown in FIG.
  • the number of discharge resistors is the same as that of the scanning chip 7.
  • Each of the discharge resistors 3 is responsible for the opening voltage VGH of the 7 branches of the corresponding scanning chip, and the heat generation of the single discharge resistor 3 is remarkably reduced, and the overall heat dissipation performance is improved.
  • the grounding circuit of the discharge resistor 3 can also add a voltage stabilizing circuit for limiting the turn-off voltage of the turn-on voltage VGH at the time of discharge.
  • the cathode of the Zener diode DP is connected to the discharge resistor 3
  • the anode of the Zener diode DP is connected to the source of the switch QP, and when the switch PQ is turned on, the anode of the Zener diode DP is connected. Grounding to achieve normal access to the voltage regulator circuit.
  • the reverse breakdown voltage of the Zener diode DP should be selected according to the magnitude of the driving voltage required by the thin film transistor to ensure that the minimum discharge voltage of the VGH can drive the thin film transistor.
  • the discharge resistor 3 is an adjustable resistor. Since the lengths of the open voltage VGH branch paths connected to the scan chip 7 and the routing methods are not uniform, the impedance and the capacitive reactance generated by the respective branches are also different, especially as the screen size increases and the update frequency When accelerating, the difference between the impedance and the capacitive reactance of each branch is more prominent. This requires adjusting the chamfer slope of the turn-on voltage VGH to match the parasitic capacitance of the corresponding branch to obtain the ideal chamfer waveform. By changing the resistance of the discharge resistor 3, the slope of the turn-on voltage VGH can be changed. The slope of the turn-on voltage VGH can be changed by changing the resistance of the discharge resistor 3. As shown in FIG.
  • the discharge resistor 3 is digitally controlled.
  • the variable resistor is controlled as an example to illustrate: the control circuit includes a digital controller 9, and the digital controller 9 receives the serial data (SDA) and the serial clock (SCL) signal of the main control chip by using I 2 C communication. And storing the signal in the digital memory 10, the digital control variable resistor has a plurality of parallel resistors therein, each set of resistors is connected in series with a control switch, and the control end of the digital control variable resistor is connected to the digital controller
  • the discharge resistor 3 can be integrated into the scan chip 7. If the discharge resistor 3 is an adjustable resistor, the resistance of the discharge resistor 3 can be adjusted according to the parasitic capacitance of the branch in use, which expands the application range of the scan chip 7; in addition, the discharge resistor 3 is integrated into the scan chip 7, two The distance between the two is closest, and the calculated parasitic capacitance of the branch is closest to the actual value, so the adjustment effect is the best. Similarly, the voltage stabilizing circuit and the second switching circuit 6 can be integrated into the scanning chip 7, which can further improve the integration of the circuit, thereby further saving development and production time.
  • the load resistor group 8 of the turn-on voltage VGH is dispersed into a plurality of discharge resistors, and the respective scan chips are matched, the number of discharge resistors is the same as the number of the scan chips, so that each discharge resistor only needs to be responsible for the load of the scan chip.
  • the discharge energy of each discharge resistor can be reduced, so it is not easy to generate overheating problem; in addition, the discharge resistor can be dispersed in various positions, the layout of the drive circuit can be more flexible, and the dispersion of the discharge resistor can also make the heat dissipation uniform, avoiding The local temperature is too high and affects the performance and service life of the circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶面板驱动电路和使用该电路的液晶显示装置，多个扫描芯片(7)及与各扫描芯片(7)一一对应的多个放电电阻(3)，所述放电电阻(3)用于负载对应的扫描芯片和扫描驱动的扫描线。由于将切角电路的负荷电阻群分散为多个与每个扫描芯片(7)配合的放电电阻(3)，这样每个放电电阻(3)只需要负责所在扫描芯片的负荷，放电能量将会降低，不容易产生过热问题；另外，放电电阻(3)可以分散在各个位置，驱动电路的布局可以有更灵活的选择，放电电阻(3)的分散也可以使散热均匀，避免局部温度过高而影响电路的性能。

Description

一种液晶面板驱动电路和使用该电路的液晶显示装置
【技术领域】
本发明涉及液晶显示领域， 更具体的说， 涉及一种液晶面板驱动电路和使 用该电路的液晶显示装置。
【背景技术】
在 LCD 的驱动架构中， 广泛应用切角电路来降低馈通电压效应 ( Feed-through )和行失真（ Line distortion )。 如图 1所示为一种常见的带有切角 电路的液晶驱动电路， 所述液晶驱动电路包括数据驱动线路和扫描驱动线路切 角控制电路用了三个作为开关组件的 M0SFET (场效应管）， 在时序控制电路 2 控制关信号时序关闭信号 GV0FF高电平的时候， 开关 PQ8导通， 直流模块 1 产生用于驱动薄膜晶体管（TFT )门极（Gate )的直流电源 VGHP输出到扫描驱 动电路 4中； 当时序控制电路 2中的导通信号 GVON高电平的时候， QP7 B通 道的开关导通， 开启电压 VGH通过负荷电阻群 8 ( RP43、 RP44 )接地放电， 电 压拉低， 形成切角波， 整个电路的波形参见图 2。 由于负荷电阻群 8在导通信号 GVON导通期间需要 受所有电流， 如此一来， 负荷电阻群 8的温度会因为负 载端有许多的电荷而逐渐上升， 在更新频率加快的情况下， 如果散热不及时， 又会造成加乘效应， 温度进一步上升， 因此现有技术必须选用多颗大尺寸电阻 并联， 并在电阻底部铺设大面积的散热器件， 以便热能平均分散开来， 而不至 使电阻烧毁。 然而此方式会因为这些电阻排列紧密， 仍然使该区域的温度偏高， 影响驱动电路的性能和使用寿命。
【发明内容】
本发明所要解决的技术问题是提供一种具有良好散热性能的液晶面板驱 动电路以及使用该电路的液晶显示装置。
本发明的目的是通过以下技术方案来实现的： 一种液晶面板驱动电路， 包括多个扫描芯片， 其特征在于所述液晶面板驱 动电路还包括与各扫描芯片——对应的多个用于负载扫描芯片的放电电阻。 所 述放电电阻位于扫描芯片的输入端和地之间。
优选的， 所述扫描芯片输出端形成有寄生电容。
优选的， 所述放电电阻为阻值可调的可变电阻。 由于每条开扫描芯片支路 的寄生电容都不同， 只有开启电压 VGH的斜率跟相应直流的寄生电容相匹配， 才能达到最佳的调节效果， 而通过调节各支路放电电阻的阻值， 可以更方便地 调整所在支路开启电压 VGH的斜率， 也有利于提高通用性。
优选的， 所述可变电阻为数位控制可变电阻， 所述的液晶面板驱动电路还 包括用于控制数位控制可变电阻阻值变化的数位控制器。 数位控制可变电阻可 以方便地通过数字信号控制可变电阻的阻值， 实现放电电阻阻值的自动调节， 提高电路的智能化水平。
优选的， 所述液晶面板驱动电路还包括与所述数位控制器连接的数位存储 器， 所述数位控制器将接收到的串行资料及串行时脉信号存储到数位存储器中， 并跟据存储到数位存储器中的信息调整所述数位控制可变电阻的阻值。 此为利 用数位存储器进行数位控制可变电阻的具体控制方式。
优选的， 所述每个放电电阻集成到其对应的扫描芯片当中。 此方案可以提 高电路集成度， 另外， 当需要计算开启电压 VGH在该支路的寄生电容时， 由于 放电电阻集成化到扫描芯片中， 离扫描芯片最近， 该处计算值最接近实际值， 而寄生电容的计算之间关系到放电电阻的调节，进而影响到开启电压 VGH的切 角斜率， 寄生电容的计算越接近实际值， 开启电压 VGH的调节效果越好。
优选的， 所述液晶面板驱动电路包括用于提供所述扫描芯片电源的直流模 块， 所述液晶面板驱动电路还包括时序控制电路、 第一开关电路和第二开关电 路， 所述第一开关电路位于所述直流模块的输出端与所述扫描芯片之间； 所述 第二开关电路位于所述放电电阻和地之间； 所述第一开关电路和第二开关电路 的控制端与所述时序控制电路耦合。 这是配合本发明的切角电路的一种具体形 式， 采用分散的开关电路来实现切角电路功能， 可以降低成本； 而且结构设计 筒洁， 使用元器件的数量少， 减少 PCB板的占用面积， 电路运行可靠度高。
优选的， 所述每个第二开关电路集成到其对应的扫描芯片当中。 可以提高 电路集成度， 同时可以筒化布线。
优选的， 所述放电电阻与所述第二开关电路之间还串接有稳压电路， 所述 稳压电路的一端连接放电电阻， 另外一端通过所述第二开关电路接地。 稳压电 路可以稳定开启电压 VGH在放电过程中的电压， 以确保开启电压 VGH有足够 的电压驱动薄膜晶体管 （TFT )。
一种液晶显示装置， 其特征在于， 所述的液晶显示装置包括有上述液晶面 板驱动电路。
本发明由于将开启电压 VGH的负荷电阻群分散为多个放电电阻， 与各个 扫描芯片配合， 放电电阻数量与所述扫描芯片数量一致， 这样每个放电电阻的 只需要负责所在扫描芯片的负荷， 每个放电电阻的放电能量可以降低， 因此不 容易产生过热问题； 另外， 放电电阻可以分散在各个位置， 驱动电路的布局可 以有更灵活的选择， 放电电阻的分散也可以使散热均匀， 避免局部温度过高而 影响电路的性能和使用寿命。
【附图说明】
图 1是现有技术原理框图；
图 2是控制信号的波形图；
图 3是本发明的原理框图；
图 4是采用本发明的液晶面板框图；
图 5是本发明带有稳压电路的放电电阻接地回路原理框图；
图 6是本发明放电电阻的接地回路集成到扫描芯片中的原理框图； 图 7是本发明数位方式控制电阻的阻值的原理框图。
附图标示说明： 1、 直流模块； 2、 时序控制电路； 3、 放电电阻； 4、 扫描驱动电路； 5、 第一开关电路； 6、 第二开关电路； 7、 扫描芯片； 8、 负荷电阻群； 9、 数位控 制器； 10、 数位存储器。
【具体实施方式】
下面结合附图和较佳的实施例对本发明作进一步说明。
如图 3、 4所示， 本实施例中的液晶面板驱动电路， 包括直流模块 1 , 与直流 模块 1输出端连接的扫描驱动电路 4,所述扫描驱动电路 4包括多个扫描芯片 7, 所述直流模块 1输出端分别与每个扫描芯片 7—一连接， 形成多条支路， 所述 液晶面板驱动电路还包括与各扫描芯片——对应的多个用于负载扫描芯片的放 电电阻。 所述放电电阻位于扫描芯片的输入端和地之间。 本发明还可以包括第 一开关电路 5和第二开关电路 6,第一开关电路 5位于所述直流模块 1的输出端 和扫描芯片 7之间， 所述第二开关电路位于放电电阻 3和地之间。
在液晶显示驱动电路中， 一般都包括一个时序控制电路 2, 时序控制电路 2 根据传输过来的图像帧信号， 会周期性交替产生导通信号 GVON 和关闭信号 GVOFF。 本实施例中， 我们可以采用这两个信号来控制第一开关电路 5和第二 开关电路 6, 当时序控制电路 2的关闭信号 GVOFF信号为高电平时， 第一开关 电路 5导通， 第二开关电路 6闭合， 此时第一开关电路 5输出的开启电压 VGH 等于直流电源 VGHP; 当时序控制电路 2的时序导通信号 GVON信号为高电平 时， 第一开关电路 5关闭， 第二开关电路 6导通， 此时开启电压 VGH通过放电 电阻 3对地放电， 电压逐步拉低， 形成切角波形。 扫描芯片 7将开启电压 VGH 加载到扫描线中， 用于驱动薄膜晶体管 （TFT )。 所述第二开关电路 6可以采用 继电器、 三极管、 场效应管等可以实现导通、 关闭控制的元器件， 本发明采用 场效应管作为第二开关（以下筒称开关 QP ) 为例进行说明， 开关 QP的源极连 接所述放电电阻 3, 漏极接地，栅极连接时序控制电路 2的时序导通信号 GVON 信号。 当时序导通信号 GVON高电平时， 时序关闭信号 GVOFF信号为低电平， 此时， 第一开关电路 5关闭， 开关 QP导通， 开启电压 VGH通过放电电阻 3放 电， 电压逐步降低； 时序控制电路 2的时序关闭信号 GVOFF信号为高电平时， 时序导通信号 GVON信号为低电平， 此时， 第一开关电路 5导通， 开关 QP关 闭， 开启电压 VGH停止放电， 恢复为直流电源 VGHP的电压。 通过第一开关电 路 5和开关 QP的交替导通 /关闭， 开启电压 VGH形成如图 2所示的切角波。
放电电阻 3数跟扫描芯片 7数量一致， 每个放电电阻 3只负责相应扫描芯片 7支路的开启电压 VGH放电， 单个放电电阻 3的发热量显著减小， 整体散热性 能得到了提高。
进一步的， 如图 5所示， 放电电阻 3的接地回路还可以增加稳压电路， 用于 限制开启电压 VGH在放电时候的截止电压。 以稳压二极管 DP为例进行说明， 稳压管 DP的阴极连接所述放电电阻 3, 稳压管 DP的阳极连接到开关 QP的源 极， 开关 PQ导通时， 将稳压管 DP的阳极接地， 实现稳压电路的正常接入。 所 述稳压管 DP 的反向击穿电压应根据薄膜晶体管所要求的驱动电压幅值进行选 择， 以保证开启电 VGH最低放电电压能驱动薄膜晶体管。
进一步的， 如图 6所示， 所述放电电阻 3为可调电阻。 由于连接到扫描芯片 7的各条开启电压 VGH支路路径长短、 走线方式等并不一致， 因此各支路产生 的阻抗和容抗也不一样， 特别是随着画面尺寸加大， 以及更新频率加快的时候， 各支路的阻抗和容抗的差别更为突出，这就需要调整开启电压 VGH的切角斜率， 与相应支路的寄生电容相匹配， 才能得到理想的切角波形。 通过改变放电电阻 3 的阻值可以改变开启电压 VGH的切角斜率，可以通过改变放电电阻 3的阻值来 改变开启电压 VGH的切角斜率， 如图 7所示， 以放电电阻 3采用数位控制可变 电阻进行控制为例来说明： 该控制电路包括数位控制器 9, 数位控制器 9采用 I 2 C通信方式接受主控芯片的串行资料（SDA )及串行时脉（SCL )信号， 并将 信号存储到数位存储器 10中， 所述数位控制可变电阻里面有多组并联的电阻， 每组电阻串联一个控制开关， 数位控制可变电阻的控制端连接所述数位控制器
9, 通过接受数位控制器 9的数据来控制各个开关的分、 合， 设定投入使用的电 阻阻值， 进而调整所在支路开启电压 VGH的切角斜率。
为了筒化电路， 节省开发及生产时间， 放电电阻 3可以集成到扫描芯片 7当 中。 如果放电电阻 3是可调电阻， 还可以在使用时根据所在支路的寄生电容调 节放电电阻 3阻值， 拓展了扫描芯片 7的应用范围； 另外， 放电电阻 3集成到 扫描芯片 7 当中， 两者之间的距离最近， 计算出来的支路寄生电容最为接近实 际值， 因此调节效果最好。 同样的， 所述稳压电路和第二开关电路 6 同样可以 集成到扫描芯片 7 内部， 可以进一步提高电路的集成度， 有利于进一步节省开 发及生产时间。
本发明由于将开启电压 VGH的负荷电阻群 8分散为多个放电电阻， 与各个 扫描芯片配合， 放电电阻数量与所述扫描芯片数量一致， 这样每个放电电阻的 只需要负责所在扫描芯片的负荷， 每个放电电阻的放电能量可以降低， 因此不 容易产生过热问题； 另外， 放电电阻可以分散在各个位置， 驱动电路的布局可 以有更灵活的选择， 放电电阻的分散也可以使散热均匀， 避免局部温度过高而 影响电路的性能和使用寿命。 以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不能 认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通技 术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干筒单推演或替换， 都应当视为属于本发明的保护范围。

Claims

权利要求
1、 一种液晶面板驱动电路， 包括： 多个扫描芯片， 与各扫描芯片—— 对应的多个用于负载扫描芯片的放电电阻。
2、如权利要求 1所述的一种液晶面板驱动电路， 其特征在于所述扫描 芯片输出端形成有寄生电容。
3、如权利要求 2所述的一种液晶面板驱动电路， 其特征在于所述放电 电阻为阻值可调的可变电阻。
4、如权利要求 3所述的一种液晶面板驱动电路， 其特征在于所述可变 电阻为数位控制可变电阻， 所述的液晶面板驱动电路还包括用于控制数位 控制可变电阻阻值变化的数位控制器。
5、如权利要求 4所述的一种液晶面板驱动电路， 其特征在于所述液晶 面板驱动电路还包括与所述数位控制器连接的数位存储器， 所述数位控制 器将接收到的串行资料及串行时脉信号存储到数位存储器中， 并跟据存储 到数位存储器中的信息调整所述数位控制可变电阻的阻值。
6、如权利要求 2所述的一种液晶面板驱动电路， 其特征在于所述每个 放电电阻集成到其对应的扫描芯片当中。
7、如权利要求 1所述的一种液晶面板驱动电路， 其特征在于所述液晶 面板驱动电路包括用于提供所述扫描芯片电源的直流模块， 所述液晶面板 驱动电路还包括时序控制电路、 第一开关电路和第二开关电路， 所述第一 开关电路位于所述直流模块的输出端与所述扫描芯片之间； 所述第二开关 电路位于所述放电电阻和地之间； 所述第一开关电路和第二开关电路的控 制端与所述时序控制电路耦合。
8、如权利要求 7所述的一种液晶面板驱动电路， 其特征在于所述每个 第二开关电路集成到其对应的扫描芯片当中。
9、如权利要求 7所述的一种液晶面板驱动电路， 其特征在于所述放电 电阻与所述第二开关电路之间还串接有稳压电路， 所述稳压电路的一端连 接放电电阻， 另外一端通过所述第二开关电路接地。
10、 一种液晶显示装置， 包括： 液晶面板驱动电路； 所述液晶面板驱 动电路包括： 多个扫描芯片， 与各扫描芯片一一对应的多个用于负载扫描 芯片的放电电阻。
11、如权利要求 10所述的一种液晶显示装置， 其特征在于所述扫描芯 片输出端形成有寄生电容。
12、如权利要求 11所述的一种液晶显示装置， 其特征在于所述放电电 阻为阻值可调的可变电阻。
13、如权利要求 12所述的一种液晶显示装置， 其特征在于所述可变电 阻为数位控制可变电阻， 所述的液晶面板驱动电路还包括用于控制数位控 制可变电阻阻值变化的数位控制器。
14、如权利要求 13所述的一种液晶显示装置， 其特征在于所述液晶面 板驱动电路还包括与所述数位控制器连接的数位存储器， 所述数位控制器 将接收到的串行资料及串行时脉信号存储到数位存储器中， 并跟据存储到 数位存储器中的信息调整所述数位控制可变电阻的阻值。
15、如权利要求 11所述的一种液晶显示装置， 其特征在于所述每个放 电电阻集成到其对应的扫描芯片当中。
16、如权利要求 10所述的一种液晶显示装置， 其特征在于所述液晶面 板驱动电路包括用于提供所述扫描芯片电源的直流模块， 所述液晶面板驱 动电路还包括时序控制电路、 第一开关电路和第二开关电路， 所述第一开 关电路位于所述直流模块的输出端与所述扫描芯片之间； 所述第二开关电 路位于所述放电电阻和地之间； 所述第一开关电路和第二开关电路的控制 端与所述时序控制电路耦合。
17、如权利要求 16所述的一种液晶显示装置， 其特征在于所述每个第 二开关电路集成到其对应的扫描芯片当中。
18、如权利要求 16所述的一种液晶显示装置， 其特征在于所述放电电 阻与所述第二开关电路之间还串接有稳压电路， 所述稳压电路的一端连接 放电电阻， 另外一端通过所述第二开关电路接地。
PCT/CN2011/079350 2011-08-16 2011-09-05 一种液晶面板驱动电路和使用该电路的液晶显示装置 WO2013023392A1 (zh)

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