WO2013021582A1

WO2013021582A1 - Display drive circuit and display device provided with same

Info

Publication number: WO2013021582A1
Application number: PCT/JP2012/004873
Authority: WO
Inventors: 英司廣田
Original assignee: シャープ株式会社
Priority date: 2011-08-05
Filing date: 2012-07-31
Publication date: 2013-02-14

Abstract

This display drive circuit is provided with: a memory unit that stores regular pulse intervals for control signals (LS (0) - LS (k)) corresponding to specifications for a display device; a timing comparison unit that compares the pulse intervals among the control signals (LS (0) - LS (k)) that have been input and the pulse intervals stored in the memory and detects offsets in the pulse timing for the control signals (LS (0) - LS (k)); a regular signal generating unit that generates regular control signals (LS (0)' - LS (k)'); and a signal substitution unit that substitutes the regular control signals (LS (0)' - LS (k)') generated by the regular signal generating unit for the control signals (LS (0) - LS (k)) for which an offset in the pulse timing has been detected by the timing comparison unit.

Description

Display drive circuit and display device including the same

The present invention relates to a display drive circuit and a display device including the display drive circuit, and more particularly to measures for preventing a shift in pulse timing of a control signal for controlling the operation of the display drive circuit.

The liquid crystal display device includes a liquid crystal display panel for displaying an image, a source driver and a gate driver which are display driving circuits, and a controller, and a display driver input from the outside is processed by the controller, and the source driver and the gate driver And the liquid crystal display panel is driven by these two drivers to display an image.

The liquid crystal display panel is configured such that a pair of substrates are bonded together via a frame-shaped sealing material, and a liquid crystal layer is sealed inside the sealing material between both substrates. On one substrate constituting the liquid crystal display panel, a plurality of source wirings and gate wirings extending in directions intersecting each other are provided as display wirings so as to form a lattice shape as a whole. At the intersection of each source line and each gate line, a TFT (Thin Film 接続 Transistor) connected to these two wires and a pixel electrode connected thereto are provided.

The source driver is connected to each source wiring, and includes a shift register circuit, a sampling memory circuit, a hold memory circuit, a level shifter circuit, a digital-analog (Digital-Analog) conversion circuit (hereinafter referred to as a DA conversion circuit), and an output circuit. Yes.

The source driver receives a digital display data signal from the controller and a source start pulse signal, a source clock signal, a horizontal synchronization signal (latch signal), a polarity inversion signal, and the like as a control signal. Each of these control signals has a pulse that rises at a timing according to the specifications of the liquid crystal display device, and is a signal that controls the operation of the source driver according to the input timing of the pulse.

Then, the source driver samples the display data signal in a sampling memory circuit in a time division manner based on the source start pulse signal, the source clock signal, and the horizontal synchronization signal, and transfers the sampled display data signal to the hold memory circuit. After the hold, the signal is converted into an analog signal by the DA conversion circuit, the signal polarity is inverted based on the polarity inversion signal, and the analog signal is output as a source signal from the output circuit to the source wiring.

The gate driver is connected to each gate wiring and includes a shift register circuit, a level shifter circuit, and an output circuit. The gate driver receives a gate start pulse signal, a gate clock signal, and the like as a control signal for the display data from the controller. Each of these control signals has a pulse that rises at a timing according to the specifications of the liquid crystal display device, and is a signal that controls the operation of the gate driver according to the input timing of the pulse.

Based on the gate start pulse signal and the gate clock signal, the gate driver outputs the pulse signal sequentially delayed from each stage of the shift register circuit to one stage of the level shifter circuit, and outputs the pulse signal to the level shifter circuit. After being converted to a voltage level that can drive the gate of the TFT by the circuit, it is configured to output it from the output circuit to the gate wiring as a gate signal.

As such a liquid crystal display device, for example, Patent Document 1 includes a comparison determination circuit and a switching circuit for detecting and repairing a defect in the source driver in a state where the electrical connection with the liquid crystal display panel is disconnected. There is disclosed a display device that executes processing for detecting a failure of a source driver at the timing of switching a channel or switching from a program to CM (Commercial Message) by a comparison determination circuit and a switching circuit. According to this, it is described that self-detection and self-repair of a circuit failure can be performed at an appropriate timing.

JP 2010-122513 A

However, the liquid crystal display device disclosed in Patent Document 1 self-repairs only malfunctions of internal circuits caused by problems in the manufacture of the source driver, so that control signals such as a horizontal synchronization signal and a polarity inversion signal are externally supplied to the source driver. If the pulse timing of the signal is shifted and the signal is out of the specifications of the display device in the first place, the data position may be shifted during data transfer from the sampling memory circuit to the hold memory circuit. An error may occur during conversion from a digital signal to an analog signal, and a desired data signal may not be supplied to the source wiring, resulting in a display failure.

The present invention has been made in view of such a point, and an object of the present invention is to compensate for a shift in the pulse timing of a control signal and to avoid occurrence of a display defect.

In order to achieve the above object, according to the present invention, when a plurality of control signals input to the display drive circuit include a signal outside the specification whose pulse timing is shifted, the signal outside the specification corresponds to the specification. A regular control signal having pulse timing is replaced.

Specifically, the present invention is directed to a display driving circuit for performing image display and a display device having the display driving circuit, and has taken the following solution.

That is, the first invention is a display driving circuit, and stores normal pulse intervals between a plurality of control signals having pulses rising at predetermined intervals with timing according to the specifications of the display device. The control unit receives the control signal in parallel with the memory unit, and compares the pulse interval between the control signals with the normal pulse interval stored in the memory unit, thereby shifting the pulse timing of the control signal. A timing comparison unit that detects a deviation in pulse timing by the timing comparison unit, and a normal signal generation unit that generates a normal control signal having a pulse timing according to the specifications. And a signal replacement unit that replaces the normal control signal generated by the generation unit.

In the first aspect of the invention, the normal pulse interval between the control signals input in parallel to the display drive circuit is stored as data in the memory unit. When each control signal is input, first, the timing comparison unit The pulse interval between the control signals is compared with the regular pulse interval stored in the memory unit. At this time, if there is a control signal outside the specification whose pulse timing is shifted from the specification of the display device, the control signal outside the specification is detected. In addition, the normal signal generation unit generates a normal control signal having a pulse timing according to the specifications of the display device. When the control signal outside the specification is detected by the timing comparison unit, the control signal outside the specification is replaced by the normal control signal generated by the normal signal generation unit at the signal replacement unit. Thereby, even if the pulse timing of the control signal is shifted at the stage of input from the outside, the shift of the pulse timing of the control signal is compensated. As a result, it is possible to avoid the occurrence of display defects.

According to a second aspect of the present invention, in the display drive circuit according to the first aspect of the invention, the timing comparison unit sets a pulse interval between the individual control signals and the other two control signals excluding the control signal in the memory unit. The comparison is made with a stored regular pulse interval.

In the second aspect of the invention, the pulse interval between each of the four or more input control signals and the other two control signals excluding the control signal is stored in the memory unit in the timing comparison unit. And the pulse timing deviation in each control signal is inspected. According to this method, since the number of comparisons with the regular pulse interval is smaller than when comparing all pulse intervals between the control signals, it is possible to efficiently inspect the deviation of the pulse timing in each control signal. Is possible.

According to a third aspect of the present invention, the display drive circuit of the first or second aspect further includes an alarm unit that issues an alarm when the timing comparison unit detects a shift in pulse timing of at least one of the control signals. It is characterized by that.

In the third aspect of the invention, since the alarm unit issues an alarm when the timing comparison unit detects a shift in the pulse timing of at least one control signal, the input signal to the display drive circuit is specified by performing the display inspection. It is possible to easily recognize that it is in an outside state, and it is possible to improve product development efficiency and increase efficiency when analyzing defective products.

According to a fourth invention, in the display drive circuit according to the first invention, a source start pulse signal and a source clock signal are inputted as the control signal, and the source start pulse signal is transferred based on the source clock signal. A sampling memory circuit that receives a display data signal of a digital value, samples and outputs the display data signal based on a source start pulse signal transferred from the shift register circuit, and a plurality of horizontal synchronization signals as the control signal. A hold memory circuit that receives a signal, holds a display data signal output from the sampling memory circuit based on the horizontal synchronization signals, and outputs the display data signal based on a horizontal synchronization signal input next; A plurality of polarity inversion signals are input as the control signal. A DA conversion circuit that converts the display data signal output from the hold memory circuit into an analog signal and inverts the polarity of the analog signal based on each polarity inversion signal, and outputs the analog signal. A source driver that drives at least one of the source start pulse signal and the source clock signal, the plurality of horizontal synchronization signals, and the plurality of polarity inversion signals by the timing comparison unit and the signal replacement unit. It is characterized by processing.

In the fourth aspect of the invention, the source clock signal and source start pulse signal input to the shift register circuit of the source driver, the plurality of horizontal synchronization signals input to the hold memory circuit, and the plurality of signals input to the DA converter circuit At least one of the polarity inversion signals is processed by the timing comparison unit and the signal replacement unit. When the source clock signal and the source start pulse signal are processed by the timing comparison unit and the signal replacement unit, the timing deviation of the pulse signal transferred to the sampling memory circuit is prevented. Further, when the plurality of horizontal synchronization signals are processed by the timing comparison unit and the signal replacement unit, it is possible to prevent the data position from being shifted when the data signal is transferred from the sampling memory circuit to the hold memory circuit. Furthermore, when the plurality of polarity inversion signals are processed by the timing comparison unit and the signal replacement unit, it is possible to prevent an error from occurring when the DA signal is converted from a digital signal to an analog signal.

According to a fifth aspect of the present invention, in the display drive circuit according to the first aspect, a shift register circuit that receives a gate start pulse signal and a gate clock signal as the control signal and transfers the gate start pulse signal based on the gate clock signal And a gate driver for driving the gate wiring of the display device, wherein the gate start pulse signal and the gate clock signal are processed by the timing comparison unit and the signal replacement unit.

In the fifth aspect of the invention, the gate clock signal and the gate start pulse signal input to the shift register circuit of the gate driver are processed by the timing comparison unit and the signal replacement unit. As a result, timing deviation of the pulse signal transferred from the shift register circuit is prevented.

A sixth invention is a display device, comprising: the display drive circuit according to any one of the first to fifth inventions; and a display panel having a display wiring connected to the display drive circuit. It is characterized by that.

In the sixth aspect of the invention, the display drive circuit of the first to fifth aspects of the invention has an excellent characteristic that can compensate for the deviation of the pulse timing of the control signal and avoid the occurrence of display failure. It is possible to avoid the occurrence of display defects and perform good image display.

According to the present invention, when there are non-specification signals whose pulse timings are shifted in the plurality of control signals input to the display drive circuit, the normal control having the non-specification signal with the pulse timings according to the specifications. Since it is replaced with a signal, it is possible to compensate for the deviation in the pulse timing of the control signal and to avoid the occurrence of display defects.

FIG. 1 is a block diagram illustrating a configuration of a main part of the liquid crystal display device according to the first embodiment. FIG. 2 is an equivalent circuit diagram showing a configuration in the display area of the liquid crystal display panel. FIG. 3 is a block diagram illustrating a configuration of a source driver IC (Integrated Circuit) according to the first embodiment. FIG. 4 is a block diagram illustrating a configuration of the control signal compensation circuit of the source driver IC according to the first embodiment. FIG. 5 is a conceptual diagram showing a schematic operation when each normal horizontal synchronization signal is input to the control signal compensation circuit in the first embodiment. FIG. 6 is a conceptual diagram showing a schematic operation when a part of the horizontal synchronization signal out of the specification is inputted to the control signal compensation circuit in the first embodiment. FIG. 7 is a block diagram illustrating a configuration of the gate driver IC according to the second embodiment. FIG. 8 is a block diagram illustrating a configuration of the control signal compensation circuit of the gate driver IC according to the second embodiment. FIG. 9 is a conceptual diagram illustrating a schematic operation when a normal gate start pulse signal and a gate clock signal are input to the control signal compensation circuit according to the second embodiment. FIG. 10 is a conceptual diagram showing a schematic operation when a gate start pulse signal and a gate clock signal out of specification are input to the control signal compensation circuit in the second embodiment. FIG. 11 is a block diagram illustrating a configuration of a control signal compensation circuit according to the third embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
In the first embodiment, an active matrix liquid crystal display device S will be described as an example of a display device.

The structure of the main part of the liquid crystal display device S is shown in FIG.

The liquid crystal display device S includes a liquid crystal display panel 1 that performs image display, a gate driver 2 and a source driver 3 that are display drive circuits, a controller 4 that supplies display signals to both the

drivers

2 and 3, and a liquid crystal drive power source. 5, and in response to the output from the controller 4, the

drivers

2 and 3 selectively apply the voltage from the liquid crystal driving power source 5 to the liquid crystal display panel 1, thereby displaying an image on the liquid crystal display panel 1. It is configured.

Although not shown, the liquid crystal display panel 1 includes an active matrix substrate and a counter substrate disposed so as to face each other, and the outer peripheral edges of both the substrates are bonded together with a frame-shaped sealing material. A liquid crystal layer is sealed between the substrates inside the sealing material. The liquid crystal display panel 1 has a display area for displaying an image in an area where a liquid crystal layer is provided. The display area is configured by arranging a plurality of pixels, which are the minimum unit of an image, in a matrix.

The circuit configuration in the display area of the liquid crystal display panel 1 is shown in FIG.

In the display area of the liquid crystal display panel 1, a plurality of gate wirings 11 are provided so as to extend in parallel to each other, and a plurality of source wirings 13 extend in parallel to each other in a direction orthogonal to the gate wirings 11. Is provided. The gate lines 11 and the source lines 13 are insulated from each other through an insulating film, and are formed in a lattice shape as a whole so as to partition each pixel P.

Each pixel P includes a TFT 15, a pixel electrode 17 connected to the TFT 15, a common electrode 19 facing the pixel electrode 17, and a liquid crystal capacitor having a structure in which the pixel electrode 17 and the common electrode 19 sandwich a liquid crystal layer. Clc. The gate of each TFT 15 is connected to one gate wiring 11 that partitions the corresponding pixel P. The source of each TFT 15 is connected to one source line 13 that partitions the corresponding pixel P. The drain of each TFT 15 is connected to the pixel electrode 17 disposed in the corresponding pixel P.

The gate driver 2 is connected to each gate line 11 of the liquid crystal display panel 1 and is a circuit that drives each gate line 11. More specifically, the gate driver 3 sequentially selects one gate line 11 from all the gate lines 11 and applies a selection voltage (for example, a high level voltage) to the selected gate line 11. In addition, a non-selection voltage (for example, a low level voltage) is applied to the other gate wirings 11. Thereby, the gate driver 2 makes each TFT 15 connected to the selected gate wiring 11 conductive, and makes the pixel electrode 17 connected to each TFT 15 in the conductive state ready for voltage writing.

The source driver 3 is connected to each source wiring 13 of the liquid crystal display panel 1 and is a circuit that drives each source wiring 13 by, for example, dot inversion. More specifically, the source driver 3 switches the positive voltage and the negative voltage corresponding to the display data signal for each source line 13 for each source line 13 and each gate line 11 is selected. In addition, the positive voltage and the negative voltage corresponding to the display data signal are inverted and applied. Thus, the source driver 3 writes a positive voltage or a negative voltage corresponding to the display data signal to each pixel electrode 17 in a voltage writable state.

The gate driver 2 includes a plurality of gate driver ICs 20 as shown in FIG. A predetermined number of gate wirings 11 are distributed and connected to each gate driver IC 20. The source driver 3 is composed of a plurality of source driver ICs 30. A predetermined number of source lines 13 are distributed and connected to each source driver IC 30. The gate driver IC 20 and the source driver IC 30 are mounted on the liquid crystal display panel 1 as, for example, a TCP (Tape Carrier Package) in which an IC chip is mounted on a wiring board.

The controller 4 outputs a control signal S1 such as a gate start pulse signal GSP, a gate clock signal GCLK, and a gate ON signal to the gate driver 2. The gate clock signal GCLK and the gate ON signal are input to each gate driver IC 20, but the gate start pulse signal GSP is supplied to any one gate driver IC (for example, the gate driver IC closest to the controller 4) 20. Only entered.

In addition, the controller 4 controls the source driver 3 as a control signal S2 for controlling the source driver IC 30 as a source start pulse signal SSP, a source clock signal SCLK, a horizontal synchronization signal (latch signal) LS, and a polarity inversion signal. For example, the signals DR, DG, and DB corresponding to red, green, and blue are output as REV and the digitized display data signal DS. Note that the source clock signal SCLK, the horizontal synchronization signal LS, the display data signal DS, and the polarity inversion signal REV are input to each source driver IC 30, but the source start pulse signal SSP is any one source driver IC (for example, It is input only to the source driver IC 30 that is closest to the controller 4.

The liquid crystal driving power supply 5 supplies an analog voltage for displaying an image on the display panel 1 to each gate driver IC 20 and each source driver IC 30, for example, a reference voltage VR for generating a gradation display voltage in each source driver IC 30. Is a circuit for supplying Here, a power source for supplying a voltage for driving each of the

drivers

2 and 3 is omitted.

In the present embodiment, since the source driver 3 has a characteristic configuration, the configuration of the source driver 3 will be described in detail below with reference to FIGS.

The configuration of the source driver IC 30 is shown in FIG.

Each source driver IC 30 included in the source driver 3 includes a shift register circuit 31, an input latch circuit 33, a sampling memory circuit 35, a hold memory circuit 37, a level shifter circuit 39, a gradation voltage generation circuit 41, a DA conversion circuit 43, and an output circuit. 45.

The shift register circuit 31 is an n-stage shift register, and sequentially shifts the source start pulse signal SSP in synchronization with the source clock signal SCLK input from the controller 4, and a pulse signal based on the source start pulse signal SSP is transmitted from each stage. It is a circuit that outputs to the sampling memory circuit 35 in order. The output signal of the shift register circuit 31 determines the sampling position of the display data signal DS (DR, DG, DB).

The source start pulse signal SSP is a signal synchronized with the horizontal synchronization signal LS, and after being shifted to the final stage in the shift register circuit 31, the source start pulse signal SSP is sent to the shift register circuit 31 in the adjacent source driver IC 30. Input as signal SSP and similarly shifted. Then, the data is transferred to the shift register circuit 31 in the source driver IC 30 farthest from the controller 4.

The input latch circuit 33 temporarily latches the serially input display data signal DS of s bits (for example, each of 6 bits of DR, RG, DB, 18 bits in total) according to the source clock signal SCLK, and the latched display data This is a circuit for outputting the signal DS (DR, DG, DB) to the sampling memory circuit 35.

The sampling memory circuit 35 is an s-bit display data signal DS (DR, DG, DB) sent in a time-sharing manner from the input latch circuit 33 at a position specified by an output signal from each stage of the shift register circuit 31. ) And each display data signal DS is stored until n display data signals DS (DR, DG, DB) for one horizontal synchronization period are prepared.

The hold memory circuit 37 is based on the horizontal synchronization signal LS input from the control signal compensation circuit 50 described later, that is, at the rising edge of the latch pulse, the n display data signals DS (DR, DG) stored in the sampling memory circuit 35. , DB) are collectively held.

The level shifter circuit 39 is adapted to the DA conversion circuit 43 that processes the voltage level applied to the source line 13, and the signal level of the n display data signals DS (DR, DG, DB) stored in the hold memory circuit 37. Is converted by boosting or the like.

The gradation voltage generation circuit 41 includes a resistance dividing circuit, and generates a γ-corrected 2 ^S level gradation voltage based on the reference voltage VR input from the liquid crystal driving power supply 5 using the resistor dividing circuit, and a DA conversion circuit 43 is a circuit that outputs the data.

The DA conversion circuit 43 outputs one of the 2 ^S levels generated by the gradation voltage generation circuit 41 for each of the n display data signals DS (DR, DG, DB) input from the level shifter circuit 39. Outputs after selecting a regulated voltage and converting the selected gradation voltage into an analog signal by switching to a positive polarity voltage or a negative polarity voltage in accordance with a polarity inversion signal REV input from a control signal compensation circuit 50 described later. This is a circuit that outputs to the circuit 45.

The output circuit 45 includes n voltage followers composed of, for example, an operational amplifier and an output buffer. The output circuit 45 amplifies an analog signal input from the DA converter circuit 43 using the voltage follower and converts the amplified analog signal into a low-impedance output. As shown in FIG.

Each source driver IC 3 in this embodiment further includes a control signal compensation circuit 50 in addition to the

various circuits

31, 33, 35, 37, 39, 41, 43, 45 described above.

The control signal compensation circuit 50 is a circuit that compensates the pulse timing of the horizontal synchronization signal LS and the polarity inversion signal REV input from the controller 4. Here, the horizontal synchronization signal LS and the polarity inversion signal REV are control signals having pulses that rise with a predetermined interval from each other at a timing according to the specifications of the liquid crystal display device S, and are input to the source driver 3 in parallel. The

Hereinafter, the individual horizontal synchronization signals LS and the polarity inversion signals REV are distinguished and expressed as horizontal synchronization signals LS (0) to (k) and polarity inversion signals REV (0) to (k). Here, k is a number corresponding to the number of source lines 13 connected to each source driver IC 30. When the pulse timing of each of the horizontal synchronization signals LS (0) to (k) or the polarity inversion signals REV (0) to (k) is deviated from the specification of the liquid crystal display device S, a display defect is caused. I will.

The configuration of the control signal compensation circuit 50 is shown in FIG.

The control signal compensation circuit 50 includes a first compensation circuit 51 that compensates for pulse timing deviations of the horizontal synchronization signals LS (0) to (k), and pulse timings of the polarity inversion signals REV (0) to (k). And a second compensation circuit 57 for compensating for the deviation.

The first compensation circuit 51 includes a first timing comparison unit 53 that detects a pulse timing shift of the horizontal synchronization signals LS (0) to (k), and a pulse timing shift by the first timing comparison unit 53. And a first signal replacement unit 55 that replaces the horizontal synchronization signals LS (0) to (k) in which are detected with normal horizontal synchronization signals LS (0) ′ to (k) ′ corresponding thereto.

The first timing comparison unit 53 has a first memory unit 54 therein. In the first memory unit 54, a normal pulse interval between the horizontal synchronization signals LS (0) to (k) is stored in advance as data. Then, the first timing comparison unit 53 detects the pulse interval between the plurality of horizontal synchronization signals LS (0) to (k) inputted in parallel and the normal pulse stored in the first memory unit 54. By comparing the interval, a deviation in pulse timing of each horizontal synchronization signal LS (0) to (k) is detected.

In the first timing comparison unit 53 in this embodiment, the individual horizontal synchronization signals LS (0) to (k) and the other two horizontal synchronization signals LS excluding the horizontal synchronization signals LS (0) to (k). The pulse interval between (0) to (k) is compared with the regular pulse interval stored in the first memory unit.

Specifically, regular pulse intervals in which the horizontal synchronization signals LS of three each in the order of the earliest pulse timing are set as one set, and the mutual pulse intervals between the horizontal synchronization signals LS in each set are stored in the first memory unit 54. Compare with Here, when the horizontal synchronization signals LS (k−1) and LS (k) having late pulse timing cannot be combined into three sets, the horizontal synchronization signals LS (0) and LS (1) having early pulse timing are left. Is added as necessary to form a set of three.

For example, the horizontal synchronization signals LS (0) to (2), the horizontal synchronization signals LS (3) to (6),..., The horizontal synchronization signals LS (k−2), LS (k), and LS (0) are each 1 The horizontal synchronization signal LS (0) and the horizontal synchronization signal (1), the horizontal synchronization signal LS (0) and the horizontal synchronization signal (2), the horizontal synchronization signal LS (1) and the horizontal synchronization signal (2), and the horizontal synchronization Signal LS (2) and horizontal synchronization signal (3),..., Horizontal synchronization signal LS (k−1) and horizontal synchronization signal (k), horizontal synchronization signal LS (k−1) and horizontal synchronization signal (0), and Each pulse interval in the horizontal synchronization signal LS (k) and the horizontal synchronization signal (0) is compared with a normal pulse interval.

Then, the first timing comparison unit 53 outputs to the first signal replacement unit 55 a determination signal indicating whether or not the pulse timing is shifted for each of the horizontal synchronization signals LS (0) to (k). It has become.

The first signal replacement unit 55 has a first normal signal generation unit 56 therein. The first normal signal generator 56 is a circuit that generates normal horizontal synchronization signals LS (0) ′ to (k) ′ having pulse timings according to the specifications of the liquid crystal display device S.

Then, the first signal replacement unit 55 uses the horizontal synchronization signals LS (0) to (k) in which the deviation of the pulse timing is detected based on the determination signal input from the first timing comparison unit 53 as the first signal. The normal horizontal synchronization signals LS (0) ′ to (k) ′ corresponding to the normal signal generation unit 56 generated by the normal signal generation unit 56 are replaced.

Note that the first signal replacement unit 55 outputs the horizontal synchronization signals LS (0) to (k) for which no shift in pulse timing has been detected by the first timing comparison unit 53 as they are. .

The second compensation circuit 57 includes a second timing comparison unit 59 that detects a pulse timing shift of each polarity inversion signal REV (0) to (k), and a pulse timing shift by the second timing comparison unit 59. And a second signal replacement unit 61 that replaces the polarity reversal signals REV (0) to (k) in which are detected with normal polarity reversal signals REV (0) ′ to (k) ′ corresponding thereto.

The second timing comparison unit 59 has a second memory unit 60 inside. In the second memory unit 60, the normal pulse interval between the polarity inversion signals REV (0) to (k) is stored in advance as data.

Then, the second timing comparison unit 59 detects the pulse interval between the plurality of polarity reversal signals REV (0) to (k) input in parallel and the normal pulse stored in the second memory unit 60. By comparing the interval, a deviation in pulse timing of each polarity inversion signal REV (0) to (k) is detected.

Also in the second timing comparison unit 59 in this embodiment, the pulse interval in the combination of the polarity inversion signals REV (0) to (k) similar to the first timing comparison unit 53 is set in the second memory unit 60. Compare with the stored regular pulse interval.

Then, the second timing comparison unit 59 outputs a determination signal indicating whether or not the pulse timings of the polarity inversion signals REV (0) to (k) are shifted to the second signal replacement unit 61. It has become.

The second signal replacement unit 61 has a second normal signal generation unit 62 therein. The second normal signal generator 62 is a circuit that generates normal polarity inversion signals REV (0) ′ to (k) ′ having pulse timings according to the specifications of the liquid crystal display device S.

Then, the second signal replacement unit 61 converts the polarity reversal signals REV (0) to (k) from which the pulse timing deviation is detected based on the determination signal input from the second timing comparison unit 59 into the second The normal polarity inversion signals REV (0) ′ to (k) ′ corresponding to the normal signal generation unit 62 generated by the normal signal generation unit 62 are replaced.

Note that the second signal replacement unit 61 outputs the polarity reversal signals REV (0) to (k) for which the pulse timing deviation is not detected by the second timing comparison unit 59 as they are. .

FIG. 5 and FIG. 6 show schematic operations when the horizontal synchronization signals LS (0) to (k) are input in the control signal compensation circuit 50 configured as described above. FIG. 5 shows a case where the pulse timings of all the horizontal synchronization signals LS (0) to (k) are regular timings. FIG. 6 shows a case where the pulse timings of some horizontal synchronization signals LS are out of specification. Here, a case where the horizontal synchronization signals LS (1) and LS (k) have pulse timings out of specification will be described as an example.

In FIGS. 5 and 6, “◯” indicates that the pulse timing is regular according to the specification of the liquid crystal display device S, and “x” is out of specification due to deviation from the regular pulse timing. Indicates that it is pulse timing. This also applies to FIGS. 9 and 10 referred to later.

In the control signal compensation circuit 50, as shown in FIG. 5, the pulse timings of all the horizontal synchronization signals LS (0) to (k) input from the controller 4 are normal timings according to the specifications of the liquid crystal display device S. In this case, all the horizontal synchronization signals LS (0) to (k) are output to the hold memory circuit 37 as they are.

On the other hand, as shown in FIG. 6, when some of the horizontal synchronization signals LS (1) and LS (k) input from the controller 4 are out of specification because the pulse timing is shifted, The horizontal synchronization signals LS (1) and LS (k) outside these specifications are detected by the first timing comparison unit 53. Then, the out-of-specification horizontal synchronization signals LS (1) and LS (k) detected by the first timing comparison unit 53 are converted into normal horizontal synchronization signals LS (1) ′ and LS by the first signal replacement unit 55. After being replaced with (k) ′, it is output to the hold memory circuit 37. The other horizontal synchronization signals LS (0), LS (2) to (k−1) are output to the hold memory circuit 37 as they are.

As described above, even if the pulse timings of the horizontal synchronization signals LS (1) and LS (k) are shifted at the stage of external input, the pulse timings of the horizontal synchronization signals LS (1) and LS (k) are shifted. Is compensated by replacement with the regular horizontal synchronization signals LS (1) ′ and LS (k) ′. As a result, the data position can be prevented from shifting when the display data signal DS (DR, DG, DB) is transferred from the sampling memory circuit 35 to the hold memory circuit 37.

For the polarity inversion signals REV (0) to (k), the horizontal synchronization signals LS (0) to (k) are also generated by the second timing comparison unit 59 and the second signal replacement unit 61 of the control signal compensation circuit 50. By processing in the same manner as described above, a deviation in pulse timing is compensated.

That is, in the control signal compensation circuit 50, although not shown, the pulse timings of all polarity inversion signals REV (0) to (k) input from the controller 4 are normal timings according to the specifications of the liquid crystal display device S. In this case, all the polarity inversion signals REV (0) to (k) are output to the DA conversion circuit 43 as they are.

On the other hand, for some of the polarity inversion signals REV (for example, REV (1) and REV (k), the parenthesized text follows this example) input from the controller 4, the pulse timing is shifted and the timing is out of specification. If so, the polarity reversal signals REV (REV (1) and REV (k)) outside these specifications are detected by the second timing comparison unit 59. Then, the non-specification polarity reversal signals REV (REV (1) and REV (k)) detected by the second timing comparison unit 59 are converted into normal polarity reversal signals REV ′ ( After being replaced by REV (1) ′, REV (k) ′), it is output to the DA conversion circuit 43.

As described above, even if the pulse timings of the polarity reversal signals REV (REV (1) and REV (k)) are shifted at the stage of external input, the polarity reversal signals REV (REV (1) and REV (k)) ) Is compensated by replacement with the normal polarity inversion signal REV (REV (1) ′, REV (k) ′). Thereby, it is possible to prevent an error from occurring when the DA conversion circuit 43 converts a digital signal into an analog signal.

As described above, in each source driver IC 30 of the present embodiment, the horizontal synchronization signals LS (0) to (k) and the polarity inversion signals REV (0) to (k) are once input to the control signal compensation circuit 50. The control signal compensation circuit 50 inspects deviations in pulse timings of these control signals LS (0) to (k) and REV (0) to (k). If there is a horizontal synchronization signal LS (0) to (k) that is out of specification with the pulse timing shifted, it is replaced with the corresponding normal horizontal synchronization signal LS (0) ′ to (k) ′. If there are non-specification polarity reversal signals REV (0) to (k) that are output to the hold memory circuit 37 later and the pulse timing is shifted, these are converted to the corresponding normal polarity reversal signals REV (0) ′ to (K) Output to the DA converter circuit 43 after replacing with '.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, the pulse timing is shifted to the horizontal synchronization signals LS (0) to (k) or the polarity inversion signals REV (0) to (k) input to the source driver 3, and the specification is out of specification. Even when the control signals LS (0) to (k) and REV (0) to (k) exist, the control signals LS (0) to (k) and REV (0) to (k) outside the specification are specified. Are output in place of regular control signals LS (0) ′ to (k) ′ and REV (0) ′ to (k) ′ having pulse timings corresponding to the horizontal synchronization signals LS (0) to (k). ) And the pulse timing deviations of the polarity inversion signals REV (0) to (k) can be compensated to avoid the occurrence of display defects.

<< Embodiment 2 of the Invention >>
FIG. 7 is a block diagram showing a configuration of the gate driver IC 20 according to the second embodiment. In the present embodiment, the configuration of the liquid crystal display device S is the same as that of the first embodiment except that the configuration of the gate driver IC 20 is different from that of the first embodiment. Therefore, only the gate driver IC 20 having a different configuration will be described. The same components are left to the description of the first embodiment based on FIGS. 1 to 6, and the detailed description thereof is omitted.

In the first embodiment, the source driver 3 has a characteristic configuration, but in the present embodiment, the gate driver 2 has a characteristic configuration in addition to this.

Each gate driver IC 20 included in the gate driver 2 includes a shift register circuit 71, a level shifter circuit 73, and an output circuit 75.

The shift register circuit 71 is an m-stage shift register, and sequentially shifts the gate start pulse signal GSP in synchronization with a gate clock signal GCLK input from a control signal compensation circuit 80, which will be described later. This is a circuit for outputting a signal to the level shifter circuit 73 in order from each stage.

The gate start pulse signal GSP is shifted to the final stage in the shift registration circuit 71, and then input to the shift register circuit 71 in the adjacent gate driver IC 20 as the gate start pulse signal GSP, and is similarly shifted. Then, the data is transferred to the shift register circuit 71 in the gate driver IC 20 farthest from the controller 4.

The level shifter circuit 73 is a circuit that converts an output signal sent from each stage of the shift register circuit 71 into a voltage level that can drive the gate of the TFT 15 of the liquid crystal display panel 1 and then outputs the voltage level to the output circuit 75. The level shifter circuit 73 also receives a gate ON signal from the controller 4. This gate ON signal is a high level signal for turning on the gate of the TFT 15 in order to turn off the entire liquid crystal display panel 1 during the power OFF sequence.

The output circuit 75 is a circuit that buffers the signal input from the level shifter circuit 73 and outputs it as a selection voltage or a non-selection voltage to each gate wiring 11 at a predetermined timing.

Each gate driver IC 20 in the present embodiment further includes a control signal compensation circuit 80 in addition to the

various circuits

71, 73, and 75 described above.

The control signal compensation circuit 80 is a circuit that compensates the pulse timing of the gate start pulse signal GSP with respect to the gate clock signal GCLK input from the controller 4. Here, the gate start pulse signal GSP and the gate clock signal GCLK are control signals having pulses that rise with a predetermined interval from each other at a timing according to the specifications of the liquid crystal display device S, and are input to the gate driver 2 in parallel. Is done. That is, when the pulse timing of the gate start pulse signal GSP with respect to the gate clock signal GCLK is deviated from the specification of the liquid crystal display device S, a display defect is caused.

The configuration of the control signal compensation circuit 80 is shown in FIG.

The control signal compensation circuit 80 includes a third timing comparison unit 81 that detects a shift in the pulse timing of the gate start pulse signal GSP, and a gate start pulse signal in which the shift in the pulse timing is detected by the third timing comparison unit 81. And a third signal replacement unit 83 for replacing the GSP with the corresponding normal gate start pulse signal GSP ′.

The third timing comparison unit 81 has a third memory unit 82 therein. In the third memory unit 82, a regular pulse interval corresponding to the specification of the liquid crystal display device S of the gate start pulse signal GSP with respect to the gate clock signal GCLK is stored in advance as data.

The third timing comparison unit 81 compares the pulse interval between the gate start pulse signal GSP and the gate clock signal GCLK input in parallel with the regular pulse interval stored in the third memory unit 82. By doing so, the shift of the pulse timing of the gate start pulse signal GSP is detected.

The third timing comparison unit 81 outputs a determination signal indicating whether or not the pulse timing of the gate start pulse signal GSP is shifted to the third signal replacement unit 83.

The third signal replacement unit 83 has a third normal signal generation unit 84 therein. The third normal signal generator 84 is a circuit that generates a normal gate start pulse signal GSP ′ having a pulse timing according to the specifications of the liquid crystal display device S.

Then, the third signal replacement unit 83 converts the gate start pulse signal GSP in which the deviation of the pulse timing is detected based on the determination signal input from the third timing comparison unit 81 to the third normal signal generation unit 84. Is replaced with the corresponding normal gate start pulse signal GSP ′ generated in step (b).

The third signal replacement unit 83 outputs the gate start pulse signal GSP as it is when the third timing comparison unit 81 does not detect a shift in the pulse timing in the gate start pulse signal GSP. Yes.

9 and 10 show schematic operations when the gate start pulse signal GSP and the gate clock signal GCLK are input in the control signal compensation circuit 80 configured as described above. FIG. 9 shows a case where the pulse timing of the gate start pulse signal GSP is a normal timing. FIG. 10 shows a case where the pulse timing of the gate start pulse signal GSP is out of specification.

In the control signal compensation circuit 80, as shown in FIG. 9, when the pulse timing of the gate start pulse signal GSP input from the controller 4 is a normal timing according to the specifications of the liquid crystal display device S, the gate start pulse The signal GSP is output to the shift register circuit 71 as it is.

On the other hand, as shown in FIG. 10, when the gate timing of the gate start pulse signal GSP input from the controller 4 is shifted and the timing is out of specification in the first place, It is detected by the third timing comparison unit 81. The non-specification gate start pulse signal GSP detected by the third timing comparison unit 81 is replaced by the regular gate start pulse signal GSP ′ by the third signal replacement unit 83, and is then sent to the shift register circuit 71. Is output.

In this way, even if the pulse timing of the gate start pulse signal GSP is deviated when it is input from the outside, the deviation of the pulse timing of the gate start pulse signal GSP is compensated by replacement with the normal gate start pulse signal GSP ′. Is done. As a result, a timing shift of the pulse signal transferred to the shift register circuit 71 can be prevented.

As described above, in each gate driver IC 20 of the present embodiment, the gate start pulse signal GSP and the gate clock signal GCLK are once input to the control signal compensation circuit 80, and the control signal compensation circuit 80 determines the gate start pulse signal GSP. The pulse timing deviation is inspected. If the pulse timing of the gate start pulse signal GSP is out of specification due to a shift, this is replaced with the corresponding normal gate start pulse signal GSP 'and output to the shift register circuit 71.

-Effect of Embodiment 2-
According to the second embodiment, the same effects as those of the first embodiment can be obtained, and even when the gate start pulse signal GSP input to the gate driver 2 is out of specification with the pulse timing shifted, Since the gate start pulse signal GSP outside the specification is replaced with a normal gate start pulse signal GSP ′ having a pulse timing according to the specification and output, the deviation of the pulse timing of the gate start pulse signal GSP is also compensated and displayed. The occurrence of defects can be avoided more reliably.

<< Embodiment 3 of the Invention >>
FIG. 11 is a block diagram showing the configuration of the control signal compensation circuit 50 of the source driver IC 30 according to the third embodiment. In the present embodiment, the configuration of the control signal compensation circuit 50 is the same as that of the first embodiment except that the configuration of the control signal compensation circuit 50 is different from that of the first embodiment. Only the circuit 50 portion will be described, and the same components will be left to the description of the first embodiment based on FIGS. 1 to 6, and the detailed description thereof will be omitted.

The control signal compensation circuit 50 according to the present embodiment further includes an alarm unit 90 in addition to the same configuration as that of the first embodiment. The alarm unit 90 receives from the second timing comparison unit 59 a determination signal indicating whether or not the pulse timings of the horizontal synchronization signals LS (0) to (k) are shifted from the first timing comparison unit 53. A determination signal indicating whether the pulse timing has shifted for each of the polarity inversion signals REV (0) to (k) is input.

Then, when the alarm unit 90 determines that a shift in the pulse timing of at least one horizontal synchronization signal LS (0) to (k) has been detected based on the determination signal from the first timing comparison unit 53, or Based on the determination signal from the second timing comparison unit 59, an alarm is issued when it is determined that a pulse timing shift of at least one polarity inversion signal REV (0) to (k) is detected.

-Effect of Embodiment 3-
According to the third embodiment, at least one horizontal synchronization signal LS (0) to (k) or polarity inversion signal REV (0) to (k) is generated in the first timing comparison unit 53 or the second timing comparison unit 59. When the deviation of the pulse timing is detected, the alarm unit 90 issues an alarm, so that it is possible to easily recognize that the input signal to the source driver 3 is out of specification by performing the display inspection. It is possible to improve development efficiency and efficiency when analyzing defective products.

<< Other Embodiments >>
In the first embodiment, the horizontal synchronization signals LS (0) to (k) and the polarity inversion signals REV (0) to (k) are supplied to the control signal compensation circuit (

timing comparison units

53 and 59 and signal replacement units 55 and 61) 50. However, the present invention is not limited to this. For example, the control signal compensation circuit 50 may further have a function of compensating for a deviation in pulse timing of the source start pulse signal SSP with respect to the source clock signal SCLK.

That is, the control signal compensation circuit 50 includes a timing comparison unit that detects a shift in the pulse timing of the source start pulse signal SSP separately from the first and

second compensation circuits

51 and 57, and a pulse timing by the timing comparison unit. A signal replacement unit that replaces the source start pulse signal SSP in which the deviation is detected with a normal source start pulse signal SSP ′ corresponding thereto may be included. Here, the timing comparison unit has a configuration corresponding to the first and second

timing comparison units

53 and 59, and the signal replacement unit has a configuration corresponding to the first and second

signal replacement units

55 and 61. . According to such a configuration, it is possible to prevent timing deviation of the pulse signal transferred from the shift register circuit 31 to the sampling memory circuit 35.

Further, in the first embodiment, the first timing comparison unit 53 is the first memory unit 54, the first signal replacement unit 55 is the first normal signal generation unit 56, and the second timing comparison unit 59 is the second timing comparison unit 59. Although the second signal replacement unit 61 has the second normal signal generation unit 62 in the second memory unit 60, the first timing comparison unit 53, the first memory unit 54, and the first The signal replacement unit 55 and the first normal signal generation unit 56, the second timing comparison unit 59 and the second memory unit 60, and the second signal replacement unit 61 and the second normal signal generation unit 62 are separately provided. May be provided.

In the second embodiment, the third timing comparison unit 81 includes the third memory unit 82, and the third signal replacement unit 83 includes the third normal signal generation unit 84. The third timing comparison unit 81, the third memory unit 82, the third signal replacement unit 83, and the third normal signal generation unit 84 may be provided separately.

In the third embodiment, the case where the alarm unit 90 is provided in the control signal compensation circuit 50 of the source driver IC 30 has been described. However, the alarm unit 90 similar to the control signal compensation circuit 80 of the gate driver IC 20 in the second embodiment is described. May be provided.

The preferred embodiments of the present invention have been described above, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be understood by those skilled in the art that the above-described embodiment is an example, and that various modifications can be made to the combination of each component and each processing process, and such modifications are within the scope of the present invention. By the way.

For example, in each of the above embodiments, the gate driver 2 includes a plurality of gate driver ICs 20 mounted on the liquid crystal display panel 1 as TCP, and the source driver 3 also includes a plurality of source driver ICs 30 mounted on the liquid crystal display panel 1 as TCP. However, the present invention is not limited to this, and the gate driver 2 and the source driver 3 include the TFT 15 and the like constituting each pixel P on the active matrix substrate constituting the liquid crystal display panel 1. It may be integrated as a monolithic circuit.

In each of the above embodiments, the liquid crystal display device has been described as an example. However, the present invention is not limited thereto, and of course, other various display devices such as an organic EL (Electro-Luminescence) display device and a plasma display device. Can be applied.

As described above, the present invention is useful for a display driving circuit and a display device including the display driving circuit, and in particular, it is desired to compensate for a shift in the pulse timing of a control signal and avoid occurrence of a display defect. It is suitable for a display drive circuit and a display device including the display drive circuit.

S Liquid crystal display device 1 Liquid crystal display panel 2 Gate driver (display drive circuit)
3 Source driver (display drive circuit)
11 Gate wiring (display wiring)
13 Source wiring (display wiring)
31 Shift register circuit 35 Sampling memory circuit 37 Hold memory circuit 43 DA conversion circuit (digital analog conversion circuit)
53 First Timing Comparison Unit 54 First Memory Unit 55 First Signal Replacement Unit 56 First Normal Signal Generation Unit 59 Second Timing Comparison Unit 60 Second Memory Unit 61 Second Signal Replacement Unit 62 Second 2 normal signal generation unit 71 shift register circuit 81 third timing comparison unit 82 third memory unit 83 third signal replacement unit 84 third normal signal generation unit 90 alarm unit

Claims

A memory unit that stores, as data, regular pulse intervals between a plurality of control signals having pulses that rise with a predetermined interval at a timing according to the specifications of the display device;
The timing at which the control signals are input in parallel, and the pulse timing difference between the control signals is detected by comparing the pulse interval between the control signals with the normal pulse interval stored in the memory unit. A comparison unit;
A normal signal generation unit that generates a normal control signal having a pulse timing according to the above specifications;
A display drive circuit comprising: a signal replacement unit that replaces a control signal in which a pulse timing shift is detected by the timing comparison unit with a normal control signal generated by the normal signal generation unit.
The display drive circuit according to claim 1,
Four or more of the control signals are input to the timing comparison unit,
The timing comparison unit compares a pulse interval between the individual control signal and the other two control signals excluding the control signal with a normal pulse interval stored in the memory unit. circuit.
The display drive circuit according to claim 1 or 2,
A display drive circuit, further comprising an alarm unit that issues an alarm when the timing comparison unit detects a shift in pulse timing of at least one of the control signals.
The display drive circuit according to claim 1,
A shift register circuit that receives a source start pulse signal and a source clock signal as the control signal and transfers the source start pulse signal based on the source clock signal;
A sampling memory circuit that receives a display data signal of a digital value and samples and outputs the display data signal based on a source start pulse signal transferred from the shift register circuit;
A plurality of horizontal synchronization signals are input as the control signal, a display data signal output from the sampling memory circuit is held based on each horizontal synchronization signal, and the display data signal is converted into a next input horizontal synchronization signal. A hold memory circuit based on the output;
A plurality of polarity inversion signals are input as the control signal, the display data signal output from the hold memory circuit is converted into an analog signal, and the polarity of the analog signal is inverted based on each polarity inversion signal and output. A digital-analog conversion circuit,
Configure a source driver to drive the source wiring of the display device,
Display driving characterized in that at least one of the source start pulse signal and source clock signal, the plurality of horizontal synchronization signals, and the plurality of polarity inversion signals is processed by the timing comparison unit and the signal replacement unit. circuit.
The display drive circuit according to claim 1,
A shift register circuit that receives a gate start pulse signal and a gate clock signal as the control signal and transfers the gate start pulse signal based on the gate clock signal;
Configure the gate driver to drive the gate wiring of the display device,
A display driving circuit, wherein the gate start pulse signal and the gate clock signal are processed by the timing comparison unit and the signal replacement unit.
A display driving circuit according to any one of claims 1 to 5;
And a display panel having a display wiring connected to the display drive circuit.