WO2013019250A1 - Dispositif photovoltaïque et procédé de production d'un dispositif photovoltaïque - Google Patents

Dispositif photovoltaïque et procédé de production d'un dispositif photovoltaïque Download PDF

Info

Publication number
WO2013019250A1
WO2013019250A1 PCT/US2011/051264 US2011051264W WO2013019250A1 WO 2013019250 A1 WO2013019250 A1 WO 2013019250A1 US 2011051264 W US2011051264 W US 2011051264W WO 2013019250 A1 WO2013019250 A1 WO 2013019250A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
layer
substrate
semiconductor layer
face
Prior art date
Application number
PCT/US2011/051264
Other languages
English (en)
Inventor
Steven DUVALL
Michael Stuber
Peter ATANACKOVIC
Andrew Read
Original Assignee
The Silanna Group Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Silanna Group Pty Ltd filed Critical The Silanna Group Pty Ltd
Publication of WO2013019250A1 publication Critical patent/WO2013019250A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photovoltaic device and a process for producing a photovoltaic device.
  • the semiconductor layer is epitaxially grown on a transparent, single crystal substrate ⁇ e.g., sapphire
  • defects arising from crystal mismatch and trapped states at the interface between the semiconductor layer and the supporting substrate significantly reduce the diffusion length of carriers within these devices, significantly reducing the energy conversion efficiency.
  • a process for forming a photovoltaic device including:
  • planar interconnect layer having electrically conductive paths with electrically insulating regions therebetween, the planar interconnect layer being formed on one of the semiconductor substrate and a planar handle substrate;
  • the process includes selecting the reduced thickness of the semiconductor to provide a balance between absorption of incident photons and allowing charge carriers generated by the absorbed photons to be collected.
  • the process includes selecting the reduced thickness of the semiconductor to provide sufficient heat extraction from the device.
  • said thinning removes substantially all of the semiconductor between the second face of the semiconductor substrate and the photovoltaic solar cells therein.
  • the photovoltaic devices are lateral field photovoltaic devices.
  • the electrically conductive paths of the interconnect layer include one or more electrically conductive paths extending to one or more edges of the interconnect layer to provide one or more electrical contacts to the photovoltaic devices.
  • the handle substrate is electrically insulating, and the process includes forming one or more electrically conductive paths through the handle substrate, wherein the electrically conductive paths of the interconnect layer include one or more electrically conductive paths that electrically connect one end of each electrically conductive path through the handle layer to the photovoltaic devices, the other end of each electrically conductive path through the handle layer providing an external electrical contact to the photovoltaic devices.
  • the process includes forming electronic circuitry in the handle substrate to process output of the photovoltaic devices.
  • the handle substrate is made from a material having a high thermal conductivity to provide cooling to the photovoltaic device.
  • a photovoltaic device including:
  • an interconnect layer disposed between the semiconductor layer and the handle substrate and including electrically conductive paths electrically connected to the photovoltaic solar cells in the semiconductor layer.
  • the semiconductor layer has opposed first and second faces, the semiconductor layer is attached to the interconnect layer by the first face, and the photovoltaic devices are formed in the first face.
  • the photovoltaic devices are spaced from the second face of the semiconductor layer by a thickness of semiconductor.
  • the semiconductor between the second face and the photovoltaic devices has a thickness that provides a balance between absorption of photons incident on the second face and allowing charge carriers generated by the absorbed photons to be collected.
  • the interconnect layer includes a plurality of metal layers.
  • the photovoltaic devices are lateral field photovoltaic devices.
  • the electrically conductive paths of the interconnect layer include one or more electrically conductive paths extending to one or more edges of the interconnect layer to provide one or more electrical contacts to the photovoltaic devices.
  • the handle substrate is electrically insulating but includes one or more electrically conductive paths through the handle substrate, and the electrically conductive paths of the interconnect layer include one or more electrically conductive paths that electrically connect one end of each electrically conductive path through the handle layer to the photovoltaic devices, and the other end of each electrically conductive path through the handle layer provides an external electrical contact to the photovoltaic devices.
  • the handle substrate includes electronic circuitry configured to process output of the photovoltaic devices.
  • the device includes an integrated circuit chip that is flip chip bonded to conductive paths of the handle substrate.
  • the handle substrate is made from a material having a high thermal conductivity to provide cooling to the photovoltaic device.
  • a process for forming a photovoltaic device including:
  • each pair of adjacent and oppositely doped conductive regions forms a corresponding space charge region having a corresponding electric field therein, the space charge region extending substantially from the surface of the semiconductor layer and into the semiconductor layer such that electron-hole pairs created substantially at the surface of the semiconductor layer by photons entering the space charge region are separated in opposing directions by the electric field and collected by the corresponding pair of doped regions, thereby providing an electrical current to be conducted from the device.
  • the doped regions extend into the semiconductor layer in a direction substantially orthogonal to the face of the semiconductor layer, where the depth of each doped region is greater than its width.
  • the depth of each doped region is at least twice its width.
  • each pair of adjacent and oppositely doped conductive regions and the region therebetween forms a corresponding p-i-n diode.
  • the sets of conductive regions having respective opposite doping polarities have an interdigitated configuration.
  • the mutually spaced recesses include a first set of mutually spaced recesses extending into the semiconductor layer to a first depth, and a second set of mutually spaced recesses extending into the semiconductor layer to a second depth greater than the first depth, at least the sidewalls of the first set of mutually spaced recesses being doped to a first polarity, and at least the sidewalls of the second set of mutually spaced recesses being doped to a second polarity opposite to the first polarity.
  • the sidewalls and bases of the second set of recesses are doped to form a corresponding set of mutually spaced doped regions that extend through the semiconductor layer to a doped layer of the second polarity.
  • the process includes forming electrical contacts to the conductive regions, and bonding the electrical contacts to corresponding electrical contacts of a support.
  • the semiconductor layers are semiconductor wafers
  • the process includes applying the process of any one of claims 21 to 27 to a plurality of semiconductor wafers, forming electrical contacts to the conductive regions of the processed semiconductor wafers, and bonding the electrical contacts of the processed semiconductor wafers to corresponding electrical contacts of a support so that the processed semiconductor wafers are supported by and electrically interconnected by the support.
  • the semiconductor layers are semiconductor-on-insulator wafers.
  • the sets of conductive regions are spaced from a second face of the semiconductor layer opposite to the face in which the recesses were formed, and the process includes removing a portion of the semiconductor layer from the second face to reduce the thickness of semiconductor between the conductive regions and the second face.
  • the sets of conductive regions are spaced from a second face of the semiconductor layer opposite to the face in which the recesses were formed, and the process includes removing a portion of the semiconductor layer from the second face to remove the semiconductor between at least one of the sets of conductive regions and the second face. In some embodiments, said removing reduces the thickness of an inner portion of the semiconductor layer while leaving a relatively thick peripheral portion of the semiconductor layer to act as a structural support for the processed semiconductor layer.
  • the process includes:
  • a process for forming a photovoltaic device including:
  • the remaining portions of the face of the semiconductor substrate between the recesses have a masking layer thereover to substantially prevent those portions of the face from being implanted, the different relative orientations between the energetic beam and the substrate being selected so that the buried non- planar defective layer extends beneath the masked portions of the face.
  • the process includes:
  • micro-electronic and/or micro-mechanical devices in the semiconductor substrate
  • heating causes the substrate to split into two layers, one of which remains bonded to the support and includes the devices.
  • the support includes electrically conductive paths that form electrical connections to the devices when the support is bonded to the semiconductor substrate.
  • the devices are photovoltaic devices, and the electrically conductive paths interconnect the photovoltaic devices.
  • the photovoltaic devices are lateral field p-i-n photovoltaic devices with high aspect ratio doped regions.
  • the devices include dielectric and metal regions that cause light passing through the semiconductor layer without being absorbed to be redirected back into the semiconductor layer for absorption therein.
  • the process includes forming an anti-reflection coating on the non-planar surface of one of the layers.
  • the process includes forming a second non-planar semiconductor layer on the non-planar surface of one of the layers, the second semiconductor layer having a larger bandgap than the other semiconductor layer to preferentially absorb high energy photons therein.
  • the process includes forming an anti-reflection coating on the second non-planar semiconductor layer.
  • the anti-reflection coating includes trapped charge to reduce surface recombination of charge carriers.
  • the non-planar surface may have advantageous optical properties for the photovoltaic device.
  • Figures 1A and IB are schematic diagrams illustrating the operation of a standard prior art photovoltaic device having a planar space-charge region orthogonal to incident photons;
  • Figure 2 is a schematic diagram illustrating the operation of a lateral field photovoltaic device having a space-charge region parallel and coincident with incident photons;
  • Figure 3 is a schematic diagram illustrating an embodiment of a stacked photovoltaic device module having an interconnect layer disposed between a thin semiconductor device layer and a handle substrate;
  • Figures 4A to 4F are schematic diagrams illustrating the steps of a process for forming the stacked photovoltaic device module of Figure 3;
  • Figure 5 is a schematic diagram illustrating some different forms of recesses or trenches that can be formed in the surface of a semiconductor
  • Figures 6A to 6F are schematic diagrams illustrating the steps of various processes for forming pairs of trenches having doped sidewalls with opposite doping polarities;
  • Figure 7 is a schematic diagram illustrating a method for forming electrical connections to the doped sidewalls of a trench;
  • Figures 8A to 81 are schematic diagrams illustrating the processes for forming high aspect ratio lateral field p-i-n solar cell modules in accordance with some embodiments of the present invention.
  • Figures 9A and 9B are schematic diagrams illustrating different forms of p-i-n solar cells that can be produced by thinning the semiconductor substrate to different final thicknesses;
  • Figure 10 is a graph of the projected range of hydrogen ions in silicon as a function of ion energy
  • Figure 11 includes schematic diagrams illustrating the formation of buried defective regions by implanting ions into mutually spaced trenches formed in a semiconductor substrate, where the trenches are relatively wide (upper diagram) or narrow (lower diagram);
  • Figure 12 is a schematic diagram illustrating the effects of changing the relative orientation between the implanting ion beam and the semiconductor substrate on the buried defective regions;
  • Figure 13 is a schematic diagram illustrating how the relative orientation between the implanting ion beam and the semiconductor substrate can be changed during implantation to cause the buried defective regions to overlap and thereby form a continuous non-planar defective layer;
  • Figures 14 to 16 are schematic diagrams illustrating how a semiconductor substrate containing the continuous non-planar defective layer can be flip-chip bonded to a handle substrate, and then thermally processed to cause the semiconductor substrate to split into two layers along the defective layer to provide a thin semiconductor layer bonded to the handle substrate;
  • Figure 17 is a flow diagram of a layer transfer or 'zip-cut' process for forming the structures shown in Figures 14 to 16;
  • Figure 18 is a schematic diagram illustrating a complete photovoltaic device incorporating high aspect ratio lateral field photovoltaic cells bonded to an interconnect layer and a handle substrate, and having a non-planar photon receiving surface formed by the zip-cut process;
  • Figure 19 is a schematic diagram illustrating a modification of the embodiment of Figure 18 in which a second, wide band gap semiconductor is deposited on the non- planar surface formed by the zip-cut process;
  • Figure 20 is a schematic diagram illustrating the spatial arrangement of energy bands in the embodiment of Figure 19.
  • Figure 21 is a schematic diagram illustrating the spatial arrangement of energy bands in a modification of the embodiment of Figure 19 in which the initial semiconductor layer is thinned down to the doped regions so that the second, wide band gap semiconductor is immediately adjacent the doped regions.
  • Figure 1 is a schematic diagram of a standard prior art photovoltaic device in which incident photons 102 must travel through a doped surface layer 104 before reaching a relatively narrow depletion (or 'space charge') region 106 in the form of a thin sheet, layer or plane that extends in directions that are orthogonal to the direction of photon travel. Consequently, only electron-hole pairs generated within the narrow depletion region 106 or within a diffusion length of its edges can be collected by the electric field in the depletion region 106 and thereby contribute to the device photocurrent.
  • such devices are referred to here in as vertical field or vertical junction devices because the electric field is oriented vertically when the photon receiving surface is oriented horizontally, which is usually the case when such devices are used or represented.
  • This enhancement is due not only to the resulting increase in the photon path length within the depletion region 202, but also to the fact that high energy ⁇ i.e., short wavelength) photons are very strongly absorbed in the semiconductor body, as described above, thus generating electron-hole pairs (EHP) within the depletion region 202 with an exponentially and rapidly decaying generation rate 206 with distance z 208 from the surface 204, as shown by the graph in the right hand side of Figure 2.
  • EHP electron-hole pairs
  • FIG. 2 Although only one lateral pn junction is shown in Figure 2 for the sake of clarity, in practice a large array of such devices are formed in a single semiconductor wafer or thin film and interconnected to form a single device. This allows a far greater proportion of the semiconductor wafer to be used to form the depletion or space charge regions than would be the case for vertical field devices, where the depletion region is limited to a narrow buried band. By densely packing the lateral field devices, a majority of the wafer or thin film can be used as active regions from which EHPs are collected.
  • the overall efficiency of the device is generally increased by forming the doped regions 210, 212 to be deep (to extend the space charge regions deeper into the semiconductor, and thereby capture more EHPs along the paths of the photons 1210) but narrow (to reduce or eliminate the proportion of EHPs created within the doped regions 210, 212 and further than a diffusion length from the corresponding edge of the depletion region 202).
  • a series of parallel narrow sheets of doped semiconductor arranged vertically ⁇ i.e., as stripes in plan view) can be formed in a semiconductor wafer using standard lithography and masked ion implantation, as will be apparent to those skilled in the art.
  • the width L D 214 of the p-n junction depletion region 202 is limited to being about 1 ⁇ or less, which limits the overall efficiency of the device.
  • an intrinsic or at least not intentionally doped (NID) region of relatively high resistivity is disposed between the /?-type 210 and n-type 212 doped regions to provide a lateral p-i-n photovoltaic device where the width L D 214 of the space charge region for generating/collecting EHPs is substantially increased over the p-n lateral field device 200 described above, thus providing increased efficiency.
  • NID intrinsic or at least not intentionally doped
  • the terms "intrinsic region” and “NID region” refer to a region that is either undoped or is lightly doped relative to the p-type and n-type doped regions disposed on either side such that the doped regions establish an electric field across the intrinsic region to form a p-i-n diode structure or equivalent thereof.
  • the "intrinsic region” in such a structure is nominally undoped, or background doped only, in some cases it may be desirable to lightly dope the "intrinsic region” to increase carrier mobility and lifetime therein.
  • the p-i-n device can have an almost arbitrarily large "intrinsic" region, which enables the simultaneous optimization of optical absorption and EHP carrier extraction. Further details of lateral field devices are provided in the lateral field device patent application.
  • FIG. 3 is a schematic illustration of a cross-section of a portion of a high efficiency photovoltaic (PV) module in accordance with some embodiments of the present invention.
  • the module includes (i) a handle substrate 3001 , with through- vias and solder bumps 3005, (ii) an interconnect stack 3002, and (iii) a thin film semiconductor active layer 3003, with doping 3006 indicated schematically, and surface coatings 3004.
  • Figure 3 provides only a simplified high level schematic view of the module for the purposes of explaining the roles of the handle substrate 3001 , interconnect stack 3002, and semiconductor active layer 3003. For the sake of clarity, details of these three components in an actual module are not shown.
  • the handle substrate 3001 provides mechanical support for the photovoltaic device; it can facilitate thermal management, and it can allow additional circuitry to be integrated with the photovoltaic device. Such circuitry can perform power conditioning functions and can transform the DC power generated by the photovoltaic device into AC power.
  • the handle substrate 3001 may be composed of any suitable material. Metal handles are used in concentrating photovoltaic systems in order to act as heat sinks. Glass handles are used in flat plate photovoltaic systems in order to reduce cost.
  • Silicon (or other semiconductor) handles are used when it is advantageous to integrate electronic circuitry, such as power conditioning circuits, with the handle.
  • silicon-on- sapphire (SOS) handles can be used when it is advantageous for the integrated electronic circuitry to be radiation hard.
  • Electrically insulating handles can also be used to integrate electronic circuitry with the device by providing conducting paths on the insulator to connect the semiconductor active layer 3003 with at least one separate die containing the electronic circuitry. The separate die may be flip chip bonded to the insulating handle, which may be optically transparent.
  • the interconnect stack 3002 consists of one or more layers of conductors 3007 in a dielectric medium 3008.
  • the conductors can be any low resistance material, including aluminium, copper or sp 2 -bonded carbon.
  • the dielectric medium 3008 can be any compatible insulating material, including silicon dioxide, carbon-doped silicon dioxide or sp 3 -bonded carbon. A good thermal conductor is typically used.
  • the conductors 3007 interconnect the junction devices in the semiconductor active layer 3003 and also provide connections to external power lines. The connections to external power lines can be through vias 3005 formed in the handle substrate 3001, or by running the conductors to the edge of the interconnect stack 3002 to provide electrical contacts, as shown.
  • the semiconductor active layer 3003 includes arrays of solar cell devices, which are not shown for the sake of clarity. In the described embodiments, these are lateral field p-i-n solar cell devices as described above. However, a wide variety of different junction architectures are possible. Examples of additional device structures that are compatible with the overall solar cell architecture described herein are described in US Patent Application Nos. 61/214,305 and 61/218,862.
  • the passivation layer 3004 consists of layers of coatings that act to passivate and protect the semiconductor surface and to trap light within the semiconductor. Techniques for forming these layers are well known in the art.
  • Figure 4 illustrates a method for forming ultra-thin single crystal photovoltaic devices such as that shown in Figure 3. Not shown or described are standard steps known to those skilled in the art for preparing a substrate for semiconductor processing, including cleaning and stripping steps.
  • the process starts with a single crystal semiconductor substrate 3003 or alternatively a thin-film semiconductor-on-insulator (SOI) substrate.
  • the single crystal semiconductor substrate can be a conventional bulk, single-crystal silicon wafer. It can be of any available thickness, but is typically in the range of 400 to 600 microns.
  • the thin-film SOI substrate can be an SOI wafer formed using any available and known process, including SIMOX processes and bonded wafer SOI processes known to those skilled in the art.
  • the silicon layer on a SOI wafer should be approximately equal to the desired thickness of the final silicon layer 3003 in the device, as described further below.
  • Step 4001 n- and p-type impurities are introduced into selected regions 3006 of the single crystal semiconductor using standard patterning and doping techniques well known in the art. It should be understood that the doped regions are represented schematically as regions 3006 in Figures 3 and 4 for the sake of simplicity, and further details of actual doping structures formed within the semiconductor are described below.
  • the impurities may be introduced by many techniques well known in the art.
  • impurities may diffuse into the semiconductor from a solid source deposited on the surface of the semiconductor.
  • the n-type dopant phosphorus may be introduced by depositing a layer of phosphorus-doped silica glass (PSG) on the semiconductor surface.
  • PSG phosphorus-doped silica glass
  • the impurities diffuse from the source into the semiconductor upon thermal processing.
  • boron is used for the p-type dopant and phosphorus is used for the n-type dopant.
  • the boron may be introduced before the phosphorus because boron is less mobile than phosphorus and therefore will not diffuse as significantly under further thermal processing.
  • Patterned areas of dopant introduction can be obtained using techniques well known to one skilled in the art, such as depositing and selectively removing a barrier material, such as silicon nitride or undoped silicon dioxide, to allow dopant penetration only where desired.
  • impurities are introduced through recesses or trenches formed in the surface of the semiconductor, as described further below.
  • the interconnect stack 3002 is formed on the semiconductor substrate 3003 using conventional semiconductor processing techniques, although it will be apparent to those skilled in the art that the interconnect stack 3002 can alternatively be formed on the handle substrate 3001.
  • the conductors 3007 can be formed of aluminium doped with copper and silicon in order to reduce electro-migration
  • the dielectric 3008 can be formed of silicon dioxide, possibly doped with impurities such as carbon.
  • the dielectric can be formed from silicon dioxide glasses that are deposited by PECVD, spun onto the exposed surface, or applied using other well known techniques.
  • the aluminium can be deposited using PVD and the deposited layer can be planarized using CMP, although sufficient planarity can often by achieved without the use of CMP.
  • the aluminium layer can be patterned into wires by using conventional optical photolithography.
  • the conductors can be formed of copper or conductive carbon in order to further reduce electromigration.
  • the dielectric medium 3008 can be of an insulating material that is thermally conductive.
  • Step 4003 the completed photovoltaic device of Figure 4-B is bonded to the handle substrate 3001.
  • Techniques for bonding two substrates are well-known in the art.
  • the exposed surface of the interconnect stack is planarised and bonded to an activated surface or layer disposed upon the handle substrate.
  • plasma nitridation of a silicon oxide layer is used to increase the bond energy between the two surfaces.
  • the substrates are bonded by fusion bonding, involving a first wafer bonding step and an optional second bond strengthening step. Prior to bonding, the surfaces to be bonded are cleaned so that they are sufficiently free of particles and are sufficiently flat to enable wafer fusion bonding to occur.
  • the surfaces of the respective substrates further undergo one or more optional surface activation steps, such as chemical treatment or deposition of one or more layers, or physical treatment to improve the chemical bonding strength.
  • a hydrogen covered/terminated silicon surface exhibits a surface energy E surf ⁇ 0.02 J/m 2 , involving a hydrophobic surface that results from a hydrofluoric acid wash to remove the native oxide from the underlying silicon.
  • the substrates are aligned so that the surfaces to be bonded are substantially parallel, and localized pressure is then applied substantially at the center of the two articles to be bonded.
  • This initiating localized pressure is typically applied to an external surface of one substrate while the other substrate is fixed, using a wafer bonding system such as those manufactured by the Electronic Visions Group and described at http://w ⁇ w.evgroup om/en/products/bonding/waferbonding/.
  • the bonding wavefront expands radially outward toward the periphery of the substrates and forms a first wafer bond.
  • the bond may be initiated at the edge of the substrates aligned appropriately to form an initial wedge with bonding wavefront expanding to close the gap between the two substrates.
  • the first bonding step is performed under vacuum.
  • the strength of the bonds holding the two substrates together via a first wafer bond can be strengthened via heating to a temperature of about 100-1000 °C, depending upon the materials utilized, and for a period of time ranging from 1 minute to several hours.
  • laser assisted bonding can be utilized, wherein optical radiation is utilized to impart thermal energy or activate a chemical process that improves the bond strength of the surfaces.
  • localized or substantially uniform bonding can be utilized via laser assisted bonding. For example, solders can be melted in specific regions such as interconnect paths between the active substrate and the handle. The general method of local bonding regions between the two articles can be used to manage stress.
  • semiconductor glues or waxes are be used to bond the two substrates together.
  • the semiconductor or SOI wafer is thinned from the backside in step 4004.
  • backside removal is typically performed by a combination of grinding, polishing, and chemical etching, but other methods known in the art may alternatively be used.
  • the surface remaining after thinning does not need to be smooth. Indeed, a rough final surface can enhance the light-trapping capabilities of the device.
  • the substrate layer can be removed by a wet etch, with the oxide layer acting as an etch- stop.
  • contacts 3005 are made to the conductors in the interconnect stack of the solar cell device. In some embodiments, these are formed through the handle wafer (e.g., by etching or by laser or ion beam machining) as shown in Figure 4-E, or by running metal interconnects to the edge of the solar cell. In some embodiments, the contacts are formed in the handle prior to bonding.
  • passivating, anti-reflective and protective coatings 3004 are formed on the exposed silicon surface, as described in the lateral field device patent application and/or using standard methods known to those skilled in the art. High aspect ratio photovoltaic devices
  • the lateral field devices described above are formed by the selective introduction of dopant impurities, such as boron and phosphorus, into the semiconductor lattice.
  • dopant impurities such as boron and phosphorus
  • These impurities can be introduced using conventional semiconductor processing techniques, including implantation and diffusion into the planar surface of a silicon wafer. However, these techniques are limited in their ability to form deep, high aspect ratio doped regions.
  • the methods described below overcome these limitations by introducing the impurities through physical features or recesses etched into the surface of the semiconductor.
  • Figure 5 depicts various types of physical features that can be formed by using different methods for etching bulk single crystal semiconductors 5014.
  • High aspect ratio features 5010, 5013 and 5015 can be produced via many techniques, including dry etching (e.g., the Bosch method, advanced silicon etch methods, and through silicon deep via technologies), laser micromachining and undercutting beneath a mask.
  • Mask layers 5011 and 5012 are typically silicon-nitride and silicon oxide, respectively, although other materials may be used.
  • Figure 6 depicts several methods that can be used to form impurity doped regions through trenches etched into a semiconductor, including solid-phase diffusion ( Figures 6a and 6b), ion implantation ( Figures 6c and 6d), and a combination of solid-phase diffusion and ion implantation ( Figures 6e and 6f).
  • impurities are introduced via diffusion from solid-phase materials deposited in the trenches, with an n-type impurity source in trenches that are desired to be n-doped 6011 and a p-type impurity source in trenches that are desired to be p-type 6021.
  • the trenches that are to be doped n-type are first filled with the n-type dopant source material, and then the trenches that are to be doped p-type are etched and filled with the p-type dopant source material.
  • all of the trenches are formed in a single etch step, with photo-resist used to selectively deposit impurity source material in the desired trenches.
  • thermal processing drives the impurities into the semiconductor, causing the trench sidewalls and bottoms to be selectively doped n-type 6012 or p-type 6022, as appropriate.
  • the dopant source material is poly-silicon deposited in a silicon substrate, then the polysilicon can be left in place and will partially crystallize during thermal processing.
  • the source material is a silica glass, the glass can be removed with an HF wet etch and the trenches can then be filled with a conductive material.
  • n- and p-type trenches are formed by the use of photo-resist to select the trenches to be doped with the different species.
  • the ion implantation is performed at different angles, as represented schematically by the arrows in these Figures.
  • the trenches are selectively doped by a combination of diffusion from a solid source and ion implantation.
  • This method has the advantage of using a single polysilicon deposition to fill both types of trench and to provide the doping for one type.
  • Figure 7 depicts a method for solid-phase doping through trenches, in which successive (or alternative in some cases) processing steps are illustrated as adjacent trenches proceeding from left to right in each part of the Figure.
  • the trenches are represented in Figure 7 as having substantially rectangular cross-sections, in practice the trenches may have rather different shapes.
  • an etched trench (left-hand trench of 7001) is filled with an impurity-containing glass 7050 capable of diffusing a high concentration (10 15 -10 20 cm "3 ) of a specified dopant species into the semiconductor layer.
  • the wafer is annealed (center trench of 7001), driving impurities into the semiconductor.
  • the doped glass 7050 is then stripped from all surfaces to reveal a trench 7052 (right-hand trench of 7001) with doped sidewalls and bottoms.
  • the diffused regions 7051 can be electrically contacted by complete 7053 or partial 7054 coverage and filling of the trench 7052 with metallic or semiconducting layers, such as poly-silicon.
  • a deposited poly-silicon layer 7054 can be subsequently implanted to achieve a high dopant concentration, or can be deposited as an in situ-doped polysilicon layer.
  • a contact layer such as Ti/TiN can be directly deposited forming a liner 7055, as shown in the right-hand trench of 7002.
  • a low resistance electrode 7056 is then formed to contact the doped region.
  • Lateral isolation can be achieved using a highly conformal chemical vapor deposition (CVD) of TEOS-oxide (not shown), with trench/via/plug metallization formed by MOCVD of tungsten, and with optional MOCVD-TiN as a barrier layer.
  • CVD chemical vapor deposition
  • MOCVD metal-organic chemical vapor deposition
  • Etch-back for metal plug formation is performed via dry etch or chemical mechanical polish (CMP).
  • CMP chemical mechanical polish
  • the lateral electrical connection of, for example, tungsten-filled trenches with an uppermost metal level of the device can be performed by standard Al metallization.
  • high aspect ratio, lateral field p-i-n photovoltaic devices are formed with doped regions extending deep into the interior of a bulk or thin-film semiconductor.
  • Figure 8 shows the process flow for producing these devices in thin film, single-crystal silicon.
  • these devices can be formed in other semiconductors, which may be in bulk or in thin-film form, including, for example, amorphous silicon (a-Si), cadmium telluride CdTe, copper-indium-gallium-sulfur-selenide (CIGS), gallium- indium-nitride (GalnN), and gallium arsenide (GaAs), to name but a few well-known semiconductors.
  • a-Si amorphous silicon
  • CdTe copper-indium-gallium-sulfur-selenide
  • GaN gallium- indium-nitride
  • GaAs gallium arsenide
  • a PADOX/nitride comprising a thermally-grown silicon oxide layer 8112 and an overlying silicon nitride layer 8111 , is formed on the surface of a prepared, clean single crystal silicon substrate 8114. During growth of the oxide 8112, the backside of the substrate 8104 may also be exposed to form an oxide layer 8100 on the backside of the substrate 8104.
  • a set of mutually spaced high-aspect ratio trenches or features 8200 are formed in the substrate 8104, extending from the substrate surface to a depth Di below the surface. In the described embodiments, the depth Di depends on the final thickness of the silicon layer.
  • trenches extending 60-80% into the final silicon layer have been found to provide good collection efficiency without punching through to the underlying oxide.
  • the trench depth Di is selected to be about 4, 8, and 16 ⁇ , respectively.
  • the term "aspect ratio" when applied to a feature such as a trench or recess refers to the ratio of the depth of the feature to its width.
  • the term “high aspect ratio” refers to an aspect ratio greater than 1 :1 (i.e., the feature is deeper than it is wide), and typically greater than 2: 1.
  • Standard silicon dry etch tools and processes available today can form trenches with aspect ratios as high as 40: 1, although this is generally limited by factors such as feature width, spacing between features, and the like.
  • a doped layer 8201 is deposited on the entire front side of the patterned substrate.
  • the doped layer 8201 can be a doped glass, polysilicon or other impurity- carrying material capable of altering the conductivity type of the semiconductor.
  • the deposited layer 8201 is a phosphorous doped silicon oxide (PSO) deposited by plasma-enhanced chemical vapour deposition (PECVD).
  • the thickness of the doped layer 8201 is selected to form a conformal coating lining the bases and sidewalls of the trenches 8200, as shown in Figure 8 A, and at step 8004, a not- intentionally-doped silicon oxide (NSO) 8102 is deposited to fill the trenches 8200 and serve as a diffusion barrier and protective cap, also as shown in Figure 8A.
  • NSO not- intentionally-doped silicon oxide
  • the diffusion barrier layer 8102 is omitted, and the doped layer 8201 is deposited to fill the trenches 8200, as shown in Figure 8B (refer step 8005, for example).
  • Step 8005 a second set of high aspect ratio trenches 8300 interleaved with the first set 8200 is formed, extending deep into the interior of the substrate 8014.
  • the depth D 2 of the second set of trenches 8300 is equal to the depth Di of the first set of trenches 8200.
  • the second set of trenches may be deeper than, or shallower than, the first set of trenches 8200, as described further below.
  • a doped layer 8301 capable of inducing the opposite conductivity type is disposed across the entire substrate surface, forming plugs 8302 that substantially fill the trenches 8300 with material that will induce conductivity of the opposite type of the preceding doped layer 8201.
  • the material 8301 is boron-doped silicon oxide (BSO).
  • BSO boron-doped silicon oxide
  • PSO and BSO are capable of diffusing phosphorus and boron impurities into the immediately surrounding silicon, with well defined penetration depth into the sidewalls and base of each trench.
  • Step 8008 during thermal treatment, dopant impurities diffuse in all directions from the filled trenches 8202 and 8302. Regions 8203 and 8303 formed after diffusion and activation annealing are thus composed of n-type phosphorus doped silicon (P:Si) and p-type boron-doped silicon (B:Si), respectively.
  • P:Si n-type phosphorus doped silicon
  • B:Si p-type boron-doped silicon
  • the penetration depth and concentration of diffused species is controlled by: (i) the doping density in the initial doping layer deposited; (ii) the impurity species and its diffusivity in Si; (iii) the quality of the doping layer/silicon interface; (iv) the diffusion vector relative to the Si crystallographic directions; (v) the temperature and thermal budget of the activation step; and (vi) point defect concentrations in the regions 8203 and 8303 during thermal processing.
  • Step 8009 shows the depleted doped-glasses 8200 and 8300 removed and stripped from the surface, where the (typically silicon nitride) barrier layer 8111 prevents the oxide 8112 from being removed.
  • the initial PADOX/nitride layers 8111, 8112 can be optionally removed and one or more high quality insulating dielectric layers 8120, 8121 formed as shown.
  • the initial PADOX/nitride layers 8111, 8112 can be optionally removed and one or more high quality insulating dielectric layers 8120, 8121 formed as shown.
  • two layers are formed: a first layer 8120 of high quality, low-trapped charge silicon-oxide, and a second, overlying layer 8121 of a not- intentionally doped glass or an electrically insulating dielectric suitable for use with an electrical interconnect.
  • a uniform metal contact layer 8123 is deposited and patterned to electrically isolate regions of opposite conductivity-type 8203 and 8303.
  • this layer 8123 is composed of Ti or TiN, although other high quality contact materials can be alternatively used.
  • high conductivity electrical interconnect metal or alloy is deposited and patterned to produce low resistance Ohmic contacts 8125 and 8126 to the doped silicon regions 8203 and 8303, respectively.
  • these electrical interconnect and doped regions are patterned to produce densely packed lateral field p- i-n devices using an inter-digitated electrode topology, as described in US Patent Application Nos. 61/214,305 and 61/218,862.
  • other electrode configurations can be used in other embodiments.
  • step 8014 the electrodes 8125 and 8126 are encapsulated within an insulating dielectric material 8127 to produce the completed silicon device wafer 8130.
  • the p-type and n-type trenches have the same depth and aspect ratio in the embodiments described above, this need not be the case in other embodiments, as in the embodiments 8015 and 8016 shown in Figure 8F, which can provide improved operation where substantially different carrier mobilities and/or carrier lifetimes in the semiconductor material of the substrate.
  • another conductivity type layer 8162 is formed on the opposite face (i.e., the backside) of the substrate to provide a region that is electrically connected to the doped regions 8161 having the same conductivity type.
  • the resulting structure 8016 is a hybrid photovoltaic device capable of producing substantially high conversion efficiency by utilizing a majority of the bulk semiconductor volume.
  • the completed single crystal silicon devices are wafer bonded to a low cost electrical interconnect backplane, as shown in Figure 8G.
  • the backplane comprises an insulating substrate 8173, an insulating dielectric 8172, electrical contacts 8171, and an electrical joining compound 8170.
  • Compound 8170 may comprise solder or paste, enabling high integrity and uniform electrical interconnection between the processed silicon device substrate and the backplane.
  • the resulting bonded article is shown in step 8018.
  • the major benefit of this arrangement is the ability to produce a large array of processed silicon wafers that can be wafer bonded to a single large planar backplane.
  • Steps 8019 and 8020 of Figure 8H depict one method of forming a thin film of single crystal silicon containing processed electrical devices and coupled to a handle substrate or backplane, where the bonding compound has been omitted for clarity.
  • a relatively thick bulk silicon substrate 8180 is used for the initial CMOS style device processing, as shown in step 8021, followed by etching and/or grinding of a majority of the backside silicon surface to a depth X 8185.
  • annular (or other peripheral shaped) portion 8182 of the bulk silicon substrate of width 8181 can be exempt from removal to provide a mechanically robust support for the device layer. If the handle layer 8173 is subsequently removed, the integrity and ease of handling the thinned device layer can be achieved by way of this annular portion 8182.
  • a protective coating and or passivation layer 8184 can be deposited on the etched portion of the substrate, as shown in step 8022.
  • ion implantation is used to introduce impurity species into the semiconductor trench sidewalls and bases as an alternative to doped glasses, allowing the number of manufacturing steps to be reduced. Furthermore, when ion implantation is used, there is no need to remove glass from the deep trenches, which can be relatively difficult in very deep trenches with high aspect ratios.
  • Figure 9 shows the doped trenches created in the previous process after wafer thinning.
  • Figure 9a shows the wafer thinned to the depth of the doped trench bases, with a surface passivation/anti-re flection coating (which may be provided by residual oxide if the semiconductor layer was originally part of an SOI wafer) on the photon-receiving surface of the semiconductor.
  • FIG. 9b shows the wafer thinned to a smaller depth so as to leave some undoped silicon between the silicon surface the doped trench base regions. This provides 100% active photon collection area at the surface, at the expense of reduced electric field strength at the silicon surface.
  • Optoelectronic, photovoltaic and/or electronic devices can attain higher performance in thin, single crystal silicon than in bulk, single crystal silicon.
  • Thin, single crystal silicon SOI substrates are typically formed by bonding a silicon wafer to a support substrate and then thinning the bulk, single-crystal silicon wafer by etching, grinding and polishing, a process referred to in the art as bond and etch-back SOI, or BESOI.
  • BESOI bond and etch-back SOI
  • Described herein is a modification of the smart-cut process, in which ion implantation into the high aspect-ratio trench or recess features formed in the semiconductor surface and typically extending 0.1 to lOOum into the semiconductor crystal is used to form a non-planar fracture zone that allows the top-most layer to be removed without significant "kerf loss.
  • the resulting non-planar surface has desirable optical properties, as described below.
  • Relatively high energy implantation may be required to form a fracture zone deep within the semiconductor.
  • Figure 10 shows the depth of the peak of the depth distribution of hydrogen ions (H+) beneath a bulk Si surface as a function of the hydrogen implant energy.
  • An energy of greater than lOOkeV is required to form a peak ion distribution ⁇ 1 micron beneath the surface.
  • An energy approaching lMeV is required to form a peak 10 microns or deeper in the silicon.
  • Figures 11-16 illustrate the steps of the layer transfer process described herein.
  • Figure 11 shows the implantation of H+ ions or other light ions (e.g., He, B or P) 3100 into patterned semiconductor substrates 3101, 3102 with features 3103, 3104 such as trenches of different widths formed in the respective substrates 3101, 3102.
  • Protective and implant mask layers 3105 and 3106 enable implanted species 3100 to penetrate into only the exposed portions of the substrates 3102, 3103, being limited to the trenches themselves in these embodiments 3001, 3002.
  • the implanted species form defective regions 3108 and 3109.
  • the implanted regions 3103 are commensurately wider than the regions 3109 and are substantially parallel to the remaining surface of the substrate 3101.
  • the substrate 3102 and ion beam 3100 are not mutually orthogonal but are inclined at an angle 3110 or 3111, then implanted regions 3112 and 3113 are formed that extend substantially beneath the protective cap layers 3105 and 3106.
  • Steps 3005 and 3006 of Figure 13 show the effect of increasing the angle of the trenches/substrate relative to the implant beam while keeping the lateral trench width constant.
  • the upper part of Figure 14 shows 3007 a silicon wafer with trenches 3120 following masked and angle-varied H+ implantation as described above to form a buried non- planar defective region 3122.
  • the lower part of the Figure shows 3008 the wafer flip- bonded (i.e., face down) onto a handle substrate 3123.
  • thermal activation 3131 of the H+ implanted regions 3122 generates volume expansion of region 3122, producing a net force 3128 that separates the device layer 3126 from the remaining bulk substrate 3127. Due to the multi-angle implantation through the trenches, the separated surfaces 3129 are highly non-planar and may also exhibit roughness on a smaller length scale both of these non-planarities being advantageous for light scattering and light-trapping.
  • a bulk silicon substrate is prepared using a standard cleaning process at step 1702 and then patterned at step 1704 using a standard lithography process.
  • a standard subtractive process e.g., deep reactive ion etching
  • recessed features e.g., trenches
  • high aspect ratio features typically deep and/or high aspect ratio features
  • one or more light ion species capable of forming a buried fracture zone are then implanted into the recessed features at a plurality of different angles (i.e., relative orientations) to produce a buried non-planar defect region due to the implantation angles and the shape or shapes of the recessed features.
  • the ion implantation involves implantation at multiple energies and/or multiple implant species (in addition to the multiple implant angles).
  • a single ion species is implanted at two different energies; in other embodiments, two different ion species (e.g., H and He ions) are implanted at either the same or different energies.
  • microelectronic devices are fabricated between the trenches using substantially standard MEMS and CMOS style processes, modified so that the thermal budget avoids premature layer separation.
  • the top surface of the substrate is bonded to a low-cost handle substrate or backplane using a standard bonding process.
  • the bonding process can include fusion or anodic wafer bonding, or adhesive bonding, or other standard bonding processes known to those skilled in the art.
  • the bonded pair is thermally processed to cause the defective region to form a continuous fracture zone so that the bulk silicon substrate splits into two portions, comprising the thin layer (containing the devices) bonded to the handle backplane, and the bulk silicon below the fracture zone.
  • the first of these provides the completed device wafer 1716, and the remaining portion of the bulk silicon substrate can be polished and reused at step 1718.
  • the use of H+ ions for the implantation step 1708 provides the additional advantage of passivating defects in the active layer.
  • Figure 18 is a schematic illustration of an embodiment combining the zip-cut layer transfer process with the embodiment of step 8018 or 8021, incorporating high aspect ratio lateral field p-i-n photovoltaic devices and bonded interconnect backplane.
  • Incident solar radiation 1802 enters the active region semiconductor 1804 through an antireflection coating 1806 reducing reflected optical energy 1808 formed on the non- planar surface formed by the Zip-Cut interface.
  • Laterally disposed high aspect ratio p- type 1810 and n-type 1812 regions collect photo-generated electrons and holes.
  • Unabsorbed light 1814 is reflected from the backside metalized contacts 1816, metal electrodes 1818, and dielectric layers comprising the electrically insulating materials in the interconnect stack.
  • the regular pattern of in-plane and out-of-plane dielectric regions and metal contacts can also be used to form high efficiency reflective and diffractive function to aid in the light-trapping of solar radiation in the active semiconductor layer 1804, as described in US Patent Application Nos. 61/214,305 and 61/218,862.
  • a second semiconductor layer 1902 is formed over a first semiconductor layer 1904, where the first and second layers 1902, 1904 have respective band gap energies E G i ⁇ E G2 incident solar radiation 1906 enters the second active semiconductor layer 1902 through an antireflection coating 1908.
  • incident high energy photons with ⁇ > EG 2 are preferentially absorbed in the second semiconductor layer 1902, whereas most lower energy photon E ⁇ EQ 2 will pass through this layer 1902 to the underlying first semiconductor layer 1904.
  • Low energy photons EQ 2 > ⁇ > EGI are preferentially absorbed in the first semiconductor layer 1904.
  • Lateral field, high aspect ratio p-type 1910 and n-type 1912 regions collect photo- generated electrons and holes.
  • unabsorbed light is reflected from backside metalized contacts 1914, metal electrodes 1916 and dielectric layers comprising the electrically insulating materials in the interconnect stack.
  • the regular pattern of in-plane and out-of-plane dielectric regions and metal contacts form high efficiency reflective and diffractive structures to aid in the trapping of solar radiation in the active semiconductor layers 1902, 1904.
  • the interconnect stack can be bound to a handle substrate 1918.
  • the handle can be of any suitable material, including, metal, glass or silicon. Photo-generated carriers collected from the active region are conducted to external power circuitry via interconnects that run to the edge of the module or through the handle.
  • silicon is used as the first semiconductor 1904 and a wide band-gap material is used as the second semiconductor 1902.
  • Amorphous silicon or microcrystalline silicon can be used as the wide band-gap material.
  • Techniques for depositing films of amorphous silicon and microcrystalline silicon are well-known in the art and include techniques based on plasma-enhanced CVD.
  • Compound semiconductors such as indium-aluminium-gallium-nitride (InAlGaN), gallium phosphide (GaP), cadmium telluride (CdTe), compounds of cadmium telluride (CdZnTe or CdSSe) and copper-indium-gallium-sulphur-selenide (CIGS), can also be used as the wide band-gap materials.
  • Techniques for depositing or growing these films are well-known in the art and include MOCVD, MBE and other epitaxial growth techniques.
  • Vicinal surface orientations of silicon such as (1 1 1)- and (21 l)-orientations favor the high quality epitaxy of CdTe and or CdZnTe and or CdSSe compositions.
  • Copper-indium-gallium-sulphur-sellenide (CIGS) may also be utilized with the advantage of requiring only a high quality intrinsic epilayer upon a silicon backplane.
  • Gallium phosphide (GaP) can also be used, as it possesses a larger band gap than silicon and it has very low lattice mismatch with crystalline silicon.
  • GaP is an indirect bandgap semiconductor, as known to those skilled in the art, it can be engineered to exhibit favourable absorption properties for solar cell operation. For example, high doping levels can enhance the higher energy absorption due to phase space filling effects at the lowest lying indirect valley.
  • Figure 20 is a schematic diagram representing the spatial arrangement of energy bands associated with the impurity doped regions 1910, 1912 of the first semiconductor 1904, the second, wide bandgap semiconductor 1902, and the sealing layer 1908.
  • Doped regions 1910 are n-type and regions 1912 are p-type.
  • the not- intentionally-doped (NID) regions between the doped regions 1910, 1912 have substantially the same carrier concentration as the initial semiconductor prior to processing.
  • the resulting modulation doping of the lateral field p-i-n structure along the x-direction 2001 acts to separate electrons and holes.
  • Hot electron 2002 and hole 2004 pairs photo-created by direct absorption of high energy incident photons 2006 can drift and diffuse laterally along the surface or be transported across the heterojunction formed between the first and second semiconductors 1904, 1904.
  • the heterojunction can have a large conduction or valence band offset.
  • a hot electron 2008 experiences a large energy step upon being transported along a vector substantially parallel to the Z-direction 2010 and toward the first semiconductor 1904 and is efficiently collected by the p-i-n devices.
  • Figure 21 illustrates an alternative embodiment, wherein the first semiconductor layer 1902 is no thicker than the doped regions 1910, 1912, so that a majority of the absorbed high energy species are generated in the second semiconductor 1902, enabling efficient carrier transport to the lateral field p-i-n backplane.
  • Figures 20 and 21 also show an environmental sealing layer 1908 that also functions as an antireflection coating.
  • This layer 1908 is typically composed of stoichiometric or non-stoichiometric aluminium oxide (AI 2 O 3 ), silicon-dioxide (Si0 2 ) and silicon nitride (S1 3 N 4 ), although other materials can be alternatively used.
  • AI 2 O 3 stoichiometric or non-stoichiometric aluminium oxide
  • Si0 2 silicon-dioxide
  • Si1 3 N 4 silicon nitride
  • Introducing trapped charges into the layer 1908 can be used to preferentially enhance the carrier transport in the wide band gap semiconductor layer 1902.
  • trapped positive or negative charges can form an inversion, accumulation or depletion layer at the interface between the sealing layer 1908 and the wide bandgap semiconductor layer 1902.
  • Such control can be used as an effective field effect to modify the surface recombination velocity at and within the second semiconductor layer 1902.
  • the photovoltaic device can be optimised in this respect.
  • the first semiconductor layer 1904 is typically composed of high quality and high resistivity silicon.
  • the thickness of this silicon layer 1904 is typically in the range of ⁇ 0.1-100 ⁇ , and is patterned and processed to form a plurality of lateral field p-i-n diodes electrically interconnected in series and/or parallel.
  • the second semiconductor 1902 is typically hydrogenated amorphous silicon having a band gap in the range of 1.5-2.0 eV.
  • the wide band gap semiconductor 1902 is GaP, InAlGaN, CIGS or CdTe.
  • the environmental sealing layer 1908 is selected to provide a high degree of passivation of the second semiconductor layer 1902, and is selected to have a high bandgap energy substantially transparent to the incident solar radiation.
  • one of the two sets of doped regions 1910, 1912 extends into the wide bandgap layer 1902, while the other set (for example, doped regions 1912) remains confined within the narrow bandgap layer 1904.
  • a graded bandgap semiconductor layer is disposed on the narrow bandgap layer 1904 instead of the wide bandgap layer 1902.
  • the trenches are alternately filled with different semiconductors to form a lateral heterojunction device.
  • the photovoltaic devices described herein do not suffer from topside electrode obstruction of incident solar radiation and provide substantially greater effective depletion region volumes capable of separating photo-created charge carriers.
  • the high-aspect ratio, lateral field p-i-n solar cells with thinned backsides described herein enable long carrier lifetimes by the defect-free, single crystal semiconductor active layer. Carrier diffusion lengths of more than 100 microns are typically achieved. This enables the majority of the carriers that are generated by absorbed photons to be collected.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

Cette invention concerne un dispositif photovoltaïque comprenant une couche de semi-conducteur dans laquelle sont formées des cellules solaires photovoltaïques, un substrat raidisseur et une couche d'interconnexion disposée entre la couche de semi-conducteur et le substrat raidisseur. Ladite couche d'interconnexion comprend des pistes conductrices en contact électrique avec les cellules solaires photovoltaïques dans la couche de semi-conducteur. L'invention concerne en outre un procédé de production d'un dispositif photovoltaïque, comprenant les étapes consistant à : former une couche d'interconnexion plane présentant des pistes conductrices isolées, ladite couche d'interconnexion plane étant formée sur le substrat semi-conducteur ou sur un substrat raidisseur plan ; souder l'autre des deux substrats à la couche d'interconnexion pour former un empilement soudé dans lequel les pistes conductrices sont en contact électrique avec les dispositifs photovoltaïques ; et amincir le substrat semi-conducteur au moins pour réduire l'épaisseur du substrat semi-conducteur entre une face et les dispositifs photovoltaïques afin d'améliorer l'efficacité des dispositifs photovoltaïques.
PCT/US2011/051264 2011-08-02 2011-09-12 Dispositif photovoltaïque et procédé de production d'un dispositif photovoltaïque WO2013019250A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161514422P 2011-08-02 2011-08-02
US61/514,422 2011-08-02

Publications (1)

Publication Number Publication Date
WO2013019250A1 true WO2013019250A1 (fr) 2013-02-07

Family

ID=47629570

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/051264 WO2013019250A1 (fr) 2011-08-02 2011-09-12 Dispositif photovoltaïque et procédé de production d'un dispositif photovoltaïque

Country Status (1)

Country Link
WO (1) WO2013019250A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105689B1 (en) 2014-03-24 2015-08-11 Silanna Semiconductor U.S.A., Inc. Bonded semiconductor structure with SiGeC layer as etch stop
US9269608B2 (en) 2014-03-24 2016-02-23 Qualcomm Switch Corp. Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131984A (en) * 1976-05-26 1979-01-02 Massachusetts Institute Of Technology Method of making a high-intensity solid-state solar cell
US4352948A (en) * 1979-09-07 1982-10-05 Massachusetts Institute Of Technology High-intensity solid-state solar-cell device
US20110120531A1 (en) * 2008-04-15 2011-05-26 Renewable Energy Corporation Asa Method for production of wafer based solar panels

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131984A (en) * 1976-05-26 1979-01-02 Massachusetts Institute Of Technology Method of making a high-intensity solid-state solar cell
US4352948A (en) * 1979-09-07 1982-10-05 Massachusetts Institute Of Technology High-intensity solid-state solar-cell device
US20110120531A1 (en) * 2008-04-15 2011-05-26 Renewable Energy Corporation Asa Method for production of wafer based solar panels

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105689B1 (en) 2014-03-24 2015-08-11 Silanna Semiconductor U.S.A., Inc. Bonded semiconductor structure with SiGeC layer as etch stop
WO2015148212A1 (fr) * 2014-03-24 2015-10-01 Silanna Semiconductor U.S.A., Inc. Structure semi-conductrice liée comportant une couche de sigec en tant qu'arrêt de gravure
US9269608B2 (en) 2014-03-24 2016-02-23 Qualcomm Switch Corp. Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop

Similar Documents

Publication Publication Date Title
JP6652578B2 (ja) 薄膜はんだ接合
EP2609628B1 (fr) Dispositif photovoltaïque et module ayant une passivation améliorée et procédé de fabrication
US9748415B2 (en) Fast process flow, on-wafer interconnection and singulation for MEPV
US7863157B2 (en) Method and structure for fabricating solar cells using a layer transfer process
US7759220B2 (en) Method and structure for fabricating solar cells using a layer transfer process
US8753957B2 (en) Method for production of wafer based solar panels
KR101362688B1 (ko) 광전 변환 장치 및 그 제조 방법
US10686090B2 (en) Wafer bonded solar cells and fabrication methods
US20110174376A1 (en) Monocrystalline Thin Cell
WO2014127067A1 (fr) Photopiles à contact arrière et à jonction arrière à îlot monolithique utilisant des tranches massives
EP2256820A2 (fr) Dispositif photo-électronique comportant une jonction verticale p-n ou p-i-n et son procédé the fabrication
US8114702B2 (en) Method of manufacturing a monolithic thin-film photovoltaic device with enhanced output voltage
KR101396027B1 (ko) 고효율 후면 접촉 후면 접합 태양 전지의 이온 주입 및 어닐링
WO2013019250A1 (fr) Dispositif photovoltaïque et procédé de production d'un dispositif photovoltaïque
EP2056362A2 (fr) Convertisseur solaire multi-spectral à plusieurs jonctions
US20180226533A1 (en) Thin Film Solder Bond
KR101244791B1 (ko) 실리콘 웨이퍼의 텍스쳐링 방법, 태양전지의 제조방법 및태양전지
WO2015100392A2 (fr) Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique
KR101026587B1 (ko) 솔라셀 제조방법
WO2013175354A2 (fr) Procédé de fabrication d'un module de cellules solaires à jonction arrière avec contact arrière
CA2643540A1 (fr) Convertisseur solaire multispectral multijonction
JP2002198548A (ja) 光電変換装置
JP2015133339A (ja) 光電変換装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11870246

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11870246

Country of ref document: EP

Kind code of ref document: A1