WO2013018842A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2013018842A1
WO2013018842A1 PCT/JP2012/069627 JP2012069627W WO2013018842A1 WO 2013018842 A1 WO2013018842 A1 WO 2013018842A1 JP 2012069627 W JP2012069627 W JP 2012069627W WO 2013018842 A1 WO2013018842 A1 WO 2013018842A1
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Prior art keywords
insulating film
layer
upper electrode
resistance change
variable resistance
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PCT/JP2012/069627
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French (fr)
Japanese (ja)
Inventor
阪本　利司
宗弘 多田
信 宮村
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日本電気株式会社
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Publication of WO2013018842A1 publication Critical patent/WO2013018842A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2011-169399 (filed on August 2, 2011), the entire content of which is incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device in which a programmable logic device or a nonvolatile memory device having a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) is provided in a multilayer wiring layer, and It relates to the manufacturing method.
  • the resistance change element whose resistance is changed by applying a voltage can be used as a nonvolatile memory or a nonvolatile switch.
  • a non-volatile memory it is advantageous in that it can operate at a low voltage and can read out information faster than a conventional flash memory.
  • a non-volatile switch by using it as a switch in a programmable logic device, the element size is greatly reduced, and further improvement in power consumption and operation speed is expected.
  • the resistance change element is divided into a unipolar type and a bipolar type from the electric conduction characteristics.
  • a unipolar variable resistance element does not depend on the polarity of the applied voltage, and its resistance changes depending on the magnitude of the applied voltage.
  • the resistance of the bipolar variable resistance element changes depending on the polarity of the applied voltage.
  • FIG. 8A shows the resistance change element 10.
  • the resistance change element 10 has a structure in which the resistance change layer 13 is sandwiched between two electrodes (first electrode 11 and second electrode 12). The difference in electrode material, the resistance change layer material, etc. makes the electric conduction characteristics bipolar.
  • the electrode used for the bipolar variable resistance element is defined as follows. When a voltage is applied between the electrodes, a transition is made to a low resistance (on state) in the case of a high resistance (off state), and a low resistance state is maintained in the case of a low resistance. The higher potential at this time is defined as “first electrode”, and the lower potential is defined as “second electrode”.
  • FIGS. 8B and 8C respectively show a connection method for transitioning states and a schematic diagram of current-voltage characteristics.
  • the first electrode 11 is connected to the first node 14 to which the voltage source 16 is connected, and the second electrode is connected to the second node 15 that is grounded.
  • a positive voltage is applied to the voltage source.
  • the resistance change element 10 when the variable resistance element 10 is in the on state, there is no change in resistance, and the voltage and current are proportional.
  • the resistance change element 10 when the resistance change element 10 is in the off state, the resistance change element 10 changes from the off state to the on state at a certain threshold voltage. The change from the off state to the on state is called “set operation”, and the threshold voltage at that time is called “set voltage”.
  • a negative voltage is applied to the voltage source. When the variable resistance element 10 is in the off state, no current changes and no current flows.
  • the resistance change element 10 when the resistance change element 10 is in the on state, the state changes from an on state in which current flows at a certain threshold voltage to an off state in which no current flows.
  • the change from the on state to the off state is called “reset operation”, and the threshold voltage at that time is called “reset voltage”.
  • Patent Document 1 Non-Patent Document 1, and Patent Document 2 describe an example of a resistance change element using a metal precipitation phenomenon by an electrochemical reaction.
  • the variable resistance layer in the variable resistance element is an ion conductive layer capable of conducting metal ions
  • the first electrode is an oxidizable electrode that is oxidized by applying a voltage and supplies the metal ions to the variable resistance layer.
  • the second electrode is an electrode that does not participate in an electrochemical reaction such as an oxidation-reduction reaction.
  • a positive voltage is applied to the first electrode.
  • a part of the metal of the first electrode is converted into metal ions by an electrochemical reaction (oxidation reaction) and dissolved in the ion conductive layer.
  • metal ions in the ion conductive layer are deposited (reduced) as a metal at the interface between the second electrode and the resistance change layer, and a metal bridge in which the first electrode and the second electrode are connected is formed.
  • the first electrode and the second electrode are electrically connected via the metal bridge, so that the low resistance state (ON state) is obtained.
  • a negative voltage is applied to the first electrode. When a negative voltage is applied, a part of the metal bridge is cut and transitions to a high resistance state (off state).
  • metal ions are used as metal ions
  • copper is used as the first electrode serving as a supply source thereof
  • metal oxides such as tantalum oxide are used as an ion conductive layer, which further contributes to the reaction.
  • Platinum or ruthenium is used as the second electrode that is difficult to perform.
  • variable resistance element When the variable resistance element described above is used together with a conventional semiconductor element in a semiconductor integrated circuit (LSI; Large Scale Integration), the guaranteed operation period of the element is required to be 10 years or more, which is the same as that of the semiconductor element.
  • LSI semiconductor integrated circuit
  • the conventional resistance change element there is a problem of malfunction that even when the applied voltage is equal to or lower than the threshold voltage that causes the resistance change, the state transitions to another state due to deterioration over time. The problem caused by this malfunction is called “disturbance failure”. For example, in FIG. 8C, it is necessary to apply a voltage higher than the set voltage to the resistance change element to make a transition from the off state to the on state, while the resistance change element in the off state is the LSI operating voltage.
  • FIG. 9 shows a case where the first electrodes 11 of FIG. 8 are connected.
  • the electrodes to be connected can have a simpler structure by sharing one electrode.
  • FIG. 9 (b) shows the switch structure of FIG. 9 (a) with symbols.
  • the second node 27 is the first electrode 21, the first node 26 is the second electrode 23, and the third node 28 is the second electrode. 25.
  • the variable resistance element described above is formed in a multilayer wiring of an LSI.
  • the wiring material of the multilayer wiring is mainly composed of copper, and a method of efficiently forming a resistance change element in the multilayer copper wiring is desired.
  • Patent Document 3 and Non-Patent Document 2 disclose a technique for integrating a resistance change element using an electrochemical reaction in a semiconductor device. According to them, as shown in FIG. 10, the resistance change element is formed between two copper wirings (first copper wiring 31 and second copper wiring 35). A technique that also serves as one electrode is described.
  • the first copper wiring 31 is a wiring that goes in a direction perpendicular to the paper surface
  • the second copper wiring 35 is a wiring that goes in a direction parallel to the paper surface.
  • the resistance change element includes a first copper wiring 31 that also serves as a first electrode, a resistance change layer 33, and a second electrode 32.
  • the second electrode 32 and the second copper wiring 35 are electrically connected by a via 34.
  • FIG. 11 shows an example in which a resistance change element (see FIG. 8) is used for a crossbar switch.
  • the crossbar switch is a switch for selecting whether the respective lines are electrically connected or not connected to the intersections of the input lines X1 to XN, the output lines Y1 to YN, and the input line and the output line. It consists of a change element.
  • the crossbar switch is an important component of a programmable device such as an FPGA (Field Programmable Gate Array).
  • Non-Patent Document 2 describes a 32 ⁇ 32 crossbar switch using a resistance change element.
  • the crossbar switch is formed in a multilayer copper wiring, and the output line and the input line are each formed of a copper wiring.
  • FIG. 8 shows an example in which a resistance change element (see FIG. 8) is used for a crossbar switch.
  • the crossbar switch is a switch for selecting whether the respective lines are electrically connected or not connected to the intersections of the input lines X1 to XN
  • the cross section of the intersection of the input line and the output line is as shown in FIG. If the minimum feature size of the wiring and F, 1 single element of the crossbar switch is vertical and horizontal length is 2F, the area is 4F 2.
  • the copper wiring width and the distance between the wirings are equal to F.
  • FIG. 12 shows a crossbar switch using a complementary resistance change element (see FIG. 9).
  • the crossbar switch is a switch for selecting whether to electrically connect or not connect each of the input lines X1 to XN, the output lines Y1 to YN, and the intersection of the input line and the output line. It consists of a variable resistance element.
  • the input lines X1 to XN and the output lines Y1 to YN in FIG. 12 are copper wirings.
  • one element of the crossbar switch requires an area of 36F 2 according to the inventors' estimation, and requires 9 times as much area as the crossbar switch using the resistance change element of FIG. To do.
  • the main object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the number of steps or make the area of the resistance change element as small as possible.
  • a semiconductor device having two or more variable resistance elements inside a multilayer wiring layer on a semiconductor substrate, wherein the variable resistance element is interposed between a lower electrode and an upper electrode.
  • a variable resistance layer with variable resistance is interposed, and the wiring of a predetermined wiring layer in the multilayer wiring layer also serves as the lower electrode, and the upper electrode is formed in a line extending in one direction. And also serves as an upper electrode of another first variable resistance element adjacent to the variable resistance element along the one direction.
  • variable resistance elements are provided in the multilayer wiring layer, and are arranged in a two-dimensional array. It is formed in a line extending in a direction perpendicular to the direction, and also serves as a lower electrode of another second variable resistance element adjacent to the variable resistance element along the right direction in one direction. preferable.
  • the lower electrode includes a material serving as a metal ion supply source
  • the upper electrode is formed of a material that is less likely to be ionized than the lower electrode
  • the resistance change layer includes the metal It is preferable that the ion conductive layer is capable of conducting ions.
  • variable resistance layer is disposed so as to overlap the upper electrode.
  • a semiconductor device having two or more complementary variable resistance elements inside a multilayer wiring layer on a semiconductor substrate, wherein the complementary variable resistance element includes a lower electrode and a first electrode.
  • a second resistance whose resistance changes between the lower electrode and the second upper electrode at a position spaced apart from the first upper electrode is interposed between the first resistance change layer whose resistance changes between the upper electrode and the upper electrode.
  • the change layer is interposed, the lower electrode is arranged in a predetermined wiring layer in the multilayer wiring layer, and the first upper electrode is formed in a line extending in one direction, It also serves as a first upper electrode of another first complementary variable resistance element adjacent to the complementary variable resistance element along the one direction.
  • the complementary resistance change element has four or more inside the multilayer wiring layer and is arranged in a two-dimensional array, and the wiring of another predetermined wiring layer in the multilayer wiring layer Is formed in a line extending in a direction perpendicular to the one direction, and is adjacent to the second upper electrode and the complementary resistance change element along the direction perpendicular to the one direction. It is preferable that the second complementary resistance change element is connected to each of the second upper electrodes through vias.
  • the lower electrode extends in a direction perpendicular to the one direction from a region where the first upper electrode and a wiring of another predetermined wiring layer in the multilayer wiring layer overlap. 2 It is preferable that the upper electrode and the wiring of another predetermined wiring layer in the multilayer wiring layer are arranged in a region up to a region where they overlap.
  • the lower electrode includes a material serving as a metal ion supply source
  • the first upper electrode and the second upper electrode are made of a material that is less ionized than the lower electrode
  • the first variable resistance layer and the second variable resistance layer are preferably ion conductive layers capable of conducting the metal ions.
  • the first upper electrode and the second upper electrode are arranged in the same layer, and the first resistance change layer and the second resistance change layer are arranged in the same layer. .
  • the first variable resistance layer is disposed so as to overlap the first upper electrode
  • the second variable resistance layer is disposed so as to overlap the second upper electrode. Is preferred.
  • a step of forming a wiring groove extending in one direction with a predetermined length in the first interlayer insulating film, a step of embedding a lower electrode in the wiring groove, and the lower electrode Including a step of depositing a first barrier insulating film on the first interlayer insulating film, a step of forming two openings communicating with the lower electrode in the first barrier insulating film, and the first including the lower electrode.
  • a line-shaped first upper electrode and a first variable resistance layer extending in a direction perpendicular to the one direction so as to pass over one opening of the opening are formed, and the other opening of the two openings Block-like second upper arranged above Characterized in that it comprises a step of forming an electrode and the second resistance variable layer.
  • a second interlayer insulating layer is formed on the first barrier insulating film including the first upper electrode, the first variable resistance layer, the second upper electrode, and the second variable resistance layer.
  • the copper wiring used conventionally and the via for connecting to the copper wiring become unnecessary, the area of the resistance change element can be reduced, and the production thereof The number of processes can be reduced. Furthermore, the copper wiring that is no longer used can be used for other purposes.
  • FIG. 1A is a top view and FIG. 2B is a cross-sectional view schematically showing a configuration of a variable resistance element in a semiconductor device according to Example 1 of the present invention.
  • A Top view which showed typically the structure of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device based on Example 1 of this invention,
  • (b) (a) It is sectional drawing between XX '. It is process sectional drawing which showed typically the manufacturing method of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device which concerns on Example 1 of this invention.
  • 4A is a top view and FIG.
  • FIG. 5B is a cross-sectional view schematically showing a configuration of a complementary resistance change element in a semiconductor device according to Example 2 of the present invention.
  • A Top view which showed typically the structure of the crossbar switch using the complementary resistance change element formed in the multilayer copper wiring in the semiconductor device based on Example 2 of this invention
  • b (a FIG. 6 is a cross-sectional view taken along the line XX ′ in FIG. It is 1st process sectional drawing which showed typically the manufacturing method of the crossbar switch using the complementary resistance change element formed in the multilayer copper wiring in the semiconductor device which concerns on Example 2 of this invention.
  • the semiconductor device according to Embodiment 1 of the present invention is a semiconductor device having two or more variable resistance elements (100 in FIG. 2) inside a multilayer wiring layer on a semiconductor substrate (101 in FIG. 2),
  • the variable resistance element has a configuration in which a variable resistance layer (111 in FIG. 2) whose resistance changes is interposed between a lower electrode (105 in FIG. 2) and an upper electrode (112 in FIG. 2).
  • a wiring of a predetermined wiring layer in the wiring layer also serves as the lower electrode, and the upper electrode is formed in a line extending in one direction and adjacent to the resistance change element along the one direction. It also serves as the upper electrode of the other first variable resistance element.
  • the semiconductor device according to Embodiment 2 of the present invention is a semiconductor device having two or more complementary resistance change elements (200 in FIG. 5) inside a multilayer wiring layer on a semiconductor substrate (301 in FIG. 5).
  • a complementary resistance change element a first resistance change layer (311 in FIG. 5) whose resistance changes is interposed between the lower electrode (305 in FIG. 5) and the first upper electrode (313 in FIG. 5).
  • a configuration in which a second variable resistance layer (312 in FIG. 5) having a resistance change is interposed between the lower electrode and the second upper electrode (314 in FIG. 5) at a position separated from the first upper electrode.
  • the lower electrode is disposed on a predetermined wiring layer in the multilayer wiring layer, the first upper electrode is formed in a line extending in one direction, and the complementary resistance change element Another first phase adjacent to each other along the one direction with respect to Also serve as the first upper electrode type variable resistance element.
  • a step of forming a wiring groove extending in one direction in the interlayer insulating film (step in FIG. 3A) and a lower electrode are embedded in the wiring groove.
  • a step of forming a communicating opening step of FIG. 3B), a step of depositing a variable resistance layer on the barrier insulating film including the lower electrode (step of FIG. 3C), and the resistance change
  • a step of forming a wiring trench extending in one direction with a predetermined length in the first interlayer insulating film (step of FIG. 6A), A step of embedding the lower electrode in the wiring trench (step of FIG. 6A) and a step of depositing a first barrier insulating film on the first interlayer insulating film including the lower electrode (step of FIG. 6A)
  • a step of forming two openings communicating with the lower electrode in the first barrier insulating film step of FIG. 6B
  • a variable resistance layer on the first barrier insulating film including the lower electrode step of depositing (step of FIG. 6C), step of depositing the upper electrode layer on the variable resistance layer (step of FIG.
  • part of the upper electrode layer and the variable resistance layer Removing one of the two openings A linear first upper electrode and a first variable resistance layer extending in a direction perpendicular to the one direction so as to pass through, and a block-like shape disposed on the other opening of the two openings Forming a second upper electrode and a second variable resistance layer (step of FIG. 7A).
  • FIG. 1A is a top view and FIG. 1B is a cross-sectional view schematically showing a configuration of a variable resistance element in a semiconductor device according to Example 1 of the present invention.
  • FIGS. 2A and 2B schematically show the configuration of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device according to the first embodiment of the present invention, and FIG. It is sectional drawing between XX 'of (a).
  • FIG. 1 shows a variable resistance element that is one component of the crossbar switch.
  • FIG. 1 shows a variable resistance element that is one component of the crossbar switch.
  • the semiconductor device according to Example 1 has a multilayer copper wiring layer in which a multilayer copper wiring is formed in an insulator on a semiconductor substrate.
  • the semiconductor device has a resistance change element in the multilayer copper wiring.
  • the variable resistance element has a variable resistance layer 43 stacked on a portion of the first copper wiring 41, and a second electrode 42 is formed so as to cover the variable resistance layer 43.
  • the first copper wiring 41 extends in a direction perpendicular to the paper surface, and is another first resistor having the same structure adjacent along the direction perpendicular to the paper surface. It also serves as the first copper wiring 41 of the change element.
  • the second electrode 42 extends in parallel in the left-right direction with respect to the paper surface, and another second resistance change element (other It also serves as the second electrode (which is different from the first variable resistance element).
  • the resistance change layer 43 extends parallel to the paper surface in the left-right direction so as to overlap the second electrode 42, but is disposed only in the region where the first copper wiring 41 and the second electrode 42 overlap. May be.
  • the second electrode 42 is formed of a material different from copper between the two copper wirings in the multilayer copper wiring layer. In the conventional example, two layers of copper wiring are required to form the crossbar switch. However, according to the first embodiment of the present invention, only one layer of copper wiring may be used. As a result, process man-hours are reduced.
  • the area per one variable resistance element is 4F 2, is the same as the conventional example.
  • two layers of copper wiring were required.
  • two layers of crossbar switches were stacked in order to suffice for one layer.
  • a crossbar switch can be formed with twice the degree of integration.
  • FIG. 2 shows an example in which a crossbar switch using the resistance change element shown in FIG. 1 is formed inside a multilayer copper wiring layer on the semiconductor substrate 101.
  • the multilayer copper wiring layer has an insulating stacked body in which an interlayer insulating film 102, a barrier insulating film 103, an interlayer insulating film 104, a barrier insulating film 107, and an interlayer insulating film 120 are stacked in this order on the semiconductor substrate 101.
  • a first copper wiring 105 is embedded in a wiring groove formed in the interlayer insulating film 104 and the barrier insulating film 103 via a barrier metal 106.
  • a variable resistance layer 111 and an upper electrode 112 are formed on the first copper wiring 105.
  • the variable resistance element 100 is formed in a region where the first copper wiring 105 overlaps with the variable resistance layer 111 and the upper electrode 112.
  • the first copper wiring 105 corresponds to the first electrode 11 in FIG. 8A
  • the upper electrode 112 corresponds to the second electrode 12 in FIG.
  • the variable resistance element 100 is a variable resistance nonvolatile element, and can be, for example, a switching element that utilizes metal ion migration and an electrochemical reaction in an ion conductor.
  • the resistance change element 100 has a configuration in which a resistance change layer 111 is interposed between a first copper wiring 105 serving as a first electrode and an upper electrode 112 serving as a second electrode.
  • a barrier insulating film 107 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106.
  • the barrier insulating film 107 has an opening in a region where the variable resistance element 100 is formed.
  • the bottom surface of the variable resistance layer 111 and the top surface of the first copper wiring 105 are in contact with each other in the region of the opening formed in the barrier insulating film 107.
  • the bottom surface of the upper electrode 112 is in contact.
  • the resistance change element 100 performs switching between a high resistance state and a low resistance state by applying a voltage or passing a current, for example, metal ions included in the first copper wiring 105 into the resistance change layer 111. Switching is performed using diffusion caused by electrolysis.
  • An interlayer insulating film 120 is formed on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112.
  • the semiconductor substrate 101 is a substrate on which a semiconductor element (not shown) is formed.
  • a semiconductor substrate 101 for example, a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, a substrate such as a liquid crystal manufacturing substrate, or a silicon substrate provided with a multilayer copper wiring layer is used. be able to.
  • the interlayer insulating film 102 is an insulating film formed on the semiconductor substrate 101.
  • the interlayer insulating film 102 for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 102 may be a stack of a plurality of insulating films.
  • the barrier insulating film 103 is an insulating film having a barrier property interposed between the interlayer insulating films 102 and 104.
  • the barrier insulating film 103 serves as an etching stop layer when the first copper wiring 105 is processed.
  • As the barrier insulating film 103 for example, a SiN film, a SiC film, a SiCN film, or the like can be used.
  • the barrier insulating film 103 can be removed depending on the selection of the etching conditions for the wiring trench.
  • the interlayer insulating film 104 is an insulating film formed on the barrier insulating film 103.
  • the interlayer insulating film 104 for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 104 may be a stack of a plurality of insulating films.
  • a wiring trench for embedding the first copper wiring 105 is formed in the interlayer insulating film 104.
  • the wiring groove is a groove extending in a direction perpendicular to the paper surface in FIG.
  • a first copper wiring 105 is embedded in the wiring trench via a first barrier metal 106.
  • the first copper wiring 105 is a wiring buried in a wiring groove formed in the interlayer insulating film 104 and the barrier insulating film 103 via the first barrier metal 106.
  • the first copper wiring 105 also serves as the first electrode of the variable resistance element 100 and is in direct contact with the variable resistance layer 111 at a predetermined position.
  • An electrode layer or the like may be inserted between the first copper wiring 105 and the resistance change layer 111.
  • the upper electrode 112 and the resistance change layer 111 are deposited in a continuous process and processed in the continuous process.
  • copper capable of diffusing and ion conducting in the resistance change layer 111 is used.
  • the first copper wiring 105 may be alloyed with Al, silicided, or nitrided.
  • the barrier metal 106 is a conductive material having a barrier property that covers the side surface or the bottom surface of the first copper wiring 105 in order to prevent the metal contained in the first copper wiring 105 from diffusing into the interlayer insulating film 104 or the lower layer. It is a membrane.
  • the barrier metal 106 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). ), A refractory metal thereof, a nitride thereof, or a laminated film thereof.
  • the barrier insulating film 107 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106 to prevent oxidation of a metal (for example, copper) related to the first copper wiring 105 or in the interlayer insulating film 104. It has a role of preventing the diffusion of the metal related to the first copper wiring 105 to the metal.
  • a metal for example, copper
  • the barrier insulating film 107 for example, a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used.
  • the barrier insulating film 107 has an opening in a region where the first copper wiring 105 and the resistance change layer 111 on the first copper wiring 105 overlap.
  • the first copper wiring 105 and the resistance change layer 111 are in contact with each other.
  • the opening of the barrier insulating film 107 is formed in the region of the first copper wiring 105.
  • the variable resistance element 100 can be formed on the surface of the first copper wiring 105 having small irregularities.
  • the resistance change layer 111 is a film whose resistance changes.
  • the resistance change layer 111 can be made of a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of the metal related to the first copper wiring 105 (corresponding to the first electrode 11 in FIG. 8).
  • a film capable of ion conduction is used.
  • an oxide insulating film containing Ta such as Ta 2 O 5 or TaSiO can be used.
  • the resistance change layer 111 can have a stacked structure in which Ta 2 O 5 and TaSiO are stacked in this order from the bottom.
  • the resistance change layer 111 when used as an ion conductive layer, metal ions (for example, copper ions) formed inside the ion conductive layer at the time of low resistance (ON) are used. By dividing the cross-linking with the Ta 2 O 5 layer, metal ions can be easily recovered at the time of OFF, and switching characteristics can be improved.
  • the resistance change layer 111 is formed on the first copper wiring 105 and the opening of the barrier insulating film 107 or on the barrier insulating film 107.
  • the resistance change layer 111 extends in the left-right direction in FIG. 2A and is arranged so as to overlap in the same region as the upper electrode 112.
  • the upper electrode 112 plays the role of the second electrode 12 in FIG. 8 and is in contact with the upper surface of the resistance change layer 111.
  • the upper electrode 112 includes, for example, a refractory metal such as platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), or nitride thereof. A thing etc. or those laminated films can be used. Further, oxygen may be added to a top surface and a side surface of the upper electrode 112 with a metal material such as Pt or Ru as a main component, or a stacked structure with a layer to which oxygen is added may be employed.
  • the upper electrode 112 extends in the left-right direction in FIG. 2A and is disposed so as to overlap in the same region as the resistance change layer 111.
  • the first copper wiring 105, the upper electrode 112, and the resistance change layer 111 have a pattern shown in FIG. That is, the first copper wiring 105 has a pattern extending in the vertical direction in FIG. 2A, and a plurality of first copper wirings 105 are formed with a line width F and a line interval F.
  • the upper electrode 112 and the resistance change layer 111 have a pattern extending in the left-right direction in FIG. 2A, and are arranged above the first copper wiring 105 with respect to the paper surface of FIG.
  • the first copper wiring 105 is orthogonal (three-dimensionally intersected), and a plurality of lines are formed with a line width F and a line interval F.
  • the resistance change layer 111 has the same shape as the upper electrode 112. Further, F indicates a minimum processing dimension, for example, 180 nm or less and 20 nm or more.
  • the interlayer insulating film 120 is an insulating film formed on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112.
  • the interlayer insulating film 120 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 120 may be a laminate of a plurality of insulating films.
  • the interlayer insulating film 120 may be made of the same material as the interlayer insulating film 104.
  • FIG. 3 is a process cross-sectional view schematically showing the method for manufacturing the crossbar switch according to the first embodiment of the present invention.
  • an interlayer insulating film 102 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 101 (for example, a substrate on which a semiconductor element is formed), and then a barrier insulating film 103 (for example, on the interlayer insulating film 102).
  • a SiN film having a film thickness of 50 nm is deposited, and thereafter, an interlayer insulating film 104 (for example, a silicon oxide film having a film thickness of 300 nm) is deposited on the barrier insulating film 103.
  • Etching and photoresist removal are used to form a wiring groove in the interlayer insulating film 104, and then the first wiring via the barrier metal 106 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring groove.
  • the copper wiring 105 is embedded, and then the barrier insulating film 1 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106.
  • 7 eg, SiN film, thickness 50 nm
  • step A1 see Figure 3 (a)).
  • the interlayer insulating films 102 and 104 and the barrier insulating films 103 and 107 can be formed by a plasma CVD method.
  • the plasma CVD (Chemical Vapor Deposition) method refers to, for example, vaporizing a gas source or a liquid source to continuously supply the reaction chamber under reduced pressure, bringing the molecules into an excited state by plasma energy, In this method, a continuous film is formed on a substrate by a phase reaction or a substrate surface reaction.
  • the first copper wiring 105 is formed by forming a barrier metal 106 (for example, a TaN / Ta laminated film) by, for example, PVD (Physical Vapor Deposition) method, and after forming a Cu seed by PVD method, electrolysis It can be formed by embedding copper in the wiring trench by a plating method, after heat treatment at a temperature of 200 ° C. or higher, and then removing excess copper other than in the wiring trench by a CMP (Chemical-Mechanical-Polishing) method. As a method for forming such a series of copper wirings, a general method in this technical field can be used.
  • PVD Physical Vapor Deposition
  • the CMP method is a method of flattening by polishing the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface.
  • the excess copper embedded in the wiring trench is polished to form a buried wiring (damascene wiring), or the interlayer insulating film is polished to perform planarization.
  • a silicon oxide film or the like (not shown) is deposited on the barrier insulating film 107, and a photoresist (not shown) having a pattern for forming the opening 108 is formed on the silicon oxide film or the like.
  • the silicon oxide film etc. is dry etched using the photoresist as a mask to transfer the opening forming pattern to the silicon oxide film etc., and then the photoresist is removed by oxygen plasma ashing etc., and then the silicon oxide film etc. is masked Etchback (dry etching) the barrier insulating film 107 exposed from the opening forming pattern to form an opening 108 in the barrier insulating film 107, and the first copper wiring from the opening 108 of the barrier insulating film 107.
  • step A2 when the photoresist opening formation pattern is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop at the upper surface of the barrier insulating film 107, and reaches the inside of the barrier insulating film 107. You may do it.
  • the shape of the opening 108 of the barrier insulating film 107 can be a circle, and the diameter of the circle can be 10 nm to 500 nm.
  • a resistance change layer 111 (for example, Ta 2 O 5 , film thickness of 15 nm) is deposited on the barrier insulating film 107 including the first copper wiring 105, and then the upper electrode is formed on the resistance change layer 111 by the PVD method.
  • 112 (for example, a laminated structure having a Ru film thickness of 10 nm and a Ta film thickness of 50 nm) is formed.
  • a silicon oxide film or the like (not shown) is deposited on the upper electrode 112, and then the upper portion is formed on the silicon oxide film or the like.
  • a photoresist (not shown) having an electrode formation pattern is formed, and then the upper electrode formation pattern is transferred to a silicon oxide film or the like by dry etching the silicon oxide film using the photoresist as a mask.
  • the photoresist is removed by oxygen plasma ashing, etc., and then etched back using the silicon oxide film as a mask (dry etching)
  • the upper electrode 112 and the resistance change layer 111 are processed, and then the silicon oxide film or the like used for the etching mask is removed (step A3; see FIG. 3C).
  • the resistance change layer 111 can be formed using a PVD method or a CVD method.
  • the opening (108 in FIG. 3B) is attached with moisture or the like by the organic peeling process in Step A2, so that the resistance change layer 111 is deposited at a temperature of about 250 ° C. to 350 ° C. It is preferable to degas by applying a heat treatment under reduced pressure. At this time, care must be taken such as in a vacuum or a nitrogen atmosphere so that the copper surface is not oxidized again.
  • Step A3 when a resistance change layer using a transition metal oxide (eg, TiO, NiO) is used as the resistance change layer 111, an electrode is formed before the resistance change layer 111 is deposited.
  • a transition metal oxide eg, TiO, NiO
  • an electrode is formed before the resistance change layer 111 is deposited.
  • the upper electrode 112 for example, Ti, TiN, W, WN, Ta, TaN, Ru, RuOx, or the like can be used.
  • the laminated structure for example, TaN (lower layer) / Ru (upper layer). There may be.
  • the total film thickness of the laminated structure is preferably 10 nm or less for the convenience of forming the resistance change layer 111 inside the opening 108.
  • step A3 when the upper electrode formation pattern of the photoresist is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the upper electrode 112, and reaches the inside of the upper electrode 112. You may do it.
  • an interlayer insulating film 120 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112 (Step A4; see FIG. 2B). Although not shown, a multilayer wiring layer is formed on the interlayer insulating film 120.
  • the copper wiring used conventionally and the via for connecting to the copper wiring become unnecessary, and the area of the resistance change element can be reduced.
  • the number of manufacturing steps can be reduced.
  • the copper wiring that is no longer used can be used for other purposes.
  • a crossbar switch using the resistance change element 100 can be formed by using the upper electrode 112 as a wiring and using only one layer of the first copper wiring 105 among the multilayer copper wiring. Since there is no need to electrically connect the upper and lower copper wirings, the number of steps can be reduced. Furthermore, since it is not necessary to electrically connect the upper electrode 112 with an upper copper wiring having a generally large wiring width, the area of the resistance change element 100 can be made as small as possible.
  • FIG. 4A is a top view and FIG. 4B is a cross-sectional view schematically showing a configuration of a complementary resistance change element in a semiconductor device according to Example 2 of the present invention.
  • 5A is a top view schematically showing the configuration of a crossbar switch using complementary resistance change elements formed in a multilayer copper wiring in a semiconductor device according to Example 2 of the present invention
  • FIG. 2B is a cross-sectional view taken along the line XX ′ in FIG. 2A
  • FIG. FIG. 4 shows a complementary resistance change element which is one component of the crossbar switch.
  • FIG. 12 for a circuit diagram of a crossbar switch using a complementary resistance change element.
  • the semiconductor device according to Example 2 has a multilayer copper wiring layer in which a multilayer copper wiring is formed in an insulator on a semiconductor substrate.
  • the semiconductor device has a complementary resistance change element in the multilayer copper wiring.
  • the complementary resistance change element includes a first resistance change layer 62 and a second resistance change layer 63 laminated on a part of the first copper wiring 61, and the upper surfaces of the resistance change layers 63 and 63.
  • a first upper electrode 67 and a second upper electrode 64 are formed so as to cover each other.
  • the first resistance change layer 62 and the second resistance change layer 63 are arranged to be separated from each other in the same layer.
  • the first upper electrode 67 and the second upper electrode 64 are spaced apart from each other in the same layer.
  • the first variable resistance layer 62 and the first upper electrode 67 extend in a direction perpendicular to the paper surface and have the same structure adjacent in the direction perpendicular to the paper surface. It also serves as a first variable resistance layer and a first upper electrode of another first complementary variable resistance element.
  • the second copper wiring 66 extends in the left-right direction with respect to the plane of the paper, and another second complementary variable resistance element (the other first complementary variable element) of the same structure adjacent to the plane of the paper along the left-right direction. This also serves as the second copper wiring of the type variable resistance element.
  • the area required for one complementary variable resistance element can be 8F 2 .
  • FIG. 5 is an example in which a crossbar switch using the complementary resistance change element shown in FIG. 4 is formed inside a multilayer copper wiring layer on the semiconductor substrate 301.
  • the multilayer copper wiring layer is formed on the semiconductor substrate 301 by an interlayer insulating film 302, a barrier insulating film 303, an interlayer insulating film 304, a barrier insulating film 307, an interlayer insulating film 320, a barrier insulating film 315, an interlayer insulating film 316, and a barrier insulating.
  • An insulating stacked body in which a film 325 and an interlayer insulating film 326 are stacked in this order is included.
  • the first copper wiring 305 is embedded in the wiring trench formed in the interlayer insulating film 304 and the barrier insulating film 303 via the barrier metal 306.
  • the second copper wiring 332 is embedded in the wiring groove formed in the interlayer insulating film 316 and the barrier insulating film 315 via the barrier metal 323, and the interlayer insulating film 320 and the barrier insulating film 307 are embedded in the multilayer copper wiring layer.
  • a via 330 is embedded in the formed prepared hole via a barrier metal 323, and the second copper wiring 332 and the via 330 are integrated, and the side surface or the bottom surface of the second copper wiring 332 and the via 330 are barrier metal. 323.
  • the first copper wiring 305 corresponds to the first electrode 21 in FIG. 9A
  • the first upper electrode 313 corresponds to the second electrode 25 in FIG. 9A
  • the second upper electrode 314 corresponds to the first electrode 21 in FIG. ) Of the second electrode 23.
  • the complementary resistance change element 200 can be, for example, a switching element utilizing metal ion migration and electrochemical reaction in an ion conductor.
  • the complementary resistance change element 200 is an element in which two resistance change elements are connected in series.
  • a first resistance change layer 311 is interposed between the first copper wiring 305 corresponding to the first electrode 21 in FIG. 9A and the first upper electrode 313 serving as the second electrode 25, and FIG.
  • the second resistance change layer 312 is interposed between the first copper wiring 305 corresponding to the first electrode 21 and the second upper electrode 314 serving as the second electrode 23.
  • Each of the resistance change layers 311, 312 is in contact with the bottom surface of the first resistance change layer 311 and the second resistance change layer 312 and the top surface of the first copper wiring 305 in the region of the opening formed in the barrier insulating film 307. Furthermore, the top surfaces of the first variable resistance layer 311 and the second variable resistance layer 312 are in contact with the bottom surfaces of the first upper electrode 313 and the second upper electrode 314. The resistance change layers 311 and 312 are separated from each other, and the upper electrodes 313 and 314 are also separated from each other.
  • the complementary resistance change element 200 transitions between a high resistance state and a low resistance state by applying a voltage or passing a current.
  • the first resistance change layer 311 and the first resistance change layer 312 have a first resistance change layer 312. Switching is performed by utilizing diffusion of metal ions contained in the copper wiring 305 by electrolysis.
  • the semiconductor substrate 301 is a substrate on which a semiconductor element (not shown) is formed.
  • a substrate such as a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, a liquid crystal manufacturing substrate, or a silicon substrate provided with a multilayer copper wiring layer is used. be able to.
  • the interlayer insulating film 302 is an insulating film formed on the semiconductor substrate 301.
  • a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 302 may be a stack of a plurality of insulating films.
  • the barrier insulating film 303 is an insulating film having a barrier property interposed between the interlayer insulating films 302 and 304.
  • the barrier insulating film 303 serves as an etching stop layer when the wiring groove of the first copper wiring 305 is processed.
  • a SiN film, a SiC film, a SiCN film, or the like can be used for the barrier insulating film 303.
  • a wiring groove for embedding the first copper wiring 305 is formed, and the first copper wiring 305 is embedded in the wiring groove via a barrier metal 306.
  • the barrier insulating film 303 can be omitted depending on the selection of the etching conditions for the wiring trench.
  • the interlayer insulating film 304 is an insulating film formed on the barrier insulating film 303.
  • the interlayer insulating film 304 for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 304 may be a stack of a plurality of insulating films.
  • a wiring groove for embedding the first copper wiring 305 is formed in the interlayer insulating film 304, and the first copper wiring 305 is embedded in the wiring groove via a barrier metal 306.
  • the first copper wiring 305 is a wiring buried in a wiring groove formed in the interlayer insulating film 304 and the barrier insulating film 303 via the barrier metal 306.
  • the first copper wiring 305 also serves as an electrode corresponding to the first electrode 21 in FIG. 9 of the variable resistance element, and is in direct contact with the first variable resistance layer 311 and the second variable resistance layer 312.
  • An electrode layer or the like may be inserted between the first copper wiring 305 and each resistance change layer. When the electrode layer is formed, the electrode layer and the resistance change layer are deposited in a continuous process and processed in the continuous process.
  • a metal capable of diffusing and ion conducting in the resistance change layer is used, and for example, copper or the like can be used.
  • the first copper wiring 305 may be alloyed with Al, silicided, or nitrided.
  • the surface of the first copper wiring 305 may be silicided or nitrided.
  • the first copper wiring 305 is formed in a part of the region of the second copper wiring 332 extending in the left-right direction in FIG. 5A, and a plurality of first copper wirings 305 are formed in the region of the second copper wiring 332.
  • the first copper wiring 305 extends in the left-right direction in FIG. 5B from the region where the second copper wiring 332 and the first upper electrode 313 overlap, and the second copper wiring 332 and the second upper electrode 314 overlap. It is formed between the areas.
  • the first copper wiring 305 is separated from other adjacent first copper wirings (not shown) in the horizontal direction of FIG. 5B and in the direction perpendicular to the paper surface.
  • the barrier metal 306 covers the side surface or bottom surface of the first copper wiring 305 and prevents the metal contained in the first copper wiring 305 from diffusing into the interlayer insulating film 304 or the lower layer. It is a membrane.
  • the barrier metal 306 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). ), A refractory metal thereof, a nitride thereof, or a laminated film thereof.
  • the barrier insulating film 307 is an insulating film formed on the interlayer insulating film 304 including the first copper wiring 305 and the barrier metal 306, and prevents oxidation of a metal (for example, Cu) related to the first copper wiring 305, It plays a role of preventing diffusion of the metal related to the first copper wiring 305 into the interlayer insulating film 304.
  • a metal for example, Cu
  • the barrier insulating film 307 for example, a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used.
  • the barrier insulating film 307 has an opening on the first copper wiring 305.
  • the first copper wiring 305 is in contact with the first resistance change layer 311 and the second resistance change layer 312.
  • the opening of the barrier insulating film 307 is formed in the region of the first copper wiring 305. In this way, the complementary resistance change element 200 can be formed on the surface of the first copper wiring 305 with small unevenness.
  • the first resistance change layer 311 and the second resistance change layer 312 are films whose resistance changes.
  • the first resistance change layer 311 and the second resistance change layer 312 can be made of a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of the metal related to the first copper wiring 305 (first electrode).
  • a film capable of ion conduction is used.
  • an oxide insulating film containing Ta such as Ta 2 O 5 or TaSiO can be used.
  • the first resistance change layer 311 and the second resistance change layer 312 may have a stacked structure in which Ta 2 O 5 and TaSiO are stacked in this order from the bottom.
  • first variable resistance layer 311 and the second variable resistance layer 312 are used as the ion conductive layer, they are formed inside the ion conductive layer when the resistance is low (ON).
  • metal ions for example, copper ions
  • the first resistance change layer 311 and the second resistance change layer 312 are formed on the first copper wiring 105 and the opening of the barrier insulating film 107 or on the barrier insulating film 107.
  • the first resistance change layer 311 and the second resistance change layer 312 are separated from each other in the same layer.
  • the first resistance change layer 311 extends in the vertical direction in FIG. 5A and is arranged so as to overlap in the same region as the first upper electrode 313.
  • the second resistance change layer 312 is disposed at a position separated from the first resistance change layer 311 in a region where the second copper wiring 332 and the first copper wiring 305 overlap.
  • the first upper electrode 313 plays the role of the second electrode 25 in FIG. 9 and is in contact with the upper surface of the first variable resistance layer 311.
  • the second upper electrode 314 serves as the second electrode 23 in FIG. 9 and is in contact with the upper surface of the second resistance change layer 312.
  • the first upper electrode 313 and the second upper electrode 314 are made of a metal that is less likely to ionize than the metal related to the first copper wiring 305 and is less likely to diffuse and ion-conduct in the first resistance change layer 311 and the second resistance change layer 312. It is preferable to use a metal material that is used and has an absolute value of free energy of oxidation smaller than that of the metal component (Ta) related to the first resistance change layer 311 and the second resistance change layer 312.
  • first upper electrode 313 and the second upper electrode 314 examples include platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). Such a refractory metal, a nitride thereof, or a laminated film thereof can be used. Further, oxygen may be added to the top and side surfaces of the first upper electrode 313 and the second upper electrode 314 as a main component of a metal material such as Pt or Ru, or a laminated structure with a layer to which oxygen is added. Good. The first upper electrode 313 and the second upper electrode 314 are separated from each other in the same layer.
  • the first upper electrode 313 extends in the vertical direction in FIG. 5A and is arranged to overlap in the same region as the first resistance change layer 311.
  • the second upper electrode 314 is disposed at a position separated from the first upper electrode 313 in a region where the second copper wiring 332 and the first copper wiring 305 overlap.
  • the upper electrodes 313 and 314 and the resistance change layers 311 and 312 have a pattern shown in FIG. That is, the first upper electrode 313 and the first resistance change layer 311 have a pattern extending in the vertical direction in FIG.
  • the second upper electrode 314 and the second resistance change layer 312 are disposed between adjacent first upper electrodes 313 in the region of the second copper wiring 332 extending in the left-right direction in FIG.
  • the second upper electrode 314 and the second variable resistance layer 312 that are matched with each other are separated from each other.
  • the upper electrodes 313 and 314 and the resistance change layers 311 and 312 are arranged below the first copper wiring 305 with respect to the paper surface of FIG.
  • a plurality of first upper electrodes 313 and first resistance change layers 311 are formed orthogonal to the first copper wiring 305 (three-dimensional intersection).
  • the first resistance change layer 311 has the same shape as the first upper electrode 313, and the second resistance change layer 312 has the same shape as the second upper electrode 314.
  • the interlayer insulating film 320 is an insulating film formed on the barrier insulating film 307 including the upper electrodes 313 and 314 and the resistance change layers 311 and 312.
  • the interlayer insulating film 320 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 320 may be a stack of a plurality of insulating films.
  • the interlayer insulating film 320 may be made of the same material as the interlayer insulating film 304.
  • a pilot hole for embedding the via 330 is formed in the interlayer insulating film 320, and the via 330 is embedded in the pilot hole via the barrier metal 323.
  • the barrier insulating film 315 is an insulating film interposed between the interlayer insulating film 320 and the interlayer insulating film 316 (see FIG. 5C).
  • the barrier insulating film 315 has a role of preventing oxidation of the metal (for example, Cu) related to the via 330 and preventing diffusion of the metal related to the via 330 into the interlayer insulating film 320.
  • a SiN film, a SiC film, a SiCN film, or the like can be used.
  • a wiring groove for embedding the second copper wiring 332 is formed, and the second copper wiring 332 is embedded in the wiring groove via the barrier metal 323.
  • the interlayer insulating film 316 is an insulating film formed on the barrier insulating film 315 (see FIG. 5C).
  • the interlayer insulating film 316 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 316 may be a stack of a plurality of insulating films.
  • the interlayer insulating film 316 may be made of the same material as the interlayer insulating film 304.
  • a wiring groove for embedding the second copper wiring 332 is formed, and the second copper wiring 332 is embedded in the wiring groove via a barrier metal 323.
  • the barrier metal 323 covers the side surface or bottom surface of the via 330 and the second copper wiring 332 in order to prevent the metal contained in the via 330 and the second copper wiring 332 from diffusing into the interlayer insulating film 320 or the lower layer. It is a conductive film having a barrier property.
  • the barrier metal 323 include platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and a refractory metal such as tungsten carbonitride (WCN). A thing etc. or those laminated films can be used.
  • the second copper wiring 332 is a wiring buried in a wiring groove formed in the interlayer insulating film 316 and the barrier insulating film 315 via the barrier metal 323.
  • the second copper wiring 332 extends in the left-right direction in FIG. 5A, and a plurality of the second copper wirings 332 are formed apart from each other in the same layer.
  • the second copper wiring 332 is integrated with the via 330.
  • the via 330 is embedded in a pilot hole formed in the interlayer insulating film 320 via a barrier metal 323 and is electrically connected to the second upper electrode 314 via the barrier metal 323.
  • Al, Cu, W, or the like can be used for the second copper wiring 332 and the via 330.
  • Cu may be alloyed with Al.
  • the second copper wiring 332 and the via 330 may be silicided or nitrided.
  • the barrier insulating film 325 is formed on the interlayer insulating film 316 including the second copper wiring 332, prevents oxidation of a metal (for example, Cu) related to the second copper wiring 332, and forms an upper layer of the second copper wiring 332. It is an insulating film having a role of preventing diffusion of the metal.
  • a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used.
  • the interlayer insulating film 326 is an insulating film formed on the barrier insulating film 325.
  • the interlayer insulating film 326 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 316 may be a stack of a plurality of insulating films.
  • 6 and 7 are process cross-sectional views schematically showing a method for manufacturing a crossbar switch using complementary resistance change elements formed in a multilayer copper wiring in a semiconductor device according to Example 2 of the present invention. is there.
  • an interlayer insulating film 302 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 301 (for example, a substrate on which a semiconductor element (not shown) is formed), and then the interlayer insulating film 302 is formed.
  • a semiconductor substrate 301 for example, a substrate on which a semiconductor element (not shown) is formed
  • a barrier insulating film 303 (for example, a SiN film, a film thickness of 50 nm) is deposited, and then an interlayer insulating film 304 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on the barrier insulating film 303, and then a lithography method ( (Including photoresist formation, dry etching, and photoresist removal), a wiring groove is formed in the interlayer insulating film 304, and then the barrier metal 306 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring groove.
  • the barrier metal 306 for example, TaN / Ta, film thickness 5 nm / 5 nm
  • the first copper wiring 305 is embedded via the first insulating film 304 and the first copper wiring 305 and the interlayer insulating film 304 including the barrier metal 306 are then buried.
  • a dielectric film 307 eg, SiN film, thickness 50 nm is deposited (step B1; see FIG. 6 (a)).
  • the interlayer insulating films 302 and 304 and the barrier insulating films 303 and 307 can be formed by a plasma CVD method.
  • the first copper wiring 305 is formed by forming a barrier metal 306 (for example, a TaN / Ta laminated film) by the PVD method, and forming copper seed by the PVD method, and then copper by the electrolytic plating method. It can be formed by embedding in the wiring trench, after heat treatment at a temperature of 200 ° C. or higher, and then removing excess copper other than in the wiring trench by CMP.
  • a method for forming such a series of copper wirings a general method in this technical field can be used.
  • a silicon oxide film or the like is deposited on the barrier insulating film 307, and then a photoresist (not shown) having a pattern for forming the opening 308 is formed on the silicon oxide film or the like.
  • the silicon oxide film is dry-etched as a mask to transfer the opening formation pattern to the silicon oxide film, etc., and then the photoresist is removed by oxygen plasma ashing, etc., and then the silicon oxide film is used as a mask to form the opening.
  • the barrier insulating film 307 exposed from the pattern for use is etched back (dry etching) to form an opening 308 in the barrier insulating film 307, and the first copper wiring 305 is exposed from the opening 308 in the barrier insulating film 307.
  • the first copper wiring 30 is obtained by performing an organic stripping treatment with an amine stripping solution or the like.
  • the etching by-product generated during the etch back is removed, and then the silicon oxide film and the like on the barrier insulating film 307 are removed (step B2; FIG. 6). (See (b)).
  • step B2 when the photoresist opening formation pattern is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the barrier insulating film 307, and reaches the inside of the barrier insulating film 307. You may do it.
  • the shape of the opening 308 of the barrier insulating film 307 can be a circle, and the diameter of the circle can be 10 nm to 500 nm.
  • a resistance change layer 309 (for example, Ta 2 O 5 , film thickness of 15 nm) is formed on the barrier insulating film 307 including the first copper wiring 305, and further a metal layer 310 (for example, Ru film thickness of 10 nm and Ta A laminated structure having a thickness of 50 nm is formed (step B3; see FIG. 6C).
  • the resistance change layer 309 can be formed using a PVD method or a CVD method.
  • step B3 since the opening 308 is attached with moisture or the like by the organic peeling process in step B2, heat treatment is performed under reduced pressure at a temperature of about 250 ° C. to 350 ° C. before the resistance change layer 309 is deposited. It is preferable to degas. At this time, care must be taken such as in a vacuum or a nitrogen atmosphere so that the copper surface is not oxidized again.
  • step B3 when a resistance change layer using a transition metal oxide (eg, TiO, NiO, etc.) is used as the resistance change layer 309, an electrode is formed before the resistance change layer 309 is deposited. May be.
  • the electrode for example, Ti, TiN, W, WN, Ta, TaN, Ru, RuOx, etc. can be used.
  • their laminated structure for example, TaN (lower layer) / Ru (upper layer) Also good.
  • a silicon oxide film or the like is deposited on the metal layer (310 in FIG. 6C), and then a photoresist (not shown) having an upper electrode formation pattern is formed on the silicon oxide film or the like, Thereafter, the silicon oxide film or the like is dry-etched using the photoresist as a mask to transfer the upper electrode forming pattern to the silicon oxide film or the like. Thereafter, the photoresist is removed by oxygen plasma ashing or the like, and then the silicon oxide film is removed. Etching back (dry etching) using the above as a mask to process the metal layer (310 in FIG. 6C) and the resistance change layer (309 in FIG.
  • Step B4 when the upper electrode formation pattern of the photoresist is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the metal layer 310, and has reached the inside of the metal layer 310. May be.
  • an interlayer insulating film 320 (for example, a silicon oxide film) is formed on the barrier insulating film 307 including the first resistance change layer 311 / first upper electrode layer 313 and the second resistance change layer 312 / second upper electrode layer 314.
  • the surface of the interlayer insulating film 320 is flattened by a CMP method, and then a barrier insulating film 315 (for example, a SiN film, film thickness of 50 nm) is deposited on the interlayer insulating film 320, and then barrier insulation is performed.
  • An interlayer insulating film 316 (for example, a silicon oxide film having a thickness of about 300 nm) is deposited on the film 315 (step B5; see FIG. 7B). In step B5, the thickness of the interlayer insulating film 320 is set to about 300 nm after planarization.
  • the second copper wiring 332 and the via 330 are formed in the interlayer insulating film 316 and the interlayer insulating film 320 by the dual damascene method which is a conventional technique (step B6; see FIG. 7C).
  • the lower surface and side surfaces of the second copper wiring 332 and the via 330 are covered with the barrier metal 323.
  • a barrier insulating film 325 for example, SiN film
  • an interlayer insulating film 326 for example, silicon oxide film, film thickness of 300 nm
  • a multilayer wiring layer is formed on the interlayer insulating film 120.
  • the complementary resistance change element 200 can be formed.
  • the used crossbar switch can be formed, the copper wiring used conventionally, and the via for connecting to the copper wiring become unnecessary, the area of the resistance change element can be reduced, and the number of manufacturing steps can be reduced. it can. Further, since it is not necessary to electrically connect the first upper electrode 313 with an upper copper wiring having a generally wide wiring width, the area of the complementary resistance change element 200 can be made as small as possible.
  • Resistance change element 20 Complementary resistance change element 11 1st electrode 12 2nd electrode 13 Resistance change layer 14 1st node 15 2nd node 16 Voltage source 21 1st electrode 22 Resistance change layer 23, 25 2nd electrode 24 Resistance change Layer 26 First node 27 Second node 28 Third node 31 First copper wiring 32 Second electrode 33 Resistance change layer 34 Via 35 Second copper wiring 41 First copper wiring 42 Second electrode 43 Resistance change layer 61 First copper Wiring 62 First variable resistance layer 63 Second variable resistance layer 64 Second upper electrode 65 Via 66 Second copper wiring 67 First upper electrode 100 Variable resistance element 101 Semiconductor substrate 102, 104, 120 Interlayer insulating film 103, 107 Barrier insulation Film 105 First copper wiring (lower electrode) 106 Barrier metal 108 Opening 111 Resistance change layer 112 Upper electrode 200 Complementary variable resistance element 301 Semiconductor substrate 302, 326 Interlayer insulating film 303, 325 Barrier insulating film 304 Interlayer insulating film (first interlayer insulating film) 305 First

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Abstract

Provided are: a semiconductor device which is capable of reducing the processes or reducing the area of a variable resistance element as much as possible; and a method for manufacturing the semiconductor device. A semiconductor device, which comprises two or more variable resistance elements (100) inside a multilayer wiring layer on a semiconductor substrate (101), and wherein: each variable resistance element (100) has a configuration in which a variable resistance layer (111) having a variable resistance is interposed between a lower electrode (105) and an upper electrode (112); a wiring line in a predetermined wiring layer in the multilayer wiring layer also serves as the lower electrode (105); and the upper electrode (112) is formed as a line that extends in one direction and also serves as an upper electrode of another variable resistance element that is adjacent to the variable resistance element (100) in the above-mentioned one direction.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　［関連出願についての記載］
　本発明は、日本国特許出願：特願２０１１－１６９３９９号（２０１１年　８月　２日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
　本発明は、半導体装置及びその製造方法に関し、特に、多層配線層の内部に抵抗変化型不揮発素子（以下、「抵抗変化素子」）を有するプログラマブルロジックデバイス又は不揮発性メモリデバイスを搭載した半導体装置及びその製造方法に関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2011-169399 (filed on August 2, 2011), the entire content of which is incorporated herein by reference. Shall.
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device in which a programmable logic device or a nonvolatile memory device having a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) is provided in a multilayer wiring layer, and It relates to the manufacturing method.
　電圧を印加することにより抵抗が変化する抵抗変化素子は、不揮発性メモリ又は不揮発性スイッチとして用いることができる。不揮発性メモリとしては、従来のフラッシュメモリに比べて、低電圧で動作が可能であること、情報を読み出す速度をより高速にできることが利点となる。また、不揮発性スイッチとしては、プログラマブルロジックデバイスにおけるスイッチに用いることで、素子寸法を大幅に小面積化し、さらに消費電力・動作速度の改善が期待されている。 The resistance change element whose resistance is changed by applying a voltage can be used as a nonvolatile memory or a nonvolatile switch. As a non-volatile memory, it is advantageous in that it can operate at a low voltage and can read out information faster than a conventional flash memory. Moreover, as a non-volatile switch, by using it as a switch in a programmable logic device, the element size is greatly reduced, and further improvement in power consumption and operation speed is expected.
　抵抗変化素子は、電気伝導特性からユニポーラ型とバイポーラ型に分かれる。ユニポーラ型抵抗変化素子は、印加電圧の極性に依存せず、印加電圧の大きさでその抵抗が変化する。バイポーラ型抵抗変化素子は、印加電圧の極性に依存して抵抗が変化する。 The resistance change element is divided into a unipolar type and a bipolar type from the electric conduction characteristics. A unipolar variable resistance element does not depend on the polarity of the applied voltage, and its resistance changes depending on the magnitude of the applied voltage. The resistance of the bipolar variable resistance element changes depending on the polarity of the applied voltage.
　図８（ａ）に抵抗変化素子１０を示す。抵抗変化素子１０は、抵抗変化層１３を２つの電極（第１電極１１及び第２電極１２）で挟んだ構造を備える。電極材料の違いや、抵抗変化層材料等で電気伝導特性がバイポーラ型となる。バイポーラ型抵抗変化素子に用いられる電極について、次のように定義する。電極間に電圧を印加すると、高抵抗（オフ状態）の場合には低抵抗（オン状態）に遷移し、低抵抗の場合は低抵抗状態が維持されたとする。このときの電位が高い方を「第１電極」、低い方を「第２電極」と定義する。図８（ｂ）及び（ｃ）は、状態を遷移させるための接続方法、及び、電流電圧特性の模式図をそれぞれ示している。電圧源１６が接続される第１節点１４には第１電極１１が接続され、接地されている第２節点１５には、第２電極が接続されている。まず、電圧源に正の電圧を印加する。すると、抵抗変化素子１０がオン状態にあるときは、抵抗の変化はなく、電圧と電流は比例する。一方、抵抗変化素子１０がオフ状態にあるときは、ある閾電圧でオフ状態からオン状態へと変化する。オフからオン状態への変化は「セット動作」、そのときの閾電圧は「セット電圧」と呼ばれている。次に、電圧源に負の電圧を印加する。抵抗変化素子１０がオフ状態にあるときは、状態の変化なく、電流はほぼ流れない。一方、抵抗変化素子１０がオン状態にあるときは、ある閾電圧で電流が流れるオン状態から電流がほぼ流れないオフ状態へと変化する。オンからオフ状態への変化は「リセット動作」、そのときの閾電圧は「リセット電圧」と呼ばれている。 FIG. 8A shows the resistance change element 10. The resistance change element 10 has a structure in which the resistance change layer 13 is sandwiched between two electrodes (first electrode 11 and second electrode 12). The difference in electrode material, the resistance change layer material, etc. makes the electric conduction characteristics bipolar. The electrode used for the bipolar variable resistance element is defined as follows. When a voltage is applied between the electrodes, a transition is made to a low resistance (on state) in the case of a high resistance (off state), and a low resistance state is maintained in the case of a low resistance. The higher potential at this time is defined as “first electrode”, and the lower potential is defined as “second electrode”. FIGS. 8B and 8C respectively show a connection method for transitioning states and a schematic diagram of current-voltage characteristics. The first electrode 11 is connected to the first node 14 to which the voltage source 16 is connected, and the second electrode is connected to the second node 15 that is grounded. First, a positive voltage is applied to the voltage source. Then, when the variable resistance element 10 is in the on state, there is no change in resistance, and the voltage and current are proportional. On the other hand, when the resistance change element 10 is in the off state, the resistance change element 10 changes from the off state to the on state at a certain threshold voltage. The change from the off state to the on state is called “set operation”, and the threshold voltage at that time is called “set voltage”. Next, a negative voltage is applied to the voltage source. When the variable resistance element 10 is in the off state, no current changes and no current flows. On the other hand, when the resistance change element 10 is in the on state, the state changes from an on state in which current flows at a certain threshold voltage to an off state in which no current flows. The change from the on state to the off state is called “reset operation”, and the threshold voltage at that time is called “reset voltage”.
　特許文献１、非特許文献１、及び特許文献２に、電気化学反応による金属の析出現象を利用した抵抗変化素子の一例が記載されている。この抵抗変化素子における抵抗変化層は金属イオンが伝導可能なイオン伝導層であり、第１電極は電圧を印加することで酸化されて金属イオンを抵抗変化層に供給する酸化可能な電極であり、第２電極は酸化還元反応等の電気化学反応に関与しない電極である。オフからオン状態へ遷移させるには、第１電極に正電圧を印加する。このとき、第１電極の金属の一部が電気化学反応（酸化反応）によって金属イオンに変わり、イオン伝導層に溶解する。そして、イオン伝導層中の金属イオンが第２電極と抵抗変化層の界面で金属となって析出（還元）し、第１電極と第２電極が接続された金属架橋が形成される。第１電極と第２電極が金属架橋を介して電気的に接続されることで、低抵抗状態（オン状態）になる。一方、オンの状態かオフ状態へ遷移させるには、第１電極に負電圧を印加する。負の電圧の印加で、金属架橋の一部が切断されて高抵抗状態（オフ状態）へ遷移する。特許文献２によると、金属イオンには銅イオンが用いられ、その供給源となる第１電極は銅が用いられ、イオン伝導層として酸化タンタル等の金属酸化物が用いられ、さらに、反応に寄与しにくい第２電極として白金やルテニウムが用いられる。 Patent Document 1, Non-Patent Document 1, and Patent Document 2 describe an example of a resistance change element using a metal precipitation phenomenon by an electrochemical reaction. The variable resistance layer in the variable resistance element is an ion conductive layer capable of conducting metal ions, and the first electrode is an oxidizable electrode that is oxidized by applying a voltage and supplies the metal ions to the variable resistance layer. The second electrode is an electrode that does not participate in an electrochemical reaction such as an oxidation-reduction reaction. In order to transition from the off state to the on state, a positive voltage is applied to the first electrode. At this time, a part of the metal of the first electrode is converted into metal ions by an electrochemical reaction (oxidation reaction) and dissolved in the ion conductive layer. Then, metal ions in the ion conductive layer are deposited (reduced) as a metal at the interface between the second electrode and the resistance change layer, and a metal bridge in which the first electrode and the second electrode are connected is formed. The first electrode and the second electrode are electrically connected via the metal bridge, so that the low resistance state (ON state) is obtained. On the other hand, in order to transition from the on state to the off state, a negative voltage is applied to the first electrode. When a negative voltage is applied, a part of the metal bridge is cut and transitions to a high resistance state (off state). According to Patent Document 2, copper ions are used as metal ions, copper is used as the first electrode serving as a supply source thereof, and metal oxides such as tantalum oxide are used as an ion conductive layer, which further contributes to the reaction. Platinum or ruthenium is used as the second electrode that is difficult to perform.
国際公開第０３／０９４２２７号パンフレットInternational Publication No. 03/094227 Pamphlet 特開２００６－３１９０２８号公報JP 2006-319028 A 国際公開第２０１０／０７９８１６号パンフレットInternational Publication No. 2010/0779816 Pamphlet
　以下の分析は、本願発明者により与えられる。 The following analysis is given by the present inventor.
　上述した抵抗変化素子を半導体集積回路（ＬＳＩ；Large Scale Integration）の中で従来の半導体素子とともに用いる場合、素子の動作保障年数は半導体素子と同じ１０年以上が要求される。しかしながら、従来の抵抗変化素子において、印加される電圧が抵抗変化を引き起こす閾電圧以下であっても、経時劣化によって、別の状態に遷移してしまう誤動作の問題があった。この誤動作による問題は、「ディスターブ不良」と呼ばれる。例えば、図８（ｃ）において、抵抗変化素子にセット電圧以上の電圧を印加してオフ状態からオン状態へ遷移する必要がある一方で、オフ状態にある抵抗変化素子にＬＳＩの動作電圧である約１Ｖの電圧を印加してもオフ状態を維持する必要がある。一般的なＬＳＩの動作電圧は０．９～１．２Ｖ付近である。しかし、約１Ｖの電圧が連続的に印加され続けると、半導体素子の保障年数以下（例えば、５年間程度）で、オフ状態からオン状態へ遷移する誤動作が生じてしまう。 When the variable resistance element described above is used together with a conventional semiconductor element in a semiconductor integrated circuit (LSI; Large Scale Integration), the guaranteed operation period of the element is required to be 10 years or more, which is the same as that of the semiconductor element. However, in the conventional resistance change element, there is a problem of malfunction that even when the applied voltage is equal to or lower than the threshold voltage that causes the resistance change, the state transitions to another state due to deterioration over time. The problem caused by this malfunction is called “disturbance failure”. For example, in FIG. 8C, it is necessary to apply a voltage higher than the set voltage to the resistance change element to make a transition from the off state to the on state, while the resistance change element in the off state is the LSI operating voltage. Even when a voltage of about 1 V is applied, it is necessary to maintain the off state. The operating voltage of a general LSI is around 0.9 to 1.2V. However, if a voltage of about 1 V is continuously applied, a malfunction that shifts from the off state to the on state occurs within a warranty period of the semiconductor element (for example, about five years).
　このような抵抗変化素子の誤動作を防止する手法として、バイポーラ型の抵抗変化素子を直列に接続することが考えられる。接続の方法は、図８の抵抗変化素子１０の第１電極１１同士、又は、第２電極１２同士を接続するようにする。図９は、図８の第１電極１１同士を接続した場合を示している。接続される電極は１つの電極を共有することで、より簡便な構造をとることができる。図９（ｂ）は図９（ａ）のスイッチ構造を記号で示したもので、第２節点２７が第１電極２１、第１節点２６が第２電極２３、第３節点２８が第２電極２５に対応する。ここで、接続した２つの抵抗変化素子がオフ状態にあって、第３節点２８と第１節点２６間に正又は負の電圧を印加する場合を考える。接続された２つの抵抗変化素子の内、第２電極から第１電極に向かう方向で正電圧が印加されている抵抗変化素子はオフ状態を維持され、第１節点２６と第３節点２８との間に印加された電圧を支える。正又は負のいずれの電圧に対しても、接続された２つの抵抗変化素子のいずれかが相補的に電圧を支え、安定したオフ状態が得られる。図９のように、２つのバイポーラ型抵抗変化素子を直列に接続させた素子を「相補型抵抗変化素子」と呼ぶ。 As a technique for preventing such a malfunction of the variable resistance element, it is conceivable to connect a bipolar variable resistance element in series. As a connection method, the first electrodes 11 or the second electrodes 12 of the resistance change element 10 in FIG. 8 are connected. FIG. 9 shows a case where the first electrodes 11 of FIG. 8 are connected. The electrodes to be connected can have a simpler structure by sharing one electrode. FIG. 9 (b) shows the switch structure of FIG. 9 (a) with symbols. The second node 27 is the first electrode 21, the first node 26 is the second electrode 23, and the third node 28 is the second electrode. 25. Here, consider a case where two connected resistance change elements are in an OFF state and a positive or negative voltage is applied between the third node 28 and the first node 26. Of the two connected resistance change elements, the resistance change element to which a positive voltage is applied in the direction from the second electrode toward the first electrode is maintained in the OFF state, and the first node 26 and the third node 28 Supports the voltage applied between them. For either positive or negative voltage, either one of the two connected resistance change elements supports the voltage in a complementary manner, and a stable OFF state is obtained. An element in which two bipolar variable resistance elements are connected in series as shown in FIG. 9 is referred to as a “complementary variable resistance element”.
　ところで、上記に記載の抵抗変化素子は、ＬＳＩの多層配線中に形成される。多層配線の配線材料は主に銅で構成されており、多層銅配線内に抵抗変化素子を効率的に形成する手法が望まれる。電気化学反応を利用する抵抗変化素子の半導体装置への集積化する技術について、特許文献３及び非特許文献２に開示されている。それらによると、抵抗変化素子は、図１０にあるように、２つの銅配線（第１銅配線３１及び第２銅配線３５）に間に形成され、第１銅配線３１と抵抗変化素子の第１電極とを兼用する技術が記載されている。図１０（ｂ）において、第１銅配線３１は紙面に垂直方向に向かう配線であり、第２銅配線３５は紙面に対して平行方向に向かう配線である。抵抗変化素子は、第１電極を兼ねる第１銅配線３１、抵抗変化層３３、第２電極３２で構成されている。第２電極３２と第２銅配線３５とは、ビア３４で電気的に接続されている。 Incidentally, the variable resistance element described above is formed in a multilayer wiring of an LSI. The wiring material of the multilayer wiring is mainly composed of copper, and a method of efficiently forming a resistance change element in the multilayer copper wiring is desired. Patent Document 3 and Non-Patent Document 2 disclose a technique for integrating a resistance change element using an electrochemical reaction in a semiconductor device. According to them, as shown in FIG. 10, the resistance change element is formed between two copper wirings (first copper wiring 31 and second copper wiring 35). A technique that also serves as one electrode is described. In FIG. 10B, the first copper wiring 31 is a wiring that goes in a direction perpendicular to the paper surface, and the second copper wiring 35 is a wiring that goes in a direction parallel to the paper surface. The resistance change element includes a first copper wiring 31 that also serves as a first electrode, a resistance change layer 33, and a second electrode 32. The second electrode 32 and the second copper wiring 35 are electrically connected by a via 34.
　図１１は、抵抗変化素子（図８参照）をクロスバースイッチに用いた例である。クロスバースイッチは、入力線Ｘ１からＸＮ、出力線Ｙ１からＹＮ、及び入力線及び出力線の交点に、それぞれの線を電気的に接続するか接続しないかを選択するためのスイッチ、ここでは抵抗変化素子から成る。クロスバースイッチは、ＦＰＧＡ（フィールドプログラマブルゲートアレイ）等のプログラマブルデバイスの重要な構成要素である。非特許文献２では、抵抗変化素子を用いた３２×３２クロスバースイッチについて記載されている。非特許文献２では、クロスバースイッチは多層銅配線中に形成され、出力線、入力線はそれぞれ銅配線で形成されている。図１１において、例えば、入力線Ｘ１からＸＮ（非特許文献２ではＮ＝３２）は、図１０の第２銅配線３５であり、出力線Ｙ１からＹＮは、図１０の第１銅配線３１とできる。入力線と出力線の交点の断面は、図１０（ｂ）のようになっている。配線の最小加工寸法をＦとすると、クロスバースイッチの１つの要素は縦及び横の長さは２Ｆであり、面積は４Ｆ２である。ここで、銅配線幅と配線間の距離がＦに等しいとしている。 FIG. 11 shows an example in which a resistance change element (see FIG. 8) is used for a crossbar switch. The crossbar switch is a switch for selecting whether the respective lines are electrically connected or not connected to the intersections of the input lines X1 to XN, the output lines Y1 to YN, and the input line and the output line. It consists of a change element. The crossbar switch is an important component of a programmable device such as an FPGA (Field Programmable Gate Array). Non-Patent Document 2 describes a 32 × 32 crossbar switch using a resistance change element. In Non-Patent Document 2, the crossbar switch is formed in a multilayer copper wiring, and the output line and the input line are each formed of a copper wiring. In FIG. 11, for example, input lines X1 to XN (N = 32 in Non-Patent Document 2) are the second copper wirings 35 of FIG. 10, and output lines Y1 to YN are the same as the first copper wirings 31 of FIG. it can. The cross section of the intersection of the input line and the output line is as shown in FIG. If the minimum feature size of the wiring and F, 1 single element of the crossbar switch is vertical and horizontal length is 2F, the area is 4F 2. Here, it is assumed that the copper wiring width and the distance between the wirings are equal to F.
　図１２は、相補型抵抗変化素子（図９参照）を用いたクロスバースイッチである。クロスバースイッチは、入力線Ｘ１からＸＮ、出力線Ｙ１からＹＮ、及び入力線及び出力線の交点に、それぞれの線を電気的に接続するか接続しないかを選択するためのスイッチ、ここでは相補型抵抗変化素子から成る。多層銅配線中に形成されたクロスバースイッチでは、図１２の入力線Ｘ１からＸＮ及び出力線Ｙ１からＹＮは銅配線である。また、クロスバースイッチの１つの要素は、発明者らの見積りによると３６Ｆ２の面積を必要とし、図１１の抵抗変化素子を用いたクロスバースイッチの場合に比べて９倍もの面積を必要とする。 FIG. 12 shows a crossbar switch using a complementary resistance change element (see FIG. 9). The crossbar switch is a switch for selecting whether to electrically connect or not connect each of the input lines X1 to XN, the output lines Y1 to YN, and the intersection of the input line and the output line. It consists of a variable resistance element. In the crossbar switch formed in the multilayer copper wiring, the input lines X1 to XN and the output lines Y1 to YN in FIG. 12 are copper wirings. Also, one element of the crossbar switch requires an area of 36F 2 according to the inventors' estimation, and requires 9 times as much area as the crossbar switch using the resistance change element of FIG. To do.
　抵抗変化素子（相補型抵抗変化素子を含む）を多層銅配線層中に作製するにあたり、工程数を少なく、又は抵抗変化素子の面積をできるだけ小さくすることが要求されているが、そのような要求に応える技術は見当たらない。 In producing a resistance change element (including a complementary resistance change element) in a multilayer copper wiring layer, it is required to reduce the number of steps or to make the area of the resistance change element as small as possible. There is no technology that meets the requirements.
　本発明の主な課題は、工程数を少なく、又は抵抗変化素子の面積をできるだけ小さくすることができる半導体装置及びその製造方法を提供することである。 The main object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the number of steps or make the area of the resistance change element as small as possible.
　本発明の第１の視点においては、半導体基板上の多層配線層の内部に２つ以上の抵抗変化素子を有する半導体装置であって、前記抵抗変化素子は、下部電極と上部電極との間に抵抗が変化する抵抗変化層が介在した構成となっており、前記多層配線層における所定の配線層の配線は、前記下部電極を兼ね、前記上部電極は、一方向に延在したライン状に形成されるとともに、前記抵抗変化素子に対して前記一方向に沿って隣接する他の第１の抵抗変化素子の上部電極をも兼ねることを特徴とする。 According to a first aspect of the present invention, there is provided a semiconductor device having two or more variable resistance elements inside a multilayer wiring layer on a semiconductor substrate, wherein the variable resistance element is interposed between a lower electrode and an upper electrode. A variable resistance layer with variable resistance is interposed, and the wiring of a predetermined wiring layer in the multilayer wiring layer also serves as the lower electrode, and the upper electrode is formed in a line extending in one direction. And also serves as an upper electrode of another first variable resistance element adjacent to the variable resistance element along the one direction.
　本発明の前記半導体装置において、前記抵抗変化素子は、前記多層配線層の内部に４つ以上有するとともに、２次元アレイ状に配置され、前記多層配線層における所定の配線層の配線は、前記一方向の直角方向に延在したライン状に形成されるとともに、前記抵抗変化素子に対して前記一方向の直角方向に沿って隣接する他の第２の抵抗変化素子の下部電極をも兼ねることが好ましい。 In the semiconductor device of the present invention, four or more variable resistance elements are provided in the multilayer wiring layer, and are arranged in a two-dimensional array. It is formed in a line extending in a direction perpendicular to the direction, and also serves as a lower electrode of another second variable resistance element adjacent to the variable resistance element along the right direction in one direction. preferable.
　本発明の前記半導体装置において、前記下部電極は、金属イオンの供給源となる材料を含み、前記上部電極は、前記下部電極よりもイオン化しにくい材料で構成され、前記抵抗変化層は、前記金属イオンが伝導可能なイオン伝導層であることが好ましい。 In the semiconductor device of the present invention, the lower electrode includes a material serving as a metal ion supply source, the upper electrode is formed of a material that is less likely to be ionized than the lower electrode, and the resistance change layer includes the metal It is preferable that the ion conductive layer is capable of conducting ions.
　本発明の前記半導体装置において、前記抵抗変化層は、前記上部電極と重なるように配されていることが好ましい。 In the semiconductor device of the present invention, it is preferable that the variable resistance layer is disposed so as to overlap the upper electrode.
　本発明の第２の視点においては、半導体基板上の多層配線層の内部に２つ以上の相補型抵抗変化素子を有する半導体装置であって、前記相補型抵抗変化素子は、下部電極と第１上部電極との間に抵抗が変化する第１抵抗変化層が介在するとともに、前記第１上部電極から離間した位置にて前記下部電極と第２上部電極との間に抵抗が変化する第２抵抗変化層が介在した構成となっており、前記下部電極は、前記多層配線層における所定の配線層に配され、前記第１上部電極は、一方向に延在したライン状に形成されるとともに、前記相補型抵抗変化素子に対して前記一方向に沿って隣接する他の第１の相補型抵抗変化素子の第１上部電極をも兼ねることを特徴とする。 According to a second aspect of the present invention, there is provided a semiconductor device having two or more complementary variable resistance elements inside a multilayer wiring layer on a semiconductor substrate, wherein the complementary variable resistance element includes a lower electrode and a first electrode. A second resistance whose resistance changes between the lower electrode and the second upper electrode at a position spaced apart from the first upper electrode is interposed between the first resistance change layer whose resistance changes between the upper electrode and the upper electrode. The change layer is interposed, the lower electrode is arranged in a predetermined wiring layer in the multilayer wiring layer, and the first upper electrode is formed in a line extending in one direction, It also serves as a first upper electrode of another first complementary variable resistance element adjacent to the complementary variable resistance element along the one direction.
　本発明の前記半導体装置において、前記相補型抵抗変化素子は、前記多層配線層の内部に４つ以上有するとともに、２次元アレイ状に配置され、前記多層配線層における他の所定の配線層の配線は、前記一方向の直角方向に延在したライン状に形成されるとともに、前記第２上部電極、及び、前記相補型抵抗変化素子に対して前記一方向の直角方向に沿って隣接する他の第２の相補型抵抗変化素子の第２上部電極のそれぞれとビアを介して接続されることが好ましい。 In the semiconductor device of the present invention, the complementary resistance change element has four or more inside the multilayer wiring layer and is arranged in a two-dimensional array, and the wiring of another predetermined wiring layer in the multilayer wiring layer Is formed in a line extending in a direction perpendicular to the one direction, and is adjacent to the second upper electrode and the complementary resistance change element along the direction perpendicular to the one direction. It is preferable that the second complementary resistance change element is connected to each of the second upper electrodes through vias.
　本発明の前記半導体装置において、前記下部電極は、前記第１上部電極と前記多層配線層における他の所定の配線層の配線とが重なる領域から前記一方向の直角方向に延在して前記第２上部電極と前記多層配線層における他の所定の配線層の配線とが重なる領域までの間の領域に配されることが好ましい。 In the semiconductor device of the present invention, the lower electrode extends in a direction perpendicular to the one direction from a region where the first upper electrode and a wiring of another predetermined wiring layer in the multilayer wiring layer overlap. 2 It is preferable that the upper electrode and the wiring of another predetermined wiring layer in the multilayer wiring layer are arranged in a region up to a region where they overlap.
　本発明の前記半導体装置において、前記下部電極は、金属イオンの供給源となる材料を含み、前記第１上部電極及び前記第２上部電極は、前記下部電極よりもイオン化しにくい材料で構成され、前記第１抵抗変化層及び前記第２抵抗変化層は、前記金属イオンが伝導可能なイオン伝導層であることが好ましい。 In the semiconductor device of the present invention, the lower electrode includes a material serving as a metal ion supply source, and the first upper electrode and the second upper electrode are made of a material that is less ionized than the lower electrode, The first variable resistance layer and the second variable resistance layer are preferably ion conductive layers capable of conducting the metal ions.
　本発明の前記半導体装置において、前記第１上部電極及び第２上部電極は、同一層に配され、前記第１抵抗変化層及び前記第２抵抗変化層は、同一層に配されることが好ましい。 In the semiconductor device of the present invention, it is preferable that the first upper electrode and the second upper electrode are arranged in the same layer, and the first resistance change layer and the second resistance change layer are arranged in the same layer. .
　本発明の前記半導体装置において、前記第１抵抗変化層は、前記第１上部電極と重なるように配され、前記第２抵抗変化層は、前記第２上部電極と重なるように配されていることが好ましい。 In the semiconductor device of the present invention, the first variable resistance layer is disposed so as to overlap the first upper electrode, and the second variable resistance layer is disposed so as to overlap the second upper electrode. Is preferred.
　本発明の第３の視点においては、半導体装置の製造方法において、層間絶縁膜において一方向に延在した配線溝を形成する工程と、前記配線溝に下部電極を埋め込む工程と、前記下部電極を含む前記層間絶縁膜上にバリア絶縁膜を堆積する工程と、前記バリア絶縁膜において前記下部電極に通ずる開口部を形成する工程と、前記下部電極を含む前記バリア絶縁膜上に抵抗変化層を堆積する工程と、前記抵抗変化層上に上部電極層を堆積する工程と、前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記一方向の直角方向に延在したライン状の前記上部電極及び前記抵抗変化層を形成する工程と、を含むことを特徴とする。 According to a third aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a wiring groove extending in one direction in an interlayer insulating film, a step of embedding a lower electrode in the wiring groove, Depositing a barrier insulating film on the interlayer insulating film including the step of forming an opening communicating with the lower electrode in the barrier insulating film, and depositing a resistance change layer on the barrier insulating film including the lower electrode A step of depositing an upper electrode layer on the variable resistance layer, and removing a part of the upper electrode layer and the variable resistance layer to form a line extending in a direction perpendicular to the one direction. Forming the upper electrode and the variable resistance layer.
　本発明の第４の視点においては、第１層間絶縁膜において一方向に所定の長さで延在した配線溝を形成する工程と、前記配線溝に下部電極を埋め込む工程と、前記下部電極を含む前記第１層間絶縁膜上に第１バリア絶縁膜を堆積する工程と、前記第１バリア絶縁膜において前記下部電極に通ずる２つの開口部を形成する工程と、前記下部電極を含む前記第１バリア絶縁膜上に抵抗変化層を堆積する工程と、前記抵抗変化層上に上部電極層を堆積する工程と、前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記２つの開口部の一方の開口部上を通るように前記一方向の直角方向に延在したライン状の第１上部電極及び第１抵抗変化層を形成するとともに、前記２つの開口部の他方の開口部上に配されたブロック状の第２上部電極及び第２抵抗変化層を形成する工程と、を含むことを特徴とする。 In a fourth aspect of the present invention, a step of forming a wiring groove extending in one direction with a predetermined length in the first interlayer insulating film, a step of embedding a lower electrode in the wiring groove, and the lower electrode Including a step of depositing a first barrier insulating film on the first interlayer insulating film, a step of forming two openings communicating with the lower electrode in the first barrier insulating film, and the first including the lower electrode. A step of depositing a resistance change layer on the barrier insulating film; a step of depositing an upper electrode layer on the resistance change layer; and removing the upper electrode layer and a part of the resistance change layer, A line-shaped first upper electrode and a first variable resistance layer extending in a direction perpendicular to the one direction so as to pass over one opening of the opening are formed, and the other opening of the two openings Block-like second upper arranged above Characterized in that it comprises a step of forming an electrode and the second resistance variable layer.
　本発明の前記半導体装置の製造方法において、前記第１上部電極及び前記第１抵抗変化層並びに前記第２上部電極及び前記第２抵抗変化層を含む前記第１バリア絶縁膜上に第２層間絶縁膜を堆積する工程と、前記第２層間絶縁膜の表面を平坦化する工程と、平坦化された前記第２層間絶縁膜上に第２バリア絶縁膜を堆積する工程と、前記第２バリア絶縁膜上に第３層間絶縁膜を堆積する工程と、前記第３層間絶縁膜において前記一方向に延在したライン状の配線溝を形成するとともに、前記第２バリア絶縁膜及び前記第２層間絶縁膜において前記第３層間絶縁膜の前記配線溝から前記第２上部電極に通ずる下穴を形成する工程と、前記第３層間絶縁膜の前記配線溝、及び、前記第２層間絶縁膜の前記下穴に金属を埋め込む工程と、を含むことが好ましい。 In the method of manufacturing a semiconductor device according to the present invention, a second interlayer insulating layer is formed on the first barrier insulating film including the first upper electrode, the first variable resistance layer, the second upper electrode, and the second variable resistance layer. Depositing a film, planarizing a surface of the second interlayer insulating film, depositing a second barrier insulating film on the planarized second interlayer insulating film, and the second barrier insulation. Depositing a third interlayer insulating film on the film; forming a line-shaped wiring groove extending in the one direction in the third interlayer insulating film; and forming the second barrier insulating film and the second interlayer insulating film Forming a prepared hole in the film from the wiring groove of the third interlayer insulating film to the second upper electrode; the wiring groove of the third interlayer insulating film; and the lower part of the second interlayer insulating film. Embedding a metal in the hole. It is preferred.
　本発明によれば、抵抗変化素子の上部電極を配線に用いることで、従来用いていた銅配線、および銅配線へ接続するためのビアが不要となり、抵抗変化素子の面積を小さくでき、その作製工程数も少くできる。さらに、使われなくなった銅配線を他の用途に用いることができる。 According to the present invention, by using the upper electrode of the resistance change element for the wiring, the copper wiring used conventionally and the via for connecting to the copper wiring become unnecessary, the area of the resistance change element can be reduced, and the production thereof The number of processes can be reduced. Furthermore, the copper wiring that is no longer used can be used for other purposes.
本発明の実施例１に係る半導体装置における抵抗変化素子の構成を模式的に示した（ａ）上面図、及び（ｂ）断面図である。1A is a top view and FIG. 2B is a cross-sectional view schematically showing a configuration of a variable resistance element in a semiconductor device according to Example 1 of the present invention. 本発明の実施例１に係る半導体装置における多層銅配線中に形成された抵抗変化素子を用いたクロスバースイッチの構成を模式的に示した（ａ）上面図、及び（ｂ）（ａ）のＸ－Ｘ´間の断面図である。(A) Top view which showed typically the structure of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device based on Example 1 of this invention, (b) (a) It is sectional drawing between XX '. 本発明の実施例１に係る半導体装置における多層銅配線中に形成された抵抗変化素子を用いたクロスバースイッチの製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例２に係る半導体装置における相補型抵抗変化素子の構成を模式的に示した（ａ）上面図、及び（ｂ）断面図である。4A is a top view and FIG. 5B is a cross-sectional view schematically showing a configuration of a complementary resistance change element in a semiconductor device according to Example 2 of the present invention. 本発明の実施例２に係る半導体装置における多層銅配線中に形成された相補型抵抗変化素子を用いたクロスバースイッチの構成を模式的に示した（ａ）上面図、及び（ｂ）（ａ）のＸ－Ｘ´間の断面図、並びに（ｃ）（ａ）のＹ－Ｙ´間の断面図である。(A) Top view which showed typically the structure of the crossbar switch using the complementary resistance change element formed in the multilayer copper wiring in the semiconductor device based on Example 2 of this invention, (b) (a FIG. 6 is a cross-sectional view taken along the line XX ′ in FIG. 本発明の実施例２に係る半導体装置における多層銅配線中に形成された相補型抵抗変化素子を用いたクロスバースイッチの製造方法を模式的に示した第１の工程断面図である。It is 1st process sectional drawing which showed typically the manufacturing method of the crossbar switch using the complementary resistance change element formed in the multilayer copper wiring in the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例２に係る半導体装置における多層銅配線中に形成された相補型抵抗変化素子を用いたクロスバースイッチの製造方法を模式的に示した第２の工程断面図である。It is 2nd process sectional drawing which showed typically the manufacturing method of the crossbar switch using the complementary resistance change element formed in the multilayer copper wiring in the semiconductor device which concerns on Example 2 of this invention. 抵抗変化素子の（ａ）断面構造、及び（ｂ）記号、並びに（ｃ）電圧印加の様子を示した模式図である。It is the schematic diagram which showed the (a) cross-section of a resistance change element, the (b) symbol, and the state of (c) voltage application. 相補型抵抗変化素子の（ａ）断面構造、及び（ｂ）接続構成を示した模式図である。It is the schematic diagram which showed (a) cross-section of a complementary resistance change element, and (b) connection structure. 従来例に係る半導体装置における抵抗変化素子の構成を模式的に示した（ａ）平面図、及（ｂ）（ａ）のＸ－Ｘ´間の断面図である。It is (a) top view which showed typically the structure of the resistance change element in the semiconductor device which concerns on a prior art example, and sectional drawing between XX 'of (b) and (a). 抵抗変化素子を用いた従来例のクロスバースイッチを模式的に示した回路図である。It is the circuit diagram which showed typically the crossbar switch of the prior art example using a resistance change element. 相補型抵抗変化素子を用いた従来例のクロスバースイッチを模式的に示した回路図である。It is the circuit diagram which showed typically the crossbar switch of the prior art example using a complementary resistance change element.
　本発明の実施形態１に係る半導体装置では、半導体基板（図２の１０１）上の多層配線層の内部に２つ以上の抵抗変化素子（図２の１００）を有する半導体装置であって、前記抵抗変化素子は、下部電極（図２の１０５）と上部電極（図２の１１２）との間に抵抗が変化する抵抗変化層（図２の１１１）が介在した構成となっており、前記多層配線層における所定の配線層の配線は、前記下部電極を兼ね、前記上部電極は、一方向に延在したライン状に形成されるとともに、前記抵抗変化素子に対して前記一方向に沿って隣接する他の第１の抵抗変化素子の上部電極をも兼ねる。 The semiconductor device according to Embodiment 1 of the present invention is a semiconductor device having two or more variable resistance elements (100 in FIG. 2) inside a multilayer wiring layer on a semiconductor substrate (101 in FIG. 2), The variable resistance element has a configuration in which a variable resistance layer (111 in FIG. 2) whose resistance changes is interposed between a lower electrode (105 in FIG. 2) and an upper electrode (112 in FIG. 2). A wiring of a predetermined wiring layer in the wiring layer also serves as the lower electrode, and the upper electrode is formed in a line extending in one direction and adjacent to the resistance change element along the one direction. It also serves as the upper electrode of the other first variable resistance element.
　本発明の実施形態２に係る半導体装置では、半導体基板（図５の３０１）上の多層配線層の内部に２つ以上の相補型抵抗変化素子（図５の２００）を有する半導体装置であって、前記相補型抵抗変化素子は、下部電極（図５の３０５）と第１上部電極（図５の３１３）との間に抵抗が変化する第１抵抗変化層（図５の３１１）が介在するとともに、前記第１上部電極から離間した位置にて前記下部電極と第２上部電極（図５の３１４）との間に抵抗が変化する第２抵抗変化層（図５の３１２）が介在した構成となっており、前記下部電極は、前記多層配線層における所定の配線層に配され、前記第１上部電極は、一方向に延在したライン状に形成されるとともに、前記相補型抵抗変化素子に対して前記一方向に沿って隣接する他の第１の相補型抵抗変化素子の第１上部電極をも兼ねる。 The semiconductor device according to Embodiment 2 of the present invention is a semiconductor device having two or more complementary resistance change elements (200 in FIG. 5) inside a multilayer wiring layer on a semiconductor substrate (301 in FIG. 5). In the complementary resistance change element, a first resistance change layer (311 in FIG. 5) whose resistance changes is interposed between the lower electrode (305 in FIG. 5) and the first upper electrode (313 in FIG. 5). In addition, a configuration in which a second variable resistance layer (312 in FIG. 5) having a resistance change is interposed between the lower electrode and the second upper electrode (314 in FIG. 5) at a position separated from the first upper electrode. The lower electrode is disposed on a predetermined wiring layer in the multilayer wiring layer, the first upper electrode is formed in a line extending in one direction, and the complementary resistance change element Another first phase adjacent to each other along the one direction with respect to Also serve as the first upper electrode type variable resistance element.
　本発明の実施形態３に係る半導体装置の製造方法では、層間絶縁膜において一方向に延在した配線溝を形成する工程（図３（ａ）のステップ）と、前記配線溝に下部電極を埋め込む工程（図３（ａ）のステップ）と、前記下部電極を含む前記層間絶縁膜上にバリア絶縁膜を堆積する工程（図３（ａ）のステップ）と、前記バリア絶縁膜において前記下部電極に通ずる開口部を形成する工程（図３（ｂ）のステップ）と、前記下部電極を含む前記バリア絶縁膜上に抵抗変化層を堆積する工程（図３（ｃ）のステップ）と、前記抵抗変化層上に上部電極層を堆積する工程（図３（ｃ）のステップ）と、前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記一方向の直角方向に延在したライン状の前記上部電極及び前記抵抗変化層を形成する工程（図３（ｃ）のステップ）と、を含む。 In the method of manufacturing a semiconductor device according to the third embodiment of the present invention, a step of forming a wiring groove extending in one direction in the interlayer insulating film (step in FIG. 3A) and a lower electrode are embedded in the wiring groove. A step (step of FIG. 3 (a)), a step of depositing a barrier insulating film on the interlayer insulating film including the lower electrode (step of FIG. 3 (a)), and the lower electrode in the barrier insulating film; A step of forming a communicating opening (step of FIG. 3B), a step of depositing a variable resistance layer on the barrier insulating film including the lower electrode (step of FIG. 3C), and the resistance change A step of depositing an upper electrode layer on the layer (step of FIG. 3C), and a line extending in a direction perpendicular to the one direction by removing a part of the upper electrode layer and the variable resistance layer. The upper electrode and the resistance change A step of forming a (step FIG. 3 (c)), including.
　本発明の実施形態４に係る半導体装置の製造方法では、第１層間絶縁膜において一方向に所定の長さで延在した配線溝を形成する工程（図６（ａ）のステップ）と、前記配線溝に下部電極を埋め込む工程（図６（ａ）のステップ）と、前記下部電極を含む前記第１層間絶縁膜上に第１バリア絶縁膜を堆積する工程（図６（ａ）のステップ）と、前記第１バリア絶縁膜において前記下部電極に通ずる２つの開口部を形成する工程（図６（ｂ）のステップ）と、前記下部電極を含む前記第１バリア絶縁膜上に抵抗変化層を堆積する工程（図６（ｃ）のステップ）と、前記抵抗変化層上に上部電極層を堆積する工程（図６（ｃ）のステップ）と、前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記２つの開口部の一方の開口部上を通るように前記一方向の直角方向に延在したライン状の第１上部電極及び第１抵抗変化層を形成するとともに、前記２つの開口部の他方の開口部上に配されたブロック状の第２上部電極及び第２抵抗変化層を形成する工程（図７（ａ）のステップ）と、を含む。 In the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, a step of forming a wiring trench extending in one direction with a predetermined length in the first interlayer insulating film (step of FIG. 6A), A step of embedding the lower electrode in the wiring trench (step of FIG. 6A) and a step of depositing a first barrier insulating film on the first interlayer insulating film including the lower electrode (step of FIG. 6A) A step of forming two openings communicating with the lower electrode in the first barrier insulating film (step of FIG. 6B), and a variable resistance layer on the first barrier insulating film including the lower electrode. Step of depositing (step of FIG. 6C), step of depositing the upper electrode layer on the variable resistance layer (step of FIG. 6C), part of the upper electrode layer and the variable resistance layer Removing one of the two openings A linear first upper electrode and a first variable resistance layer extending in a direction perpendicular to the one direction so as to pass through, and a block-like shape disposed on the other opening of the two openings Forming a second upper electrode and a second variable resistance layer (step of FIG. 7A).
　なお、本出願において図面参照符号を付している場合は、それらは、専ら理解を助けるためのものであり、図示の態様に限定することを意図するものではない。 In addition, when drawing reference numerals are given in the present application, they are exclusively for helping understanding, and are not intended to be limited to the illustrated modes.
　本発明の実施例１に係る半導体装置について図面を用いて説明する。図１は、本発明の実施例１に係る半導体装置における抵抗変化素子の構成を模式的に示した（ａ）上面図、及び（ｂ）断面図である。図２は、本発明の実施例１に係る半導体装置における多層銅配線中に形成された抵抗変化素子を用いたクロスバースイッチの構成を模式的に示した（ａ）上面図、及び（ｂ）（ａ）のＸ－Ｘ´間の断面図である。なお、図１は、クロスバースイッチの一つの構成要素である抵抗変化素子を示している。また、抵抗変化素子を用いたクロスバースイッチの回路図については、図１１を参照されたい。 A semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1A is a top view and FIG. 1B is a cross-sectional view schematically showing a configuration of a variable resistance element in a semiconductor device according to Example 1 of the present invention. FIGS. 2A and 2B schematically show the configuration of the crossbar switch using the resistance change element formed in the multilayer copper wiring in the semiconductor device according to the first embodiment of the present invention, and FIG. It is sectional drawing between XX 'of (a). FIG. 1 shows a variable resistance element that is one component of the crossbar switch. For a circuit diagram of a crossbar switch using a resistance change element, refer to FIG.
　実施例１に係る半導体装置は、半導体基板上に、絶縁体中に多層の銅配線が形成された多層銅配線層を有するものである。半導体装置は、多層銅配線中において抵抗変化素子を有する。抵抗変化素子は、図１に示すように、第１銅配線４１の上の一部分に抵抗変化層４３が積層され、抵抗変化層４３を覆うように第２電極４２が形成されている。図１（ｂ）の断面図において、第１銅配線４１は紙面に対して垂直な方向に延びていて、紙面に対して垂直な方向に沿って隣接する同じ構造を有する他の第１の抵抗変化素子の第１銅配線４１を兼ねている。一方、第２電極４２は紙面に対して左右方向に平行に延びていて、紙面に対して左右方向に平行な方向に沿って隣接する同じ構造を有する他の第２の抵抗変化素子（他の第１の抵抗変化素子とは異なるもの）の第２電極を兼ねている。なお、抵抗変化層４３は、第２電極４２と重なるように、紙面に対して左右方向に平行に延びているが、第１銅配線４１と第２電極４２とが重なる領域にのみ配されていてもよい。第２電極４２は、多層銅配線層における２つ銅配線間に、銅とは異なる材料で形成されている。従来例では、クロスバースイッチを形成するために２層の銅配線を必要としたが、本発明の実施例１によると、一層の銅配線を用いるだけでよい。その結果、プロセス工数が削減される。ただし、１つの抵抗変化素子あたりの面積は、４Ｆ２であり、従来例と同じである。従来の多層銅配線層中にクロスバースイッチを形成するには二層の銅配線が必要であったが、本発明の実施例１では一層分で済むために、クロスバースイッチを２つ積層した場合には、２倍の集積度でクロスバースイッチを形成できるようになる。 The semiconductor device according to Example 1 has a multilayer copper wiring layer in which a multilayer copper wiring is formed in an insulator on a semiconductor substrate. The semiconductor device has a resistance change element in the multilayer copper wiring. As shown in FIG. 1, the variable resistance element has a variable resistance layer 43 stacked on a portion of the first copper wiring 41, and a second electrode 42 is formed so as to cover the variable resistance layer 43. In the cross-sectional view of FIG. 1B, the first copper wiring 41 extends in a direction perpendicular to the paper surface, and is another first resistor having the same structure adjacent along the direction perpendicular to the paper surface. It also serves as the first copper wiring 41 of the change element. On the other hand, the second electrode 42 extends in parallel in the left-right direction with respect to the paper surface, and another second resistance change element (other It also serves as the second electrode (which is different from the first variable resistance element). The resistance change layer 43 extends parallel to the paper surface in the left-right direction so as to overlap the second electrode 42, but is disposed only in the region where the first copper wiring 41 and the second electrode 42 overlap. May be. The second electrode 42 is formed of a material different from copper between the two copper wirings in the multilayer copper wiring layer. In the conventional example, two layers of copper wiring are required to form the crossbar switch. However, according to the first embodiment of the present invention, only one layer of copper wiring may be used. As a result, process man-hours are reduced. However, the area per one variable resistance element is 4F 2, is the same as the conventional example. In order to form a crossbar switch in a conventional multilayer copper wiring layer, two layers of copper wiring were required. However, in Example 1 of the present invention, two layers of crossbar switches were stacked in order to suffice for one layer. In some cases, a crossbar switch can be formed with twice the degree of integration.
　図２は、図１に示した抵抗変化素子を用いたクロスバースイッチを半導体基板１０１上の多層銅配線層の内部に形成した一例である。多層銅配線層は、半導体基板１０１上にて、層間絶縁膜１０２、バリア絶縁膜１０３、層間絶縁膜１０４、バリア絶縁膜１０７、層間絶縁膜１２０の順に積層した絶縁積層体を有する。多層銅配線層は、層間絶縁膜１０４及びバリア絶縁膜１０３に形成された配線溝にバリアメタル１０６を介して第１銅配線１０５が埋め込まれている。第１銅配線１０５上には抵抗変化層１１１及び上部電極１１２が形成されている。第１銅配線１０５と抵抗変化層１１１及び上部電極１１２とが重なった領域に抵抗変化素子１００が形成される。 FIG. 2 shows an example in which a crossbar switch using the resistance change element shown in FIG. 1 is formed inside a multilayer copper wiring layer on the semiconductor substrate 101. The multilayer copper wiring layer has an insulating stacked body in which an interlayer insulating film 102, a barrier insulating film 103, an interlayer insulating film 104, a barrier insulating film 107, and an interlayer insulating film 120 are stacked in this order on the semiconductor substrate 101. In the multilayer copper wiring layer, a first copper wiring 105 is embedded in a wiring groove formed in the interlayer insulating film 104 and the barrier insulating film 103 via a barrier metal 106. A variable resistance layer 111 and an upper electrode 112 are formed on the first copper wiring 105. The variable resistance element 100 is formed in a region where the first copper wiring 105 overlaps with the variable resistance layer 111 and the upper electrode 112.
　抵抗変化素子１００において、第１銅配線１０５は図８（ａ）の第１電極１１に対応し、上部電極１１２は図８（ａ）の第２電極１２に対応している。抵抗変化素子１００は、抵抗変化型不揮発素子であり、例えば、イオン伝導体中における金属イオン移動と電気化学反応とを利用したスイッチング素子とすることができる。抵抗変化素子１００は、第１電極となる第１銅配線１０５と、第２電極となる上部電極１１２との間に抵抗変化層１１１が介在した構成となっている。第１銅配線１０５及びバリアメタル１０６を含む層間絶縁膜１０４上には、バリア絶縁膜１０７が形成されている。バリア絶縁膜１０７は抵抗変化素子１００が形成される領域で開口部が形成されている。抵抗変化素子１００は、バリア絶縁膜１０７に形成された開口部の領域にて、抵抗変化層１１１の底面と第１銅配線１０５の上面とが接しており、さらに、抵抗変化層１１１の上面と上部電極１１２の底面とが接している。抵抗変化素子１００は、電圧の印加、あるいは電流を流すことで高抵抗状態と低抵抗状態との間のスイッチングを行い、例えば、抵抗変化層１１１中への第１銅配線１０５に含まれる金属イオンの電解による拡散を利用してスイッチングを行う。抵抗変化層１１１及び上部電極１１２を含むバリア絶縁膜１０７上には層間絶縁膜１２０が形成されている。 In the resistance change element 100, the first copper wiring 105 corresponds to the first electrode 11 in FIG. 8A, and the upper electrode 112 corresponds to the second electrode 12 in FIG. The variable resistance element 100 is a variable resistance nonvolatile element, and can be, for example, a switching element that utilizes metal ion migration and an electrochemical reaction in an ion conductor. The resistance change element 100 has a configuration in which a resistance change layer 111 is interposed between a first copper wiring 105 serving as a first electrode and an upper electrode 112 serving as a second electrode. A barrier insulating film 107 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106. The barrier insulating film 107 has an opening in a region where the variable resistance element 100 is formed. In the variable resistance element 100, the bottom surface of the variable resistance layer 111 and the top surface of the first copper wiring 105 are in contact with each other in the region of the opening formed in the barrier insulating film 107. The bottom surface of the upper electrode 112 is in contact. The resistance change element 100 performs switching between a high resistance state and a low resistance state by applying a voltage or passing a current, for example, metal ions included in the first copper wiring 105 into the resistance change layer 111. Switching is performed using diffusion caused by electrolysis. An interlayer insulating film 120 is formed on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112.
　半導体基板１０１は、半導体素子（図示せず）が形成された基板である。半導体基板１０１には、例えば、シリコン基板、単結晶基板、ＳＯＩ（Silicon on Insulator）基板、ＴＦＴ（Thin Film Transistor）基板、液晶製造用基板等の基板、あるいは多層銅配線層備えたシリコン基板を用いることができる。 The semiconductor substrate 101 is a substrate on which a semiconductor element (not shown) is formed. As the semiconductor substrate 101, for example, a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, a substrate such as a liquid crystal manufacturing substrate, or a silicon substrate provided with a multilayer copper wiring layer is used. be able to.
　層間絶縁膜１０２は、半導体基板１０１上に形成された絶縁膜である。層間絶縁膜１０２には、例えば、シリコン酸化膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）等を用いることができる。層間絶縁膜１０２は、複数の絶縁膜を積層したものであってもよい。 The interlayer insulating film 102 is an insulating film formed on the semiconductor substrate 101. As the interlayer insulating film 102, for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used. The interlayer insulating film 102 may be a stack of a plurality of insulating films.
　バリア絶縁膜１０３は、層間絶縁膜１０２、１０４間に介在したバリア性を有する絶縁膜である。バリア絶縁膜１０３は、第１銅配線１０５の加工時にエッチングストップ層としての役割を有する。バリア絶縁膜１０３には、例えば、ＳｉＮ膜、ＳｉＣ膜、ＳｉＣＮ膜等を用いることができる。バリア絶縁膜１０３は、配線溝のエッチング条件の選択によっては削除することもできる。 The barrier insulating film 103 is an insulating film having a barrier property interposed between the interlayer insulating films 102 and 104. The barrier insulating film 103 serves as an etching stop layer when the first copper wiring 105 is processed. As the barrier insulating film 103, for example, a SiN film, a SiC film, a SiCN film, or the like can be used. The barrier insulating film 103 can be removed depending on the selection of the etching conditions for the wiring trench.
　層間絶縁膜１０４は、バリア絶縁膜１０３上に形成された絶縁膜である。層間絶縁膜１０４には、例えば、シリコン酸化膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）等を用いることができる。層間絶縁膜１０４は、複数の絶縁膜を積層したものであってもよい。層間絶縁膜１０４には、第１銅配線１０５を埋め込むための配線溝が形成されている。当該配線溝は、図２（ｂ）において紙面に対する垂直方向に延在した溝である。当該配線溝には、第１バリアメタル１０６を介して第１銅配線１０５が埋め込まれている。 The interlayer insulating film 104 is an insulating film formed on the barrier insulating film 103. As the interlayer insulating film 104, for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used. The interlayer insulating film 104 may be a stack of a plurality of insulating films. In the interlayer insulating film 104, a wiring trench for embedding the first copper wiring 105 is formed. The wiring groove is a groove extending in a direction perpendicular to the paper surface in FIG. A first copper wiring 105 is embedded in the wiring trench via a first barrier metal 106.
　第１銅配線１０５は、層間絶縁膜１０４及びバリア絶縁膜１０３に形成された配線溝に第１バリアメタル１０６を介して埋め込まれた配線である。第１銅配線１０５は、抵抗変化素子１００の第１電極を兼ね、所定の位置にて抵抗変化層１１１と直接接している。なお、第１銅配線１０５と抵抗変化層１１１との間には、電極層などが挿入されていてもよい。電極層が形成される場合は、上部電極１１２と抵抗変化層１１１は連続工程にて堆積され、連続工程にて加工される。第１銅配線１０５には、抵抗変化層１１１において拡散、イオン伝導可能な銅が用いられる。第１銅配線１０５は、Ａｌと合金化されていてもよく、シリサイド化、又は窒化されていてもよい。 The first copper wiring 105 is a wiring buried in a wiring groove formed in the interlayer insulating film 104 and the barrier insulating film 103 via the first barrier metal 106. The first copper wiring 105 also serves as the first electrode of the variable resistance element 100 and is in direct contact with the variable resistance layer 111 at a predetermined position. An electrode layer or the like may be inserted between the first copper wiring 105 and the resistance change layer 111. When the electrode layer is formed, the upper electrode 112 and the resistance change layer 111 are deposited in a continuous process and processed in the continuous process. For the first copper wiring 105, copper capable of diffusing and ion conducting in the resistance change layer 111 is used. The first copper wiring 105 may be alloyed with Al, silicided, or nitrided.
　バリアメタル１０６は、第１銅配線１０５に含まれる金属が層間絶縁膜１０４や下層へ拡散することを防止するために、第１銅配線１０５の側面乃至底面を被覆する、バリア性を有する導電性膜である。バリアメタル１０６には、例えば、第１銅配線１０５がＣｕを主成分とする金属元素からなる場合には、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）、炭窒化タングステン（ＷＣＮ）のような高融点金属やその窒化物等、又はそれらの積層膜を用いることができる。 The barrier metal 106 is a conductive material having a barrier property that covers the side surface or the bottom surface of the first copper wiring 105 in order to prevent the metal contained in the first copper wiring 105 from diffusing into the interlayer insulating film 104 or the lower layer. It is a membrane. For example, when the first copper wiring 105 is made of a metal element containing Cu as a main component, the barrier metal 106 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). ), A refractory metal thereof, a nitride thereof, or a laminated film thereof.
　バリア絶縁膜１０７は、第１銅配線１０５及びバリアメタル１０６を含む層間絶縁膜１０４上に形成され、第１銅配線１０５に係る金属（例えば、銅）の酸化を防いだり、層間絶縁膜１０４中への第１銅配線１０５に係る金属の拡散を防いだりする役割を有する。バリア絶縁膜１０７には、例えば、ＳｉＣ膜、ＳｉＣＮ膜、ＳｉＮ膜、及びそれらの積層構造等を用いることができる。バリア絶縁膜１０７は、第１銅配線１０５上の第１銅配線１０５と抵抗変化層１１１とが重なる領域にて開口部を有する。バリア絶縁膜１０７の開口部においては、第１銅配線１０５と抵抗変化層１１１とが接している。バリア絶縁膜１０７の開口部は、第１銅配線１０５の領域内に形成されている。このようにすることで、凹凸の小さい第１銅配線１０５の表面上に抵抗変化素子１００を形成することができるようになる。 The barrier insulating film 107 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106 to prevent oxidation of a metal (for example, copper) related to the first copper wiring 105 or in the interlayer insulating film 104. It has a role of preventing the diffusion of the metal related to the first copper wiring 105 to the metal. For the barrier insulating film 107, for example, a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used. The barrier insulating film 107 has an opening in a region where the first copper wiring 105 and the resistance change layer 111 on the first copper wiring 105 overlap. In the opening of the barrier insulating film 107, the first copper wiring 105 and the resistance change layer 111 are in contact with each other. The opening of the barrier insulating film 107 is formed in the region of the first copper wiring 105. By doing so, the variable resistance element 100 can be formed on the surface of the first copper wiring 105 having small irregularities.
　抵抗変化層１１１は、抵抗が変化する膜である。抵抗変化層１１１は、第１銅配線１０５（図８の第１電極１１に相当）に係る金属の作用（拡散、イオン伝導など）により抵抗が変化する材料を用いることができ、抵抗変化素子１００の抵抗変化を金属イオンの析出によって行う場合には、イオン伝導可能な膜が用いられ、例えば、Ｔａを含む酸化物絶縁膜であって、Ｔａ２Ｏ５、ＴａＳｉＯ等を用いることができる。また、抵抗変化層１１１は、下からＴａ２Ｏ５、ＴａＳｉＯの順に積層した積層構造とすることができる。このような積層構造とすることで、抵抗変化層１１１をイオン伝導層として用いた場合には、低抵抗時（ＯＮ時）にイオン伝導層内部に形成される金属イオン（例えば、銅イオン）による架橋を、Ｔａ２Ｏ５層で分断することで、ＯＦＦ時に金属イオンを容易に回収することができるようになり、スイッチング特性を向上させることができるようになる。抵抗変化層１１１は、第１銅配線１０５、バリア絶縁膜１０７の開口部乃至バリア絶縁膜１０７上に形成されている。抵抗変化層１１１は、図２（ａ）において左右方向に延在しており、上部電極１１２と同じ領域で重なるように配されている。 The resistance change layer 111 is a film whose resistance changes. The resistance change layer 111 can be made of a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of the metal related to the first copper wiring 105 (corresponding to the first electrode 11 in FIG. 8). When the resistance change is performed by deposition of metal ions, a film capable of ion conduction is used. For example, an oxide insulating film containing Ta, such as Ta 2 O 5 or TaSiO can be used. Further, the resistance change layer 111 can have a stacked structure in which Ta 2 O 5 and TaSiO are stacked in this order from the bottom. With such a laminated structure, when the resistance change layer 111 is used as an ion conductive layer, metal ions (for example, copper ions) formed inside the ion conductive layer at the time of low resistance (ON) are used. By dividing the cross-linking with the Ta 2 O 5 layer, metal ions can be easily recovered at the time of OFF, and switching characteristics can be improved. The resistance change layer 111 is formed on the first copper wiring 105 and the opening of the barrier insulating film 107 or on the barrier insulating film 107. The resistance change layer 111 extends in the left-right direction in FIG. 2A and is arranged so as to overlap in the same region as the upper electrode 112.
　上部電極１１２は、図８の第２電極１２の役割を担い、抵抗変化層１１１の上面と接している。上部電極１１２には、第１銅配線１０５に係る金属よりもイオン化しにくく、抵抗変化層１１１において拡散、イオン伝導しにくい金属が用いられ、抵抗変化層１１１に係る金属成分（Ｔａ）よりも酸化の自由エネルギーの絶対値が小さい金属材料とすることが好ましい。上部電極１１２には、例えば、プラチナ（Ｐｔ）、ルテニウム（Ｒｕ）、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）、炭窒化タングステン（ＷＣＮ）のような高融点金属やその窒化物等、又はそれらの積層膜を用いることができる。また、上部電極１１２の上面及び側面にＰｔ、Ｒｕ等の金属材料を主成分として酸素を添加してもよく、また酸素を添加した層との積層構造にしてもよい。上部電極１１２は、図２（ａ）において左右方向に延在しており、抵抗変化層１１１と同じ領域で重なるように配されている。 The upper electrode 112 plays the role of the second electrode 12 in FIG. 8 and is in contact with the upper surface of the resistance change layer 111. For the upper electrode 112, a metal that is less ionized than the metal related to the first copper wiring 105, is less likely to diffuse and ion-conduct in the resistance change layer 111, and is oxidized more than the metal component (Ta) related to the resistance change layer 111. It is preferable to use a metal material having a small absolute value of free energy. The upper electrode 112 includes, for example, a refractory metal such as platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), or nitride thereof. A thing etc. or those laminated films can be used. Further, oxygen may be added to a top surface and a side surface of the upper electrode 112 with a metal material such as Pt or Ru as a main component, or a stacked structure with a layer to which oxygen is added may be employed. The upper electrode 112 extends in the left-right direction in FIG. 2A and is disposed so as to overlap in the same region as the resistance change layer 111.
　第１銅配線１０５、上部電極１１２及び抵抗変化層１１１は、図２（ａ）に示すパターンとなっている。つまり、第１銅配線１０５は、図２（ａ）の上下方向に延在したパターンとなっており、線幅Ｆ、線間隔Ｆで複数形成されている。上部電極１１２及び抵抗変化層１１１は、図２（ａ）の左右方向に延在したパターンとなっており、第１銅配線１０５よりも図２（ａ）の紙面に対して上側に配され、第１銅配線１０５と直交（立体交差）し、線幅Ｆ、線間隔Ｆで複数形成されている。ここで、抵抗変化層１１１は、上部電極１１２と同一の形状をしている。さらに、Ｆは最小加工寸法を示しており、例えば、１８０ｎｍ以下２０ｎｍ以上である。 The first copper wiring 105, the upper electrode 112, and the resistance change layer 111 have a pattern shown in FIG. That is, the first copper wiring 105 has a pattern extending in the vertical direction in FIG. 2A, and a plurality of first copper wirings 105 are formed with a line width F and a line interval F. The upper electrode 112 and the resistance change layer 111 have a pattern extending in the left-right direction in FIG. 2A, and are arranged above the first copper wiring 105 with respect to the paper surface of FIG. The first copper wiring 105 is orthogonal (three-dimensionally intersected), and a plurality of lines are formed with a line width F and a line interval F. Here, the resistance change layer 111 has the same shape as the upper electrode 112. Further, F indicates a minimum processing dimension, for example, 180 nm or less and 20 nm or more.
　層間絶縁膜１２０は、抵抗変化層１１１及び上部電極１１２を含むバリア絶縁膜１０７上に形成された絶縁膜である。層間絶縁膜１２０には、例えば、シリコン酸化膜、ＳｉＯＣ膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）などを用いることができる。層間絶縁膜１２０は、複数の絶縁膜を積層したものであってもよい。層間絶縁膜１２０は、層間絶縁膜１０４と同一材料としてもよい。 The interlayer insulating film 120 is an insulating film formed on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112. As the interlayer insulating film 120, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used. The interlayer insulating film 120 may be a laminate of a plurality of insulating films. The interlayer insulating film 120 may be made of the same material as the interlayer insulating film 104.
　次に、本発明の実施例１に係る半導体装置における多層銅配線中に形成された抵抗変化素子を用いたクロスバースイッチの製造方法について図面を用いて説明する。図３は、本発明の実施例１に係るクロスバースイッチの製造方法を模式的に示した工程断面図である。 Next, a method for manufacturing a crossbar switch using a resistance change element formed in a multilayer copper wiring in the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a process cross-sectional view schematically showing the method for manufacturing the crossbar switch according to the first embodiment of the present invention.
　まず、半導体基板１０１（例えば、半導体素子が形成された基板）上に層間絶縁膜１０２（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積し、その後、層間絶縁膜１０２上にバリア絶縁膜１０３（例えば、ＳｉＮ膜、膜厚５０ｎｍ）を堆積し、その後、バリア絶縁膜１０３上に層間絶縁膜１０４（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積し、その後、リソグラフィ法（フォトレジスト形成、ドライエッチング、フォトレジスト除去を含む）を用いて、層間絶縁膜１０４に配線溝を形成し、その後、当該配線溝にバリアメタル１０６（例えば、ＴａＮ／Ｔａ、膜厚５ｎｍ／５ｎｍ）を介して第１銅配線１０５を埋め込み、さらに、その後、第１銅配線１０５及びバリアメタル１０６を含む層間絶縁膜１０４上にバリア絶縁膜１０７（例えば、ＳｉＮ膜、膜厚５０ｎｍ）を堆積する（ステップＡ１；図３（ａ）参照）。 First, an interlayer insulating film 102 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 101 (for example, a substrate on which a semiconductor element is formed), and then a barrier insulating film 103 (for example, on the interlayer insulating film 102). For example, a SiN film having a film thickness of 50 nm is deposited, and thereafter, an interlayer insulating film 104 (for example, a silicon oxide film having a film thickness of 300 nm) is deposited on the barrier insulating film 103. Etching and photoresist removal are used to form a wiring groove in the interlayer insulating film 104, and then the first wiring via the barrier metal 106 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring groove. The copper wiring 105 is embedded, and then the barrier insulating film 1 is formed on the interlayer insulating film 104 including the first copper wiring 105 and the barrier metal 106. 7 (eg, SiN film, thickness 50 nm) is deposited (step A1; see Figure 3 (a)).
　ステップＡ１において、層間絶縁膜１０２、１０４、バリア絶縁膜１０３、１０７は、プラズマＣＶＤ法によって形成することができる。ここで、プラズマＣＶＤ（Chemical Vapor Deposition）法とは、例えば、気体原料、あるいは液体原料を気化させることで減圧下の反応室に連続的に供給し、プラズマエネルギーによって、分子を励起状態にし、気相反応、あるいは基板表面反応などによって基板上に連続膜を形成する手法である。 In step A1, the interlayer insulating films 102 and 104 and the barrier insulating films 103 and 107 can be formed by a plasma CVD method. Here, the plasma CVD (Chemical Vapor Deposition) method refers to, for example, vaporizing a gas source or a liquid source to continuously supply the reaction chamber under reduced pressure, bringing the molecules into an excited state by plasma energy, In this method, a continuous film is formed on a substrate by a phase reaction or a substrate surface reaction.
　また、ステップＡ１において、第１銅配線１０５は、例えば、ＰＶＤ（Physical Vapor Deposition）法によってバリアメタル１０６（例えば、ＴａＮ／Ｔａの積層膜）を形成し、ＰＶＤ法によるＣｕシードの形成後、電解めっき法によって銅を配線溝内に埋設し、２００℃以上の温度で熱処理処理後、ＣＭＰ（Chemical Mechanical Polishing）法によって配線溝内以外の余剰の銅を除去することで形成することができる。このような一連の銅配線の形成方法は、当該技術分野における一般的な手法を用いることができる。ここで、ＣＭＰ法とは、多層配線形成プロセス中に生じるウェハ表面の凹凸を、研磨液をウェハ表面に流しながら回転させた研磨パッドに接触させて研磨することによって平坦化する方法である。配線溝に埋め込まれた余剰の銅を研磨することによって埋め込み配線（ダマシン配線）を形成したり、層間絶縁膜を研磨したりすることで平坦化を行う。 Further, in step A1, the first copper wiring 105 is formed by forming a barrier metal 106 (for example, a TaN / Ta laminated film) by, for example, PVD (Physical Vapor Deposition) method, and after forming a Cu seed by PVD method, electrolysis It can be formed by embedding copper in the wiring trench by a plating method, after heat treatment at a temperature of 200 ° C. or higher, and then removing excess copper other than in the wiring trench by a CMP (Chemical-Mechanical-Polishing) method. As a method for forming such a series of copper wirings, a general method in this technical field can be used. Here, the CMP method is a method of flattening by polishing the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface. The excess copper embedded in the wiring trench is polished to form a buried wiring (damascene wiring), or the interlayer insulating film is polished to perform planarization.
　次に、バリア絶縁膜１０７上にシリコン酸化膜等（図示せず）を堆積し、当該シリコン酸化膜等上に開口部１０８の形成用パターンを有するフォトレジスト（図示せず）を形成し、当該フォトレジストをマスクとしてシリコン酸化膜等をドライエッチングすることにより開口部形成用パターンをシリコン酸化膜等に転写し、その後、酸素プラズマアッシング等によってフォトレジストを除去し、その後、シリコン酸化膜等をマスクとして開口部形成用パターンから露出するバリア絶縁膜１０７をエッチバック（ドライエッチング）することにより、バリア絶縁膜１０７に開口部１０８を形成して、バリア絶縁膜１０７の開口部１０８から第１銅配線１０５を露出させ、その後、アミン系の剥離液などで有機剥離処理を行うことで、第１銅配線１０５の露出面に形成された酸化銅を除去するとともに、エッチバック時に発生したエッチング複生成物などを除去し、さらに、その後、バリア絶縁膜１０７上のシリコン酸化膜等を取り除く（ステップＡ２；図３（ｂ）参照）。 Next, a silicon oxide film or the like (not shown) is deposited on the barrier insulating film 107, and a photoresist (not shown) having a pattern for forming the opening 108 is formed on the silicon oxide film or the like. The silicon oxide film etc. is dry etched using the photoresist as a mask to transfer the opening forming pattern to the silicon oxide film etc., and then the photoresist is removed by oxygen plasma ashing etc., and then the silicon oxide film etc. is masked Etchback (dry etching) the barrier insulating film 107 exposed from the opening forming pattern to form an opening 108 in the barrier insulating film 107, and the first copper wiring from the opening 108 of the barrier insulating film 107. 105 is exposed, and then an organic stripping process is performed with an amine-based stripping solution, etc. The copper oxide formed on the exposed surface of 105 is removed, the etching by-product generated at the time of etch back is removed, and then the silicon oxide film on the barrier insulating film 107 is removed (step A2; FIG. 3 (b)).
　ステップＡ２において、フォトレジストの開口部形成用パターンをシリコン酸化膜等に転写するとき、ドライエッチングは必ずしもバリア絶縁膜１０７の上面で停止している必要はなく、バリア絶縁膜１０７の内部にまで到達していてもよい。また、バリア絶縁膜１０７の開口部１０８の形状は円形とし、円の直径は１０ｎｍから５００ｎｍとすることができる。 In step A2, when the photoresist opening formation pattern is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop at the upper surface of the barrier insulating film 107, and reaches the inside of the barrier insulating film 107. You may do it. The shape of the opening 108 of the barrier insulating film 107 can be a circle, and the diameter of the circle can be 10 nm to 500 nm.
　次に、第１銅配線１０５を含むバリア絶縁膜１０７上に抵抗変化層１１１（例えば、Ｔａ２Ｏ５、膜厚１５ｎｍ）を堆積し、その後、ＰＶＤ法によって、抵抗変化層１１１上に上部電極１１２（例えば、Ｒｕ膜厚１０ｎｍとＴａ膜厚５０ｎｍの積層構造）を形成し、その後、上部電極１１２上にシリコン酸化膜等（図示せず）を堆積し、その後、シリコン酸化膜等上に上部電極形成用パターンを有するフォトレジスト（図示せず）を形成し、その後、そのフォトレジストをマスクとしてシリコン酸化膜をドライエッチングすることにより上部電極形成用パターンをシリコン酸化膜等に転写し、その後、酸素プラズマアッシング等によってフォトレジストを除去し、その後、シリコン酸化膜をマスクとしてをエッチバック（ドライエッチング）することにより、上部電極１１２及び抵抗変化層１１１を加工し、さらに、その後、エッチングのマスクに用いたシリコン酸化膜等を取り除く（ステップＡ３；図３（ｃ）参照）。 Next, a resistance change layer 111 (for example, Ta 2 O 5 , film thickness of 15 nm) is deposited on the barrier insulating film 107 including the first copper wiring 105, and then the upper electrode is formed on the resistance change layer 111 by the PVD method. 112 (for example, a laminated structure having a Ru film thickness of 10 nm and a Ta film thickness of 50 nm) is formed. Thereafter, a silicon oxide film or the like (not shown) is deposited on the upper electrode 112, and then the upper portion is formed on the silicon oxide film or the like. A photoresist (not shown) having an electrode formation pattern is formed, and then the upper electrode formation pattern is transferred to a silicon oxide film or the like by dry etching the silicon oxide film using the photoresist as a mask. The photoresist is removed by oxygen plasma ashing, etc., and then etched back using the silicon oxide film as a mask (dry etching) Thus, the upper electrode 112 and the resistance change layer 111 are processed, and then the silicon oxide film or the like used for the etching mask is removed (step A3; see FIG. 3C).
　ステップＡ３において、抵抗変化層１１１は、ＰＶＤ法やＣＶＤ法を用いて形成することができる。ステップＡ３では、開口部（図３（ｂ）の１０８）はステップＡ２の有機剥離処理によって水分などが付着しているため、抵抗変化層１１１の堆積前に２５０℃から３５０℃程度の温度にて、減圧下で熱処理を加えて脱ガスしておくことが好ましい。この際、銅表面を再度酸化させないよう、真空下、あるいは窒素雰囲気などにするなどの注意が必要である。 In step A3, the resistance change layer 111 can be formed using a PVD method or a CVD method. In Step A3, the opening (108 in FIG. 3B) is attached with moisture or the like by the organic peeling process in Step A2, so that the resistance change layer 111 is deposited at a temperature of about 250 ° C. to 350 ° C. It is preferable to degas by applying a heat treatment under reduced pressure. At this time, care must be taken such as in a vacuum or a nitrogen atmosphere so that the copper surface is not oxidized again.
　また、ステップＡ３では、抵抗変化層１１１として、遷移金属酸化物（例えば、ＴｉＯ、ＮｉＯ等）を用いた抵抗変化層を用いる場合には、抵抗変化層１１１を堆積する前に電極を成膜してもよい。上部電極１１２には、例えば、Ｔｉ、ＴｉＮ、Ｗ、ＷＮ、Ｔａ、ＴａＮ、Ｒｕ、ＲｕＯｘ等を用いることができ、例えば、それらの積層構造（例えば、ＴａＮ（下層）／Ｒｕ（上層））であっても良い。この時、積層構造の合計膜厚は、抵抗変化層１１１を開口部１０８内部に形成する都合上、好ましくは１０ｎｍ以下であると良い。 In Step A3, when a resistance change layer using a transition metal oxide (eg, TiO, NiO) is used as the resistance change layer 111, an electrode is formed before the resistance change layer 111 is deposited. May be. For the upper electrode 112, for example, Ti, TiN, W, WN, Ta, TaN, Ru, RuOx, or the like can be used. For example, in the laminated structure (for example, TaN (lower layer) / Ru (upper layer)). There may be. At this time, the total film thickness of the laminated structure is preferably 10 nm or less for the convenience of forming the resistance change layer 111 inside the opening 108.
　さらに、ステップＡ３では、フォトレジストの上部電極形成用パターンをシリコン酸化膜等に転写するとき、ドライエッチングは必ずしも上部電極１１２の上面で停止している必要はなく、上部電極１１２の内部にまで到達していてもよい。 Furthermore, in step A3, when the upper electrode formation pattern of the photoresist is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the upper electrode 112, and reaches the inside of the upper electrode 112. You may do it.
　最後に、抵抗変化層１１１及び上部電極１１２を含むバリア絶縁膜１０７上に層間絶縁膜１２０（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積する（ステップＡ４；図２（ｂ）参照）。なお、図示していないが、層間絶縁膜１２０上には多層配線層が形成される。 Finally, an interlayer insulating film 120 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on the barrier insulating film 107 including the resistance change layer 111 and the upper electrode 112 (Step A4; see FIG. 2B). Although not shown, a multilayer wiring layer is formed on the interlayer insulating film 120.
　実施例１によれば、抵抗変化素子１００の上部電極１１２を配線に用いることで、従来用いていた銅配線、および銅配線へ接続するためのビアが不要となり、抵抗変化素子の面積を小さくでき、その作製工程数も少くできる。さらに、使われなくなった銅配線を他の用途に用いることができる。また、上部電極１１２を配線として用い、かつ、多層銅配線のうち第１銅配線１０５の１層を使うだけで、抵抗変化素子１００を用いたクロスバースイッチを形成することができ、上部電極１１２を上層の銅配線を用いて電気的に接続する必要がなくなるので、工程数を少なくすることができる。さらに、上部電極１１２を、一般的に配線幅が太い上層の銅配線で電気的に接続する必要がなくなるので、抵抗変化素子１００の面積をできるだけ小さくすることができる。 According to the first embodiment, by using the upper electrode 112 of the resistance change element 100 for the wiring, the copper wiring used conventionally and the via for connecting to the copper wiring become unnecessary, and the area of the resistance change element can be reduced. The number of manufacturing steps can be reduced. Furthermore, the copper wiring that is no longer used can be used for other purposes. Further, a crossbar switch using the resistance change element 100 can be formed by using the upper electrode 112 as a wiring and using only one layer of the first copper wiring 105 among the multilayer copper wiring. Since there is no need to electrically connect the upper and lower copper wirings, the number of steps can be reduced. Furthermore, since it is not necessary to electrically connect the upper electrode 112 with an upper copper wiring having a generally large wiring width, the area of the resistance change element 100 can be made as small as possible.
　本発明の実施例２に係る半導体装置について図面を用いて説明する。図４は、本発明の実施例２に係る半導体装置における相補型抵抗変化素子の構成を模式的に示した（ａ）上面図、及び（ｂ）断面図である。図５は、本発明の実施例２に係る半導体装置における多層銅配線中に形成された相補型抵抗変化素子を用いたクロスバースイッチの構成を模式的に示した（ａ）上面図、及び（ｂ）（ａ）のＸ－Ｘ´間の断面図、並びに（ｃ）（ａ）のＹ－Ｙ´間の断面図である。なお、図４は、クロスバースイッチの一つの構成要素である相補型抵抗変化素子を示している。また、相補型抵抗変化素子を用いたクロスバースイッチの回路図は図１２を参照されたい。 Example 2 A semiconductor device according to Example 2 of the present invention will be described with reference to the drawings. FIG. 4A is a top view and FIG. 4B is a cross-sectional view schematically showing a configuration of a complementary resistance change element in a semiconductor device according to Example 2 of the present invention. 5A is a top view schematically showing the configuration of a crossbar switch using complementary resistance change elements formed in a multilayer copper wiring in a semiconductor device according to Example 2 of the present invention, and FIG. 2B is a cross-sectional view taken along the line XX ′ in FIG. 2A, and FIG. FIG. 4 shows a complementary resistance change element which is one component of the crossbar switch. Also, refer to FIG. 12 for a circuit diagram of a crossbar switch using a complementary resistance change element.
　実施例２に係る半導体装置は、半導体基板上に、絶縁体中に多層の銅配線が形成された多層銅配線層を有するものである。半導体装置は、多層銅配線中において相補型抵抗変化素子を有する。相補型抵抗変化素子は、図４に示すように、第１銅配線６１の上の一部分に第１抵抗変化層６２、第２抵抗変化層６３が積層され、各抵抗変化層６３、６３の上面を覆うように第１上部電極６７、第２上部電極６４がそれぞれ形成されている。第１抵抗変化層６２及び第２抵抗変化層６３は、同一層にて離間して配されている。第１上部電極６７及び第２上部電極６４は、同一層にて離間して配されている。図４（ｂ）の断面図において、第１抵抗変化層６２及び第１上部電極６７は紙面に対して垂直な方向に延びていて、紙面に対して垂直な方向に沿って隣接する同じ構造の他の第１の相補型抵抗変化素子の第１抵抗変化層及び第１上部電極を兼ねている。一方、第２銅配線６６は紙面に対して左右方向に延びていて、紙面に対して左右方向に沿って隣接する同じ構造の他の第２の相補型抵抗変化素子（他の第１の相補型抵抗変化素子と異なるもの）の第２銅配線を兼ねている。実施例２によると、１つの相補型抵抗変化素子に必要な面積を８Ｆ２とすることができる。 The semiconductor device according to Example 2 has a multilayer copper wiring layer in which a multilayer copper wiring is formed in an insulator on a semiconductor substrate. The semiconductor device has a complementary resistance change element in the multilayer copper wiring. As shown in FIG. 4, the complementary resistance change element includes a first resistance change layer 62 and a second resistance change layer 63 laminated on a part of the first copper wiring 61, and the upper surfaces of the resistance change layers 63 and 63. A first upper electrode 67 and a second upper electrode 64 are formed so as to cover each other. The first resistance change layer 62 and the second resistance change layer 63 are arranged to be separated from each other in the same layer. The first upper electrode 67 and the second upper electrode 64 are spaced apart from each other in the same layer. In the cross-sectional view of FIG. 4B, the first variable resistance layer 62 and the first upper electrode 67 extend in a direction perpendicular to the paper surface and have the same structure adjacent in the direction perpendicular to the paper surface. It also serves as a first variable resistance layer and a first upper electrode of another first complementary variable resistance element. On the other hand, the second copper wiring 66 extends in the left-right direction with respect to the plane of the paper, and another second complementary variable resistance element (the other first complementary variable element) of the same structure adjacent to the plane of the paper along the left-right direction. This also serves as the second copper wiring of the type variable resistance element. According to the second embodiment, the area required for one complementary variable resistance element can be 8F 2 .
　図５は、図４に示した相補型抵抗変化素子を用いたクロスバースイッチを半導体基板３０１上の多層銅配線層の内部に形成した一例である。多層銅配線層は、半導体基板３０１上にて、層間絶縁膜３０２、バリア絶縁膜３０３、層間絶縁膜３０４、バリア絶縁膜３０７、層間絶縁膜３２０、バリア絶縁膜３１５、層間絶縁膜３１６、バリア絶縁膜３２５、層間絶縁膜３２６の順に積層した絶縁積層体を有する。多層銅配線層は、層間絶縁膜３０４及びバリア絶縁膜３０３に形成された配線溝にバリアメタル３０６を介して第１銅配線３０５が埋め込まれている。多層銅配線層は、層間絶縁膜３１６及びバリア絶縁膜３１５に形成された配線溝にバリアメタル３２３を介して第２銅配線３３２が埋め込まれており、層間絶縁膜３２０、及びバリア絶縁膜３０７に形成された下穴にバリアメタル３２３を介してビア３３０が埋め込まれており、第２銅配線３３２とビア３３０が一体となっており、第２銅配線３３２及びビア３３０の側面乃至底面がバリアメタル３２３によって覆われている。第１銅配線３０５は図９（ａ）の第１電極２１に対応し、第１上部電極３１３は図９（ａ）の第２電極２５に対応し、第２上部電極３１４は図９（ａ）の第２電極２３に対応している。 FIG. 5 is an example in which a crossbar switch using the complementary resistance change element shown in FIG. 4 is formed inside a multilayer copper wiring layer on the semiconductor substrate 301. The multilayer copper wiring layer is formed on the semiconductor substrate 301 by an interlayer insulating film 302, a barrier insulating film 303, an interlayer insulating film 304, a barrier insulating film 307, an interlayer insulating film 320, a barrier insulating film 315, an interlayer insulating film 316, and a barrier insulating. An insulating stacked body in which a film 325 and an interlayer insulating film 326 are stacked in this order is included. In the multilayer copper wiring layer, the first copper wiring 305 is embedded in the wiring trench formed in the interlayer insulating film 304 and the barrier insulating film 303 via the barrier metal 306. In the multilayer copper wiring layer, the second copper wiring 332 is embedded in the wiring groove formed in the interlayer insulating film 316 and the barrier insulating film 315 via the barrier metal 323, and the interlayer insulating film 320 and the barrier insulating film 307 are embedded in the multilayer copper wiring layer. A via 330 is embedded in the formed prepared hole via a barrier metal 323, and the second copper wiring 332 and the via 330 are integrated, and the side surface or the bottom surface of the second copper wiring 332 and the via 330 are barrier metal. 323. The first copper wiring 305 corresponds to the first electrode 21 in FIG. 9A, the first upper electrode 313 corresponds to the second electrode 25 in FIG. 9A, and the second upper electrode 314 corresponds to the first electrode 21 in FIG. ) Of the second electrode 23.
　相補型抵抗変化素子２００は、例えば、イオン伝導体中における金属イオン移動と電気化学反応とを利用したスイッチング素子とすることができる。相補型抵抗変化素子２００は、２つの抵抗変化素子が直列に接続された素子である。図９（ａ）の第１電極２１に相当する第１銅配線３０５と、第２電極２５となる第１上部電極３１３との間に第１抵抗変化層３１１が介在し、図９（ａ）の第１電極２１に相当する第１銅配線３０５と、第２電極２３となる第２上部電極３１４との間に第２抵抗変化層３１２が介在した構成となっている。各抵抗変化層３１１、３１２は、バリア絶縁膜３０７に形成された開口部の領域にて第１抵抗変化層３１１及び第２抵抗変化層３１２の底面と第１銅配線３０５の上面とが接しており、さらに、第１抵抗変化層３１１及び第２抵抗変化層３１２の上面と第１上部電極３１３及び第２上部電極３１４の底面が接している。各抵抗変化層３１１、３１２は互いに離間しており、各上部電極３１３、３１４も互いに離間している。相補型抵抗変化素子２００は、電圧の印加、あるいは電流を流すことで高抵抗状態と低抵抗状態間の遷移し、例えば、第１抵抗変化層３１１及び第２抵抗変化層３１２中への第１銅配線３０５に含まれる金属イオンの電解による拡散を利用してスイッチングを行う。 The complementary resistance change element 200 can be, for example, a switching element utilizing metal ion migration and electrochemical reaction in an ion conductor. The complementary resistance change element 200 is an element in which two resistance change elements are connected in series. A first resistance change layer 311 is interposed between the first copper wiring 305 corresponding to the first electrode 21 in FIG. 9A and the first upper electrode 313 serving as the second electrode 25, and FIG. The second resistance change layer 312 is interposed between the first copper wiring 305 corresponding to the first electrode 21 and the second upper electrode 314 serving as the second electrode 23. Each of the resistance change layers 311, 312 is in contact with the bottom surface of the first resistance change layer 311 and the second resistance change layer 312 and the top surface of the first copper wiring 305 in the region of the opening formed in the barrier insulating film 307. Furthermore, the top surfaces of the first variable resistance layer 311 and the second variable resistance layer 312 are in contact with the bottom surfaces of the first upper electrode 313 and the second upper electrode 314. The resistance change layers 311 and 312 are separated from each other, and the upper electrodes 313 and 314 are also separated from each other. The complementary resistance change element 200 transitions between a high resistance state and a low resistance state by applying a voltage or passing a current. For example, the first resistance change layer 311 and the first resistance change layer 312 have a first resistance change layer 312. Switching is performed by utilizing diffusion of metal ions contained in the copper wiring 305 by electrolysis.
　半導体基板３０１は、半導体素子（図示せず）が形成された基板である。半導体基板３０１には、例えば、シリコン基板、単結晶基板、ＳＯＩ（Silicon on Insulator）基板、ＴＦＴ（Thin Film Transistor）基板、液晶製造用基板、あるいは多層銅配線層備えたシリコン基板等の基板を用いることができる。 The semiconductor substrate 301 is a substrate on which a semiconductor element (not shown) is formed. As the semiconductor substrate 301, for example, a substrate such as a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, a liquid crystal manufacturing substrate, or a silicon substrate provided with a multilayer copper wiring layer is used. be able to.
　層間絶縁膜３０２は、半導体基板３０１上に形成された絶縁膜である。層間絶縁膜３０２には、例えば、シリコン酸化膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）等を用いることができる。層間絶縁膜３０２は、複数の絶縁膜を積層したものであってもよい。 The interlayer insulating film 302 is an insulating film formed on the semiconductor substrate 301. As the interlayer insulating film 302, for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used. The interlayer insulating film 302 may be a stack of a plurality of insulating films.
　バリア絶縁膜３０３は、層間絶縁膜３０２、３０４間に介在したバリア性を有する絶縁膜である。バリア絶縁膜３０３は、第１銅配線３０５の配線溝の加工時にエッチングストップ層としての役割を有する。バリア絶縁膜３０３には、例えば、ＳｉＮ膜、ＳｉＣ膜、ＳｉＣＮ膜等を用いることができる。バリア絶縁膜３０３には、第１銅配線３０５を埋め込むための配線溝が形成されており、当該配線溝にバリアメタル３０６を介して第１銅配線３０５が埋め込まれている。バリア絶縁膜３０３は、配線溝のエッチング条件の選択によっては省略することもできる。 The barrier insulating film 303 is an insulating film having a barrier property interposed between the interlayer insulating films 302 and 304. The barrier insulating film 303 serves as an etching stop layer when the wiring groove of the first copper wiring 305 is processed. For the barrier insulating film 303, for example, a SiN film, a SiC film, a SiCN film, or the like can be used. In the barrier insulating film 303, a wiring groove for embedding the first copper wiring 305 is formed, and the first copper wiring 305 is embedded in the wiring groove via a barrier metal 306. The barrier insulating film 303 can be omitted depending on the selection of the etching conditions for the wiring trench.
　層間絶縁膜３０４は、バリア絶縁膜３０３上に形成された絶縁膜である。層間絶縁膜３０４には、例えば、シリコン酸化膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）等を用いることができる。層間絶縁膜３０４は、複数の絶縁膜を積層したものであってもよい。層間絶縁膜３０４には、第１銅配線３０５を埋め込むための配線溝が形成されており、当該配線溝にバリアメタル３０６を介して第１銅配線３０５が埋め込まれている。 The interlayer insulating film 304 is an insulating film formed on the barrier insulating film 303. As the interlayer insulating film 304, for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used. The interlayer insulating film 304 may be a stack of a plurality of insulating films. A wiring groove for embedding the first copper wiring 305 is formed in the interlayer insulating film 304, and the first copper wiring 305 is embedded in the wiring groove via a barrier metal 306.
　第１銅配線３０５は、層間絶縁膜３０４及びバリア絶縁膜３０３に形成された配線溝にバリアメタル３０６を介して埋め込まれた配線である。第１銅配線３０５は、抵抗変化素子の図９の第１電極２１に相当する電極を兼ね、第１抵抗変化層３１１及び第２抵抗変化層３１２と直接接している。なお、第１銅配線３０５と各抵抗変化層の間には、電極層などが挿入されていてもよい。電極層が形成される場合は、電極層と抵抗変化層は連続工程にて堆積され、連続工程にて加工される。第１銅配線３０５には、抵抗変化層において拡散、イオン伝導可能な金属が用いられ、例えば、銅等を用いることができる。第１銅配線３０５は、Ａｌと合金化されていてもよく、シリサイド化、又は窒化されていてもよい。第１銅配線３０５は、表面がシリサイド化、又は窒化されていてもよい。第１銅配線３０５は、図５（ａ）の左右方向に延在する第２銅配線３３２の領域の一部に形成され、第２銅配線３３２の領域内において複数個形成されている。第１銅配線３０５は、第２銅配線３３２と第１上部電極３１３とが重なる領域から図５（ｂ）の左右方向に延在して第２銅配線３３２と第２上部電極３１４とが重なる領域までの間に形成されている。第１銅配線３０５は、図５（ｂ）の左右方向及び紙面に対する垂直方向で隣合う他の第１銅配線（図示せず）と離間している。 The first copper wiring 305 is a wiring buried in a wiring groove formed in the interlayer insulating film 304 and the barrier insulating film 303 via the barrier metal 306. The first copper wiring 305 also serves as an electrode corresponding to the first electrode 21 in FIG. 9 of the variable resistance element, and is in direct contact with the first variable resistance layer 311 and the second variable resistance layer 312. An electrode layer or the like may be inserted between the first copper wiring 305 and each resistance change layer. When the electrode layer is formed, the electrode layer and the resistance change layer are deposited in a continuous process and processed in the continuous process. For the first copper wiring 305, a metal capable of diffusing and ion conducting in the resistance change layer is used, and for example, copper or the like can be used. The first copper wiring 305 may be alloyed with Al, silicided, or nitrided. The surface of the first copper wiring 305 may be silicided or nitrided. The first copper wiring 305 is formed in a part of the region of the second copper wiring 332 extending in the left-right direction in FIG. 5A, and a plurality of first copper wirings 305 are formed in the region of the second copper wiring 332. The first copper wiring 305 extends in the left-right direction in FIG. 5B from the region where the second copper wiring 332 and the first upper electrode 313 overlap, and the second copper wiring 332 and the second upper electrode 314 overlap. It is formed between the areas. The first copper wiring 305 is separated from other adjacent first copper wirings (not shown) in the horizontal direction of FIG. 5B and in the direction perpendicular to the paper surface.
　バリアメタル３０６は、第１銅配線３０５に含まれる金属が層間絶縁膜３０４や下層へ拡散することを防止するために、第１銅配線３０５の側面乃至底面を被覆する、バリア性を有する導電性膜である。バリアメタル３０６には、例えば、第１銅配線３０５が銅を主成分とする金属元素からなる場合には、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）、炭窒化タングステン（ＷＣＮ）のような高融点金属やその窒化物等、又はそれらの積層膜を用いることができる。 The barrier metal 306 covers the side surface or bottom surface of the first copper wiring 305 and prevents the metal contained in the first copper wiring 305 from diffusing into the interlayer insulating film 304 or the lower layer. It is a membrane. For example, when the first copper wiring 305 is made of a metal element mainly composed of copper, the barrier metal 306 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). ), A refractory metal thereof, a nitride thereof, or a laminated film thereof.
　バリア絶縁膜３０７は、第１銅配線３０５及びバリアメタル３０６を含む層間絶縁膜３０４上に形成された絶縁膜であり、第１銅配線３０５に係る金属（例えば、Ｃｕ）の酸化を防いだり、層間絶縁膜３０４中への第１銅配線３０５に係る金属の拡散を防いだりする役割を有する。バリア絶縁膜３０７には、例えば、ＳｉＣ膜、ＳｉＣＮ膜、ＳｉＮ膜、及びそれらの積層構造等を用いることができる。バリア絶縁膜３０７は、第１銅配線３０５上にて開口部を有する。バリア絶縁膜３０７の開口部においては、第１銅配線３０５と第１抵抗変化層３１１及び第２抵抗変化層３１２とが接している。バリア絶縁膜３０７の開口部は、第１銅配線３０５の領域内に形成されている。このようにすることで、凹凸の小さい第１銅配線３０５の表面上に相補型抵抗変化素子２００を形成することができるようになる。 The barrier insulating film 307 is an insulating film formed on the interlayer insulating film 304 including the first copper wiring 305 and the barrier metal 306, and prevents oxidation of a metal (for example, Cu) related to the first copper wiring 305, It plays a role of preventing diffusion of the metal related to the first copper wiring 305 into the interlayer insulating film 304. For the barrier insulating film 307, for example, a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used. The barrier insulating film 307 has an opening on the first copper wiring 305. In the opening of the barrier insulating film 307, the first copper wiring 305 is in contact with the first resistance change layer 311 and the second resistance change layer 312. The opening of the barrier insulating film 307 is formed in the region of the first copper wiring 305. In this way, the complementary resistance change element 200 can be formed on the surface of the first copper wiring 305 with small unevenness.
　第１抵抗変化層３１１、第２抵抗変化層３１２は、その抵抗が変化する膜である。第１抵抗変化層３１１、第２抵抗変化層３１２は、第１銅配線３０５（第１電極）に係る金属の作用（拡散、イオン伝導など）により抵抗が変化する材料を用いることができ、抵抗変化を金属イオンの析出によって行う場合には、イオン伝導可能な膜が用いられ、例えば、Ｔａを含む酸化物絶縁膜であって、Ｔａ２Ｏ５、ＴａＳｉＯ等を用いることができる。また、第１抵抗変化層３１１、第２抵抗変化層３１２は、下からＴａ２Ｏ５、ＴａＳｉＯの順に積層した積層構造とすることができる。このような積層構造とすることで、第１抵抗変化層３１１、第２抵抗変化層３１２をイオン伝導層として用いた場合には、低抵抗時（ＯＮ時）にイオン伝導層内部に形成される金属イオン（例えば、銅イオン）による架橋を、Ｔａ２Ｏ５層で分断することで、ＯＦＦ時に金属イオンを容易に回収することができるようになり、スイッチング特性を向上させることができるようになる。第１抵抗変化層３１１、第２抵抗変化層３１２は、第１銅配線１０５、バリア絶縁膜１０７の開口部乃至バリア絶縁膜１０７上に形成されている。第１抵抗変化層３１１、第２抵抗変化層３１２は、同一層にて互いに離間している。第１抵抗変化層３１１は、図５（ａ）において上下方向に延在しており、第１上部電極３１３と同じ領域で重なるように配されている。第２抵抗変化層３１２は、第２銅配線３３２と第１銅配線３０５とが重なる領域のうち、第１抵抗変化層３１１から離間した位置に配されている。 The first resistance change layer 311 and the second resistance change layer 312 are films whose resistance changes. The first resistance change layer 311 and the second resistance change layer 312 can be made of a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of the metal related to the first copper wiring 305 (first electrode). When the change is performed by precipitation of metal ions, a film capable of ion conduction is used. For example, an oxide insulating film containing Ta, such as Ta 2 O 5 or TaSiO can be used. The first resistance change layer 311 and the second resistance change layer 312 may have a stacked structure in which Ta 2 O 5 and TaSiO are stacked in this order from the bottom. With such a laminated structure, when the first variable resistance layer 311 and the second variable resistance layer 312 are used as the ion conductive layer, they are formed inside the ion conductive layer when the resistance is low (ON). By breaking the cross-linking with metal ions (for example, copper ions) with the Ta 2 O 5 layer, the metal ions can be easily recovered at the OFF time, and the switching characteristics can be improved. . The first resistance change layer 311 and the second resistance change layer 312 are formed on the first copper wiring 105 and the opening of the barrier insulating film 107 or on the barrier insulating film 107. The first resistance change layer 311 and the second resistance change layer 312 are separated from each other in the same layer. The first resistance change layer 311 extends in the vertical direction in FIG. 5A and is arranged so as to overlap in the same region as the first upper electrode 313. The second resistance change layer 312 is disposed at a position separated from the first resistance change layer 311 in a region where the second copper wiring 332 and the first copper wiring 305 overlap.
　第１上部電極３１３は、図９の第２電極２５の役割を担い、第１抵抗変化層３１１の上面と接している。第２上部電極３１４は、図９の第２電極２３の役割を担い、第２抵抗変化層３１２の上面と接している。第１上部電極３１３、第２上部電極３１４には、第１銅配線３０５に係る金属よりもイオン化しにくく、第１抵抗変化層３１１、第２抵抗変化層３１２において拡散、イオン伝導しにくい金属が用いられ、第１抵抗変化層３１１、第２抵抗変化層３１２に係る金属成分（Ｔａ）よりも酸化の自由エネルギーの絶対値が小さい金属材料とすることが好ましい。第１上部電極３１３、第２上部電極３１４には、例えば、プラチナ（Ｐｔ）、ルテニウム（Ｒｕ）、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）、炭窒化タングステン（ＷＣＮ）のような高融点金属やその窒化物等、又はそれらの積層膜を用いることができる。また、第１上部電極３１３、第２上部電極３１４の上面及び側面にＰｔ、Ｒｕ等の金属材料を主成分として酸素を添加してもよく、また酸素を添加した層との積層構造にしてもよい。第１上部電極３１３、第２上部電極３１４は、同一層にて互いに離間している。第１上部電極３１３は、図５（ａ）において上下方向に延在しており、第１抵抗変化層３１１と同じ領域で重なるように配されている。第２上部電極３１４は、第２銅配線３３２と第１銅配線３０５とが重なる領域のうち、第１上部電極３１３から離間した位置に配されている。 The first upper electrode 313 plays the role of the second electrode 25 in FIG. 9 and is in contact with the upper surface of the first variable resistance layer 311. The second upper electrode 314 serves as the second electrode 23 in FIG. 9 and is in contact with the upper surface of the second resistance change layer 312. The first upper electrode 313 and the second upper electrode 314 are made of a metal that is less likely to ionize than the metal related to the first copper wiring 305 and is less likely to diffuse and ion-conduct in the first resistance change layer 311 and the second resistance change layer 312. It is preferable to use a metal material that is used and has an absolute value of free energy of oxidation smaller than that of the metal component (Ta) related to the first resistance change layer 311 and the second resistance change layer 312. Examples of the first upper electrode 313 and the second upper electrode 314 include platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). Such a refractory metal, a nitride thereof, or a laminated film thereof can be used. Further, oxygen may be added to the top and side surfaces of the first upper electrode 313 and the second upper electrode 314 as a main component of a metal material such as Pt or Ru, or a laminated structure with a layer to which oxygen is added. Good. The first upper electrode 313 and the second upper electrode 314 are separated from each other in the same layer. The first upper electrode 313 extends in the vertical direction in FIG. 5A and is arranged to overlap in the same region as the first resistance change layer 311. The second upper electrode 314 is disposed at a position separated from the first upper electrode 313 in a region where the second copper wiring 332 and the first copper wiring 305 overlap.
　上部電極３１３、３１４及び抵抗変化層３１１、３１２は、図５（ａ）に示すパターンとなっている。つまり、第１上部電極３１３及び第１抵抗変化層３１１は、図５（ａ）の上下方向に延在したパターンとなっている。第２上部電極３１４及び第２抵抗変化層３１２は、図５（ａ）の左右方向に延在した第２銅配線３３２の領域のうち隣り合う第１上部電極３１３間に配されており、隣り合う他の第２上部電極３１４及び第２抵抗変化層３１２と離間している。上部電極３１３、３１４及び抵抗変化層３１１、３１２は、第１銅配線３０５よりも図５（ａ）の紙面に対して下側に配されている。第１上部電極３１３及び第１抵抗変化層３１１は、第１銅配線３０５と直交（立体交差）し、複数形成されている。ここで、第１抵抗変化層３１１は、第１上部電極３１３と同一の形状をしており、第２抵抗変化層３１２は、第２上部電極３１４と同一の形状をしている。 The upper electrodes 313 and 314 and the resistance change layers 311 and 312 have a pattern shown in FIG. That is, the first upper electrode 313 and the first resistance change layer 311 have a pattern extending in the vertical direction in FIG. The second upper electrode 314 and the second resistance change layer 312 are disposed between adjacent first upper electrodes 313 in the region of the second copper wiring 332 extending in the left-right direction in FIG. The second upper electrode 314 and the second variable resistance layer 312 that are matched with each other are separated from each other. The upper electrodes 313 and 314 and the resistance change layers 311 and 312 are arranged below the first copper wiring 305 with respect to the paper surface of FIG. A plurality of first upper electrodes 313 and first resistance change layers 311 are formed orthogonal to the first copper wiring 305 (three-dimensional intersection). Here, the first resistance change layer 311 has the same shape as the first upper electrode 313, and the second resistance change layer 312 has the same shape as the second upper electrode 314.
　層間絶縁膜３２０は、上部電極３１３、３１４及び抵抗変化層３１１、３１２を含むバリア絶縁膜３０７上に形成された絶縁膜である。層間絶縁膜３２０には、例えば、シリコン酸化膜、ＳｉＯＣ膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）などを用いることができる。層間絶縁膜３２０は、複数の絶縁膜を積層したものであってもよい。層間絶縁膜３２０は、層間絶縁膜３０４と同一材料としてもよい。層間絶縁膜３２０には、ビア３３０を埋め込むための下穴が形成されており、当該下穴にバリアメタル３２３を介してビア３３０が埋め込まれている。 The interlayer insulating film 320 is an insulating film formed on the barrier insulating film 307 including the upper electrodes 313 and 314 and the resistance change layers 311 and 312. As the interlayer insulating film 320, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used. The interlayer insulating film 320 may be a stack of a plurality of insulating films. The interlayer insulating film 320 may be made of the same material as the interlayer insulating film 304. A pilot hole for embedding the via 330 is formed in the interlayer insulating film 320, and the via 330 is embedded in the pilot hole via the barrier metal 323.
　バリア絶縁膜３１５は、層間絶縁膜３２０と層間絶縁膜３１６との間に介在した絶縁膜である（図５（ｃ）参照）。バリア絶縁膜３１５は、ビア３３０に係る金属（例えば、Ｃｕ）の酸化を防いだり、層間絶縁膜３２０中へのビア３３０に係る金属の拡散を防ぐ役割を有する。バリア絶縁膜３１５には、例えば、ＳｉＮ膜、ＳｉＣ膜、ＳｉＣＮ膜等を用いることができる。バリア膜３１５には、第２銅配線３３２を埋め込むための配線溝が形成されており、当該配線溝にバリアメタル３２３を介して第２銅配線３３２が埋め込まれている。 The barrier insulating film 315 is an insulating film interposed between the interlayer insulating film 320 and the interlayer insulating film 316 (see FIG. 5C). The barrier insulating film 315 has a role of preventing oxidation of the metal (for example, Cu) related to the via 330 and preventing diffusion of the metal related to the via 330 into the interlayer insulating film 320. For the barrier insulating film 315, for example, a SiN film, a SiC film, a SiCN film, or the like can be used. In the barrier film 315, a wiring groove for embedding the second copper wiring 332 is formed, and the second copper wiring 332 is embedded in the wiring groove via the barrier metal 323.
　層間絶縁膜３１６は、バリア絶縁膜３１５上に形成された絶縁膜である（図５（ｃ）参照）。層間絶縁膜３１６には、例えば、シリコン酸化膜、ＳｉＯＣ膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）などを用いることができる。層間絶縁膜３１６は、複数の絶縁膜を積層したものであってもよい。層間絶縁膜３１６は、層間絶縁膜３０４と同一材料としてもよい。層間絶縁膜３１６には、第２銅配線３３２を埋め込むための配線溝が形成されており、当該配線溝にバリアメタル３２３を介して第２銅配線３３２が埋め込まれている。 The interlayer insulating film 316 is an insulating film formed on the barrier insulating film 315 (see FIG. 5C). As the interlayer insulating film 316, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used. The interlayer insulating film 316 may be a stack of a plurality of insulating films. The interlayer insulating film 316 may be made of the same material as the interlayer insulating film 304. In the interlayer insulating film 316, a wiring groove for embedding the second copper wiring 332 is formed, and the second copper wiring 332 is embedded in the wiring groove via a barrier metal 323.
　バリアメタル３２３は、ビア３３０及び第２銅配線３３２に含まれる金属が層間絶縁膜３２０や下層へ拡散することを防止するために、ビア３３０及び第２銅配線３３２の側面乃至底面を被覆する、バリア性を有する導電性膜である。バリアメタル３２３には、例えば、プラチナ（Ｐｔ）、ルテニウム（Ｒｕ）、タンタル（Ｔａ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）、炭窒化タングステン（ＷＣＮ）のような高融点金属やその窒化物等、又はそれらの積層膜を用いることができる。 The barrier metal 323 covers the side surface or bottom surface of the via 330 and the second copper wiring 332 in order to prevent the metal contained in the via 330 and the second copper wiring 332 from diffusing into the interlayer insulating film 320 or the lower layer. It is a conductive film having a barrier property. Examples of the barrier metal 323 include platinum (Pt), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and a refractory metal such as tungsten carbonitride (WCN). A thing etc. or those laminated films can be used.
　第２銅配線３３２は、層間絶縁膜３１６及びバリア絶縁膜３１５に形成された配線溝にバリアメタル３２３を介して埋め込まれた配線である。第２銅配線３３２は、図５（ａ）の左右方向に延在しており、同一層にて互いに離間して複数本形成されている。第２銅配線３３２は、ビア３３０と一体になっている。ビア３３０は、層間絶縁膜３２０に形成された下穴内にてバリアメタル３２３を介して埋め込まれ、バリアメタル３２３を介して第２上部電極３１４と電気的に接続されている。第２銅配線３３２及びビア３３０には、例えば、Ａｌ、Ｃｕ、Ｗ等を用いることができる。ＣｕはＡｌと合金化されていてもよい。さらに、第２銅配線３３２及びビア３３０はシリサイド化、又は窒化されていてもよい。 The second copper wiring 332 is a wiring buried in a wiring groove formed in the interlayer insulating film 316 and the barrier insulating film 315 via the barrier metal 323. The second copper wiring 332 extends in the left-right direction in FIG. 5A, and a plurality of the second copper wirings 332 are formed apart from each other in the same layer. The second copper wiring 332 is integrated with the via 330. The via 330 is embedded in a pilot hole formed in the interlayer insulating film 320 via a barrier metal 323 and is electrically connected to the second upper electrode 314 via the barrier metal 323. For the second copper wiring 332 and the via 330, for example, Al, Cu, W, or the like can be used. Cu may be alloyed with Al. Further, the second copper wiring 332 and the via 330 may be silicided or nitrided.
　バリア絶縁膜３２５は、第２銅配線３３２を含む層間絶縁膜３１６上に形成され、第２銅配線３３２に係る金属（例えば、Ｃｕ）の酸化を防いだり、上層への第２銅配線３３２に係る金属の拡散を防いだりする役割を有する絶縁膜である。バリア絶縁膜３２５には、例えば、ＳｉＣ膜、ＳｉＣＮ膜、ＳｉＮ膜、及びそれらの積層構造等を用いることができる。 The barrier insulating film 325 is formed on the interlayer insulating film 316 including the second copper wiring 332, prevents oxidation of a metal (for example, Cu) related to the second copper wiring 332, and forms an upper layer of the second copper wiring 332. It is an insulating film having a role of preventing diffusion of the metal. For the barrier insulating film 325, for example, a SiC film, a SiCN film, a SiN film, and a stacked structure thereof can be used.
　層間絶縁膜３２６は、バリア絶縁膜３２５上に形成された絶縁膜である。層間絶縁膜３２６には、例えば、シリコン酸化膜、ＳｉＯＣ膜、シリコン酸化膜よりも比誘電率の低い低誘電率膜（例えば、ＳｉＯＣＨ膜）などを用いることができる。層間絶縁膜３１６は、複数の絶縁膜を積層したものであってもよい。 The interlayer insulating film 326 is an insulating film formed on the barrier insulating film 325. As the interlayer insulating film 326, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used. The interlayer insulating film 316 may be a stack of a plurality of insulating films.
　次に、本発明の実施例２に係る半導体装置の製造方法について図面を用いて説明する。図６、図７は、本発明の実施例２に係る半導体装置における多層銅配線中に形成された相補型抵抗変化素子を用いたクロスバースイッチの製造方法を模式的に示した工程断面図である。 Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. 6 and 7 are process cross-sectional views schematically showing a method for manufacturing a crossbar switch using complementary resistance change elements formed in a multilayer copper wiring in a semiconductor device according to Example 2 of the present invention. is there.
　まず、半導体基板３０１（例えば、半導体素子（図示せず）が形成された基板）上に層間絶縁膜３０２（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積し、その後、層間絶縁膜３０２上にバリア絶縁膜３０３（例えば、ＳｉＮ膜、膜厚５０ｎｍ）を堆積し、その後、バリア絶縁膜３０３上に層間絶縁膜３０４（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積し、その後、リソグラフィ法（フォトレジスト形成、ドライエッチング、フォトレジスト除去を含む）を用いて、層間絶縁膜３０４に配線溝を形成し、その後、当該配線溝にバリアメタル３０６（例えば、ＴａＮ／Ｔａ、膜厚５ｎｍ／５ｎｍ）を介して第１銅配線３０５を埋め込み、さらに、その後、第１銅配線３０５及びバリアメタル３０６を含む層間絶縁膜３０４上にバリア絶縁膜３０７（例えば、ＳｉＮ膜、膜厚５０ｎｍ）を堆積する（ステップＢ１；図６（ａ）参照）。 First, an interlayer insulating film 302 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 301 (for example, a substrate on which a semiconductor element (not shown) is formed), and then the interlayer insulating film 302 is formed. A barrier insulating film 303 (for example, a SiN film, a film thickness of 50 nm) is deposited, and then an interlayer insulating film 304 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on the barrier insulating film 303, and then a lithography method ( (Including photoresist formation, dry etching, and photoresist removal), a wiring groove is formed in the interlayer insulating film 304, and then the barrier metal 306 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring groove. Then, the first copper wiring 305 is embedded via the first insulating film 304 and the first copper wiring 305 and the interlayer insulating film 304 including the barrier metal 306 are then buried. A dielectric film 307 (eg, SiN film, thickness 50 nm) is deposited (step B1; see FIG. 6 (a)).
　ステップＢ１において、層間絶縁膜３０２、３０４、バリア絶縁膜３０３、３０７は、プラズマＣＶＤ法によって形成することができる。また、ステップＢ１において、第１銅配線３０５は、例えば、ＰＶＤ法によってバリアメタル３０６（例えば、ＴａＮ／Ｔａの積層膜）を形成し、ＰＶＤ法によるＣｕシードの形成後、電解めっき法によって銅を配線溝内に埋設し、２００℃以上の温度で熱処理処理後、ＣＭＰ法によって配線溝内以外の余剰の銅を除去することで形成することができる。このような一連の銅配線の形成方法は、当該技術分野における一般的な手法を用いることができる。 In step B1, the interlayer insulating films 302 and 304 and the barrier insulating films 303 and 307 can be formed by a plasma CVD method. Further, in Step B1, the first copper wiring 305 is formed by forming a barrier metal 306 (for example, a TaN / Ta laminated film) by the PVD method, and forming copper seed by the PVD method, and then copper by the electrolytic plating method. It can be formed by embedding in the wiring trench, after heat treatment at a temperature of 200 ° C. or higher, and then removing excess copper other than in the wiring trench by CMP. As a method for forming such a series of copper wirings, a general method in this technical field can be used.
　次に、バリア絶縁膜３０７上にシリコン酸化膜等を堆積し、その後、当該シリコン酸化膜等上に開口部３０８の形成用パターンを有するフォトレジスト（図示せず）を形成し、当該フォトレジストをマスクとしてシリコン酸化膜をドライエッチングすることにより開口部形成用パターンをシリコン酸化膜等に転写し、その後、酸素プラズマアッシング等によってフォトレジストを除去し、その後、シリコン酸化膜等をマスクとして開口部形成用パターンから露出するバリア絶縁膜３０７をエッチバック（ドライエッチング）することにより、バリア絶縁膜３０７に開口部３０８を形成して、バリア絶縁膜３０７の開口部３０８から第１銅配線３０５を露出させ、その後、アミン系の剥離液などで有機剥離処理を行うことで、第１銅配線３０５の露出面に形成された酸化銅を除去するとともに、エッチバック時に発生したエッチング複生成物などを除去し、さらに、その後、バリア絶縁膜３０７上のシリコン酸化膜等を取り除く（ステップＢ２；図６（ｂ）参照）。 Next, a silicon oxide film or the like is deposited on the barrier insulating film 307, and then a photoresist (not shown) having a pattern for forming the opening 308 is formed on the silicon oxide film or the like. The silicon oxide film is dry-etched as a mask to transfer the opening formation pattern to the silicon oxide film, etc., and then the photoresist is removed by oxygen plasma ashing, etc., and then the silicon oxide film is used as a mask to form the opening. The barrier insulating film 307 exposed from the pattern for use is etched back (dry etching) to form an opening 308 in the barrier insulating film 307, and the first copper wiring 305 is exposed from the opening 308 in the barrier insulating film 307. Then, the first copper wiring 30 is obtained by performing an organic stripping treatment with an amine stripping solution or the like. In addition to removing the copper oxide formed on the exposed surface of the substrate, the etching by-product generated during the etch back is removed, and then the silicon oxide film and the like on the barrier insulating film 307 are removed (step B2; FIG. 6). (See (b)).
　ステップＢ２において、フォトレジストの開口部形成用パターンをシリコン酸化膜等に転写するとき、ドライエッチングは必ずしもバリア絶縁膜３０７の上面で停止している必要はなく、バリア絶縁膜３０７の内部にまで到達していてもよい。また、バリア絶縁膜３０７の開口部３０８の形状は円形とし、円の直径は１０ｎｍから５００ｎｍとすることができる。 In step B2, when the photoresist opening formation pattern is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the barrier insulating film 307, and reaches the inside of the barrier insulating film 307. You may do it. The shape of the opening 308 of the barrier insulating film 307 can be a circle, and the diameter of the circle can be 10 nm to 500 nm.
　次に、第１銅配線３０５を含むバリア絶縁膜３０７上に抵抗変化層３０９（例えば、Ｔａ２Ｏ５、膜厚１５ｎｍ）を成膜し、さらに金属層３１０（例えば、Ｒｕ膜厚１０ｎｍとＴａ膜厚５０ｎｍの積層構造）を成膜する（ステップＢ３；図６（ｃ）参照）。 Next, a resistance change layer 309 (for example, Ta 2 O 5 , film thickness of 15 nm) is formed on the barrier insulating film 307 including the first copper wiring 305, and further a metal layer 310 (for example, Ru film thickness of 10 nm and Ta A laminated structure having a thickness of 50 nm is formed (step B3; see FIG. 6C).
　ここで、抵抗変化層３０９は、ＰＶＤ法やＣＶＤ法を用いて形成することができる。ステップＢ３では、開口部３０８はステップＢ２の有機剥離処理によって水分などが付着しているため、抵抗変化層３０９の堆積前に２５０℃から３５０℃程度の温度にて、減圧下で熱処理を加えて脱ガスしておくことが好ましい。この際、銅表面を再度酸化させないよう、真空下、あるいは窒素雰囲気などにするなどの注意が必要である。 Here, the resistance change layer 309 can be formed using a PVD method or a CVD method. In step B3, since the opening 308 is attached with moisture or the like by the organic peeling process in step B2, heat treatment is performed under reduced pressure at a temperature of about 250 ° C. to 350 ° C. before the resistance change layer 309 is deposited. It is preferable to degas. At this time, care must be taken such as in a vacuum or a nitrogen atmosphere so that the copper surface is not oxidized again.
　また、ステップＢ３では、抵抗変化層３０９として、遷移金属酸化物（例えば、ＴｉＯ、ＮｉＯ等）を用いた抵抗変化層を用いる場合には、抵抗変化層３０９を堆積する前に電極を成膜してもよい。電極には、例えば、Ｔｉ、ＴｉＮ、Ｗ、ＷＮ、Ｔａ、ＴａＮ、Ｒｕ、ＲｕＯｘ等を用いることができ、例えば、それらの積層構造（例えば、ＴａＮ（下層）／Ｒｕ（上層））であっても良い。 In step B3, when a resistance change layer using a transition metal oxide (eg, TiO, NiO, etc.) is used as the resistance change layer 309, an electrode is formed before the resistance change layer 309 is deposited. May be. For the electrode, for example, Ti, TiN, W, WN, Ta, TaN, Ru, RuOx, etc. can be used. For example, their laminated structure (for example, TaN (lower layer) / Ru (upper layer)) Also good.
　次に、金属層（図６（ｃ）の３１０）上にシリコン酸化膜等を堆積し、その後、シリコン酸化膜等上に上部電極形成用パターンを有するフォトレジスト（図示せず）を形成し、その後、当該フォトレジストをマスクとしてシリコン酸化膜等をドライエッチングすることにより上部電極形成用パターンをシリコン酸化膜等に転写し、その後、酸素プラズマアッシング等によってフォトレジストを除去し、その後、シリコン酸化膜等をマスクとしてエッチバック（ドライエッチング）することにより、金属層（図６（ｃ）の３１０）及び抵抗変化層（図６（ｃ）の３０９）を加工し、エッチングのマスクに用いたシリコン酸化膜を取り除くことにより、ライン状にパターニングされた第１抵抗変化層３１１／第１上部電極層３１３、及び、島状にパターニングされた第２抵抗変化層３１２／第２上部電極層３１４を形成する（ステップＢ４；図７（ａ）参照）。 Next, a silicon oxide film or the like is deposited on the metal layer (310 in FIG. 6C), and then a photoresist (not shown) having an upper electrode formation pattern is formed on the silicon oxide film or the like, Thereafter, the silicon oxide film or the like is dry-etched using the photoresist as a mask to transfer the upper electrode forming pattern to the silicon oxide film or the like. Thereafter, the photoresist is removed by oxygen plasma ashing or the like, and then the silicon oxide film is removed. Etching back (dry etching) using the above as a mask to process the metal layer (310 in FIG. 6C) and the resistance change layer (309 in FIG. 6C), and the silicon oxide used as the etching mask By removing the film, the first variable resistance layer 311 / first upper electrode layer 313 patterned in a line shape, and the island shape Forming the second resistance variable layer 312 / the second upper electrode layer 314 which is patterned (step B4; see FIG. 7 (a)).
　ステップＢ４では、フォトレジストの上部電極形成用パターンをシリコン酸化膜等に転写するとき、ドライエッチングは必ずしも金属層３１０の上面で停止している必要はなく、金属層３１０の内部にまで到達していてもよい。 In Step B4, when the upper electrode formation pattern of the photoresist is transferred to the silicon oxide film or the like, the dry etching does not necessarily stop on the upper surface of the metal layer 310, and has reached the inside of the metal layer 310. May be.
　次に、第１抵抗変化層３１１／第１上部電極層３１３及び第２抵抗変化層３１２／第２上部電極層３１４を含むバリア絶縁膜３０７上に層間絶縁膜３２０（例えば、シリコン酸化膜）を堆積し、その後、ＣＭＰ法により層間絶縁膜３２０の表面を平坦化し、その後、層間絶縁膜３２０上にバリア絶縁膜３１５（例えば、ＳｉＮ膜、膜厚５０ｎｍ）を堆積し、さらに、その後、バリア絶縁膜３１５上に層間絶縁膜３１６（例えば、シリコン酸化膜、膜厚３００ｎｍ程度）を堆積する（ステップＢ５；図７（ｂ）参照）。ステップＢ５において、層間絶縁膜３２０の膜厚は平坦化後に３００ｎｍ程度になるようにする。 Next, an interlayer insulating film 320 (for example, a silicon oxide film) is formed on the barrier insulating film 307 including the first resistance change layer 311 / first upper electrode layer 313 and the second resistance change layer 312 / second upper electrode layer 314. After that, the surface of the interlayer insulating film 320 is flattened by a CMP method, and then a barrier insulating film 315 (for example, a SiN film, film thickness of 50 nm) is deposited on the interlayer insulating film 320, and then barrier insulation is performed. An interlayer insulating film 316 (for example, a silicon oxide film having a thickness of about 300 nm) is deposited on the film 315 (step B5; see FIG. 7B). In step B5, the thickness of the interlayer insulating film 320 is set to about 300 nm after planarization.
　次に、層間絶縁膜３１６及び層間絶縁膜３２０に、従来技術であるデュアルダマシン法により第２銅配線３３２、ビア３３０を形成する（ステップＢ６；図７（ｃ）参照）。ここで、第２銅配線３３２及びビア３３０の下面及び側面はバリアメタル３２３で覆われている。 Next, the second copper wiring 332 and the via 330 are formed in the interlayer insulating film 316 and the interlayer insulating film 320 by the dual damascene method which is a conventional technique (step B6; see FIG. 7C). Here, the lower surface and side surfaces of the second copper wiring 332 and the via 330 are covered with the barrier metal 323.
　最後に、第２銅配線３３２を含む層間絶縁膜３１６上にバリア絶縁膜３２５（例えば、ＳｉＮ膜）及び層間絶縁膜３２６（例えば、シリコン酸化膜、膜厚３００ｎｍ）を堆積する（ステップＢ７；図５（ｂ）参照）。なお、図示していないが、層間絶縁膜１２０上には多層配線層が形成される。 Finally, a barrier insulating film 325 (for example, SiN film) and an interlayer insulating film 326 (for example, silicon oxide film, film thickness of 300 nm) are deposited on the interlayer insulating film 316 including the second copper wiring 332 (Step B7; FIG. 5 (b)). Although not shown, a multilayer wiring layer is formed on the interlayer insulating film 120.
　実施例２によれば、第１上部電極３１３を配線として用い、かつ、多層銅配線のうち第１銅配線３０５及び第２銅配線３３２の２層を使うだけで、相補型抵抗変化素子２００を用いたクロスバースイッチを形成することができ、従来用いていた銅配線、および銅配線へ接続するためのビアが不要となり、抵抗変化素子の面積を小さくでき、その作製工程数も少くすることができる。また、第１上部電極３１３を、一般的に配線幅が太い上層の銅配線で電気的に接続する必要がなくなるので、相補型抵抗変化素子２００の面積をできるだけ小さくすることができる。 According to the second embodiment, by using the first upper electrode 313 as a wiring and using only two layers of the first copper wiring 305 and the second copper wiring 332 among the multilayer copper wiring, the complementary resistance change element 200 can be formed. The used crossbar switch can be formed, the copper wiring used conventionally, and the via for connecting to the copper wiring become unnecessary, the area of the resistance change element can be reduced, and the number of manufacturing steps can be reduced. it can. Further, since it is not necessary to electrically connect the first upper electrode 313 with an upper copper wiring having a generally wide wiring width, the area of the complementary resistance change element 200 can be made as small as possible.
　なお、前述の特許文献及び非特許文献の開示を、本書に引用をもって繰り込むものとする。本発明の全開示（請求の範囲及び図面を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素（各請求項の各要素、各実施例の各要素、各図面の各要素等を含む）の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲及び図面を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。 It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.
　１０　抵抗変化素子
　２０　相補型抵抗変化素子
　１１　第１電極
　１２　第２電極
　１３　抵抗変化層
　１４　第１節点
　１５　第２節点
　１６　電圧源
　２１　第１電極
　２２　抵抗変化層
　２３、２５　第２電極
　２４　抵抗変化層
　２６　第１節点
　２７　第２節点
　２８　第３節点
　３１　第１銅配線
　３２　第２電極
　３３　抵抗変化層
　３４　ビア
　３５　第２銅配線
　４１　第１銅配線
　４２　第２電極
　４３　抵抗変化層
　６１　第１銅配線
　６２　第１抵抗変化層
　６３　第２抵抗変化層
　６４　第２上部電極
　６５　ビア
　６６　第２銅配線
　６７　第１上部電極
　１００　抵抗変化素子
　１０１　半導体基板
　１０２、１０４、１２０　層間絶縁膜
　１０３、１０７　バリア絶縁膜
　１０５　第１銅配線（下部電極）
　１０６　バリアメタル
　１０８　開口部
　１１１　抵抗変化層
　１１２　上部電極
　２００　相補型抵抗変化素子
　３０１　半導体基板
　３０２、３２６　層間絶縁膜
　３０３、３２５　バリア絶縁膜
　３０４　層間絶縁膜（第１層間絶縁膜）
　３０５　第１銅配線（下部電極）
　３０６、３２３　バリアメタル
　３０７　バリア絶縁膜（第１バリア絶縁膜）
　３０８　開口部
　３０９　抵抗変化層
　３１０　金属層
　３１１　第１抵抗変化層
　３１２　第２抵抗変化層
　３１３　第１上部電極
　３１４　第２上部電極
　３１５　バリア絶縁膜（第２バリア絶縁膜）
　３１６　層間絶縁膜（第３層間絶縁膜）
　３２０　層間絶縁膜（第２層間絶縁膜）
　３３０　ビア（金属）
　３３２　第２銅配線（金属） DESCRIPTION OF SYMBOLS 10 Resistance change element 20 Complementary resistance change element 11 1st electrode 12 2nd electrode 13 Resistance change layer 14 1st node 15 2nd node 16 Voltage source 21 1st electrode 22 Resistance change layer 23, 25 2nd electrode 24 Resistance change Layer 26 First node 27 Second node 28 Third node 31 First copper wiring 32 Second electrode 33 Resistance change layer 34 Via 35 Second copper wiring 41 First copper wiring 42 Second electrode 43 Resistance change layer 61 First copper Wiring 62 First variable resistance layer 63 Second variable resistance layer 64 Second upper electrode 65 Via 66 Second copper wiring 67 First upper electrode 100 Variable resistance element 101 Semiconductor substrate 102, 104, 120 Interlayer insulating film 103, 107 Barrier insulation Film 105 First copper wiring (lower electrode)
106 Barrier metal 108 Opening 111 Resistance change layer 112 Upper electrode 200 Complementary variable resistance element 301 Semiconductor substrate 302, 326 Interlayer insulating film 303, 325 Barrier insulating film 304 Interlayer insulating film (first interlayer insulating film)
305 First copper wiring (lower electrode)
306, 323 Barrier metal 307 Barrier insulating film (first barrier insulating film)
308 Opening 309 Variable resistance layer 310 Metal layer 311 First variable resistance layer 312 Second variable resistance layer 313 First upper electrode 314 Second upper electrode 315 Barrier insulating film (second barrier insulating film)
316 interlayer insulating film (third interlayer insulating film)
320 Interlayer insulation film (second interlayer insulation film)
330 Via (metal)
332 Second copper wiring (metal)

Claims (10)

  1. 　半導体基板上の多層配線層の内部に２つ以上の抵抗変化素子を有する半導体装置であって、
    　前記抵抗変化素子は、下部電極と上部電極との間に抵抗が変化する抵抗変化層が介在した構成となっており、
    　前記多層配線層における所定の配線層の配線は、前記下部電極を兼ね、
    　前記上部電極は、一方向に延在したライン状に形成されるとともに、前記抵抗変化素子に対して前記一方向に沿って隣接する他の第１の抵抗変化素子の上部電極をも兼ねることを特徴とする半導体装置。     A semiconductor device having two or more variable resistance elements inside a multilayer wiring layer on a semiconductor substrate,
    The resistance change element has a configuration in which a resistance change layer in which resistance changes between the lower electrode and the upper electrode.
    The wiring of the predetermined wiring layer in the multilayer wiring layer also serves as the lower electrode,
    The upper electrode is formed in a line extending in one direction, and also serves as an upper electrode of another first variable resistance element adjacent to the variable resistance element along the one direction. A featured semiconductor device.
  2. 　前記抵抗変化素子は、前記多層配線層の内部に４つ以上有するとともに、２次元アレイ状に配置され、
    　前記多層配線層における所定の配線層の配線は、前記一方向の直角方向に延在したライン状に形成されるとともに、前記抵抗変化素子に対して前記一方向の直角方向に沿って隣接する他の第２の抵抗変化素子の下部電極をも兼ねることを特徴とする請求項１記載の半導体装置。     The resistance change element has four or more inside the multilayer wiring layer and is arranged in a two-dimensional array,
    The wiring of the predetermined wiring layer in the multilayer wiring layer is formed in a line extending in a direction perpendicular to the one direction and is adjacent to the variable resistance element along the direction perpendicular to the one direction. 2. The semiconductor device according to claim 1, which also serves as a lower electrode of the second variable resistance element.
  3. 　前記下部電極は、金属イオンの供給源となる材料を含み、
    　前記上部電極は、前記下部電極よりもイオン化しにくい材料で構成され、
    　前記抵抗変化層は、前記金属イオンが伝導可能なイオン伝導層であることを特徴とする請求項２又は３記載の半導体装置。     The lower electrode includes a material that is a source of metal ions,
    The upper electrode is made of a material that is less ionized than the lower electrode,
    4. The semiconductor device according to claim 2, wherein the variable resistance layer is an ion conductive layer capable of conducting the metal ions.
  4. 　半導体基板上の多層配線層の内部に２つ以上の相補型抵抗変化素子を有する半導体装置であって、
    　前記相補型抵抗変化素子は、下部電極と第１上部電極との間に抵抗が変化する第１抵抗変化層が介在するとともに、前記第１上部電極から離間した位置にて前記下部電極と第２上部電極との間に抵抗が変化する第２抵抗変化層が介在した構成となっており、
    　前記下部電極は、前記多層配線層における所定の配線層に配され、
    　前記第１上部電極は、一方向に延在したライン状に形成されるとともに、前記相補型抵抗変化素子に対して前記一方向に沿って隣接する他の第１の相補型抵抗変化素子の第１上部電極をも兼ねることを特徴とする半導体装置。     A semiconductor device having two or more complementary resistance change elements inside a multilayer wiring layer on a semiconductor substrate,
    The complementary resistance change element includes a first resistance change layer in which resistance is changed between a lower electrode and a first upper electrode, and the second electrode and the second electrode are spaced apart from the first upper electrode. It has a configuration in which a second variable resistance layer in which resistance changes between the upper electrode,
    The lower electrode is disposed on a predetermined wiring layer in the multilayer wiring layer,
    The first upper electrode is formed in a line extending in one direction, and the first upper electrode of another complementary variable resistance element adjacent to the complementary variable resistance element along the one direction. 1. A semiconductor device that also serves as an upper electrode.
  5. 　前記相補型抵抗変化素子は、前記多層配線層の内部に４つ以上有するとともに、２次元アレイ状に配置され、
    　前記多層配線層における他の所定の配線層の配線は、前記一方向の直角方向に延在したライン状に形成されるとともに、前記第２上部電極、及び、前記相補型抵抗変化素子に対して前記一方向の直角方向に沿って隣接する他の第２の相補型抵抗変化素子の第２上部電極のそれぞれとビアを介して接続されることを特徴とする請求項４記載の半導体装置。     The complementary variable resistance elements have four or more inside the multilayer wiring layer and are arranged in a two-dimensional array.
    The wiring of another predetermined wiring layer in the multilayer wiring layer is formed in a line shape extending in a direction perpendicular to the one direction, and is connected to the second upper electrode and the complementary resistance change element. 5. The semiconductor device according to claim 4, wherein the semiconductor device is connected to each of the second upper electrodes of other second complementary variable resistance elements adjacent along the right-angle direction of the one direction via vias.
  6. 　前記下部電極は、前記第１上部電極と前記多層配線層における他の所定の配線層の配線とが重なる領域から前記一方向の直角方向に延在して前記第２上部電極と前記多層配線層における他の所定の配線層の配線とが重なる領域までの間の領域に配されることを特徴とする請求項５記載の半導体装置。 The lower electrode extends in a direction perpendicular to the one direction from a region where the first upper electrode and a wiring of another predetermined wiring layer in the multilayer wiring layer overlap, and the second upper electrode and the multilayer wiring layer 6. The semiconductor device according to claim 5, wherein the semiconductor device is arranged in a region up to a region where the wiring of another predetermined wiring layer overlaps.
  7. 　前記下部電極は、金属イオンの供給源となる材料を含み、
    　前記第１上部電極及び前記第２上部電極は、前記下部電極よりもイオン化しにくい材料で構成され、
    　前記第１抵抗変化層及び前記第２抵抗変化層は、前記金属イオンが伝導可能なイオン伝導層であることを特徴とする請求項４乃至６のいずれか一に記載の半導体装置。     The lower electrode includes a material that is a source of metal ions,
    The first upper electrode and the second upper electrode are made of a material that is less ionized than the lower electrode,
    The semiconductor device according to claim 4, wherein the first variable resistance layer and the second variable resistance layer are ion conductive layers capable of conducting the metal ions.
  8. 　層間絶縁膜において一方向に延在した配線溝を形成する工程と、
    　前記配線溝に下部電極を埋め込む工程と、
    　前記下部電極を含む前記層間絶縁膜上にバリア絶縁膜を堆積する工程と、
    　前記バリア絶縁膜において前記下部電極に通ずる開口部を形成する工程と、
    　前記下部電極を含む前記バリア絶縁膜上に抵抗変化層を堆積する工程と、
    　前記抵抗変化層上に上部電極層を堆積する工程と、
    　前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記一方向の直角方向に延在したライン状の前記上部電極及び前記抵抗変化層を形成する工程と、
    を含むことを特徴とする半導体装置の製造方法。     Forming a wiring groove extending in one direction in the interlayer insulating film;
    Burying a lower electrode in the wiring trench;
    Depositing a barrier insulating film on the interlayer insulating film including the lower electrode;
    Forming an opening communicating with the lower electrode in the barrier insulating film;
    Depositing a variable resistance layer on the barrier insulating film including the lower electrode;
    Depositing an upper electrode layer on the variable resistance layer;
    Removing the upper electrode layer and a part of the variable resistance layer to form the line-shaped upper electrode and the variable resistance layer extending in a direction perpendicular to the one direction;
    A method for manufacturing a semiconductor device, comprising:
  9. 　第１層間絶縁膜において一方向に所定の長さで延在した配線溝を形成する工程と、
    　前記配線溝に下部電極を埋め込む工程と、
    　前記下部電極を含む前記第１層間絶縁膜上に第１バリア絶縁膜を堆積する工程と、
    　前記第１バリア絶縁膜において前記下部電極に通ずる２つの開口部を形成する工程と、
    　前記下部電極を含む前記第１バリア絶縁膜上に抵抗変化層を堆積する工程と、
    　前記抵抗変化層上に上部電極層を堆積する工程と、
    　前記上部電極層及び前記抵抗変化層の一部を除去することにより、前記２つの開口部の一方の開口部上を通るように前記一方向の直角方向に延在したライン状の第１上部電極及び第１抵抗変化層を形成するとともに、前記２つの開口部の他方の開口部上に配されたブロック状の第２上部電極及び第２抵抗変化層を形成する工程と、
    を含むことを特徴とする半導体装置の製造方法。     Forming a wiring trench extending in one direction with a predetermined length in the first interlayer insulating film;
    Burying a lower electrode in the wiring trench;
    Depositing a first barrier insulating film on the first interlayer insulating film including the lower electrode;
    Forming two openings that communicate with the lower electrode in the first barrier insulating film;
    Depositing a resistance change layer on the first barrier insulating film including the lower electrode;
    Depositing an upper electrode layer on the variable resistance layer;
    By removing a part of the upper electrode layer and the resistance change layer, a linear first upper electrode extending in a direction perpendicular to the one direction so as to pass over one of the two openings. And forming a first variable resistance layer and forming a block-shaped second upper electrode and a second variable resistance layer disposed on the other opening of the two openings,
    A method for manufacturing a semiconductor device, comprising:
  10. 　前記第１上部電極及び前記第１抵抗変化層並びに前記第２上部電極及び前記第２抵抗変化層を含む前記第１バリア絶縁膜上に第２層間絶縁膜を堆積する工程と、
    　前記第２層間絶縁膜の表面を平坦化する工程と、
    　平坦化された前記第２層間絶縁膜上に第２バリア絶縁膜を堆積する工程と、
    　前記第２バリア絶縁膜上に第３層間絶縁膜を堆積する工程と
    　前記第３層間絶縁膜において前記一方向に延在したライン状の配線溝を形成するとともに、前記第２バリア絶縁膜及び前記第２層間絶縁膜において前記第３層間絶縁膜の前記配線溝から前記第２上部電極に通ずる下穴を形成する工程と、
    　前記第３層間絶縁膜の前記配線溝、及び、前記第２層間絶縁膜の前記下穴に金属を埋め込む工程と、
    を含むことを特徴とする請求項９記載の半導体装置の製造方法。     Depositing a second interlayer insulating film on the first barrier insulating film including the first upper electrode, the first resistance change layer, the second upper electrode, and the second resistance change layer;
    Planarizing the surface of the second interlayer insulating film;
    Depositing a second barrier insulating film on the planarized second interlayer insulating film;
    Depositing a third interlayer insulating film on the second barrier insulating film; forming a line-shaped wiring groove extending in the one direction in the third interlayer insulating film; and the second barrier insulating film and the Forming a pilot hole from the wiring groove of the third interlayer insulating film to the second upper electrode in the second interlayer insulating film;
    Burying a metal in the wiring groove of the third interlayer insulating film and the prepared hole of the second interlayer insulating film;
    The method of manufacturing a semiconductor device according to claim 9, comprising:
PCT/JP2012/069627 2011-08-02 2012-08-01 Semiconductor device and method for manufacturing same WO2013018842A1 (en)

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