WO2012129801A1 - 一种锁相环快速锁定的电路及方法 - Google Patents

一种锁相环快速锁定的电路及方法 Download PDF

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Publication number
WO2012129801A1
WO2012129801A1 PCT/CN2011/072327 CN2011072327W WO2012129801A1 WO 2012129801 A1 WO2012129801 A1 WO 2012129801A1 CN 2011072327 W CN2011072327 W CN 2011072327W WO 2012129801 A1 WO2012129801 A1 WO 2012129801A1
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WIPO (PCT)
Prior art keywords
loop filter
voltage
preset
loop
bandwidth loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2011/072327
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English (en)
French (fr)
Inventor
罗海军
郎华敏
张静磊
陈明君
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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Priority to PCT/CN2011/072327 priority Critical patent/WO2012129801A1/zh
Publication of WO2012129801A1 publication Critical patent/WO2012129801A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Definitions

  • the present invention relates to the field of wireless communication technologies, and in particular, to a circuit and method for fast locking of a phase locked loop.
  • DMR digital mobile radio
  • TDMA Time Division Multiple Access
  • the lock time of the phase-locked loop can be controlled within 1ms, the walkie-talkie is expected to implement full-duplex communication and frequency hopping communication in TDMA mode.
  • a phase-locked loop allows automatic tracking of the input signal frequency to the input signal frequency.
  • the output voltage maintains a fixed phase difference with the input voltage, that is, the phase of the output voltage and the input voltage are locked.
  • the phase-locked loop consists of three basic components: Phase Detector A, Loop Filter B, Voltage Controlled Oscillator C, and Divider 0. Among them, the voltage controlled oscillator C serves as a frequency source output frequency.
  • the output signal of the voltage controlled oscillator C is input to the phase detector A through the acquisition and distribution together with the reference frequency.
  • the phase detector A compares the frequency difference between the reference frequency and the output signal of the voltage controlled oscillator, and outputs a proportional to the frequency difference.
  • the error voltage is filtered by the loop filter B to remove the high frequency component of the error voltage, and a control voltage is controlled to control the voltage controlled oscillator C, so that the frequency of the output signal of the voltage controlled oscillator C is stabilized at a certain desired value, and the voltage control is performed.
  • the output frequency of the oscillator C is divided by the frequency divider D and fed back to the phase detector A.
  • FIG. 2 the figure is a waveform diagram of phase locked loop locking in the prior art.
  • the frequency changes from stable to unstable, the output frequency is very different from the reference frequency, and the phase-locked loop is in an unlocked state, requiring a large amount of pump current to capture the target frequency.
  • T2 phase - tracking phase The phase difference between the output frequency and the reference frequency is small, and the phase-locked loop tracks the output frequency, which belongs to the phase of the loop self-adjustment.
  • phase difference between the output frequency and the reference frequency is very small, and the phase locked loop is in a locked state.
  • the frequency deviation is less than ⁇ 100 Hz, the phase-locked loop enters a steady state.
  • the locking time of the target frequency is determined mainly by the T1 and T2P segments.
  • the time of T2 is mainly determined by the parameters of the loop itself.
  • the phase difference is already small, and the T3 can be quickly entered by the adjustment of the phase-locked loop itself.
  • the time consumed by the T1 capture phase has a direct impact on the overall lock time.
  • the loop In the TI P section, by presetting the voltage-controlled voltage corresponding to the target frequency for the phase-locked loop, and by the expansion of the operational amplifier, the loop is quickly charged and discharged, so that the frequency difference in the phase detector is rapidly reduced. Go to a smaller value to enter the T2 P section.
  • phase noise and locking speed of the phase locked loop are mutually constrained.
  • An increase in the loop bandwidth increases the locking speed, but at the same time the phase noise increases.
  • the loop bandwidth is reduced, which reduces phase noise, but increases the lock time.
  • the time required for the oscillation frequency of the voltage-controlled oscillator in the phase-locked loop to switch between the two frequency points is related to the frequency interval between the two frequency points.
  • the technical problem to be solved by the present invention is to provide a circuit and method for quickly locking a phase locked loop, which can improve the locking speed of the phase locked loop without affecting phase noise.
  • Embodiments of the present invention provide a circuit for fast locking of a phase locked loop, including: a controller, a memory, a digital to analog converter, an operational amplifier, a wide bandwidth loop filter, and a narrow bandwidth loop filter;
  • a controller configured to send a preset voltage control voltage stored in the memory to the DAC; and preset a preset voltage control voltage of the digital signal corresponding to the target frequency in the memory;
  • a digital-to-analog converter for converting a preset voltage-controlled voltage of the digital signal into a preset of an analog signal
  • the voltage control voltage is sent to the wide bandwidth loop filter to voltage preset the wide bandwidth loop filter;
  • the DAC is also used to send the preset voltage control voltage of the analog signal to the narrow bandwidth loop filter through the operational amplifier a voltage preset for the narrow bandwidth loop filter; at this time, the controller controls the wide bandwidth loop filter as a loop filter in the phase locked loop;
  • the controller controls
  • the DAC is disconnected from the wide bandwidth loop filter while the control DAC is disconnected from the operational amplifier; the wide bandwidth loop filter is used to voltage preset the narrow bandwidth loop filter through the operational amplifier; at this point, the controller controls the wide bandwidth loop
  • the path filter still acts as a loop filter in the phase-locked loop;
  • the controller controls the narrow-bandwidth loop filter as a loop filter in the phase-locked loop.
  • the controller controls the connection state of the digital-to-analog converter and the wide bandwidth loop filter and the digital-to-analog converter and the operational amplifier by controlling the first switch;
  • the first end of the first switch is connected to the digital-to-analog converter, the second end is connected to the operational amplifier, and the second end is connected to the wide bandwidth loop filter, and the third end is connected to the controller.
  • the controller controls the connection state of the operational amplifier and the narrow bandwidth loop filter by controlling the second switch;
  • the first end of the second switch is connected to the operational amplifier, the second end is connected to the narrow bandwidth loop filter, and the third end is connected to the controller.
  • the controller controls the connection state of the wide bandwidth loop filter and the narrow bandwidth loop filter in the phase locked loop by controlling the first loop selection switch and the second loop selection switch;
  • the first end of the first loop selection switch is connected to the output end of the phase detector in the phase locked loop, the control end of the first loop selection switch is connected to the controller, and the second end of the first loop selection switch is connected to the wide bandwidth loop.
  • a filter, the third end of the first loop selection switch is connected to the narrow bandwidth loop filter;
  • the first end of the second loop selection switch is connected to the input end of the voltage controlled oscillator in the phase locked loop, the control end of the second loop selection switch is connected to the controller, and the second end of the second loop selection switch is connected to the wide bandwidth.
  • the loop filter, the third end of the second loop selection switch is connected to the narrow bandwidth loop filter.
  • the read switch is connected between the controller and the narrow bandwidth loop filter, and the analog to digital converter is connected between the preset voltage controlled voltage read switch and the controller;
  • the controller Before the phase-locked loop is shipped from the factory, the controller is used to control the read switch to close, and the analog-to-digital converter reads the preset voltage-controlled voltage from the narrow-band loop filter, converts it into a digital preset voltage-controlled voltage, and sends it to the controller.
  • the controller stores the digital preset voltage control voltage in the memory.
  • the embodiment of the invention further provides a method for quickly locking a phase locked loop, comprising:
  • the preset voltage control voltage is stopped as a wide bandwidth loop filter and a narrow bandwidth loop filter voltage preset, and the wide bandwidth loop filter is used for voltage preset of the narrow bandwidth loop filter.
  • the wide bandwidth loop filter reaches the locked voltage control voltage under the control of the voltage control voltage output from the phase detector, and the narrow bandwidth loop filter continues to be a narrowband loop filter. Perform voltage presets;
  • the wide bandwidth loop filter acts as a loop filter in the phase locked loop during the first predetermined time period, the second predetermined time period, and the third predetermined time period; during the fourth predetermined time period, the narrow bandwidth loop
  • the filter acts as a loop filter in the phase-locked loop.
  • the method includes: before the preset voltage control voltage is simultaneously applied to the wide bandwidth loop filter and the narrow bandwidth loop filter, the method further includes: reading a digital preset voltage control voltage from the memory, and The preset voltage control voltage is converted into an analog preset voltage control voltage;
  • the preset voltage control voltage is simultaneously applied to the wide bandwidth loop filter and the narrow bandwidth loop filter by voltage presets:
  • the analog preset voltage control voltage is preset for the wide bandwidth loop filter; the analog preset voltage control voltage is expanded by the operational amplifier to perform voltage preset for the narrow bandwidth loop filter.
  • a fifth predetermined time period is further included between the third predetermined time period and the fourth predetermined time period;
  • the wide bandwidth loop filter is voltage preset for the narrow bandwidth loop filter, and the narrow bandwidth loop filter acts as a loop filter in the phase locked loop.
  • the method before the reading the digital preset voltage control voltage from the memory, the method further includes: The preset voltage control voltage is read from the wide bandwidth loop filter, converted into a digital preset voltage control voltage, and stored in the memory.
  • the present invention has the following advantages:
  • the circuit and method for quickly locking a phase-locked loop provide two loops of a wide bandwidth loop filter and a narrow bandwidth loop filter, and a wide bandwidth loop filter is initially used as a loop filter in a phase locked loop.
  • the preset voltage control voltage simultaneously presets the voltage of the wide bandwidth loop filter and the narrow bandwidth loop filter. Since the power in the wide bandwidth loop filter is small, the voltage preset speed is fast. This can quickly reduce the frequency difference in the phase detector in the phase-locked loop to a small value. The smaller the frequency difference, the shorter the time taken to capture phase T1.
  • the wide bandwidth loop filter When the wide bandwidth loop filter voltage is preset to be stable, the wide bandwidth loop filter performs voltage presets for the narrow bandwidth loop filter, so that the narrow bandwidth loop filter obtains an accurate preset voltage control voltage, which is narrow
  • the bandwidth loop filter acts as a loop filter in the phase-locked loop. Due to the narrow bandwidth loop filter used in the final stabilization phase of the phase-locked loop, the narrow-bandwidth loop filter is a narrow bandwidth loop and therefore does not deteriorate the phase noise of the phase-locked loop. Therefore, the present invention utilizes a wide bandwidth loop filter to lock a stable voltage-controlled voltage, which shortens the time of the narrow-bandwidth loop filter T1, and the final stability with a narrow-band wide loop filter does not affect phase noise.
  • FIG. 1 is a schematic diagram of a phase locked loop in the prior art
  • FIG. 2 is a schematic diagram of a waveform of a phase locked loop locked in the prior art
  • FIG. 3 is a structural diagram of a circuit embodiment provided by the present invention.
  • FIG. 4 is a structural diagram of a second embodiment of a circuit provided by the present invention.
  • FIG. 5 is a flowchart of Embodiment 1 of a method for quickly locking a phase locked loop provided by the present invention
  • FIG. 6 is a flow chart of Embodiment 2 of a method for quickly locking a phase locked loop provided by the present invention.
  • the circuit for quickly locking the phase locked loop provided by this embodiment includes: a controller 301, a memory 302, a digital analog converter (DAC) 303, an operational amplifier 304, a wide bandwidth loop filter 305, and a narrow bandwidth loop.
  • the controller 301 is configured to send a preset voltage control voltage stored in the memory 302 to the DAC 303; and store a preset voltage control voltage corresponding to the target frequency in the memory 302;
  • the DAC 303 is configured to convert the preset voltage control voltage into an analog preset voltage control voltage and then send the signal to the wide bandwidth loop filter 305 to perform voltage preset on the wide bandwidth loop filter 305.
  • the DAC 303 is also used to simulate The preset voltage control voltage is sent to the narrow bandwidth loop filter 306 through the operational amplifier 304, and the voltage is preset to the narrow bandwidth loop filter 306; at this time, the controller 301 controls the wide bandwidth loop filter 305 as the phase lock. a loop filter in the ring;
  • the controller 301 controls the DAC 303 to be disconnected from the wide bandwidth loop filter 305 while controlling the DAC 303 to be disconnected from the operational amplifier 304; wide bandwidth loop filtering
  • the controller 305 performs voltage preset on the narrow bandwidth loop filter 306 through the operational amplifier 304; at this time, the controller 301 controls the wide bandwidth loop filter 305 to still function as a loop filter in the phase locked loop;
  • the controller controls the large capacitance filter as a loop filter in the phase locked loop.
  • the circuit for quickly locking a phase-locked loop sets two loops of a wide bandwidth loop filter and a narrow bandwidth loop filter.
  • the wide bandwidth loop filter is initially used as a loop filter in the phase locked loop.
  • the preset voltage control voltage simultaneously presets the voltage of the wide bandwidth loop filter and the narrow bandwidth loop filter. Since the power in the wide bandwidth loop filter is small, the voltage preset speed is fast. This allows the frequency difference in the phase detector in the phase-locked loop to be quickly reduced to a small value. The smaller the frequency difference, the shorter the time taken during the capture phase T1.
  • the wide bandwidth loop filter When the wide bandwidth loop filter voltage is preset to be stable, the wide bandwidth loop filter performs voltage presets for the narrow bandwidth loop filter, so that the narrow bandwidth loop filter obtains an accurate preset voltage control voltage, which is narrow
  • the bandwidth loop filter acts as a loop filter in the phase-locked loop. Due to the narrow bandwidth loop filter used in the final stabilization phase of the phase-locked loop, the narrow-bandwidth loop filter is a narrow-bandwidth loop and therefore does not degrade the phase noise of the phase-locked loop. Therefore, the present invention can shorten the time of T1 by using a wide bandwidth loop filter, and the final stability by using a narrow bandwidth loop filter does not affect phase noise.
  • FIG. 4 is a structural diagram of a second embodiment of a circuit provided by the present invention. 4 increases the first switch 401, the second switch 402, the first loop selection switch 403, the second loop selection switch 404, the read switch 405, and the analog-to-digital converter (ADC, Analog Digital Converter) compared with FIG. ) 406.
  • ADC Analog Digital Converter
  • the controller 301 controls the connection state of the DAC 303 and the wide bandwidth loop filter 305 and the DAC 303 and the operational amplifier 304 by controlling the first switch 401;
  • the first end of the first switch 401 is connected to the DAC 303, the second end is connected to the operational amplifier 304, and the second end is connected to the wide bandwidth loop filter 305, and the third end is connected to the controller 301.
  • the controller 301 controls the connection state of the operational amplifier 304 and the narrow bandwidth loop filter 306 by controlling the second switch 402;
  • the first end of the second switch 402 is connected to the operational amplifier 304, the second end is connected to the narrow bandwidth loop filter 306, and the third end is connected to the controller 301.
  • the controller 301 controls the connection state of the wide bandwidth loop filter 305 and the narrow bandwidth loop filter 306 in the phase locked loop by controlling the first loop selection switch 403 and the second loop selection switch 404;
  • the first end of the selection switch 403 is connected to the output end of the phase detector A in the phase locked loop, the control end of the first loop selection switch 403 is connected to the controller 301, and the second end of the first loop selection switch 403 is connected to the wide bandwidth.
  • a loop filter 305, the third end of the first loop selection switch 403 is connected to the narrow bandwidth loop filter 306;
  • the first end of the second loop selection switch 404 is connected to the input end of the voltage controlled oscillator C in the phase locked loop, the control end of the second loop selection switch 404 is connected to the controller 301, and the second loop selection switch 404 is The two ends are connected to the wide bandwidth loop filter 305, and the third end of the second loop selection switch 404 is connected to the narrow bandwidth loop filter 306.
  • phase locked loop may further include a frequency divider D.
  • the output frequency of the voltage controlled oscillator C is divided by the frequency divider D and sent to the phase detector A.
  • the circuit provided in this embodiment further includes a read switch 405 and an ADC 406;
  • the read switch 405 is connected between the controller 301 and the wide bandwidth loop filter 305, and the ADC 406 is connected between the read switch 405 and the controller 301;
  • each phase-locked loop can establish a voltage-controlled voltage model in its controller before leaving the factory, and the voltage-controlled voltage model is based on the M frequency points collected over the entire frequency segment and the M The voltage control voltage corresponding to the frequency point is determined.
  • the controller 301 is configured to control the read switch 405 to be closed, and the ADC 406 reads the preset voltage-controlled voltage from the wide-band loop filter 305, converts it into a digital preset voltage-controlled voltage, and sends it to the controller. 301.
  • the controller 301 stores the digital preset voltage control voltage in the memory 302.
  • the controller 301 controls the first switch 401 to be closed, the DAC 303 is turned on with the operational amplifier 304, and the controller 301 controls the DAC 303 to transmit the preset voltage control voltage to the wide bandwidth loop filter 305 through the first switch 401.
  • the voltage bandwidth is preset to the wide bandwidth loop filter 305; at the same time, the controller 301 controls the second switch 402 to be closed, the operational amplifier 304 is turned on with the narrow bandwidth loop filter 306, and the preset voltage control voltage is narrow bandwidth loop filtering.
  • the device 306 performs voltage presets.
  • the wide bandwidth loop filter 305 is used as a wide bandwidth loop filter, the power is small, so the voltage is preset quickly, which can greatly shorten the frequency difference between the output frequency of the voltage controlled oscillator C and the target frequency. , greatly reducing the T1 time and allowing the phase-locked loop to quickly enter the ⁇ 2 ⁇ section.
  • the controller 301 controls the first switch 401 to open, the DAC 303 is disconnected from the wide bandwidth loop filter 305, and the wide bandwidth loop filter 305 stops the voltage preset. At this point, the phase locked loop achieves the first lock under the control of the controller 301.
  • the first switch 401 controls the first loop selection switch 403 and the second loop selection switch 404 to be connected to the wide bandwidth loop filter from the closed to the off state, that is, at this stage, small capacitance filtering
  • the device acts as a loop filter in the phase-locked loop.
  • the controller 301 controls 402 to be closed, and the voltage is preset by the wide bandwidth loop filter 305 through the operational amplifier 304 and the first switch 402 for the narrow bandwidth loop filter 306 until the narrow bandwidth loop
  • the preset voltage control voltage of filter 306 is also accurate.
  • the controller 301 controls the first loop selection switch 403 and the second loop selection switch 404 to be both connected to the narrow bandwidth loop filter 306, that is,
  • the narrow bandwidth loop filter 306 acts as a loop filter in the phase locked loop, thereby achieving a smooth transition of the preset voltage control voltage from the wide bandwidth loop filter 305 to the narrow bandwidth loop filter 306.
  • the narrow bandwidth loop filter 306 has entered the T1 section.
  • the controller 301 controls the first switch 402 to be turned off, stabilized by the phase detector ⁇ for the narrow bandwidth loop filter 306, and the narrow bandwidth loop filter 306 is entered. T3 stage.
  • narrow bandwidth loop filter 306 is used as a narrow bandwidth loop to provide preset voltage control for the phase locked loop. Pressure.
  • the circuit provided by the present invention does not degrade the phase noise of the phase locked loop.
  • the circuit provided by the invention greatly shortens the time of the T1, the fast locking of the phase locked loop can be realized, and therefore, the full duplex communication and the frequency hopping communication in the TDMA mode can be realized in a wireless communication device such as a walkie-talkie. A qualitative leap in the walkie-talkie that has been in half-duplex communication.
  • the present invention also provides a method for quickly locking a phase-locked loop, and the working flow thereof will be described in detail below in conjunction with specific embodiments.
  • FIG. 5 the figure is a flowchart of Embodiment 1 of a method for quickly locking a phase locked loop provided by the present invention.
  • the method for quickly locking a phase locked loop provided by this embodiment includes the following steps:
  • S501 performing voltage preset on the wide bandwidth loop filter and the narrow bandwidth loop filter simultaneously with the preset voltage control voltage during the first predetermined time period;
  • the wide bandwidth loop filter is a wide bandwidth loop
  • the narrow bandwidth loop filter is a narrow bandwidth loop
  • S502 Stop the preset voltage control voltage for the wide bandwidth loop filter and the narrow bandwidth loop filter for voltage preset in the second predetermined time period, and the wide bandwidth loop filter is used for the narrow bandwidth loop filter Voltage preset
  • the voltage preset is fast, and the preset voltage control is stopped when the wide bandwidth loop filter voltage is preset to the output voltage control voltage reaches the preset voltage control voltage.
  • the voltage is preset for a wide bandwidth loop filter and a narrow bandwidth loop filter voltage, while the wide bandwidth loop filter is preset for a narrow bandwidth loop filter voltage.
  • S504 Stop the wide bandwidth loop filter to perform voltage preset for the narrow bandwidth loop filter in the fourth predetermined time period; the narrow bandwidth loop filter reaches the control under the control of the voltage control voltage outputted by the phase detector Stable voltage control voltage after locking;
  • the narrow bandwidth loop filter voltage is preset to the output voltage control voltage reaches the precise voltage control voltage, the voltage preset is stopped, and the narrow bandwidth loop filter is controlled by the phase detector in the phase locked loop.
  • the broadband The wide loop filter acts as a loop filter in the phase locked loop; during the fourth predetermined time period, the narrow bandwidth loop filter acts as a loop filter in the phase locked loop.
  • a wide bandwidth loop filter is used as the loop filter in the phase-locked loop, and the narrow-band loop filter obtains a stable preset voltage-controlled voltage. After that, a narrow bandwidth loop filter is used as a loop filter in the phase locked loop. Since the narrow bandwidth loop filter is a narrow bandwidth loop filter, it does not affect the phase noise of the phase locked loop.
  • the method for quickly locking a phase-locked loop sets two loops of a wide bandwidth loop filter and a narrow bandwidth loop filter, and a wide bandwidth loop filter is initially used as a loop filter in a phase locked loop.
  • the preset voltage control voltage simultaneously presets the voltage of the wide bandwidth loop filter and the narrow bandwidth loop filter. Since the power in the wide bandwidth loop filter is small, the voltage preset speed is fast. This can quickly reduce the frequency difference in the phase detector in the phase-locked loop to a small value. The smaller the frequency difference, the capture phase.
  • the time taken by T1 is also shorter.
  • the wide bandwidth loop filter performs voltage presets for the narrow bandwidth loop filter, so that the narrow bandwidth loop filter obtains an accurate preset voltage control voltage, which is narrow
  • the bandwidth loop filter acts as a loop filter in the phase-locked loop. Due to the narrow bandwidth loop filter used in the final stabilization phase of the phase-locked loop, the narrow-bandwidth loop filter is a narrow-bandwidth loop and therefore does not degrade the phase noise of the phase-locked loop. Therefore, the present invention can shorten the time of T1 by using a wide bandwidth loop filter, and the final stability by using a narrow bandwidth loop filter does not affect phase noise.
  • FIG. 6 is a flowchart of Embodiment 2 of a method for quickly locking a phase locked loop provided by the present invention.
  • S601 Read the preset voltage control voltage from the wide bandwidth loop filter, convert it into a digital preset voltage control voltage, and store it in the memory.
  • the controller controls the ADC to read the preset voltage-controlled voltage and convert it to a digital preset voltage-controlled voltage and store it in the memory.
  • S602 reading a digital preset voltage control voltage from the memory, converting the digital preset voltage control voltage into an analog preset voltage control voltage; converting the digital preset voltage control voltage into an analog preset through the DAC Voltage controlled voltage.
  • S603 Perform voltage preset on the analog preset voltage control voltage for the wide bandwidth loop filter in the first predetermined time period; and expand the analog preset voltage control voltage through the operational amplifier to filter the narrow bandwidth loop The voltage is preset.
  • the wide bandwidth loop filter acts as a loop filter in the phase locked loop during the first predetermined time period.
  • S604 Stop the preset voltage control voltage as a wide bandwidth loop filter and a narrow bandwidth loop filter voltage preset in a second predetermined time period, and perform voltage on the narrow bandwidth loop filter by the wide bandwidth loop filter Preset
  • the wide bandwidth loop filter acts as a loop filter in the phase locked loop;
  • S605 the voltage controlled voltage of the wide bandwidth loop filter at the phase detector output during the third predetermined time period Under the control of the lock, the stable voltage control voltage is reached, and the wide bandwidth loop filter continues to perform voltage preset for the narrowband loop filter;
  • the wide bandwidth loop filter performs voltage preset for the narrow bandwidth loop filter, and the narrow bandwidth loop filter acts as a loop filter in the phase locked loop.
  • S607 Stop the wide bandwidth loop filter to perform voltage preset for the narrow bandwidth loop filter in the fourth predetermined time period; the narrow bandwidth loop filter reaches the control under the control of the voltage control voltage outputted by the phase detector Stable voltage control voltage after locking;
  • the narrow bandwidth loop filter acts as a loop filter in the phase locked loop.
  • a narrow bandwidth loop filter is used as a narrow bandwidth loop to provide a preset voltage control voltage for the phase locked loop. Since the final temperature phase uses a narrow bandwidth loop filter as a narrow bandwidth loop, the circuit provided by the present invention does not deteriorate the phase noise of the phase locked loop.
  • the method provided by the invention greatly shortens the time of the T1, the fast locking of the phase locked loop can be realized, and therefore, the full duplex communication and the frequency hopping communication in the TDMA mode can be implemented in a wireless communication device such as a walkie-talkie. A qualitative leap in the walkie-talkie that has been in half-duplex communication.

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Description

L
一种锁相环快速锁定的电路及方法 技术领域
本发明涉及无线通信技术领域，特别涉及一种锁相环快速锁定的电路及方 法。
背景技术
目前， 数字移动无线电（DMR, Digital Mobile Radio )通信对对讲机采用 时分多址（ TDMA, Time Division Multiple Access )技术， 不过由于受到锁定 时间的技术局限， 目前只能实现半双工通信。如果锁相环的锁定时间能够控制 在 1ms以内， 则对讲机有望在 TDMA模式下实现全双工通信及跳频通信。
锁相环（ PLL, Phase-Locked Loop ) 可以实现输出信号频率对输入信号频 率的自动跟踪。锁相环在工作过程中， 当输出信号的频率与输入信号的频率相 等时，输出电压与输入电压保持固定的相位差值， 即输出电压与输入电压的相 位被锁住。
下面结合图 1介绍锁相环的组成及工作原理。
锁相环包括三个基本组成部分： 鉴相器 A、 环路滤波器 B、 压控振荡器 C 和分频器0。 其中， 压控振荡器 C作为频率源输出频率。
压控振荡器 C 的输出信号经过采集并分配和参考频率一起被输入鉴相器 A, 鉴相器 A通过比较参考频率和压控振荡器的输出信号的频率差， 输出一个 与频率差成正比的误差电压， 再经过环路滤波器 B 滤去误差电压中的高频成 分，输出一个控制电压控制压控振荡器 C,使压控振荡器 C输出信号的频率稳 定在某一个期望值， 压控振荡器 C的输出频率再经过分频器 D分频后反馈给 鉴相器 A。
下面结合附图介绍频率锁定的过程。 参见图 2, 该图为现有技术中锁相环 锁定的波形示意图。
1 ) Tl P介段 -捕获阶段：
由于频点的切换， 频率从稳定到不稳定的急剧变化，输出频率与参考频率 相位差非常大， 锁相环处于失锁状态， 需要大量的泵电流来捕获目标频率。
2 ) T2阶段-跟踪阶段： 输出频率与参考频率相位差较小，锁相环对输出频率进行跟踪，属于环路 自身调节的阶段。
3 ) T3 P介段 -稳定阶段：
输出频率与参考频率相位差非常小，锁相环处于锁定的状态。 当频率偏差 小于 ± 100Hz时， 锁相环进入稳定状态。
如图 2所示， 锁定过程的三个阶段中， 主要是由 T1和 T2 P介段决定目标 频率的锁定时间。 而 T2的时间主要是由于环路自身的参数决定。 T2时， 相位 差已经比较小了， 靠锁相环自身的调节可以很快进入 T3。 然而， T1捕获阶段 所消耗的时间， 对整体锁定时间有直接的影响。
在 TI P介段， 通过为锁相环预置目标频率对应的压控电压的方式， 并通过 运算放大器的扩流作用，给环路快速充放电，使鉴相器中的频差快速减小到一 个较小值， 以进入 T2 P介段。 环路本身的充放电量越小， 预置压控电压越精确， 则 Tl P介段所能达到的频差也越小， 锁定过程所用的时间也越短。
由于压控振荡器 C带宽的限制， 锁相环的相位噪声和锁定速度相互制约。 环路带宽增大可以提高锁定速度，但同时相位噪声会增大。反之环路带宽减小， 可以降低相位噪声， 但是会延长锁定时间。
锁相环中的压控振荡器的振荡频率在两个频点之间切换所需的时间与两 个频点间的频率间隔有关， 两个频率间隔越大， 对应的压控电压相差越大， 因 此需要的切换时间越长。
因此， 需要在提高锁相环的锁定速度的同时， 不影响相位噪声是本领域技 术人员需要解决的问题。
发明内容
本发明要解决的技术问题是提供一种锁相环快速锁定的电路及方法，能够 提高锁相环的锁定速度， 同时不影响相位噪声。
本发明实施例提供一种锁相环快速锁定的电路， 包括： 控制器、 存储器、 数模转换器、 运算放大器、 宽带宽环路滤波器和窄带宽环路滤波器；
控制器， 用于将存储器中存储的预置压控电压发送给 DAC; 存储器中预 先存储与目标频率对应的数字信号的预置压控电压；
数模转换器，用于将所述数字信号的预置压控电压转换为模拟信号的预置 压控电压后发送给宽带宽环路滤波器， 对宽带宽环路滤波器进行电压预置； DAC还用于将所述模拟信号的预置压控电压通过运算放大器发送给窄带宽环 路滤波器， 对窄带宽环路滤波器进行电压预置； 此时， 控制器控制宽带宽环路 滤波器作为锁相环中的环路滤波器；
当宽带宽环路滤波器的输出电压达到所述预置压控电压后， 控制器控制
DAC与宽带宽环路滤波器断开， 同时控制 DAC与运算放大器断开； 宽带宽环 路滤波器通过运算放大器给窄带宽环路滤波器进行电压预置； 此时，控制器控 制宽带宽环路滤波器仍然作为锁相环中的环路滤波器；
当窄带宽环路滤波器获得宽带宽环路滤波器锁定后稳定的压控电压时，控 制器控制窄带宽环路滤波器作为锁相环中的环路滤波器。
优选地，控制器通过控制第一开关来控制数模转换器与宽带宽环路滤波器 以及数模转换器与运算放大器的连接状态；
第一开关的第一端连接数模转换器， 第二端连接运算放大器， 同时第二端 连接宽带宽环路滤波器， 第三端连接控制器。
优选地，控制器通过控制第二开关来控制运算放大器与窄带宽环路滤波器 的连接状态；
第二开关的第一端连接运算放大器， 第二端连接窄带宽环路滤波器， 第三 端连接控制器。
优选地，控制器通过控制第一环路选择开关和第二环路选择开关来控制宽 带宽环路滤波器和窄带宽环路滤波器在锁相环中的连接状态；
第一环路选择开关的第一端连接锁相环中的鉴相器的输出端，第一环路选 择开关的控制端连接控制器，第一环路选择开关的第二端连接宽带宽环路滤波 器， 第一环路选择开关的第三端连接窄带宽环路滤波器；
第二环路选择开关的第一端连接锁相环中的压控振荡器的输入端，第二环 路选择开关的控制端连接控制器，第二环路选择开关的第二端连接宽带宽环路 滤波器， 第二环路选择开关的第三端连接窄带宽环路滤波器。
优选地， 还包括读取开关和模数转换器；
读取开关连接在控制器和窄带宽环路滤波器之间，模数转换器连接在预置 压控电压读取开关和控制器之间； 锁相环出厂前，控制器用于控制读取开关闭合，模数转换器从窄带宽环路 滤波器中读取预置压控电压， 转换为数字的预置压控电压后发送给控制器，控 制器将该数字的预置压控电压存储于存储器中。
本发明实施例还提供一种锁相环快速锁定的方法， 包括：
在第一预定时间段内，将预置压控电压同时给宽带宽环路滤波器和窄带宽 环路滤波器进行电压预置；
在第二预定时间段内，停止预置压控电压为宽带宽环路滤波器和窄带宽环 路滤波器电压预置， 由宽带宽环路滤波器为窄带宽环路滤波器进行电压预置； 在第三预定时间段内，宽带宽环路滤波器在鉴相器输出的压控电压的控制 下达到锁定后稳定的压控电压，由宽带宽环路滤波器继续为窄带环路滤波器进 行电压预置；
在第四预定时间段内，停止宽带宽环路滤波器为窄带宽环路滤波器进行电 压预置；窄带宽环路滤波器在鉴相器输出的压控电压的控制下达到所述锁定后 稳定的压控电压；
在第一预定时间段内、第二预定时间段和第三预定时间段内， 宽带宽环路 滤波器作为锁相环中的环路滤波器； 在第四预定时间段内， 窄带宽环路滤波器 作为锁相环中的环路滤波器。
优选地， 包括： 将预置压控电压同时给宽带宽环路滤波器和窄带宽环路滤 波器进行电压预置之前还包括： 从存储器中读取数字的预置压控电压，将数字 的预置压控电压转换为模拟的预置压控电压；
将预置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压 预置具体为：
将模拟的预置压控电压为宽带宽环路滤波器进行电压预置；将模拟的预置 压控电压通过运算放大器扩流后为窄带宽环路滤波器进行电压预置。
优选地， 在第三预定时间段和第四预定时间段之间还包括第五预定时间 段；
在第五预定时间段内，宽带宽环路滤波器为窄带宽环路滤波器进行电压预 置， 且窄带宽环路滤波器作为锁相环中的环路滤波器。
优选地， 所述从存储器中读取数字的预置压控电压之前还包括： 从宽带宽环路滤波器中读取预置压控电压，转换为数字的预置压控电压后 存储于存储器中。
与现有技术相比， 本发明具有以下优点：
本发明提供的锁相环快速锁定的电路及方法，设置宽带宽环路滤波器和窄 带宽环路滤波器两个环路，开始时宽带宽环路滤波器作为锁相环中的环路滤波 器， 预置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压预 置， 由于宽带宽环路滤波器中的电^艮小， 因此电压预置速度很快。 这样可以 使锁相环中的鉴相器中的频差快速减小到一个较小值，该过程中频差越小，捕 获阶段 T1所用的时间也越短。 当宽带宽环路滤波器电压预置稳定后， 由宽带 宽环路滤波器为窄带宽环路滤波器进行电压预置，从而窄带宽环路滤波器获得 精确的预置压控电压， 由窄带宽环路滤波器作为锁相环中的环路滤波器。 由于 锁相环最终稳定阶段使用的窄带宽环路滤波器，窄带宽环路滤波器是窄带宽环 路， 因此不会恶化锁相环的相位噪声。 因此， 本发明利用宽带宽环路滤波器来 锁定稳定的压控电压， 这样可以缩短窄带宽环路滤波器 T1的时间， 利用窄带 宽环路滤波器做最终的稳定不会影响相位噪声。
附图说明
图 1是现有技术中的锁相环示意图；
图 2是现有技术中锁相环锁定的波形示意图；
图 3是本发明提供的电路实施例一结构图；
图 4是本发明提供的电路实施例二结构图；
图 5是本发明提供的锁相环快速锁定的方法实施例一流程图；
图 6是本发明提供的锁相环快速锁定的方法实施例二流程图。
具体实施方式
为了使本领域技术人员更好地理解和实施本发明的技术方案， 图 2中已经 介绍了本发明依据的理论基础。 由于锁定时间主要由 T1决定， 因此， 本发明 提供的方法可以缩短 T1的时间， 进而加快锁相环的锁定。
为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
参见图 3, 该图为本发明提供的电路实施例一结构图。 本实施例提供的锁相环快速锁定的电路， 包括： 控制器 301、存储器 302、 数模转换器（DAC, Digital Analog Converter ) 303、 运算放大器 304、 宽带宽 环路滤波器 305和窄带宽环路滤波器 306;
控制器 301 , 用于将存储器 302中存储的预置压控电压发送给 DAC303; 存储器 302中预先存储与目标频率对应的预置压控电压；
DAC303 , 用于将预置压控电压转换为模拟的预置压控电压后发送给宽带 宽环路滤波器 305 , 对宽带宽环路滤波器 305进行电压预置； 同时 DAC303还 用于将模拟的预置压控电压通过运算放大器 304 发送给窄带宽环路滤波器 306, 对窄带宽环路滤波器 306进行电压预置； 此时， 控制器 301控制宽带宽 环路滤波器 305作为锁相环中的环路滤波器；
当宽带宽环路滤波器 305 的输出电压达到预置压控电压后， 控制器 301 控制 DAC303与宽带宽环路滤波器 305断开， 同时控制 DAC303与运算放大 器 304断开；宽带宽环路滤波器 305通过运算放大器 304给窄带宽环路滤波器 306进行电压预置； 此时， 控制器 301控制宽带宽环路滤波器 305仍然作为锁 相环中的环路滤波器；
当窄带宽环路滤波器 306获得宽带宽环路滤波器锁定后稳定的压控电压， 控制器控制大电容滤波器作为锁相环中的环路滤波器。
本发明提供的锁相环快速锁定的电路，设置宽带宽环路滤波器和窄带宽环 路滤波器两个环路， 开始时宽带宽环路滤波器作为锁相环中的环路滤波器，预 置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压预置，由于 宽带宽环路滤波器中的电^艮小， 因此电压预置速度很快。这样可以使锁相环 中的鉴相器中的频差快速减小到一个较小值， 该过程中频差越小， 捕获阶段 T1 所用的时间也越短。 当宽带宽环路滤波器电压预置稳定后， 由宽带宽环路 滤波器为窄带宽环路滤波器进行电压预置，从而窄带宽环路滤波器获得精确的 预置压控电压， 由窄带宽环路滤波器作为锁相环中的环路滤波器。 由于锁相环 最终稳定阶段使用的窄带宽环路滤波器， 窄带宽环路滤波器是窄带宽环路， 因 此不会恶化锁相环的相位噪声。 因此， 本发明利用宽带宽环路滤波器可以缩短 T1的时间， 利用窄带宽环路滤波器做最终的稳定不会影响相位噪声。
参见图 4, 该图为本发明提供的电路实施例二结构图。 图 4与图 3相比增加了第一开关 401、 第二开关 402、 第一环路选择开关 403、第二环路选择开关 404、读取开关 405和模数转换器（ ADC, Analog Digital Converter ) 406。
控制器 301通过控制第一开关 401来控制 DAC303与宽带宽环路滤波器 305以及 DAC303与运算放大器 304的连接状态；
第一开关 401的第一端连接 DAC303, 第二端连接运算放大器 304, 同时 第二端连接宽带宽环路滤波器 305, 第三端连接控制器 301。
控制器 301通过控制第二开关 402来控制运算放大器 304与窄带宽环路滤 波器 306的连接状态；
第二开关 402的第一端连接运算放大器 304, 第二端连接窄带宽环路滤波 器 306, 第三端连接控制器 301。
控制器 301通过控制第一环路选择开关 403和第二环路选择开关 404来控 制宽带宽环路滤波器 305和窄带宽环路滤波器 306在锁相环中的连接状态； 第一环路选择开关 403的第一端连接锁相环中的鉴相器 A的输出端， 第 一环路选择开关 403的控制端连接控制器 301 , 第一环路选择开关 403的第二 端连接宽带宽环路滤波器 305 , 第一环路选择开关 403的第三端连接窄带宽环 路滤波器 306;
第二环路选择开关 404的第一端连接锁相环中的压控振荡器 C的输入端， 第二环路选择开关 404的控制端连接控制器 301 , 第二环路选择开关 404的第 二端连接宽带宽环路滤波器 305, 第二环路选择开关 404的第三端连接窄带宽 环路滤波器 306。
需要说明的是， 锁相环中还可以包括分频器 D, 压控振荡器 C的输出频 率经过分频器 D分频后发送给鉴相器 A。
本实施例提供的电路还包括读取开关 405和 ADC406;
读取开关 405连接在控制器 301和宽带宽环路滤波器 305之间， ADC406 连接在读取开关 405和控制器 301之间；
在实际操作中，每台锁相环在出厂前， 就可在其控制器中建立压控电压模 型， 而该压控电压模型是根据在整个频率段上所采集的 M个频率点及该 M个 频率点所对应的压控电压所确定的。 锁相环出厂前， 控制器 301用于控制读取开关 405闭合， ADC406从宽带 宽环路滤波器 305中读取预置压控电压，转换为数字的预置压控电压后发送给 控制器 301 , 控制器 301将该数字的预置压控电压存储于存储器 302中。
当需要进行频率切换时， 控制器 301控制第一开关 401闭合， DAC303与 运算放大器 304接通，控制器 301控制 DAC303将预置压控电压通过第一开关 401发送给宽带宽环路滤波器 305 , 给宽带宽环路滤波器 305进行电压预置； 同时控制器 301控制第二开关 402闭合，运算放大器 304与窄带宽环路滤波器 306接通， 预置压控电压为窄带宽环路滤波器 306进行电压预置。
由于宽带宽环路滤波器 305作为宽带宽环路滤波， 其中的电^艮小， 因此 电压预置很快， 这样可以极大缩短压控振荡器 C 的输出频率与目标频率之间 的频差， 大幅减小了 T1时间而使锁相环快速进入 Τ2 Ρ介段。
当锁相环进行 Τ2 Ρ介段时， 控制器 301控制第一开关 401断开， DAC303 与宽带宽环路滤波器 305断开， 宽带宽环路滤波器 305停止电压预置。 到此， 锁相环在控制器 301的控制下实现了第一次锁定。第一开关 401从闭合到断开 的阶段，控制器 301控制第一环路选择开关 403和第二环路选择开关 404均与 宽带宽环路滤波器接通， 即在这个阶段， 小电容滤波器作为锁相环中的环路滤 波器。
当第一开关 401断开以后， 控制器 301控制 402闭合， 由宽带宽环路滤波 器 305经过运算放大器 304、 第一开关 402为窄带宽环路滤波器 306进行电压 预置直到窄带宽环路滤波器 306的预置压控电压也达到精确。
当窄带宽环路滤波器 306的预置压控电压达到精确后，控制器 301控制第 一环路选择开关 403和第二环路选择开关 404均与窄带宽环路滤波器 306接 通， 即， 由窄带宽环路滤波器 306作为锁相环中的环路滤波器， 从而实现预置 压控电压由宽带宽环路滤波器 305到窄带宽环路滤波器 306的平稳过渡，此时， 窄带宽环路滤波器 306已经进入 Tl Ρ介段。
当窄带宽环路滤波器 306进入 Τ2 Ρ介段时， 控制器 301控制第一开关 402 断开， 由鉴相器 Α为窄带宽环路滤波器 306稳定， 使窄带宽环路滤波器 306 进入 T3阶段。
最终由窄带宽环路滤波器 306作为窄带宽环路为锁相环提供预置压控电 压。
由于最终温度阶段使用窄带宽环路滤波器 306为窄带宽环路， 因此本发明 提供的电路不会恶化锁相环的相位噪声。
由于本发明提供的电路大幅地缩短了 T1的时间， 因此可以实现锁相环的 快速锁定， 因此， 应用于对讲机等无线通信设备中可以实现在 TDMA模式下 的全双工通信及跳频通信， 对于一直处于半双工通信的对讲机实现质的飞跃。
基于上述提供的一种锁相环快速锁定的电路，本发明还提供了一种锁相环 快速锁定的方法， 下面结合具体实施例来详细说明其工作流程。
参见图 5 , 该图为本发明提供的锁相环快速锁定的方法实施例一流程图。 本实施例提供的锁相环快速锁定的方法， 包括以下步骤：
S501 : 在第一预定时间段内，将预置压控电压同时给宽带宽环路滤波器和 窄带宽环路滤波器进行电压预置；
其中，宽带宽环路滤波器为宽带宽环路，窄带宽环路滤波器为窄带宽环路。
S502: 在第二预定时间段内，停止预置压控电压为宽带宽环路滤波器和窄 带宽环路滤波器进行电压预置，由宽带宽环路滤波器为窄带宽环路滤波器进行 电压预置；
由于宽带宽环路滤波器中的电^艮小， 因此电压预置很快， 当宽带宽环路 滤波器电压预置到输出的压控电压达到预置压控电压时停止用预置压控电压 为宽带宽环路滤波器和窄带宽环路滤波器电压预置，而由宽带宽环路滤波器为 窄带宽环路滤波器电压预置。
S503: 在第三预定时间段内， 宽带宽环路滤波器在鉴相器输出的压控电压 的控制下达到锁定后稳定的压控电压，由宽带宽环路滤波器继续为窄带环路滤 波器进行电压预置；
S504: 在第四预定时间段内，停止宽带宽环路滤波器为窄带宽环路滤波器 进行电压预置；窄带宽环路滤波器在鉴相器输出的压控电压的控制下达到所述 锁定后稳定的压控电压；
当窄带宽环路滤波器电压预置到输出的压控电压达到精确的压控电压时 停止为其进行电压预置， 由锁相环中的鉴相器控制窄带宽环路滤波器稳定。
其中， 在第一预定时间段内、 第二预定时间段和第三预定时间段内， 宽带 宽环路滤波器作为锁相环中的环路滤波器； 在第四预定时间段内， 窄带宽环路 滤波器作为锁相环中的环路滤波器。
由于开始时， 宽带宽环路滤波器电压预置很快， 因此以宽带宽环路滤波器 作为锁相环中的环路滤波器， 当窄带宽环路滤波器获得稳定的预置压控电压 后， 由窄带宽环路滤波器作为锁相环中的环路滤波器。 由于窄带宽环路滤波器 为窄带宽环路滤波器， 因此， 不会影响锁相环的相位噪声。
本发明提供的锁相环快速锁定的方法，设置宽带宽环路滤波器和窄带宽环 路滤波器两个环路， 开始时宽带宽环路滤波器作为锁相环中的环路滤波器，预 置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压预置，由于 宽带宽环路滤波器中的电^艮小， 因此电压预置速度很快。这样可以使锁相环 中的鉴相器中的频差快速减小到一个较小值， 该过程中频差越小， 捕获阶段
T1 所用的时间也越短。 当宽带宽环路滤波器电压预置稳定后， 由宽带宽环路 滤波器为窄带宽环路滤波器进行电压预置，从而窄带宽环路滤波器获得精确的 预置压控电压， 由窄带宽环路滤波器作为锁相环中的环路滤波器。 由于锁相环 最终稳定阶段使用的窄带宽环路滤波器， 窄带宽环路滤波器是窄带宽环路， 因 此不会恶化锁相环的相位噪声。 因此， 本发明利用宽带宽环路滤波器可以缩短 T1的时间， 利用窄带宽环路滤波器做最终的稳定不会影响相位噪声。
参见图 6, 该图为本发明提供的锁相环快速锁定的方法实施例二流程图。
S601: 从宽带宽环路滤波器中读取预置压控电压，转换为数字的预置压控 电压后存储于存储器中。
锁相环在出厂之前， 控制器控制 ADC读取预置压控电压并转换为数字的 预置压控电压后存储于存储器中。
S602:从存储器中读取数字的预置压控电压，将数字的预置压控电压转换 为模拟的预置压控电压； 可以通过 DAC将数字的预置压控电压转换为模拟的 预置压控电压。
S603: 在第一预定时间段内，将模拟的预置压控电压为宽带宽环路滤波器 进行电压预置；将模拟的预置压控电压通过运算放大器扩流后为窄带宽环路滤 波器进行电压预置。
在第一预定时间段内， 宽带宽环路滤波器作为锁相环中的环路滤波器。 S604: 在第二预定时间段内，停止预置压控电压为宽带宽环路滤波器和窄 带宽环路滤波器电压预置，由宽带宽环路滤波器为窄带宽环路滤波器进行电压 预置；
在第二预定时间段内， 宽带宽环路滤波器作为锁相环中的环路滤波器； S605: 在第三预定时间段内， 宽带宽环路滤波器在鉴相器输出的压控电压 的控制下达到锁定后稳定的压控电压，由宽带宽环路滤波器继续为窄带环路滤 波器进行电压预置；
S606: 在第五预定时间段内， 宽带宽环路滤波器为窄带宽环路滤波器进行 电压预置， 且窄带宽环路滤波器作为锁相环中的环路滤波器。
S607: 在第四预定时间段内，停止宽带宽环路滤波器为窄带宽环路滤波器 进行电压预置；窄带宽环路滤波器在鉴相器输出的压控电压的控制下达到所述 锁定后稳定的压控电压；
在第四预定时间段内， 窄带宽环路滤波器作为锁相环中的环路滤波器。 最终由窄带宽环路滤波器作为窄带宽环路为锁相环提供预置压控电压。 由于最终温度阶段使用窄带宽环路滤波器为窄带宽环路， 因此本发明提供 的电路不会恶化锁相环的相位噪声。
由于本发明提供的方法大幅地缩短了 T1的时间， 因此可以实现锁相环的 快速锁定， 因此， 应用于对讲机等无线通信设备中可以实现在 TDMA模式下 的全双工通信及跳频通信， 对于一直处于半双工通信的对讲机实现质的飞跃。
以上所述，仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的 限制。 虽然本发明已以较佳实施例揭露如上， 然而并非用以限定本发明。 任何 熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述 揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改 为等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本 于本发明技术方案保护的范围内。

Claims

权 利 要 求
1、 一种锁相环快速锁定的电路， 其特征在于， 包括： 控制器、 存储器、 数模转换器、 运算放大器、 宽带宽环路滤波器和窄带宽环路滤波器；
控制器， 用于将存储器中存储的预置压控电压发送给 DAC; 存储器中预 先存储与目标频率对应的数字信号的预置压控电压；
数模转换器，用于将所述数字信号的预置压控电压转换为模拟信号的预置 压控电压后发送给宽带宽环路滤波器， 对宽带宽环路滤波器进行电压预置； DAC还用于将所述模拟信号的预置压控电压通过运算放大器发送给窄带宽环 路滤波器， 对窄带宽环路滤波器进行电压预置； 此时， 控制器控制宽带宽环路 滤波器作为锁相环中的环路滤波器；
当宽带宽环路滤波器的输出电压达到所述预置压控电压后， 控制器控制
DAC与宽带宽环路滤波器断开， 同时控制 DAC与运算放大器断开； 宽带宽环 路滤波器通过运算放大器给窄带宽环路滤波器进行电压预置； 此时，控制器控 制宽带宽环路滤波器仍然作为锁相环中的环路滤波器；
当窄带宽环路滤波器获得宽带宽环路滤波器锁定后稳定的压控电压时，控 制器控制窄带宽环路滤波器作为锁相环中的环路滤波器。
2、 根据权利要求 1所述的锁相环快速锁定的电路， 其特征在于， 控制器 通过控制第一开关来控制数模转换器与宽带宽环路滤波器以及数模转换器与 运算放大器的连接状态；
第一开关的第一端连接数模转换器， 第二端连接运算放大器， 同时第二端 连接宽带宽环路滤波器， 第三端连接控制器。
3、 根据权利要求 1所述的锁相环快速锁定的电路， 其特征在于， 控制器 通过控制第二开关来控制运算放大器与窄带宽环路滤波器的连接状态；
第二开关的第一端连接运算放大器， 第二端连接窄带宽环路滤波器， 第三 端连接控制器。
4、 根据权利要求 1所述的锁相环快速锁定的电路， 其特征在于， 控制器 通过控制第一环路选择开关和第二环路选择开关来控制宽带宽环路滤波器和 窄带宽环路滤波器在锁相环中的连接状态；
第一环路选择开关的第一端连接锁相环中的鉴相器的输出端，第一环路选 o
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择开关的控制端连接控制器，第一环路选择开关的第二端连接宽带宽环路滤波 器， 第一环路选择开关的第三端连接窄带宽环路滤波器；
第二环路选择开关的第一端连接锁相环中的压控振荡器的输入端，第二环 路选择开关的控制端连接控制器，第二环路选择开关的第二端连接宽带宽环路 滤波器， 第二环路选择开关的第三端连接窄带宽环路滤波器。
5、 根据权利要求 1所述的锁相环快速锁定的电路， 其特征在于， 还包括 读取开关和模数转换器；
读取开关连接在控制器和窄带宽环路滤波器之间，模数转换器连接在预置 压控电压读取开关和控制器之间；
锁相环出厂前，控制器用于控制读取开关闭合，模数转换器从窄带宽环路 滤波器中读取预置压控电压， 转换为数字的预置压控电压后发送给控制器，控 制器将该数字的预置压控电压存储于存储器中。
6、 一种锁相环快速锁定的方法， 其特征在于， 包括：
在第一预定时间段内，将预置压控电压同时给宽带宽环路滤波器和窄带宽 环路滤波器进行电压预置；
在第二预定时间段内，停止预置压控电压为宽带宽环路滤波器和窄带宽环 路滤波器电压预置， 由宽带宽环路滤波器为窄带宽环路滤波器进行电压预置； 在第三预定时间段内，宽带宽环路滤波器在鉴相器输出的压控电压的控制 下达到锁定后稳定的压控电压，由宽带宽环路滤波器继续为窄带环路滤波器进 行电压预置；
在第四预定时间段内，停止宽带宽环路滤波器为窄带宽环路滤波器进行电 压预置；窄带宽环路滤波器在鉴相器输出的压控电压的控制下达到所述锁定后 稳定的压控电压；
在第一预定时间段内、第二预定时间段和第三预定时间段内， 宽带宽环路 滤波器作为锁相环中的环路滤波器； 在第四预定时间段内， 窄带宽环路滤波器 作为锁相环中的环路滤波器。
7、 根据权利要求 6所述的锁相环快速锁定的方法， 其特征在于， 包括： 将预置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压预置 之前还包括： 从存储器中读取数字的预置压控电压，将数字的预置压控电压转 o
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换为模拟的预置压控电压；
将预置压控电压同时给宽带宽环路滤波器和窄带宽环路滤波器进行电压 预置具体为：
将模拟的预置压控电压为宽带宽环路滤波器进行电压预置；将模拟的预置 压控电压通过运算放大器扩流后为窄带宽环路滤波器进行电压预置。
8、 根据权利要求 6所述的锁相环快速锁定的方法， 其特征在于， 在第三 预定时间段和第四预定时间段之间还包括第五预定时间段；
在第五预定时间段内，宽带宽环路滤波器为窄带宽环路滤波器进行电压预 置， 且窄带宽环路滤波器作为锁相环中的环路滤波器。
9、 根据权利要求 7所述的锁相环快速锁定的方法， 其特征在于， 所述从 存储器中读取数字的预置压控电压之前还包括：
从宽带宽环路滤波器中读取预置压控电压，转换为数字的预置压控电压后 存储于存储器中。
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