WO2012097606A1 - 一种场效应晶体管的制备方法 - Google Patents

一种场效应晶体管的制备方法 Download PDF

Info

Publication number
WO2012097606A1
WO2012097606A1 PCT/CN2011/080254 CN2011080254W WO2012097606A1 WO 2012097606 A1 WO2012097606 A1 WO 2012097606A1 CN 2011080254 W CN2011080254 W CN 2011080254W WO 2012097606 A1 WO2012097606 A1 WO 2012097606A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
effect transistor
field effect
source
substrate
Prior art date
Application number
PCT/CN2011/080254
Other languages
English (en)
French (fr)
Inventor
吴东平
朴颖华
朱志炜
张世理
张卫
Original Assignee
复旦大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 复旦大学 filed Critical 复旦大学
Priority to US13/390,328 priority Critical patent/US20130295732A1/en
Publication of WO2012097606A1 publication Critical patent/WO2012097606A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present invention relates to a method of fabricating a semiconductor, and more particularly to a method of fabricating a field effect transistor.
  • MOSFET gold-oxide-semiconductor field effect transistor
  • the channel length of MOSFETs is also continuously shortened.
  • serious short channel effects occur, such as: channel length reduction.
  • the proportion of the source and drain depletion regions in the entire channel increases, and the amount of charge required to form the inversion layer on the silicon surface under the gate decreases, so that the threshold voltage is reduced and the substrate is The charge of the depletion region along the laterally widened portion of the channel width increases the threshold voltage.
  • the threshold voltage increase becomes significant, which deteriorates the performance of the semiconductor chip. Not even working properly.
  • High dielectric constant medium such as cerium-based oxides
  • the gate tunneling current can be maintained at a relatively low level.
  • replacing the conventional silicon dioxide as a gate insulating layer with a high-k dielectric replacing the conventional polysilicon gate electrode with a metal gate electrode can eliminate the depletion effect of the polysilicon and further reduce the thickness of the effective gate insulating layer.
  • the gate electrode is further enhanced in control of the channel.
  • Ion implantation and millisecond thermal annealing processes such as laser thermal annealing and flash annealing.
  • the maximum temperature during annealing is generally at least 900 or even 1000 degrees Celsius.
  • the industry's latest generation of field-effect transistor technology uses both high-k gate dielectric/metal gate electrodes and millimeter-scale laser thermal annealing processes.
  • the conventional MOSFET device process technique uses a Gate-First process, that is, the gate insulating/gate electrode is formed before the impurity annealing of the source and drain regions is activated.
  • the high-k gate dielectric/metal gate electrode technology that is now mass-produced is typically fabricated using the sophisticated Damascene Gate-Last process.
  • the feature is that the high-k gate dielectric/metal gate electrode is formed after the impurity in the source and drain regions is activated, which eliminates the influence of high-temperature annealing, but the process is complicated, the cost is high, and it is limited by the opening ratio of the Damascus process opening.
  • the microfilming ability is worse than the conventional Gate-First process.
  • the present invention proposes an improved method of fabricating a field effect transistor to eliminate or ameliorate the above problems.
  • the technical problem to be solved by the present invention is to provide a process for preparing a field effect transistor which improves or eliminates the influence of source-drainage impurity annealing on the interface of a high-k gate dielectric and a silicon substrate and a high-k gate dielectric and a metal gate electrode.
  • the invention provides a method for preparing a field effect transistor, the method comprising the steps of: providing a first type body substrate, forming a shallow trench by photolithography and etching, and growing a shallow shallow trench in the shallow trench; Isolation structure
  • Microwave annealing is performed to activate the implanted ions.
  • the first type of body substrate may be silicon or silicon on insulator.
  • the high-k gate dielectric layer may be tantalum oxide, hafnium oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, or zirconium oxide, or a multilayer structure or mixture of the foregoing.
  • the metal gate electrode layer may be titanium nitride, tantalum nitride, metal silicide, metal tungsten, metal aluminum, metal tantalum, metal platinum, or a multilayer structure or mixture composed of the above materials and they are composed of polysilicon. Multi-layer structure.
  • the metal silicide is a compound of a metal such as nickel, titanium, cobalt or platinum and silicon.
  • the second type body impurity is an N type impurity, and the ion implantation is ion implantation with phosphorus or arsenic; when the first type body substrate is an N type, the second type The body is P-type, and the impurity ion implantation is ion implantation using boron, boron fluoride, or indium.
  • the first bulk impurity ion implantation is performed to form a halo region prior to forming the source-drain extension region to improve the short channel effect of the device.
  • the first bulk impurity ion implantation is performed after forming the source-drain extension region to form a halo region to improve the short channel effect of the device.
  • the first type impurity when the first type substrate is P type, the first type impurity is boron, boron fluoride, or indium; when the first type substrate is N type, the first type impurity is phosphorus or arsenic .
  • the annealing temperature is not higher than 400 degrees Celsius.
  • the present invention has the following advantages:
  • the process of the novel field effect transistor proposed by the present invention the high-k gate dielectric/metal gate electrode of the field effect transistor is performed before the impurity in the source and drain regions is activated, and the impurity Activated by microwave annealing technology, the impurities in the source and drain regions can be activated at a lower temperature, which can reduce the influence of source-drain annealing on the high-k gate dielectric/metal gate electrode.
  • FIG. 1 is a schematic diagram of a method of fabricating a field effect transistor of the present invention - a schematic diagram of forming a shallow trench isolation structure on a semiconductor substrate;
  • FIG. 2 is a schematic diagram of a method of fabricating a field effect transistor of the present invention - a schematic diagram of forming a gate stack structure;
  • FIG. 3 is a schematic diagram of a method of fabricating a field effect transistor of the present invention - a schematic diagram of forming a gate stack structure by photolithography and etching;
  • FIG. 4 is a step of a method for fabricating a field effect transistor of the present invention - ion implantation forms source-drain extension Schematic diagram of the area;
  • FIG. 5 is a schematic diagram of a method for fabricating a field effect transistor of the present invention - a schematic diagram of depositing an insulating layer and forming a sidewall spacer;
  • Fig. 6 is a schematic view showing the steps of the method for fabricating the field effect transistor of the present invention - ion implantation, impurity microwave annealing activation, and formation of source and drain regions.
  • the method for fabricating the field effect transistor of the present invention can be applied to an N-type transistor and a P-type transistor, and the difference between the two is that the substrate is interchanged with the source-drain region doping type, that is, the N-type transistor substrate is doped with P. Type impurity, the P-type transistor substrate is doped with an N-type impurity.
  • the method for fabricating the field effect transistor of the present invention includes the following steps:
  • ⁇ -type bulk silicon substrate 11 may be replaced by a silicon-on-insulator (SOI);
  • the high-k gate dielectric layer 31 may be hafnium oxide (Hf0 2 ), HbSiO, HfSiON, SiN, A1 2 O 3 , La 2 O 3 , ZrO 2 , or the like a multilayer structure or mixture
  • the metal gate electrode layer 41 may be titanium oxide (TiO), tantalum oxide (TaO), metal silicide, metal tungsten (W), aluminum (Al), ruthenium (Ru), platinum (Pt Or a multilayer structure or mixture of the above substances and a multilayer structure composed of the same; and the above metal silicide may be nickel (Ni:), titanium (Ti:), cobalt (Co), platinum (Pt). a compound of a metal and silicon;
  • N-type impurity ion implantation to form a source-drain extension region 111, wherein the impurity may be selected from phosphorus (N) or arsenic (As); in addition, P-type impurity ions may be selected before or after this step.
  • the impurity may be selected from phosphorus (N) or arsenic (As); in addition, P-type impurity ions may be selected before or after this step.
  • Injecting, boron (B), boron fluoride (BF 2 ), indium (In) can be used as an impurity to form a Halo region to improve the short channel effect of the device;
  • an insulating layer which may be selected from silicon oxide (Si0 2 ) or silicon nitride (SiN), by anisotropic dry etching, etc., forming a sidewall 51 close to the edge of the gate; (6) performing N-type impurity (phosphorus or arsenic) ion implantation to form a source-drain region of the N-type field effect transistor, forming a PN junction interface 111a between the source and drain regions and the silicon substrate;
  • Microwave annealing is performed to activate the implanted ions, and the annealing temperature does not exceed 400 degrees Celsius to reduce the influence on the high-k gate dielectric, the metal gate electrode, and the interface between them.
  • the structure of the basic metal oxide field effect transistor is formed, and subsequent processes such as forming a metal silicide in the source and drain regions and a subsequent interconnection process are conventional processes, and are not described herein.
  • the high-k gate dielectric/metal gate electrode of the field effect transistor is formed before the impurity in the source and drain regions is activated, and the impurity is activated by microwave annealing technology, which can be at a lower temperature.
  • the activation of impurities in the source and drain regions can reduce the influence of source-drain annealing on the high-k gate dielectric/metal gate electrode, thereby forming a process integration technique for field-effect transistors for future generations.
  • the embodiment provided by the present invention is an N-type field effect transistor as an example.
  • the same can be applied to a P-type field effect transistor.
  • the difference between the two is that the opposite type is provided according to different type of body substrate. Impurity ion implantation, therefore, the first type body and the second type body can be defined.
  • the first type body When the first type body is P type, it is a P type body substrate, and the second type body is formed, that is, N type impurity ion implantation, such as Phosphorus (N) or arsenic (As); when the first type is N-type, it is an N-type substrate, and a second type is formed, that is, P-type impurity ion implantation, such as boron (B), boron fluoride ( BF 2 ), indium (In), and the like.
  • N type impurity ion implantation such as Phosphorus (N) or arsenic (As)
  • N-type impurity ion implantation such as Phosphorus (N) or arsenic (As
  • P-type impurity ion implantation such as boron (B), boron fluoride ( BF 2 ), indium (In), and the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

一种场效应晶体管的制备方法
【技术领域】
本发明涉及一种半导体的制作方法， 尤其涉及一种场效应晶体管的制备 方法。
【背景技术】
随着半导体技术的发展， 金说属-氧化物-半导体场效应晶体管（MOSFET ) 已经得到了广泛的应用。 近年来， 以硅集成电路为核心的微电子技术得到了 迅速的发展， 集成电路芯片的发展基本上遵循摩尔定律， 即半导体芯片的集 成度以每 18个月翻一番的速度增长。 书
可是随着半导体芯片集成度的不断增加， MOSFET的沟道长度也在不断 的缩短， 当 MOSFET的沟道长度变得非常短时， 会产生严重的短沟道效应， 比如： 沟道长度减小到一定程度后， 源、 漏结的耗尽区在整个沟道中所占的 比重增大，栅下面的硅表面形成反型层所需的电荷量减小， 因而阈值电压减， 同时衬底内耗尽区沿沟道宽度侧向展宽部分的电荷使阈值电压增加， 当沟道 宽度减小到与耗尽层宽度同一量级时， 阈值电压增加变得十分显著， 会使半 导体芯片性能劣化， 甚至无法正常工作。
通过提高栅极对沟道的控制以及釆用更浅的源漏结可以达到对短沟道 效应更好的控制。 在过去的几十年中， MOSFET器件的源漏深度、 栅极氧化 层的厚度以及栅极长度基本上都是按比例缩小， 这样做的目的是为了控制短 沟道器件的性能。 通常减少栅极氧化层的有效厚度是提高栅极对沟道控制最 直接的方式。
目前， 对釆用高介电常数的介质（高 K介质）来作为栅极绝缘层的研究 已经进行了十几年。 高介电常数的介质， 比如铪基氧化物可以得到 1纳米以 下的有效栅氧厚度， 同时栅极隧穿电流可以保持一个比较低的水平。 除了用 高 K介质取代传统的二氧化硅做栅极绝缘层之外，用金属栅电极取代传统的 多晶硅栅电极可以消除多晶硅的耗尽效应， 进一步减小有效的栅极绝缘层的 厚度， 从而进一步增强栅电极对沟道的控制。
为了使源漏区和衬底之间的 PN结变的更浅， 人们一直在研究超低能量 的离子注入和毫秒级的热退火工艺， 比如激光热退火和闪光退火。 为了能够 对注入的杂质离子进行充分激活， 一般退火时的最高温度至少要达到 900甚 至 1000摄氏度以上。 目前， 工业界最新世代的场效应晶体管技术就同时釆 用了高 K栅介质 /金属栅电极和毫米级的激光热退火工艺。 常规的 MOSFET 器件的工艺技术釆用先栅 （Gate-First ) 工艺， 即， 栅绝缘层 /栅电极在源漏 区的杂质退火激活之前形成。但是由于高温热退火工艺对高 K栅介质和硅衬 底以及高 K栅介质和金属栅电极界面的影响，会造成有效的栅介质厚度增加 以及阈值电压漂移和不稳定。 因此， 现在已量产的高 K栅介质 /金属栅电极 技术一般釆用复杂的大马士革 （Damascene ) 式后栅 （Gate-Last ) 工艺。 其 特点是高 K栅介质 /金属栅电极在源漏区杂质激活之后形成， 消除了高温退 火带来的影响， 但是其工艺复杂、 成本高， 而且由于受到大马士革工艺开孔 填充比的限制导致其可缩微能力比常规的 Gate-First工艺差。
如何解决或减少源漏区杂质退火对高 K栅介质和硅衬底以及高 K栅介 质和金属栅电极界面的影响， 对未来世代的 MOSFET 工艺集成技术和器件 结构的发展都至关重要。
鉴于此， 本发明即提出一种改进的场效应管制备方法， 以消除或改善上 述问题。
【发明内容】
本发明要解决的技术问题在于提供一种改善或消除源漏区杂质退火对 高 K栅介质和硅衬底以及高 K栅介质和金属栅电极界面的影响的场效应晶体 管的制备工艺。
本发明通过这样的技术方案解决上述的技术问题：
本发明提供一种场效应晶体管的制备方法， 该方法包括如下步骤： 提供第一型体衬底， 利用光刻及刻蚀的方法形成浅槽， 并在浅槽内生长 形成二氧化硅浅槽隔离结构；
在衬底与浅槽隔离结构的上面进行淀积形成高 K栅介质层以及金属栅电 极层；
利用光刻及刻蚀等工艺形成栅极结构；
进行第二型体杂质离子注入， 形成源漏扩展区；
淀积绝缘层， 形成紧贴栅极边缘的侧墙；
进行第二型体杂质离子注入， 形成第二型体场效应晶体管的源漏区， 形 成源漏区和硅衬底之间的 PN结界面；
进行微波退火， 激活注入的离子。
可选的， 第一型体衬底可以为硅或绝缘体上的硅。
可选的， 所述高 K栅介质层可以为氧化铪、 氧化硅铪、 氮氧硅铪、 氮氧 硅、 氧化铝、 氧化镧、 或者氧化锆， 或者上述物质组成的多层结构或者混合 物。
可选的， 金属栅电极层可以为氮化钛、 氮化钽、 金属硅化物、 金属钨、 金属铝、 金属钌、 金属铂， 或者上述物质组成的多层结构或混合物以及它们 与多晶硅组成的多层结构。
可选的， 上述的金属硅化物是镍、 钛、 钴、 铂等金属与硅的化合物。 可选的， 第一型体衬底为 P型时， 第二型体杂质为 N型杂质， 离子注入 为用磷或砷进行离子注入； 第一型体衬底为 N型时， 第二型体为 P型， 杂质 离子注入为用硼、 氟化硼、 或铟进行离子注入。
可选的，在形成源漏扩展区之前进行第一型体杂质离子注入以形成晕圈 区以改进器件的短沟道效应。
可选的，在形成源漏扩展区之后进行第一型体杂质离子注入以形成晕圈 区以改进器件的短沟道效应。
可选的， 第一型体衬底为 P型时， 第一型体杂质为硼、 氟化硼、 或铟； 第一型体衬底为 N型时， 第一型体杂质为磷或者砷。
可选的， 退火温度不高于 400摄氏度。
与现有技术相比较， 本发明具有以下优点： 本发明提出的这种新的场效 应晶体管的工艺，场效应晶体管的高 K栅介质 /金属栅电极在源漏区的杂质激 活之前进行， 杂质激活釆用微波退火技术， 可以在较低的温度下对源漏区的 杂质进行激活， 可以减小源漏退火对高 K栅介质 /金属栅电极的影响。
【附图说明】
图 1为本发明场效应晶体管的制备方法的步骤-在半导体衬底上形成浅 槽隔离结构的示意图；
图 2为本发明场效应晶体管的制备方法的步骤-形成栅极叠层结构的示 意图；
图 3为本发明场效应晶体管的制备方法的步骤-利用光刻、 刻蚀形成栅极 叠层结构的示意图；
图 4为本发明场效应晶体管的制备方法的步骤-离子注入形成源漏扩展 区域的示意图；
图 5为本发明场效应晶体管的制备方法的步骤 -淀积绝缘层、 形成侧墙的 示意图；
图 6为本发明场效应晶体管的制备方法的步骤-离子注入、 杂质微波退火 激活、 形成源漏区的示意图。
【具体实施方式】
下面结合附图详细说明本发明的具体实施方式。
本发明的场效应晶体管的制备方法可应用于 N型晶体管与 P型晶体管， 两者之间的区别在于衬底与源漏区域掺杂的类型互换， 即， N型晶体管衬底 掺杂 P型杂质， P型晶体管衬底掺杂 N型杂质。
请参图 1-6, 以 N型场效应晶体管为例， 本发明的场效应晶体管的制备方 法， 包括如下步骤：
( 1 ) 提供 P型体硅衬底 11 , 利用光刻及刻蚀的方法形成浅槽， 并在浅 槽内生长形成二氧化硅， 形成浅槽隔离结构 21 ( Shallow Trench Isolation ) , 于该步骤中， Ρ型体硅衬底 11可以利用绝缘衬底上的 石 :(SOI , Silicon-on-Insulator)来替代；
( 2 ) 在衬底 11与浅槽隔离结构 21的上面进行淀积形成高 K栅介质层 31 以及金属栅电极层 41 , 其中， 高 K栅介质层 31可以为氧化铪 (Hf02)、 一氧化硅铪 (HfSiO)、 氮氧硅铪 (HfSiON)、 氮氧硅 (SiN)、 氧化铝 (A1203)、 氧化镧 (La203)、 氧化锆 (Zr02), 或者上述物质组 成的多层结构或者混合物； 金属栅电极层 41可以为氧化钛 (TiO)、 氧化钽 (TaO)、 金属硅化物、 金属钨 (W)、 铝 (Al)、 钌 (Ru)、 铂 (Pt), 或者上述物质组成的多层结构或混合物以及它们与多晶硅组成 的多层结构； 上述的金属硅化物可以是镍 (Ni：)、 钛 (Ti：)、 钴 (Co)、 铂 (Pt)等金属与硅的化合物；
( 3 ) 利用光刻及刻蚀等工艺形成栅极结构；
( 4 ) 进行 N型体杂质离子注入， 形成源漏扩展区 111 , 其中的杂质可选 用磷 (N)或砷 (As); 另外， 在此步骤之前或者之后， 可选择进行 P 型体杂质离子注入， 硼（B)、 氟化硼（BF2)、 铟（In)可作为选用的杂 质， 以形成 Halo (晕圈） 区以改进器件的短沟道效应；
( 5 ) 淀积绝缘层， 可选用氧化硅 (Si02)或者氮化硅 (SiN), 利用各向异 性干法刻蚀等方法， 形成紧贴栅极边缘的侧墙 51； ( 6 ) 进行 N型杂质（磷或者砷） 离子注入， 形成 N型场效应晶体管的源 漏区 , 形成源漏区和硅^ "底之间的 PN结界面 111a;
( 7 ) 进行微波退火， 激活注入的离子， 退火温度不超过 400摄氏度， 以减小对高 K栅介质、 金属栅电极以及它们之间的界面的影响。 经过上述步骤， 基本的金属氧化物场效应晶体管的结构就形成了， 后续 的工艺如在源漏区形成金属硅化物以及后道的互连工艺为常规工艺， 这里不 作赘述。
本发明提出的这种新的场效应晶体管的工艺， 场效应晶体管的高 K栅介 质 /金属栅电极在源漏区的杂质激活之前形成， 杂质激活釆用微波退火技术， 可以在较低的温度下对源漏区的杂质进行激活， 可以减小源漏退火对高 K栅 介质 /金属栅电极的影响，从而可以形成用于未来世代的场效应晶体管的工艺 集成技术。
本发明提供的实施方式， 是以 N型场效应晶体管为例， 实际上， 可以同 样应用于 P型场效应晶体管， 两者不同之处， 仅在于根据不同的型体衬底， 提供相反型体的杂质离子注入， 因此， 可定义第一型体与第二型体， 第一型 体为 P型时， 即为 P型体衬底， 进行第二型体， 即 N型杂质离子注入， 如磷 (N) 或砷 (As); 第一型体为 N型时， 即为 N型体衬底， 进行第二型体， 即 P型杂质 离子注入， 如硼（B)、 氟化硼（BF2)、 铟（In)等。
以上所述仅为本发明的较佳实施方式，本发明的保护范围并不以上述实 施方式为限，但凡本领域普通技术人员根据本发明所揭示内容所作的等效修 饰或变化， 皆应纳入权利要求书中记载的保护范围内。

Claims

权 利 要 求 书
1、 一种场效应晶体管的制备方法， 其特征在于， 该方法包括如下步 骤：
提供第一型体衬底， 利用光刻及刻蚀的方法形成浅槽， 并在浅槽内生 长形成二氧化硅浅槽隔离结构；
在衬底与浅槽隔离结构上淀积形成高 K栅介质层以及金属栅电极层； 利用光刻及刻蚀等工艺形成栅极结构；
进行第二型体杂质离子注入， 形成源漏扩展区；
淀积绝缘层， 形成紧贴栅极边缘的侧墙；
进行第二型体杂质离子注入， 形成第二型体场效应晶体管的源漏区， 形成源漏区和硅衬底之间的 PN结界面；
进行微波退火， 激活注入的离子。
2、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 第一型体衬底可以为硅或绝缘体上的硅。
3、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 所述高 K栅介质层可以为为氧化铪、 氧化硅铪、 氮氧硅铪、 氮氧硅、 氧化铝、 氧化镧、 或者氧化锆， 或者上述物质组成的多层结构或者混合物。
4、 根据权利要求 3所述的场效应晶体管的制备方法， 其特征在于： 金属栅电极层为氮化钛、 氮化钽、 金属钨、 金属铝、 金属钌、 金属铂、 金属 硅化物， 或者上述物质组成的多层结构或混合物以及它们与多晶硅组成的多 层结构。
5、 根据权利要求 4所述的场效应晶体管的制备方法， 其特征在于： 上述的金属硅化物是镍、 钴、 钛、 铂等金属与硅的化合物。
6、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 第一型体衬底为 P型时， 第二型体杂质为 N型杂质， 离子注入为用磷或砷进行 离子注入； 第一型体衬底为 N型时， 第二型体杂质为 P型杂质， 离子注入为用 硼、 氟化硼、 或铟进行离子注入。
7、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 在形成源漏扩展区之前进行第一型体杂质离子注入以形成晕圈区以改进器 件的短沟道效应。
8、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 在形成源漏扩展区之后进行第一型体杂质离子注入以形成晕圈区以改进器
1 件的短沟道效应。
9、 根据权利要求 7或 8所述的场效应晶体管的制备方法， 其特征在 于： 第一型体衬底为 P型时， 第一型体杂质为硼、 氟化硼、 或铟； 第一型体 衬底为 N型时， 第一型体杂质为磷或者砷。
10、 根据权利要求 1所述的场效应晶体管的制备方法， 其特征在于： 退火温度不高于 400摄氏度。
11、 一种场效应晶体管的制备方法， 其特征在于， 该方法包括如下步 骤：
提供衬底；
在衬底上淀积形成高 K栅介质层以及金属栅电极层；
杂质离子注入， 形成源漏区；
在衬底上淀积形成高 K栅介质层、金属栅电极层和源漏区杂质离子注入 之后， 进行微波退火， 激活源漏区注入的杂质离子。
2
PCT/CN2011/080254 2011-01-17 2011-09-28 一种场效应晶体管的制备方法 WO2012097606A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/390,328 US20130295732A1 (en) 2011-01-17 2011-09-28 Method for making field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2011100095239A CN102104006A (zh) 2011-01-17 2011-01-17 一种场效应晶体管的制备方法
CN201110009523.9 2011-01-17

Publications (1)

Publication Number Publication Date
WO2012097606A1 true WO2012097606A1 (zh) 2012-07-26

Family

ID=44156674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/080254 WO2012097606A1 (zh) 2011-01-17 2011-09-28 一种场效应晶体管的制备方法

Country Status (3)

Country Link
US (1) US20130295732A1 (zh)
CN (1) CN102104006A (zh)
WO (1) WO2012097606A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200000093A (ko) * 2018-06-22 2020-01-02 삼성전자주식회사 반도체 소자 및 그의 제조 방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104006A (zh) * 2011-01-17 2011-06-22 复旦大学 一种场效应晶体管的制备方法
US20140094023A1 (en) * 2012-09-28 2014-04-03 National Applied Research Laboratories Fabricating method of semiconductor chip
CN103839812A (zh) * 2012-11-21 2014-06-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
CN103000579B (zh) * 2012-12-14 2016-12-21 复旦大学 一种半导体器件及其制备方法
CN104241288A (zh) * 2014-09-16 2014-12-24 复旦大学 多层场效应晶体管及其制造方法
CN104392930A (zh) * 2014-11-26 2015-03-04 上海华力微电子有限公司 嵌入式锗硅器件的制作方法
CN112424917B (zh) 2018-06-06 2022-08-19 港大科桥有限公司 金属氧化物半导体场效应晶体管及其制造方法
US11398551B2 (en) * 2019-05-07 2022-07-26 United States Of America As Represented By The Secretary Of The Air Force Self-aligned gate and drift design for high-critical field strength semiconductor power transistors with ion implantation
US11264274B2 (en) * 2019-09-27 2022-03-01 Tokyo Electron Limited Reverse contact and silicide process for three-dimensional logic devices
US20210335607A1 (en) * 2020-04-22 2021-10-28 X-FAB Texas, Inc. Method for manufacturing a silicon carbide device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1575507A (zh) * 2001-10-25 2005-02-02 先进微装置公司 低温的掺杂后活化工艺
CN101207130A (zh) * 2006-12-19 2008-06-25 国际商业机器公司 集成电路
CN101483191A (zh) * 2008-01-07 2009-07-15 国际商业机器公司 半导体结构及其形成方法
CN101630642A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 Nmos晶体管的制作方法
CN102104006A (zh) * 2011-01-17 2011-06-22 复旦大学 一种场效应晶体管的制备方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808020B2 (en) * 2007-10-09 2010-10-05 International Business Machines Corporation Self-assembled sidewall spacer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1575507A (zh) * 2001-10-25 2005-02-02 先进微装置公司 低温的掺杂后活化工艺
CN101207130A (zh) * 2006-12-19 2008-06-25 国际商业机器公司 集成电路
CN101483191A (zh) * 2008-01-07 2009-07-15 国际商业机器公司 半导体结构及其形成方法
CN101630642A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 Nmos晶体管的制作方法
CN102104006A (zh) * 2011-01-17 2011-06-22 复旦大学 一种场效应晶体管的制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200000093A (ko) * 2018-06-22 2020-01-02 삼성전자주식회사 반도체 소자 및 그의 제조 방법
KR102550651B1 (ko) 2018-06-22 2023-07-05 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US11881508B2 (en) 2018-06-22 2024-01-23 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device

Also Published As

Publication number Publication date
US20130295732A1 (en) 2013-11-07
CN102104006A (zh) 2011-06-22

Similar Documents

Publication Publication Date Title
WO2012097606A1 (zh) 一种场效应晶体管的制备方法
CN102893375B (zh) 高k金属栅极叠层
US9281390B2 (en) Structure and method for forming programmable high-K/metal gate memory device
US8405160B2 (en) Multi-strained source/drain structures
US9018709B2 (en) Semiconductor device
CN103928327B (zh) 鳍式场效应晶体管及其形成方法
US9059315B2 (en) Concurrently forming nFET and pFET gate dielectric layers
US20110303951A1 (en) Semiconductor device and method of fabricating the same
US7759748B2 (en) Semiconductor device with reduced diffusion of workfunction modulating element
US20150295067A1 (en) Method for manufacturing p-type mosfet
JP2002184973A (ja) 半導体装置及びその製造方法
WO2014082338A1 (zh) 半导体器件的制造方法
TW201240090A (en) Field-effect transistor and method of manufacturing the same
TWI633670B (zh) 功率金屬氧化物半導體場效電晶體及用於製造其之方法
US9029225B2 (en) Method for manufacturing N-type MOSFET
US20060255405A1 (en) Fully-depleted SOI MOSFET device and process for fabricating the same
WO2013159416A1 (zh) 一种半导体结构及其制造方法
WO2014082339A1 (zh) N型mosfet的制造方法
WO2014082331A1 (zh) P型mosfet的制造方法
JP2004247341A (ja) 半導体装置
US8729639B2 (en) Semiconductor device and method for producing the same
US20220199460A1 (en) Method for forming semiconductor structure
US9653550B2 (en) MOSFET structure and manufacturing method thereof
US8872285B2 (en) Metal gate structure for semiconductor devices
TWI397181B (zh) 半導體元件及其製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13390328

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11856332

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11856332

Country of ref document: EP

Kind code of ref document: A1