WO2012096774A1 - Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices - Google Patents

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices Download PDF

Info

Publication number
WO2012096774A1
WO2012096774A1 PCT/US2011/066734 US2011066734W WO2012096774A1 WO 2012096774 A1 WO2012096774 A1 WO 2012096774A1 US 2011066734 W US2011066734 W US 2011066734W WO 2012096774 A1 WO2012096774 A1 WO 2012096774A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrical conductor
substrate
lcp
layer stack
interconnect layer
Prior art date
Application number
PCT/US2011/066734
Other languages
French (fr)
Inventor
Michael Weatherspoon
David Nicol
Louis Joseph Rendek, Jr.
Original Assignee
Harris Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corporation filed Critical Harris Corporation
Priority to KR1020137018792A priority Critical patent/KR101494988B1/en
Priority to EP11815828.6A priority patent/EP2664224A1/en
Priority to CN201180064598.5A priority patent/CN103314649B/en
Publication of WO2012096774A1 publication Critical patent/WO2012096774A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1511—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49224—Contact or terminal manufacturing with coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • the present invention relates to the field of electronic device fabrication and, more particularly, to methods of forming portions of electronic devices on sacrificial substrates and electrically joining them to circuitized thin flexible organic substrates.
  • LCP liquid crystal polymer
  • a method of making an electronic device including forming an interconnect layer stack on a sacrificial substrate comprising a plurality of alternating patterned electrically conducting and dielectric layers.
  • the method also includes laminating and electrically joining a circuitized liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate, and removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer.
  • the method further includes electrically coupling at least one first device to the lowermost patterned electrical conductor layer. This method advantageously allows the formation of an electronic device on an interconnect layer stack that would be difficult to form on a circuitized LCP substrate.
  • Laminating the LCP substrate and the interconnect layer stack together may comprise applying heat and pressure to the LCP substrate and the interconnect layer stack.
  • the heat and pressure may be applied in an autoclave.
  • Forming the interconnect layer stack may be performed by forming the plurality of patterned electrical conductor layers by thin film deposition.
  • the LCP substrate may be relatively thin, that is, it may have a thickness of less than 0.0025 inches.
  • the at least one first device may include a first integrated circuit (IC) die in a flip chip arrangement.
  • At least one electrical conductor via may be formed in the LCP substrate.
  • At least one second device may be connected to the LCP substrate, and the at least one second device may be electrically coupled to the uppermost patterned electrical conductor layer using the at least one electrical conductor via.
  • the sacrificial substrate may be glass or any atomically smooth material.
  • the LCP substrate may have at least one electrical conductor via therein, and the method may also include forming an other interconnect layer stack on an other sacrificial substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers.
  • the other interconnect layer stack may be laminated and electrically joined to the LCP substrate on a side thereof opposite the other sacrificial substrate.
  • the other sacrificial substrate may be removed to expose a lowermost patterned electrical conductor layer.
  • the method may further include electrically coupling at least one other device to the lowermost patterned electrical conductor layer, and electrically coupling the interconnect layer stack and the other interconnect layer stack together.
  • the LCP substrate may have an area greater than an area of the sacrificial substrate, and at least one other LCP substrate having an aperture therein aligned with the at least one first device may be laminated to the LCP substrate.
  • At least one electrical conductor via may be formed in the at least one additional LCP substrate.
  • An other interconnect layer stack may be formed on an other sacrificial substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers.
  • the other interconnect layer stack may be laminated and electrically joined to an other LCP substrate on a side thereof opposite the other sacrificial substrate, and the other sacrificial substrate may be removed to expose a lowermost patterned electrical conductor layer.
  • the LCP substrate may comprise at least one conductor via in each of a plurality of LCP layers, and which may comprise aligning, laminating, and electrically joining the LCP substrate to the interconnect layer stack. Remaining LCP layers of the plurality thereof may be laminated to the LCP layer that was laminated to the interconnect stack. At least one second device may be electrically coupled to the uppermost patterned electrical conductor layer using the at least one electrical conductor via of each of the plurality of LCP layers.
  • a device aspect is directed to an electronic device comprising a liquid crystal polymer (LCP) substrate.
  • LCP liquid crystal polymer
  • There is a an interconnect layer stack on the LCP substrate comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, the dielectric layer comprising a material different than LCP.
  • At least one first device is electrically coupled to a lowermost patterned electrical conductor layer.
  • FIG. 1 is a flowchart of a method of making an electronic device according to the present invention.
  • FIGS. 2A-2D are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 1
  • FIG. 3 is a flowchart of another embodiment of a method of making an electronic device according to the present invention.
  • FIGS. 4A-4E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 3.
  • FIG. 5 is a flowchart of a further embodiment of a method of making an electronic device according to the present invention.
  • FIG. 7 is a flowchart of a yet another embodiment of a method of making an electronic device according to the present invention.
  • FIGS. 8A-8E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 7.
  • the interconnect layer stack 14 may be thinner than 0.0004 inches, for example, with patterned electrical conductor layers 16 as small as (or even smaller than) 0.00004 inches, and dielectric layers 17 as small as (or smaller than) 0.00016 inches.
  • the sacrificial substrate 12 is preferably glass, although other materials with a sufficiently smooth surface may also be used.
  • the interconnect layer stack 14, and therefore the plurality of patterned electrical conductor layers 16, may be formed by semiconductor thin film deposition processes.
  • a liquid crystal polymer (LCP) substrate 18 is laminated to the interconnect layer stack 14 on a side thereof opposite the sacrificial substrate 12 (at Block 53).
  • the LCP substrate 18 may have a thickness of less than 0.0025 inches, for example.
  • This lamination is performed via the application of heat and pressure to the LCP substrate 18 and the interconnect layer stack 14, such as in an autoclave.
  • An autoclave advantageously provides isostatic pressure (i.e., equal pressure from all directions), and helps to keep the LCP from deforming during the lamination process. While the use of an autoclave for lamination is preferred, a press (possibly in an inert atmosphere) may also be used to perform the lamination.
  • the lamination is preferably performed at approximately 260°C and lOOpsi.
  • LCP is a particularly advantageous material from which to form printed circuit boards for a variety of reasons, including the fact that it has a high tensile strength, providing a high resistance to abrasion and damage. Typically, LCP also has a high mechanical strength at high temperatures, high chemical resistance, inherent flame retardancy, and good weatherability. In addition, LCP is relatively inert. LCP resists stress cracking in the presence of most chemicals at elevated temperatures, including aromatic or halogenated hydrocarbons, strong acids, bases, ketones, and other aggressive industrial substances. Those skilled in the art should understand that there are a variety of LCPs that may be used in the production of electronic devices according to the present invention. The use of LCP as the substrate 18 advantageously allows the lamination without an adhesive layer, thereby reducing the overall thickness of the resulting electronic device 10.
  • the sacrificial substrate 12 is removed, thereby exposing a lowermost patterned electrical conductor layer 16 (Block 54).
  • This sacrificial substrate 12 removal is performed by dissolution in hydrofluoric acid, mechanical polishing, or a combination of chemical mechanical polishing, for example.
  • At least one first device 20 is coupled to the lowermost patterned electrical conductor layer 16 (Block 55), as shown in FIG. 2D.
  • This device 20 may be an integrated circuit (IC) die, and may be coupled in a flip chip arrangement, as will be appreciated by those skilled in the art.
  • Block 56 indicates the end of the method.
  • the method therefore results in an electronic device 10 comprising an LCP substrate 18 with an interconnect layer stack 14 formed thereon.
  • the interconnect layer stack 14 comprises a plurality of patterned electrical conductor layers 16, with dielectric layers 17 between adjacent patterned electrical conductor layers.
  • Three integrated circuit dies 20 are coupled to the lowermost patterned electrical conductor layer 16 in a flip chip arrangement. It should be appreciated that there may instead be any number of devices 20, and that they need not be integrated circuit dies.
  • flowchart 150 of FIG. 3 and FIGS. 4A-4E a further embodiment of the method of making an electronic device 110 according to the present invention is now described. It should be understood that steps in this method are performed similar to those in the flowchart 50 of FIG. 1, and that detailed descriptions of those steps are therefore not necessary.
  • an interconnect layer stack 114 is formed on a sacrificial substrate 112 using thin film deposition (at Block 152).
  • the interconnect layer stack 114 comprises a plurality of patterned electrical conductor layers 116, and a dielectric layer 117 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 117 such that pads of the uppermost patterned electrical conductor layer 116 are exposed by the apertures.
  • At least one electrical conductor via 122 is formed in an LCP substrate 118 (Block 153), as shown in FIG. 4B.
  • the electrical conductor vias 122 are formed by mechanical or laser drilling the LCP substrate 118, then selectively depositing copper in the resulting holes. Tin is then deposited on a lowermost layer of the electrical conductor vias 122.
  • the LCP substrate 118 and the interconnect layer stack 114 may be aligned. Alignment is defined as having the electrical conductive vias 122 centered in the pads of the uppermost patterned electrical conductor layer 116. This alignment may be performed by first using a fixture or guide to roughly align the LCP substrate 118 and the interconnect layer stack 114, and then finely adjusting the alignment under a microscope to reach the final alignment. This advantageously allows a positional accuracy of alignment in the range of 0.0005 inches to 0.001 inches.
  • the LCP substrate 118 is then laminated and electrically joined to the interconnect layer stack 114 on a side thereof opposite the sacrificial substrate 112 (Block 154), as shown in FIG. 4C.
  • the temperature reaches a suitable level, such as 260°C, which is the melting point of tin, and at which point the copper and tin diffuse and react to form an intermetallic compound, such as Cu 3 Sn.
  • This intermetallic compound which is responsible for establishing electrical connection between the LCP substrate and the interconnect layer stack, is thermally stable up to its melting point of at least 600°C.
  • the temperature required for successful lamination and intermetallic compound formation fall within the same range.
  • an electronic device 110 comprising a LCP substrate 118 with a plurality of conductor vias 122 formed therein.
  • An interconnect layer stack 114 is formed on the LCP substrate 118.
  • the interconnect layer stack 114 comprises a plurality of patterned electrical conductor layers 116, with dielectric layers 117 between adjacent patterned electrical conductor layers. There is a fused seam between the interconnect layer stack 114 and the LCP substrate 118.
  • Three integrated circuit dies 120 are coupled to the lowermost patterned electrical conductor layer 116 in a flip chip arrangement.
  • a radiofrequency device 124 is electrically coupled to the uppermost patterned electrical conductor layer 116 and electrically coupled to the integrated circuit dies 120 via the electrical conductor vias 122.
  • an interconnect layer stack 214 is formed on a sacrificial substrate 212 using thin film deposition (at Block 252).
  • the interconnect layer stack 214 comprises a plurality of patterned electrical conductor layers 216, and a dielectric layer 217 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 217 such that pads of the uppermost patterned electrical conductor layer 216 are exposed by the apertures.
  • At least one electrical conductor via 222 is formed in a LCP substrate 218 (Block 253), as shown in FIG. 5B.
  • the LCP substrate 218 is laminated and electrically joined through an intermetallic bond to the interconnect layer stack 214 on a side thereof opposite the sacrificial substrate 212 (Block 254), as shown in FIG. 6C.
  • An other interconnect layer stack 234 is formed on an other sacrificial substrate 232 (Block 255), as shown in FIG. 6C.
  • This other interconnect layer stack 234 likewise comprises a plurality of patterned electrical conductor layers 236 and a dielectric layer 237 between adjacent patterned electrical conductor layers.
  • This other interconnect layer stack 235 is then laminated and electrically coupled to the LCP substrate 218 on a side thereof opposite the interconnect layer stack 214 (Block 256), thereby electrically coupling the interconnect layer stack and the other interconnect layer stack together.
  • Both sacrificial substrates 212, 232 are then removed to expose the lowermost patterned electrical conductor layers 216, 236 of the interconnect layer stack 214 and interconnect layer stack 234, respectively (Block 257), as shown in FIG. 6D.
  • At least one first device 220 is electrically coupled to the lowermost patterned electrical conductor layer 216 of the interconnect layer stack 214 (Block 258), as shown in FIG. 6E.
  • At least one other device 250 is then electrically coupled to the uppermost patterned electrical conductor layer 236 of the interconnect layer stack 234 (Block 259).
  • an electronic device 210 comprising an LCP substrate 218 with a plurality of conductor vias 222 formed therein, as shown in FIG. 6E.
  • An interconnect layer stack 214 and an other interconnect layer stack 234 are formed on opposing sides of the LCP substrate 218.
  • the interconnect layer stacks 214, 234 each comprise a plurality of patterned electrical conductor layers 216, 236 with dielectric layers 217, 237 between adjacent patterned electrical conductor layers. There is a fused seam between each interconnect layer stack 214, 234 and the LCP substrate 218.
  • An integrated circuit die 220 is coupled to the lowermost patterned electrical conductor layer 216 in a flip chip arrangement.
  • a pair of integrated circuit dies 250 are electrically coupled to the uppermost patterned electrical conductor layer 236 and electrically coupled to the integrated circuit die 220 via the electrical conductor vias 222.
  • an interconnect layer stack 314 is formed on a sacrificial substrate 312 using thin film deposition (at Block 352).
  • the interconnect layer stack 314 comprises a plurality of patterned electrical conductor layers 316, and a dielectric layer 317 between adjacent patterned electrical conductor layers. The uppermost patterned electrical conductor layer 316 is exposed.
  • the sacrificial substrate 312 is removed to expose a lowermost patterned electrical conductor layer 316 (Block 355). At least one first device 320 is electrically coupled to the lowermost patterned electrical conductor layer 316 (Block 355)
  • At least one electrical conductor via 326 is formed in at least one additional LCP substrate 328, illustratively three additional LCP substrates (Block
  • the additional LCP substrates 328 have an aperture therein aligned with the device 320 which is formed by laser milling or mechanical punching.
  • the additional LCP substrates 328 are laminated to the LCP substrate 318 (Block 358), preferably at 270°C and at 200psi, although other temperatures and pressures may be used.
  • An other interconnect layer stack 334 is formed on another sacrificial substrate 350.
  • This other interconnect layer stack 334 also comprises a plurality of patterned electrical conductor layers 336 and a dielectric layer 337 between adjacent patterned electrical conductor layers (Block 359).
  • the other interconnect layer stack 334 is then laminated to and intermetallically bonded with an other LCP substrate 338 (Block 360), which has had a circuit layer 344 formed thereon.
  • the sacrificial substrate is then removed to expose the lowermost patterned electrical conductor layer 336 (Block 361).
  • Three additional LCP substrate layers 328 are laminated to the LCP substrate 318 on a same side as the interconnect layer stack 314 and have apertures defined therein that are aligned with the integrated circuit die 320.
  • the LCP substrate layers 328 have electrical conductor vias 326 formed therein. There is a fused seam between each of the three additional LCP substrate layers 328, and between the topmost additional LCP substrate layer and the LCP substrate 318.
  • an interconnect layer stack 414 is formed on a sacrificial substrate 412 using thin film deposition (at Block 452).
  • the interconnect layer stack 414 comprises a plurality of patterned electrical conductor layers 416, and a dielectric layer 417 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 417 such that pads of the uppermost patterned electrical conductor layer 416 are exposed by the apertures.
  • a layer 418 of the LCP substrate is laminated to the interconnect layer stack 414 on a side thereof opposite the sacrificial substrate 412 (Block 454), as shown in FIG. IOC. This bonding process also serves to intermetallically bond the vias 422 with the patterned electrical conductor layers 416. Before lamination, the LCP substrate 418 and the interconnect layer stack 414 may be aligned. Remaining LCP layers 418 are then laminated to the LCP layer that was laminated to the interconnect layer stack 414 (Block 455).
  • the sacrificial substrate 412 is then removed to expose a lowermost patterned electrical conductor layer 416 (Block 456), as shown in FIG. 10D.
  • At least one first device 420 illustratively a trio of integrated circuit dies, is electrically coupled to the lowermost patterned electrical conductor layer 416 (Block 457), as shown in FIG. 10E.
  • At least one second device 429 illustratively a RF device, is electrically coupled to the conductor vias 422 of the LCP substrate 418, and resides on a side of the LCP substrate 418 opposite the interconnect layer stack 414 (Block 458).
  • Block 459 indicates the end of the method.
  • an electronic device 410 comprising a LCP substrate 418 with a plurality of conductor vias 422 formed therein.
  • the LCP substrate 418 comprises a pair of LCP layers.
  • An interconnect layer stack 414 is formed on the LCP substrate 418.
  • the interconnect layer stack 414 comprises a plurality of patterned electrical conductor layers 416, with dielectric layers 417 between adjacent patterned electrical conductor layers. There is a fused seam between the interconnect layer stack 414 and the LCP substrate 418, and between the LCP layers.
  • a radio frequency device 429 is coupled to a side of the LCP substrate 418 opposite the interconnect layer stack 414, and is electrically coupled to the uppermost patterned electrical conductor layer 416 and the integrated circuit dies 420 via the electrical conductor vias 422. There is also a fused seam between the LCP substrate 418 and the second device 429.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Description

METHOD OF TRANSFERRING AND ELECTRICALLY JOINING A HIGH DENSITY MULTILEVEL THIN FILM TO A CIRCUITIZED AND FLEXIBLE ORGANIC SUBSTRATE AND ASSOCIATED DEVICES The present invention relates to the field of electronic device fabrication and, more particularly, to methods of forming portions of electronic devices on sacrificial substrates and electrically joining them to circuitized thin flexible organic substrates.
As semiconductor and integrated circuit technology has advanced, there has been a trend toward high- functionality integrated circuit components with numerous input and output (I/O) pads, together with a demand for reduced chip size, weight, and power consumption. Consequently, as integrated circuits get smaller, they increasingly have smaller I/O pads arranged more closely together than ever before.
To match these high functionality integrated circuits, there is a demand for printed wiring boards having closely arranged pads for integrated circuit component attachment. To date, the ability to fabricate substrates with sufficiently fine pitch component attach pads has not been able to keep up with miniaturization in integrated circuit components. Consequently, there is an interconnection technology gap for some modern devices.
To make such devices function, printed wiring boards may have extra routing layers to handle the pads of the integrated circuits, or utilize fan-out packaging. This results in the package size of an integrated circuit being larger than the integrated circuit itself, which may limit system miniaturization. In addition to these desires for miniaturized devices, it is also desirable in some cases to construct these devices from a flexible, and not rigid, substrate.
One material now being used as a substrate from which to construct thin and flexible printed wiring boards is biaxially-oriented liquid crystal polymer (LCP). The molecules in LCPs have rigid, rod-like shapes, and maintain a crystalline order when in a liquid phase or when heated and melted. The Processing and
Assembly of Liquid Crystalline Polymer Printed Circuits, T. Zhang, W. Johnson, B. Farrell, and M. St. Lawrence, "The processing and assembly of liquid crystalline polymer printed circuits," 2002 Int. Symp. on Microelectronics, 2002. discusses the construction of a printed circuit board using LCP as a substrate. A photoresist is first applied to a copper clad laminate, exposed, and developed to define a desired circuit pattern. The actual circuit is defined by etch removal of any exposed copper. Holes or vias are created in the substrate via mechanical or laser drilling. A desmearing step is performed to remove debris from the vias or holes, thereby preparing the LCP material for metal deposition. A metalization step is next performed, and a conventional solder mask is applied to the LCP substrate. Solder is then applied through the conventional solder mask to complete the construction of the LCP printed circuit board.
While this design does allow for the creation of thin, flexible printed circuit boards, it still suffers from the same drawbacks as described above with respect to the attachment of integrated circuits with closely spaced pads.
Traditional semiconductor processing techniques allow for fabrication of rigid, wafer substrates that would support the levels of component attached referenced above. In this process, metals are deposited from the vapor phase into very thin films and are lithographically patterned and etched similar to that described for printed circuit boards. Dielectric layers are formed between metal layers through a spun on or vapor phase deposition process. While allowing for attachment of fine pitch components, this approach lacks the ability to achieve flexible circuits due to the rigid wafer substrate requirement for semiconductor processing. As such, additional methods of connecting integrated circuits to flexible printed circuit boards are needed.
In view of the foregoing background, it is therefore an object of the present invention to provide a method of transferring and electrically joining a high density multilevel thin film fabricated on a sacrificial rigid wafer substrate to a flexible, circuitized liquid crystal polymer substrate.
This and other objects, features, and advantages in accordance with the present invention are provided by a method of making an electronic device including forming an interconnect layer stack on a sacrificial substrate comprising a plurality of alternating patterned electrically conducting and dielectric layers. The method also includes laminating and electrically joining a circuitized liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate, and removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer. The method further includes electrically coupling at least one first device to the lowermost patterned electrical conductor layer. This method advantageously allows the formation of an electronic device on an interconnect layer stack that would be difficult to form on a circuitized LCP substrate.
Laminating the LCP substrate and the interconnect layer stack together may comprise applying heat and pressure to the LCP substrate and the interconnect layer stack. The heat and pressure may be applied in an autoclave.
Forming the interconnect layer stack may be performed by forming the plurality of patterned electrical conductor layers by thin film deposition. In addition, The LCP substrate may be relatively thin, that is, it may have a thickness of less than 0.0025 inches. Further, the at least one first device may include a first integrated circuit (IC) die in a flip chip arrangement.
At least one electrical conductor via may be formed in the LCP substrate. At least one second device may be connected to the LCP substrate, and the at least one second device may be electrically coupled to the uppermost patterned electrical conductor layer using the at least one electrical conductor via.
The sacrificial substrate may be glass or any atomically smooth material. The LCP substrate may have at least one electrical conductor via therein, and the method may also include forming an other interconnect layer stack on an other sacrificial substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The other interconnect layer stack may be laminated and electrically joined to the LCP substrate on a side thereof opposite the other sacrificial substrate.
The other sacrificial substrate may be removed to expose a lowermost patterned electrical conductor layer. The method may further include electrically coupling at least one other device to the lowermost patterned electrical conductor layer, and electrically coupling the interconnect layer stack and the other interconnect layer stack together.
In some applications, the LCP substrate may have an area greater than an area of the sacrificial substrate, and at least one other LCP substrate having an aperture therein aligned with the at least one first device may be laminated to the LCP substrate.
At least one electrical conductor via may be formed in the at least one additional LCP substrate. An other interconnect layer stack may be formed on an other sacrificial substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The other interconnect layer stack may be laminated and electrically joined to an other LCP substrate on a side thereof opposite the other sacrificial substrate, and the other sacrificial substrate may be removed to expose a lowermost patterned electrical conductor layer.
At least one other device may be electrically coupled to the lowermost patterned electrical conductor layer. The other LCP substrate may be laminated to the at least one additional LCP substrate. The interconnect layer stack and the other interconnect layer stack may be electrically coupled using the at least one electrical conductor via in the at least one additional LCP substrate.
The LCP substrate may comprise at least one conductor via in each of a plurality of LCP layers, and which may comprise aligning, laminating, and electrically joining the LCP substrate to the interconnect layer stack. Remaining LCP layers of the plurality thereof may be laminated to the LCP layer that was laminated to the interconnect stack. At least one second device may be electrically coupled to the uppermost patterned electrical conductor layer using the at least one electrical conductor via of each of the plurality of LCP layers.
A device aspect is directed to an electronic device comprising a liquid crystal polymer (LCP) substrate. There is a an interconnect layer stack on the LCP substrate comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, the dielectric layer comprising a material different than LCP. There is a fused seam between the LCP substrate and the interconnect layer stack. In addition, there is an electrical interconnection between the LCP substrate and the attached interconnect layer stack. At least one first device is electrically coupled to a lowermost patterned electrical conductor layer.
FIG. 1 is a flowchart of a method of making an electronic device according to the present invention.
FIGS. 2A-2D are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 1
FIG. 3 is a flowchart of another embodiment of a method of making an electronic device according to the present invention.
FIGS. 4A-4E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 3.
FIG. 5 is a flowchart of a further embodiment of a method of making an electronic device according to the present invention.
FIGS. 6A-6E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 5.
FIG. 7 is a flowchart of a yet another embodiment of a method of making an electronic device according to the present invention.
FIGS. 8A-8E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 7.
FIG. 9 is a flowchart of a still another embodiment of a method of making an electronic device according to the present invention.
FIGS. 10A-10E are sequential schematic cross sectional views of an electronic device of the present invention as formed via the method shown in FIG. 9.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Referring initially to the flowchart 50 of FIG. 1, and FIGS. 2A-2D, a method of making an electronic device is now described. After the start (Block 51), as shown in FIG. 2A, an interconnect layer stack 14 is formed on a sacrificial substrate 12 (at Block 52). The interconnect layer stack 14 comprises a plurality of alternating patterned electrical conductor layers 16, with dielectric layers 17 between adjacent patterned electrical conductor layers. The dielectric layer 17 may be polyimide. The sacrificial substrate 12 provides dimensional stability and atomic smoothness for formation of the interconnect layer stack 14.
The interconnect layer stack 14 may be thinner than 0.0004 inches, for example, with patterned electrical conductor layers 16 as small as (or even smaller than) 0.00004 inches, and dielectric layers 17 as small as (or smaller than) 0.00016 inches. The sacrificial substrate 12 is preferably glass, although other materials with a sufficiently smooth surface may also be used. The interconnect layer stack 14, and therefore the plurality of patterned electrical conductor layers 16, may be formed by semiconductor thin film deposition processes.
As shown in FIG. 2B, a liquid crystal polymer (LCP) substrate 18 is laminated to the interconnect layer stack 14 on a side thereof opposite the sacrificial substrate 12 (at Block 53). The LCP substrate 18 may have a thickness of less than 0.0025 inches, for example. This lamination is performed via the application of heat and pressure to the LCP substrate 18 and the interconnect layer stack 14, such as in an autoclave. An autoclave advantageously provides isostatic pressure (i.e., equal pressure from all directions), and helps to keep the LCP from deforming during the lamination process. While the use of an autoclave for lamination is preferred, a press (possibly in an inert atmosphere) may also be used to perform the lamination. The lamination is preferably performed at approximately 260°C and lOOpsi.
LCP is a particularly advantageous material from which to form printed circuit boards for a variety of reasons, including the fact that it has a high tensile strength, providing a high resistance to abrasion and damage. Typically, LCP also has a high mechanical strength at high temperatures, high chemical resistance, inherent flame retardancy, and good weatherability. In addition, LCP is relatively inert. LCP resists stress cracking in the presence of most chemicals at elevated temperatures, including aromatic or halogenated hydrocarbons, strong acids, bases, ketones, and other aggressive industrial substances. Those skilled in the art should understand that there are a variety of LCPs that may be used in the production of electronic devices according to the present invention. The use of LCP as the substrate 18 advantageously allows the lamination without an adhesive layer, thereby reducing the overall thickness of the resulting electronic device 10.
Next, as shown in FIG. 2C, the sacrificial substrate 12 is removed, thereby exposing a lowermost patterned electrical conductor layer 16 (Block 54). This sacrificial substrate 12 removal is performed by dissolution in hydrofluoric acid, mechanical polishing, or a combination of chemical mechanical polishing, for example.
At least one first device 20 (illustratively three devices) is coupled to the lowermost patterned electrical conductor layer 16 (Block 55), as shown in FIG. 2D. This device 20 may be an integrated circuit (IC) die, and may be coupled in a flip chip arrangement, as will be appreciated by those skilled in the art. Block 56 indicates the end of the method.
The method therefore results in an electronic device 10 comprising an LCP substrate 18 with an interconnect layer stack 14 formed thereon. The interconnect layer stack 14 comprises a plurality of patterned electrical conductor layers 16, with dielectric layers 17 between adjacent patterned electrical conductor layers. There is a fused seam between the interconnect layer stack 14 and the LCP substrate 18. This fused seam is formed during the softening and joining of the LCP substrate and the interconnect layer stack 14, and is readily visible in a photograph of a cross sectioned device. Three integrated circuit dies 20 are coupled to the lowermost patterned electrical conductor layer 16 in a flip chip arrangement. It should be appreciated that there may instead be any number of devices 20, and that they need not be integrated circuit dies. With reference to flowchart 150 of FIG. 3 and FIGS. 4A-4E, a further embodiment of the method of making an electronic device 110 according to the present invention is now described. It should be understood that steps in this method are performed similar to those in the flowchart 50 of FIG. 1, and that detailed descriptions of those steps are therefore not necessary.
After the start (Block 151), as shown in FIG. 4A, an interconnect layer stack 114 is formed on a sacrificial substrate 112 using thin film deposition (at Block 152). The interconnect layer stack 114 comprises a plurality of patterned electrical conductor layers 116, and a dielectric layer 117 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 117 such that pads of the uppermost patterned electrical conductor layer 116 are exposed by the apertures.
Next, at least one electrical conductor via 122, illustratively a plurality of electrical conductor vias, is formed in an LCP substrate 118 (Block 153), as shown in FIG. 4B. The electrical conductor vias 122 are formed by mechanical or laser drilling the LCP substrate 118, then selectively depositing copper in the resulting holes. Tin is then deposited on a lowermost layer of the electrical conductor vias 122.
Before lamination, the LCP substrate 118 and the interconnect layer stack 114 may be aligned. Alignment is defined as having the electrical conductive vias 122 centered in the pads of the uppermost patterned electrical conductor layer 116. This alignment may be performed by first using a fixture or guide to roughly align the LCP substrate 118 and the interconnect layer stack 114, and then finely adjusting the alignment under a microscope to reach the final alignment. This advantageously allows a positional accuracy of alignment in the range of 0.0005 inches to 0.001 inches.
The LCP substrate 118 is then laminated and electrically joined to the interconnect layer stack 114 on a side thereof opposite the sacrificial substrate 112 (Block 154), as shown in FIG. 4C. During the lamination process step, the temperature reaches a suitable level, such as 260°C, which is the melting point of tin, and at which point the copper and tin diffuse and react to form an intermetallic compound, such as Cu3Sn. This intermetallic compound, which is responsible for establishing electrical connection between the LCP substrate and the interconnect layer stack, is thermally stable up to its melting point of at least 600°C.
Advantageously, the temperature required for successful lamination and intermetallic compound formation fall within the same range.
The sacrificial substrate 112 is then removed to expose a lowermost patterned electrical conductor layer 116 (Block 155), as shown in FIG. 4D. At least one first device 120, illustratively a trio thereof, is electrically coupled to the lowermost patterned electrical conductor layer 116 (Block 156), as shown in FIG. 4E. The trio of devices 120 may be integrated circuit dies in a flip chip arrangement, but may also be other devices. At least one second device 124 is electrically coupled to the uppermost patterned electrical conductor layer 116 of the interconnect layer stack 114 using the electrical conductor via 122 (Block 157). This provides connectivity between the devices 120, 124.
It should be appreciated that the devices 120, 124 may be different kinds of devices. For example, the devices 120 may be digital logic circuits, while the devices 124 may be analog radiofrequency circuits. Block 158 indicates the end of the method.
This method therefore results in an electronic device 110 comprising a LCP substrate 118 with a plurality of conductor vias 122 formed therein. An interconnect layer stack 114 is formed on the LCP substrate 118. The interconnect layer stack 114 comprises a plurality of patterned electrical conductor layers 116, with dielectric layers 117 between adjacent patterned electrical conductor layers. There is a fused seam between the interconnect layer stack 114 and the LCP substrate 118. Three integrated circuit dies 120 are coupled to the lowermost patterned electrical conductor layer 116 in a flip chip arrangement. A radiofrequency device 124 is electrically coupled to the uppermost patterned electrical conductor layer 116 and electrically coupled to the integrated circuit dies 120 via the electrical conductor vias 122. With reference to flowchart 250 of FIG. 5 and FIGS. 6A-6E, a further embodiment of the method of making an electronic device 210 according to the present invention is now described. It should be understood that steps in this method are performed similar to those in the flowcharts 50 and 150 of FIGS. 1 and 3, and that detailed descriptions of those steps are therefore not necessary.
After the start (Block 251), as shown in FIG. 5A, an interconnect layer stack 214 is formed on a sacrificial substrate 212 using thin film deposition (at Block 252). The interconnect layer stack 214 comprises a plurality of patterned electrical conductor layers 216, and a dielectric layer 217 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 217 such that pads of the uppermost patterned electrical conductor layer 216 are exposed by the apertures.
Next, at least one electrical conductor via 222, illustratively a plurality of electrical conductor vias, is formed in a LCP substrate 218 (Block 253), as shown in FIG. 5B. The LCP substrate 218 is laminated and electrically joined through an intermetallic bond to the interconnect layer stack 214 on a side thereof opposite the sacrificial substrate 212 (Block 254), as shown in FIG. 6C.
An other interconnect layer stack 234 is formed on an other sacrificial substrate 232 (Block 255), as shown in FIG. 6C. This other interconnect layer stack 234 likewise comprises a plurality of patterned electrical conductor layers 236 and a dielectric layer 237 between adjacent patterned electrical conductor layers. This other interconnect layer stack 235 is then laminated and electrically coupled to the LCP substrate 218 on a side thereof opposite the interconnect layer stack 214 (Block 256), thereby electrically coupling the interconnect layer stack and the other interconnect layer stack together. Both sacrificial substrates 212, 232 are then removed to expose the lowermost patterned electrical conductor layers 216, 236 of the interconnect layer stack 214 and interconnect layer stack 234, respectively (Block 257), as shown in FIG. 6D.
At least one first device 220 is electrically coupled to the lowermost patterned electrical conductor layer 216 of the interconnect layer stack 214 (Block 258), as shown in FIG. 6E. At least one other device 250, illustratively two devices, is then electrically coupled to the uppermost patterned electrical conductor layer 236 of the interconnect layer stack 234 (Block 259).
This method therefore results in an electronic device 210 comprising an LCP substrate 218 with a plurality of conductor vias 222 formed therein, as shown in FIG. 6E. An interconnect layer stack 214 and an other interconnect layer stack 234 are formed on opposing sides of the LCP substrate 218. The interconnect layer stacks 214, 234 each comprise a plurality of patterned electrical conductor layers 216, 236 with dielectric layers 217, 237 between adjacent patterned electrical conductor layers. There is a fused seam between each interconnect layer stack 214, 234 and the LCP substrate 218. An integrated circuit die 220 is coupled to the lowermost patterned electrical conductor layer 216 in a flip chip arrangement. A pair of integrated circuit dies 250 are electrically coupled to the uppermost patterned electrical conductor layer 236 and electrically coupled to the integrated circuit die 220 via the electrical conductor vias 222.
With reference to flowchart 350 of FIG. 7 and FIGS. 8A-8E, a further embodiment of the method of making an electronic device 310 according to the present invention is now described. It should be understood that steps in this method are performed similar to those in the flowcharts 50, 150, 250 of FIGS. 1, 3, 5 and that detailed descriptions of those steps are therefore not necessary.
After the start (Block 351), as shown in FIG. 8A, an interconnect layer stack 314 is formed on a sacrificial substrate 312 using thin film deposition (at Block 352). The interconnect layer stack 314 comprises a plurality of patterned electrical conductor layers 316, and a dielectric layer 317 between adjacent patterned electrical conductor layers. The uppermost patterned electrical conductor layer 316 is exposed.
A liquid crystal polymer (LCP) substrate 318 is formed (Block 353), as shown in FIG. 8B. Copper features are selectively patterned on the LCP substrate 318, and tin is then selectively deposited on the copper to thereby form a circuit layer 324. The LCP substrate 318 is laminated and the tin coated copper features of the LCP substrate 318 are intermetallically bonded to the interconnect layer stack 314 on a side thereof opposite the sacrificial substrate 312 (Block 354), as shown in FIG. 8C. The lamination is preferably performed at 290°C and lOOpsi, although of course other temperatures and pressure could be used.
The sacrificial substrate 312 is removed to expose a lowermost patterned electrical conductor layer 316 (Block 355). At least one first device 320 is electrically coupled to the lowermost patterned electrical conductor layer 316 (Block
356) , as shown in FIG. 8D.
At least one electrical conductor via 326 is formed in at least one additional LCP substrate 328, illustratively three additional LCP substrates (Block
357) . The additional LCP substrates 328 have an aperture therein aligned with the device 320 which is formed by laser milling or mechanical punching. The additional LCP substrates 328 are laminated to the LCP substrate 318 (Block 358), preferably at 270°C and at 200psi, although other temperatures and pressures may be used.
An other interconnect layer stack 334 is formed on another sacrificial substrate 350. This other interconnect layer stack 334 also comprises a plurality of patterned electrical conductor layers 336 and a dielectric layer 337 between adjacent patterned electrical conductor layers (Block 359). The other interconnect layer stack 334 is then laminated to and intermetallically bonded with an other LCP substrate 338 (Block 360), which has had a circuit layer 344 formed thereon. The sacrificial substrate is then removed to expose the lowermost patterned electrical conductor layer 336 (Block 361).
The other LCP substrate 338 is then laminated (Block 362) to the bottommost additional LCP substrate 328, thereby electrically coupling the interconnect layer stack 314 and the other interconnect layer stack 334 via the electrical conductor via 326, and the circuit layers 324, 344. This hermetically seals the device 320 from moisture, dust, and debris. At least one other device 350 is then coupled to the lowermost patterned electrical conductor layer (Block 363). This method therefore results in an electronic device 310 comprising a LCP substrate 318 with a circuit layer 324 formed thereon, as shown in FIG. 8E. An interconnect layer stack 314 is coupled with the LCP substrate 318. The interconnect layer stack 314 comprises a plurality of patterned electrical conductor layers 316 with a dielectric layer 317 between adjacent patterned electrical conductor layers. There is a fused seam between each the interconnect layer stack 314 and the LCP substrate 318. An integrated circuit die 320 is coupled to the lowermost patterned electrical conductor layer 316 in a flip chip arrangement.
Three additional LCP substrate layers 328 are laminated to the LCP substrate 318 on a same side as the interconnect layer stack 314 and have apertures defined therein that are aligned with the integrated circuit die 320. The LCP substrate layers 328 have electrical conductor vias 326 formed therein. There is a fused seam between each of the three additional LCP substrate layers 328, and between the topmost additional LCP substrate layer and the LCP substrate 318.
An other LCP substrate 338 is laminated to the bottommost additional LCP substrate layer 328, and there is a fused seam therebetween. An other interconnect layer stack 334 is laminated to the other LCP substrate 338, and there is also a fused seam therebetween. The other interconnect layer stack 334 comprises a plurality of patterned electrical conductor layers 336, with a dielectric layer 337 between adjacent patterned electrical conductor layers. An other integrated circuit die 350 is coupled to the lowermost patterned electrical conductor layer 336. Therefore, the integrated circuit die 320 and the other integrated circuit die 350 are electrically coupled via the circuit layers 324, 344 and the electrical conductor vias 326. The integrated circuit die 320 is therefore hermetically sealed by the surrounding LCP substrates 318, 328, 338.
With reference to flowchart 450 of FIG. 9 and FIGS. 10A-10E, a further embodiment of the method of making an electronic device 410 according to the present invention is now described. It should be understood that steps in this method are performed similar to those in the flowcharts 50, 150, 250, 350 of FIGS. 1, 3, 5, 7 and that detailed descriptions of those steps are therefore not necessary. After the start (Block 451), as shown in FIG. 10A, an interconnect layer stack 414 is formed on a sacrificial substrate 412 using thin film deposition (at Block 452). The interconnect layer stack 414 comprises a plurality of patterned electrical conductor layers 416, and a dielectric layer 417 between adjacent patterned electrical conductor layers. Apertures are defined in the uppermost dielectric layer 417 such that pads of the uppermost patterned electrical conductor layer 416 are exposed by the apertures.
Next, at least one electrical conductor via 422, illustratively a plurality of electrical conductor vias, is formed in each of a plurality of LCP layers of a LCP substrate 418 (Block 453), as shown in FIG. 10B.
A layer 418 of the LCP substrate is laminated to the interconnect layer stack 414 on a side thereof opposite the sacrificial substrate 412 (Block 454), as shown in FIG. IOC. This bonding process also serves to intermetallically bond the vias 422 with the patterned electrical conductor layers 416. Before lamination, the LCP substrate 418 and the interconnect layer stack 414 may be aligned. Remaining LCP layers 418 are then laminated to the LCP layer that was laminated to the interconnect layer stack 414 (Block 455).
The sacrificial substrate 412 is then removed to expose a lowermost patterned electrical conductor layer 416 (Block 456), as shown in FIG. 10D. At least one first device 420, illustratively a trio of integrated circuit dies, is electrically coupled to the lowermost patterned electrical conductor layer 416 (Block 457), as shown in FIG. 10E. At least one second device 429, illustratively a RF device, is electrically coupled to the conductor vias 422 of the LCP substrate 418, and resides on a side of the LCP substrate 418 opposite the interconnect layer stack 414 (Block 458). Block 459 indicates the end of the method.
This method therefore results in an electronic device 410 comprising a LCP substrate 418 with a plurality of conductor vias 422 formed therein. The LCP substrate 418 comprises a pair of LCP layers. An interconnect layer stack 414 is formed on the LCP substrate 418. The interconnect layer stack 414 comprises a plurality of patterned electrical conductor layers 416, with dielectric layers 417 between adjacent patterned electrical conductor layers. There is a fused seam between the interconnect layer stack 414 and the LCP substrate 418, and between the LCP layers.
Three integrated circuit dies 420 are coupled to the lowermost patterned electrical conductor layer 416 in a flip chip arrangement. A radio frequency device 429 is coupled to a side of the LCP substrate 418 opposite the interconnect layer stack 414, and is electrically coupled to the uppermost patterned electrical conductor layer 416 and the integrated circuit dies 420 via the electrical conductor vias 422. There is also a fused seam between the LCP substrate 418 and the second device 429.

Claims

1. A method of making an electronic device comprising:
forming an interconnect layer stack on a sacrificial substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers;
laminating and intermetallically bonding a liquid crystal polymer
(LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate;
removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer; and
electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
2. The method of Claim 1, wherein laminating the LCP substrate and the interconnect layer stack together comprises applying heat and pressure to the LCP substrate and the interconnect layer stack.
3. The method of Claim 2, wherein applying heat and pressure is performed in an autoclave.
4. The method of Claim 1, wherein forming the interconnect layer stack comprises forming the plurality of patterned electrical conductor layers by thin film deposition.
5. The method of Claim 1, wherein the LCP substrate has a thickness of less than 0.0025 inches.
6. The method of Claim 1 , wherein the at least one first device comprises a first integrated circuit (IC) die in a flip chip arrangement.
7. An electronic device comprising:
a liquid crystal polymer (LCP) substrate;
an interconnect layer stack on said LCP substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, said dielectric layer comprising a material different than LCP;
a fused seam between said LCP substrate and said interconnect layer stack;
an intermetallic bond between said LCP substrate and said interconnect layer stack; and
at least one first device electrically coupled to a lowermost patterned electrical conductor layer.
8. The electronic device of Claim 7, wherein said LCP substrate has a thickness of less than 0.0025 inches.
9. The electronic device of Claim 7, wherein said at least one first device comprises a first integrated circuit (IC) die in a flip chip arrangement.
10. The electronic device of Claim 7, wherein said LCP substrate has at least one electrical conductor via therein; and further comprising at least one second device on said LCP substrate and electrically coupled to the uppermost patterned electrical conductor layer using the at least one electrical conductor via.
PCT/US2011/066734 2011-01-14 2011-12-22 Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices WO2012096774A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020137018792A KR101494988B1 (en) 2011-01-14 2011-12-22 Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
EP11815828.6A EP2664224A1 (en) 2011-01-14 2011-12-22 Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
CN201180064598.5A CN103314649B (en) 2011-01-14 2011-12-22 By the method for RF magnetron sputtering extremely circuit and flexible to the transfer of high-density multi-layered thin film and electric interlock and associated devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/006,973 2011-01-14
US13/006,973 US8867219B2 (en) 2011-01-14 2011-01-14 Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Publications (1)

Publication Number Publication Date
WO2012096774A1 true WO2012096774A1 (en) 2012-07-19

Family

ID=45563502

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/066734 WO2012096774A1 (en) 2011-01-14 2011-12-22 Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Country Status (6)

Country Link
US (3) US8867219B2 (en)
EP (1) EP2664224A1 (en)
KR (1) KR101494988B1 (en)
CN (1) CN103314649B (en)
TW (1) TWI578417B (en)
WO (1) WO2012096774A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10877159B2 (en) 2016-05-20 2020-12-29 Qinetiq Limited Method and system for satellite signal processing

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8844125B2 (en) 2011-01-14 2014-09-30 Harris Corporation Method of making an electronic device having a liquid crystal polymer solder mask and related devices
US8877558B2 (en) 2013-02-07 2014-11-04 Harris Corporation Method for making electronic device with liquid crystal polymer and related devices
US9293438B2 (en) 2013-07-03 2016-03-22 Harris Corporation Method for making electronic device with cover layer with openings and related devices
US9521752B2 (en) 2014-09-19 2016-12-13 Harris Corporation Method of making an electronic device having a thin film resistor formed on an LCP solder mask and related devices
BR112017013830A2 (en) * 2015-03-20 2018-02-27 Opton Shunchang Optics Co Ltd Fully sealed liquid crystal screen and fabrication process.
CN106658967B (en) * 2015-10-30 2019-12-20 奥特斯(中国)有限公司 Component carrier with alternating vertically stacked layer structure of different charge density
CN112470553A (en) * 2018-10-11 2021-03-09 深圳市修颐投资发展合伙企业（有限合伙） Composite process fan-out packaging method
US11352252B2 (en) * 2019-06-21 2022-06-07 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device
CN112349694B (en) * 2020-09-28 2022-05-17 中国电子科技集团公司第二十九研究所 LCP packaging substrate, manufacturing method and multi-chip system-in-package structure
CN112349684B (en) * 2020-09-28 2022-10-21 中国电子科技集团公司第二十九研究所 LCP packaging substrate, manufacturing method and multi-chip system-in-package structure
TWI829396B (en) * 2022-10-21 2024-01-11 欣興電子股份有限公司 Circuit board structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163957A (en) * 1998-11-13 2000-12-26 Fujitsu Limited Multilayer laminated substrates with high density interconnects and methods of making the same
US20040053444A1 (en) * 2001-10-31 2004-03-18 Fujitsu Limited Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board
US20040171190A1 (en) * 2002-04-08 2004-09-02 Yuji Nishitani Circuit substrate device, method for producing the same, semiconductor device and method for producing the same
US20050037535A1 (en) * 2002-09-30 2005-02-17 Tsuyoshi Ogawa Method for fabricating high frequency module

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258236A (en) 1991-05-03 1993-11-02 Ibm Corporation Multi-layer thin film structure and parallel processing method for fabricating same
US5303862A (en) * 1992-12-31 1994-04-19 International Business Machines Corporation Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures
CN1116164C (en) * 1998-04-09 2003-07-30 可乐丽股份有限公司 Method of forming polymer film coating and method for preparing laminated body of polymer layer and metal foil layer
US6036809A (en) 1999-02-16 2000-03-14 International Business Machines Corporation Process for releasing a thin-film structure from a substrate
US6326555B1 (en) * 1999-02-26 2001-12-04 Fujitsu Limited Method and structure of z-connected laminated substrate for high density electronic packaging
US6414849B1 (en) * 1999-10-29 2002-07-02 Stmicroelectronics, Inc. Low stress and low profile cavity down flip chip and wire bond BGA package
US6931723B1 (en) * 2000-09-19 2005-08-23 International Business Machines Corporation Organic dielectric electronic interconnect structures and method for making
EP1194020A3 (en) * 2000-09-27 2004-03-31 Matsushita Electric Industrial Co., Ltd. Resin board, manufacturing process for resin board, connection medium body, circuit board and manufacturing process for circuit board
US6372992B1 (en) 2000-10-05 2002-04-16 3M Innovative Properties Company Circuit protective composites
TWI300744B (en) * 2001-04-19 2008-09-11 Nippon Steel Chemical Co
US6759600B2 (en) * 2001-04-27 2004-07-06 Shinko Electric Industries Co., Ltd. Multilayer wiring board and method of fabrication thereof
JP2003218272A (en) * 2002-01-25 2003-07-31 Sony Corp High frequency module and its manufacturing method
US6826830B2 (en) * 2002-02-05 2004-12-07 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
JP4181778B2 (en) * 2002-02-05 2008-11-19 ソニー株式会社 Wiring board manufacturing method
JP3872360B2 (en) * 2002-02-25 2007-01-24 京セラ株式会社 Multilayer wiring board
US6899815B2 (en) * 2002-03-29 2005-05-31 Intel Corporation Multi-layer integrated circuit package
EP1357773A3 (en) * 2002-04-25 2005-11-30 Matsushita Electric Industrial Co., Ltd. Wiring transfer sheet and method for producing the same, and wiring board and method for producing the same
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
US7260890B2 (en) * 2002-06-26 2007-08-28 Georgia Tech Research Corporation Methods for fabricating three-dimensional all organic interconnect structures
US20040089470A1 (en) * 2002-11-12 2004-05-13 Nec Corporation Printed circuit board, semiconductor package, base insulating film, and manufacturing method for interconnect substrate
US6998327B2 (en) 2002-11-19 2006-02-14 International Business Machines Corporation Thin film transfer join process and multilevel thin film module
TWI234210B (en) * 2002-12-03 2005-06-11 Sanyo Electric Co Semiconductor module and manufacturing method thereof as well as wiring member of thin sheet
CN1756654B (en) * 2002-12-27 2011-05-11 日本电气株式会社 Sheet material and wiring board
US7489914B2 (en) * 2003-03-28 2009-02-10 Georgia Tech Research Corporation Multi-band RF transceiver with passive reuse in organic substrates
US7164197B2 (en) * 2003-06-19 2007-01-16 3M Innovative Properties Company Dielectric composite material
US7141884B2 (en) * 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
US7408258B2 (en) * 2003-08-20 2008-08-05 Salmon Technologies, Llc Interconnection circuit and electronic module utilizing same
EP1702502A2 (en) * 2003-12-30 2006-09-20 3M Innovative Properties Company Patterned circuits and method for making same
ATE373945T1 (en) * 2004-02-23 2007-10-15 Georgia Tech Res Inst LIQUID CRYSTAL POLYMER AND MULTI-LAYER POLYMER BASED PASSIVE SIGNAL PROCESSING COMPONENTS FOR RF/WIRELESS MULTI-BAND APPLICATIONS
US8345433B2 (en) * 2004-07-08 2013-01-01 Avx Corporation Heterogeneous organic laminate stack ups for high frequency applications
US20060068576A1 (en) 2004-09-30 2006-03-30 Burdick William E Jr Lithography transfer for high density interconnect circuits
KR100716824B1 (en) * 2005-04-28 2007-05-09 삼성전기주식회사 Printed circuit board with embedded capacitors using hybrid materials, and manufacturing process thereof
JP2006339365A (en) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd Wiring board, its manufacturing method, manufacturing method of multilayer laminated wiring board and forming method of via hole
US20070004844A1 (en) * 2005-06-30 2007-01-04 Clough Robert S Dielectric material
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US20070107932A1 (en) * 2005-11-09 2007-05-17 Jauniskis Linas A Moisture resistant chip package
JP2007193999A (en) * 2006-01-17 2007-08-02 Sony Chemical & Information Device Corp Transmission cable
KR100793332B1 (en) * 2007-01-12 2008-01-11 (주)하이모 Anti-releasing treating method of cap net for wig
US8508036B2 (en) * 2007-05-11 2013-08-13 Tessera, Inc. Ultra-thin near-hermetic package based on rainier
KR100867148B1 (en) * 2007-09-28 2008-11-06 삼성전기주식회사 Printed circuit board and manufacturing method of the same
JP4853877B2 (en) * 2007-11-19 2012-01-11 日東電工株式会社 MANUFACTURING METHOD FOR CONNECTED SHEET PRODUCT, CONNECTING SHEET PRODUCT, AND METHOD FOR MANUFACTURING OPTICAL DISPLAY UNIT
US20090145651A1 (en) * 2007-12-11 2009-06-11 Panasonic Corporation Multilayer wiring board and method for producing the same
US20100066683A1 (en) 2008-09-17 2010-03-18 Shih-Chang Chang Method for Transferring Thin Film to Substrate
KR20100055011A (en) 2008-11-17 2010-05-26 삼성전자주식회사 Display device and method of manufacturing the same
JP4894910B2 (en) * 2009-01-15 2012-03-14 株式会社デンソー Manufacturing method of semiconductor device, semiconductor device, and multilayer substrate incorporating the semiconductor device
US7951663B2 (en) * 2009-05-26 2011-05-31 Stats Chippac, Ltd. Semiconductor device and method of forming IPD structure using smooth conductive layer and bottom-side conductive layer
WO2010144792A1 (en) * 2009-06-11 2010-12-16 Rogers Corporation Dielectric materials, methods of forming subassemblies therefrom, and the subassemblies formed therewith
US9351408B2 (en) * 2010-04-22 2016-05-24 I3 Electronics, Inc. Coreless layer buildup structure with LGA and joining layer
US8536459B2 (en) * 2010-04-22 2013-09-17 Endicott Interconnect Technologies, Inc. Coreless layer buildup structure with LGA
US20120098129A1 (en) * 2010-10-22 2012-04-26 Harris Corporation Method of making a multi-chip module having a reduced thickness and related devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163957A (en) * 1998-11-13 2000-12-26 Fujitsu Limited Multilayer laminated substrates with high density interconnects and methods of making the same
US20040053444A1 (en) * 2001-10-31 2004-03-18 Fujitsu Limited Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board
US20040171190A1 (en) * 2002-04-08 2004-09-02 Yuji Nishitani Circuit substrate device, method for producing the same, semiconductor device and method for producing the same
US20050037535A1 (en) * 2002-09-30 2005-02-17 Tsuyoshi Ogawa Method for fabricating high frequency module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T. ZHANG; W. JOHNSON; B. FARRELL; M. ST. LAWRENCE: "The Processing and Assembly ofliquid Crystalline Polymer Printed Circuits", INT. SYMP. ON MICROELECTRONICS, 2002

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10877159B2 (en) 2016-05-20 2020-12-29 Qinetiq Limited Method and system for satellite signal processing

Also Published As

Publication number Publication date
TW201230222A (en) 2012-07-16
KR20130115323A (en) 2013-10-21
TWI578417B (en) 2017-04-11
CN103314649B (en) 2016-06-01
US20160322284A1 (en) 2016-11-03
US9691698B2 (en) 2017-06-27
CN103314649A (en) 2013-09-18
US20120182701A1 (en) 2012-07-19
US20140376197A1 (en) 2014-12-25
US9420687B2 (en) 2016-08-16
KR101494988B1 (en) 2015-02-23
EP2664224A1 (en) 2013-11-20
US8867219B2 (en) 2014-10-21

Similar Documents

Publication Publication Date Title
US9691698B2 (en) Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
US8472207B2 (en) Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods
US10342126B2 (en) Electronic device having a liquid crystal polymer solder mask and related devices
EP2664226B1 (en) Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack
JP5261756B1 (en) Multilayer wiring board
KR20070068445A (en) Structure and method of making interconnect element having metal traces embedded in surface of dielectric
KR100704911B1 (en) Electronic chip embedded pcb and method of the same
JP2008529283A (en) Composition and method for making interconnect elements having metal traces embedded in the surface of a dielectric
JP2016181585A (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11815828

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013549432

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20137018792

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2011815828

Country of ref document: EP