WO2012077208A1 - Circuit de traitement de signal et son procédé de commande - Google Patents

Circuit de traitement de signal et son procédé de commande Download PDF

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Publication number
WO2012077208A1
WO2012077208A1 PCT/JP2010/072093 JP2010072093W WO2012077208A1 WO 2012077208 A1 WO2012077208 A1 WO 2012077208A1 JP 2010072093 W JP2010072093 W JP 2010072093W WO 2012077208 A1 WO2012077208 A1 WO 2012077208A1
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Prior art keywords
output
signal
buffer
video signal
data
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PCT/JP2010/072093
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English (en)
Japanese (ja)
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濱村　繁男
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Ｎｅｃディスプレイソリューションズ株式会社
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Priority to PCT/JP2010/072093 priority Critical patent/WO2012077208A1/fr
Publication of WO2012077208A1 publication Critical patent/WO2012077208A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
    • H04N13/106—Processing image signals
    • H04N13/161—Encoding, multiplexing or demultiplexing different image signal components

Definitions

  • the present invention relates to a signal processing circuit that outputs a video signal and a control method thereof.
  • the video shown in the video signal of the digital cinema is composed of a plurality of horizontal lines (hereinafter referred to as lines), and a blanking area 10 and a blanking area where black images are continuous from the outer edge of the video. And a video area 20 that is an area other than 10.
  • the total number of lines per frame is Y
  • the top line of the video area 20 is the top line M
  • the end line is the end line N.
  • auxiliary data necessary for processing a video signal called Ancillary Data is added to the video signal.
  • the digital cinema processing circuit processes the video signal using the Ancillary Data added to the video signal and drives, for example, a display device that displays the video indicated by the video signal.
  • FIG. 2 is a diagram showing a video signal to which Ancillary Data is added.
  • the ancillary data is added to the video signal by inserting the ancillary data into the line M-1 that is the line immediately before the head line M. Since the line M-1 is included in the blanking area 10, even if ancillary data is added, the total number of lines Y per frame, the first line M and the end line N of the video area 20 are not changed.
  • Ancillary data is added by a signal processing circuit that outputs a video signal to the digital cinema processing circuit.
  • the configuration of such a signal processing circuit is shown in FIG.
  • 3 includes an input unit 210 and an ancillary data adding unit 220.
  • the Ancillary Data adding unit 220 includes an Ancillary Data extracting unit 221, an Ancillary buffer 222, an en delay unit 223, OR circuits 224-1 and 224-2, an address counter 225, a line buffer 226, and a head line. It has a detection unit 227, a multiplexer 228, and a V Sync delay unit 229.
  • the video signal given from the signal source is input to the input unit 210.
  • the input unit 210 When the video signal is input, the input unit 210 inputs the Data signal to the Ancillary Data extraction unit 221 and the line buffer 226, and sends the Data Enable signal to the en delay unit 223, the OR circuit 224-1, the line buffer 226, and the head. Input to the line detection unit 227, input the H Sync signal to the leading line detection unit 227, and input the V Sync signal to the V Sync delay unit 229.
  • the Data signal is a signal obtained by reading the video signal for each line from the left to the right in order from the line 1 shown in FIG.
  • the Data Enable signal is a signal indicating whether or not the Data signal is a video signal of the video area 20.
  • the H Sync signal is a signal indicating the start timing of the line.
  • the V Sync signal is a signal indicating the start timing of the frame.
  • the input unit 210 inputs the 3D Left Right signal and the interlace Odd Even signal to the Ancillary Data extraction unit 221.
  • the 3D Left Right signal is a signal for discriminating between a left-eye image and a right-eye image having binocular parallax for displaying a 3D image.
  • the interlace Odd Even signal is a signal for identifying the odd-numbered and even-numbered video signals when the video signal is divided into odd-numbered lines and even-numbered lines and output to the digital cinema processing circuit 300.
  • the Ancillary Data extraction unit 221 extracts Ancillary Data from the input signal and outputs it to the Ancillary buffer 222.
  • Specific examples of Ancillary Data include 3D Left Right signal, interlace Odd Even signal, key code used to decrypt the encrypted video signal, and time code related to the frame display time. There is.
  • the Ancillary buffer 222 stores the Ancillary Data output from the Ancillary Data extraction unit 221 and outputs it to the multiplexer 228.
  • the en delay unit 223 delays the input Data Enable signal by one line and outputs it to the OR circuits 224-1 and 224-2 as Delayed Data Enable signals.
  • OR circuit 224-1 outputs a signal to address counter 225 in response to the input of Data Enable signal or Delayed Data Enable signal.
  • the address counter 225 starts counting from 0 in response to the signal output from the OR circuit 224-1 and outputs the count value to the line buffer 226.
  • the line buffer 226 writes a Data signal using the count value output from the address counter 225 as a write address.
  • the line buffer 226 reads the written Data signal using the count value output from the address counter 225 as a read address, and outputs the read Data signal to the multiplexer 228.
  • the Insert Ancillary signal indicating that the Ancillary Data is to be inserted is sent to the multiplexer 228 and the OR circuit 224- Output to 2.
  • the multiplexer 228 receives the output of the Ancillary buffer 222 and the output of the line buffer 226 as inputs, and selectively outputs either to the digital cinema processing circuit 300 as a Data Out signal according to the input of the Insert Ancillary signal.
  • the V Sync delay unit 229 delays the input V Sync signal by one line and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
  • the OR circuit 224-2 indicates whether the Data Out signal is a valid signal according to the input of the Delayed Data Enable signal or the Insert Ancillary signal, that is, whether it is the Ancillary Data or the video signal of the video area 20.
  • Data Enable Out signal is output to the digital cinema processing circuit 300.
  • FIG. 4 is a timing chart of each signal shown in FIG.
  • Ancillary Data is stored in the Ancillary buffer 222.
  • the input unit 210 causes the V Sync signal to transition from Low to High.
  • the input unit 210 changes the H Sync signal from High to Low, then changes from Low to High, and in order from line 1, the video signal for each line goes from left to right. Read out and input as Data signal. Since the line 1 to the line M-1 are the blanking area 10, the Data Enable signal remains Low.
  • the V Sync delay unit 229 transitions the V Sync Out signal from Low to High at time t12 when one line has elapsed from time t11.
  • the input unit 210 keeps the Data Enable signal Low while the video signal of the blanking area 10 is being input, and when the input of the video signal of the video area 20 is started at time t14, the Data Enable signal. Is transitioned from Low to High.
  • the input unit 201 transitions the Data Enable signal from High to Low.
  • the video signal of the video area 20 for one line (line X) is referred to as Data X.
  • the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 counts from 0 every clock according to the signal output. Is output to the line buffer 226.
  • the Write Enable signal indicating write permission transitions from Low to High
  • the line buffer 226 writes the Data signal using the count value output from the address counter 225 as the write address.
  • the video area 20 for one line is n pixels, and a video signal for one pixel is input from the input unit 210 as a Data signal every clock.
  • the address counter 225 While the video signal of the video area 20 is being input, the Data Enable signal is High, and the address counter 225 outputs the counter value. Therefore, the address counter 225 outputs a count value from 0 to n ⁇ 1, and the line buffer 226 writes the video signal of each pixel using the count value as a write address.
  • the head line detection unit 227 starts from the time t14 when the Data Enable signal transitions from Low to High for the first time, and then the Data Enable signal transitions from High to Low. Until the transition time t15, the Insert Ancillary signal is transitioned from Low to High.
  • the multiplexer 228 selects the Ancillary buffer 222 as the output source of the Data Out signal, and the digital cinema processing circuit 300 uses the Ancillary Data stored in the Ancillary buffer 222 as the Data Out signal. Output to.
  • the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal.
  • the en delay unit 223 transitions the Delayed Data Enable signal from Low to High.
  • the time from time t16 to time 17 is the same as the time from time t14 to time t15.
  • the OR circuit 224-1 When the Delayed Data Enable signal transitions to High, the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 outputs a count value from 0 to the line buffer 226 according to the signal output.
  • the address counter 225 outputs a count value from 0, and the line buffer 226 reads the written Data signal (Data M) using the count value as a read address and outputs it to the multiplexer 228.
  • Data M + 1 is input as the Data signal between time t16 and time t17.
  • the line buffer 226 reads Data M, outputs it to the multiplexer 228, and writes Data M + 1.
  • the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal
  • the Data M output from the line buffer 226 is digitally output as the Data Out signal. It is output to the cinema processing circuit 300.
  • Data M is output as a Data Out signal at time t16 delayed by one line after input is started at time t14.
  • V Sync signal is delayed by one line, the video signal with ancillary data added to the digital cinema without changing the total number of lines Y per frame, the top line M and the end line N of the video area 20 It can be output to the processing circuit 300.
  • Patent Document 1 Japanese Patent Laid-Open No. 2010-68309 discloses a technique for displaying a three-dimensional image by combining and displaying a left-eye image and a right-eye image.
  • a video signal for displaying a 3D video as described above the video area 20 is divided into a left area 21 and a right area 22 as shown in FIG.
  • a so-called side-by-side video signal is disclosed in which a left-eye video signal indicating a left-eye video is stored and a right-eye video signal indicating a right-eye video is stored in the right area 22.
  • a side-by-side video signal is referred to as a 3D video signal.
  • FIG. 9 shows an outline of the configuration of the signal processing circuit for separating the video signal and adding the ancillary data described above.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
  • the signal processing circuit 400 shown in FIG. 9 has an input unit 210, a separation unit 410, and two ancillary data addition units 220-1 and 220-2.
  • the separation unit 410 separates the left-eye video signal and the right-eye video signal, outputs the left-eye video signal to the Ancillary Data adding unit 220-1, and outputs the right-eye video signal. Output to Ancillary Data adder 220-2.
  • the Ancillary Data adding unit 220-1 adds the Ancillary Data necessary for processing the left-eye video signal to the left-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
  • the Ancillary Data adding unit 220-2 adds the Ancillary Data necessary for processing the right-eye video signal to the right-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
  • FIG. 10 is a block diagram showing a configuration of the separation unit 410.
  • 10 includes an address counter 411, an address comparison unit 412, and a line buffer 413.
  • the video signal given from the signal source is input to the input unit 210.
  • the input unit 210 inputs the Data signal to the line buffer 413, and sends the Data Enable signal to the address counter 411 and the address comparison unit. 412. Further, the Data signal is output as it is to the Ancillary Data adding unit 220-2 as a Data Right signal.
  • the address counter 411 starts counting from 0 and outputs the count value to the address comparison unit 412 and the line buffer 413.
  • the address comparison unit 412 When the count value output from the address counter 411 reaches a predetermined value, the address comparison unit 412 outputs a clear signal for returning the count value to 0 to the address counter 411.
  • the address comparison unit 412 outputs a Write Enable signal to the line buffer 413 and outputs a Data Enable Out signal to the Ancillary Data adding units 220-1 and 220-2.
  • the line buffer 413 When the Write Enable signal is output from the address comparison unit 412, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. Also, the line buffer 413 reads the written Data signal using the count value output from the address counter 411 as a read address, and outputs it to the Ancillary Data adding unit 220-1 as a Data Left signal.
  • FIG. 11 is a timing chart of each signal shown in FIG.
  • the left-eye video and the right-eye video for one line are each n pixels, and the left-eye video signal is L (0), L (1), L (2)... L (n-2), L ( n-1), and the right-eye video signals are R (0), R (1), R (2)... R (n-2), R (n-1).
  • the address counter 411 When the Data Enable signal transitions to High, the address counter 411 outputs a count value from 0 to the address comparison unit 412 and the line buffer 413 every clock. Further, the address comparison unit 412 changes the Write Enable signal from Low to High. Note that the Data Enable Out signal remains Low.
  • the line buffer 413 When the Write Enable signal transitions to High, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. As described above, the Data signal is output as the Data Right signal to the Ancillary Data adding unit 220-2. However, since the Data Enable Out signal is Low, it is not handled as an effective signal.
  • the address comparison unit 412 outputs a clear signal when the count value reaches a predetermined value n-1. Therefore, by the time the count value reaches n-1, the left-eye video signals L (0), L (1), L (2)... L (n-2), L (n-1) 413 is written.
  • the address comparison unit 412 When the count value reaches the predetermined value n ⁇ 1 at time t22, the address comparison unit 412 outputs a clear signal to the address counter 411, transitions the Write Enable signal from High to Low, and sets the Data Enable Out signal to Low. Transition from to High.
  • the address counter 411 returns the count value to zero.
  • the line buffer 413 uses the count value output from the address comparison unit 412 as a read address, and writes the left-eye video signals L (0), L (1), and L (2) that have been written. ... L (n-2) and L (n-1) are read and output to the Ancillary Data adder 220-1 as Data Left signals.
  • the Data signal is output as is to the Ancillary Data adding unit 220-2 as a Data Right signal.
  • right eye video signals R (0), R (1), R (2)... R (n-2), R (n-1) are input, so ancillary data is added.
  • the right eye video signal is output as a Data Right signal to the unit 220-2.
  • the separating unit 410 can separate the left-eye video signal and the right-eye video signal and output them to the Ancillary Data adding units 220-1 and 220-2.
  • the signal processing circuit of the present invention comprises: First and second buffers for storing half the video signal for one horizontal line; Third and fourth buffers for storing auxiliary data necessary for processing the video signals stored in the first and second buffers; An output unit for inputting the outputs of the first to fourth buffers and outputting different signals according to the content of the video signal; A first write control unit for sequentially storing the video signal for one horizontal line in the first and second buffers;
  • the video signal is a three-dimensional video signal indicating a left-eye video and a right-eye video for displaying a three-dimensional video
  • a first required for processing the left-eye video signal indicating the left-eye video Auxiliary data is stored in the third buffer
  • second auxiliary data required for processing a right-eye video signal indicating the right-eye video is stored in the fourth buffer
  • the video signal is stored in the three-dimensional
  • a second write control unit for storing, in the third buffer, third auxiliary data necessary for processing the video signal when it is not a video signal
  • the output unit in parallel with the output signal and a second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer And when the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the video signal stored in the first and second buffers A third output signal combining the above is output to the output unit.
  • a method for controlling a signal processing circuit of the present invention includes: First and second buffers for storing half the video signal for one horizontal line, and third data for storing auxiliary data required when processing the video signals stored in the first and second buffers And a fourth buffer, and a control method of a signal processing circuit having an output unit that inputs the output of the first to fourth buffers and outputs a different signal according to the content of the video signal,
  • the first writing control unit sequentially stores the video signal for one horizontal line in the first and second buffers, When the video signal is a 3D video signal indicating a left-eye video and a right-eye video for displaying a 3D video, the second writing control unit processes the left-eye video signal indicating the left-eye video.
  • First auxiliary data required at the time is stored in the third buffer, and second auxiliary data required in processing the right-eye video signal indicating the right-eye video is stored in the fourth buffer.
  • the third auxiliary data required for processing the video signal is stored in the third buffer.
  • the read control unit obtains the first auxiliary data stored in the third buffer and the video signal stored in the first buffer.
  • the combined first output signal and the second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer are parallel to each other.
  • the third auxiliary data stored in the third buffer and the first and second buffers are stored.
  • a third output signal combined with the video signal being output is output to the output unit.
  • the present invention it is possible to process a video signal to which ancillary data is added, regardless of whether the video signal is a 3D video signal or not, while suppressing an increase in the circuit scale of the signal processing circuit. Can be output to the circuit.
  • FIG. 3 It is a figure which shows the video signal of a digital cinema. It is a figure which shows the video signal in the state where Ancillary Data was added. It is a figure which shows the structure of the related signal processing circuit. 4 is a timing chart showing an operation of the signal processing circuit shown in FIG. 3. 4 is a timing chart showing a write operation to the line buffer shown in FIG. 3. FIG. 4 is a timing chart showing a read operation from the line buffer shown in FIG. 3.
  • FIG. It is a figure which shows a three-dimensional video signal. It is a figure which shows the state which isolate
  • FIG. 13 is a timing chart showing a write operation to the line buffer shown in FIG. 12.
  • FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12.
  • FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12.
  • FIG. 12 is a block diagram showing a configuration of the signal processing circuit 100 according to the embodiment of the present invention.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
  • the signal processing circuit 100 of this embodiment includes an input unit 110 and an ancillary data adding unit 120.
  • the Ancillary Data adding unit 120 includes an Ancillary Data extraction unit 121, Ancillary buffers 122-1 and 122-2, an en delay unit 123, OR circuits 124-1 to 124-3, a write control unit 125, Line buffers 128-1 and 128-2, a read control unit 129, an output unit 132, and a V Sync delay unit 133.
  • the write control unit 125 includes an address counter 126 and a Wr address comparison unit 127.
  • the read control unit 129 includes an Rd address comparison unit 130 and a head line detection unit 131.
  • the output unit 132 includes multiplexers 132-1 to 132-3.
  • the Ancillary Data extraction unit 121 is an example of a second write control unit
  • the Ancillary buffer 122-1 is an example of a third buffer
  • the Ancillary buffer 122-2 is an example of a fourth buffer.
  • the write control unit 125 is an example of a first write control unit
  • the line buffer 128-1 is an example of a first buffer
  • the line buffer 128-2 is an example of a second buffer
  • the multiplexer 132-1 is an example of a third multiplexer
  • the multiplexer 132-2 is an example of a first multiplexer
  • the multiplexer 132-3 is an example of a second multiplexer.
  • the video signal given from the signal source is input to the input unit 110.
  • the input unit 110 When the video signal is input, the input unit 110 inputs the Data signal to the Ancillary Data extraction unit 121 and the line buffers 128-1 and 128-2, and sends the Data Enable signal to the en delay unit 123 and the OR circuit 124-1. And the first line detection unit 131, the H Sync signal is input to the first line detection unit 131, the V Sync signal is input to the V Sync delay unit 133, and the 3D Left Right signal and the interlace Odd Even signal are extracted from the Ancillary Data. Input to the unit 121.
  • the input unit 110 determines whether or not the input video signal is a 3D video signal, and outputs a 3D signal indicating the determination result to the Rd address comparison unit 130, the head line detection unit 131, and the OR circuit 124-2. To enter.
  • the Ancillary Data extraction unit 121 extracts the Ancillary Data from the input signal and outputs the extracted Ancillary Data to the Ancillary buffers 122-1 and 122-2. If the input video signal is a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data necessary for processing the left-eye video signal to the Ancillary buffer 122-1, so that the right-eye video signal is output. The Ancillary Data necessary for the processing is output to the Ancillary buffer 122-2. Further, if the input video signal is not a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data to the Ancillary buffer 122-1.
  • the Ancillary buffer 122-1 stores the Ancillary Data output from the Ancillary Data extraction unit 121, and outputs it to the multiplexer 132-2.
  • the Ancillary buffer 122-2 stores the Ancillary Data output from the Ancillary Data extraction unit 121 and outputs it to the multiplexer 132-3.
  • the en delay unit 123 delays the input Data Enable signal by one line, and outputs it to the OR circuit 124-1 and the Rd address comparison unit 130 as a Delayed Data Enable signal.
  • the OR circuit 124-1 outputs a signal to the address counter 126 in response to the input of the Data Enable signal or the Delayed Data Enable signal.
  • the write controller 125 controls writing of the Data signal to the line buffers 128-1 and 128-2.
  • the address counter 126 starts counting from 0 in response to the signal output from the OR circuit 124-1, and sets the count value to the Wr address comparison unit 127, the Rd address comparison unit 130, and the line buffers 128-1 and 128-2. Output to.
  • the Wr address comparator 127 outputs a clear signal to the address counter 126 when the count value output from the address counter 126 reaches a predetermined value.
  • the Wr address comparison unit 127 outputs a Write Enable A signal indicating permission for writing to the line buffer 128-1, and outputs a Write Enable B signal indicating permission for writing to the line buffer 128-2. Output to.
  • the line buffer 128-1 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-1 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1.
  • the line buffer 128-2 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-2 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1 or the line buffer 132-3.
  • the line buffers 128-1 and 128-2 each store half of the video signal of the video area 20 for one line.
  • Read control unit 129 controls the output state of the signal from output unit 132.
  • the Rd address comparison unit 130 When the Delayed Data Enable signal is output from the en delay unit 123, the Rd address comparison unit 130 outputs the Data Enable A signal to the OR circuits 124-2 and 124-3, and the Data Enable B signal to the OR circuit 124-3. Output to.
  • the head line detection unit 131 When the video signal of the head line M is input as the Data signal, the head line detection unit 131 inputs the Insert Ancillary signal to the multiplexers 132-2 and 132-3 and the OR circuit 124-3.
  • OR circuit 124-2 outputs a signal to multiplexer 132-1 in response to the input of 3D signal or Data Enable A signal.
  • the output unit 132 combines the auxiliary data stored in the Ancillary buffers 122-1 and 122-2 and the video signal stored in the line buffers 128-1 and 128-2 in accordance with the control of the read control unit 129. , Data Left signal and Data Right signal are output.
  • the multiplexer 132-1 receives the outputs of the line buffers 128-1 and 128-2 as inputs, and selectively outputs one according to the signal output from the OR circuit 124-2.
  • the multiplexer 132-2 receives the output of the ancillary buffer 122-1 and the output of the multiplexer 132-1 as input, and selectively selects one of the data left signals according to the input of the insert ancillary signal from the head line detector 131. To the digital cinema processing circuit 300.
  • the multiplexer 132-3 receives the output of the Ancillary buffer 122-2 and the output of the line buffer 128-2 as input, and selectively selects either Data Right according to the Insert Ancillary signal input from the head line detection unit 131.
  • the signal is output to the digital cinema processing circuit 300 as a signal.
  • the OR circuit 124-3 performs digital cinema processing on the Data Enable Out signal indicating that the Data Left signal and Data Right signal are valid signals in response to the input of the Data Enable A signal, Data Enable B signal, or Insert Ancillary signal. Output to the circuit 300.
  • the V Sync delay unit 133 delays the V Sync signal input from the input unit 110 by one line, and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
  • the input unit 110 changes the Data Enable signal from Low to High.
  • the OR circuit 124-1 When the Data Enable signal transitions to High, the OR circuit 124-1 outputs a signal to the address counter 126, and the address counter 126 outputs a count value from 0 every clock according to the signal output.
  • the Wr address comparison unit 127 causes the Write Enable A signal to transition to High.
  • the line buffer 128-1 When the Write Enable A signal transitions to High, the line buffer 128-1 writes the Data signal using the count value output from the address counter 126 as the write address.
  • the Wr address comparison unit 127 outputs a clear signal to the address counter 126.
  • a data signal for one pixel is output for each clock, and the data signal is written. Therefore, between time t31 and time t32, data signals for n / 2 pixels, that is, left-eye video signals L (0), L (1), L (2)... L (n / 2-2 ), L (n / 2-1) are written into the line buffer 128-1.
  • the Wr address comparison unit 127 causes the Write Enable A signal to transition from High to Low and causes the Data Enable B signal to transition from Low to High.
  • the Write Enable A signal transitions to Low, writing to the line buffer 128-1 is completed, and when the Write Enable B signal transitions to High, writing to the line buffer 128-2 is started.
  • the address counter 126 When the clear signal is output, the address counter 126 returns the count value to zero.
  • the line buffer 128-2 When the Write Enable B signal transitions to High, the line buffer 128-2 writes the input Data signal using the count value output from the address counter 126 as a write address.
  • the video signal R (0) is output as the Data signal. Therefore, the right-eye video signals R (0), R (1), L (2)... R (n / 2-2), R (n / 2-1) are sequentially written in the line buffer 128-2. It is.
  • the Wr address comparison unit 127 When the count value reaches the predetermined value n / 2-1 again at time t33, the Wr address comparison unit 127 outputs a clear signal to the address counter 126 and changes the Write Enable B signal from Low to High. When the Write Enable B signal transitions to Low, writing to the line buffer 128-2 is completed.
  • FIG. 14 is a timing chart of each signal when the Data signal is read when the video signal is a 3D video signal.
  • the left-eye video signals L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1) are lines as the Data signal.
  • the right-eye video signals R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1) are written into the buffer 128-1, and the line buffer 128- 2 is written.
  • the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the line buffer 128-1 uses the count value as a read address, and the data buffer (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) is read and output, and the line buffer 128-2 outputs the data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1)) is read and output.
  • the Rd address comparison unit 130 simultaneously transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output.
  • the data signals (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
  • the multiplexer 132-3 also outputs the Data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / n) output from the line buffer 128-2. 2-1)) is output to the digital cinema processing circuit 300 as a Data Right signal.
  • OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal and Data Enable B signal transition to High.
  • the Data Enable Out signal transitions to High, the Data Left signal and Data Right signal output from the multiplexers 132-1 and 132-2 are treated as valid signals, and the left-eye video signals L (0), L ( 1), L (2) ... L (n / 2-2), L (n / 2-1) and right-eye video signal R (0), R (1), R (2) ... R ( n / 2-2) and R (n / 2-1) are separated and output to the digital cinema processing circuit 300.
  • the multiplexer 132-2 adds the Ancillary Data stored in the Ancillary buffer 122-1 to the left-eye video signal and outputs it to the digital cinema processing circuit 300 in response to the input of the Insert Ancillary signal. That is, the multiplexer 132-2 combines the left eye video signal stored in the line buffer 128-1 and the Ancillary Data stored in the Ancillary buffer 122-1, and digitally converts the Data Left signal as the first output signal. Output to the cinema processing circuit 300.
  • the multiplexer 132-3 adds the Ancillary Data stored in the Ancillary buffer 122-2 to the right-eye video signal in response to the input of the Insert Ancillary signal, and outputs it to the digital cinema processing circuit 300. That is, the multiplexer 132-3 combines the right eye video signal stored in the line buffer 128-2 and the Ancillary Data stored in the Ancillary buffer 122-2, and digitally converts the Data Right signal as the second output signal. Output to the cinema processing circuit 300.
  • Ancillary data is added in the same manner as the operation described with reference to FIG.
  • FIG. 15 is a timing chart of each signal when the Data signal is read when the video signal is not a 3D video signal.
  • the line buffer 128-1 includes data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1). Is written.
  • the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the line buffer 128-1 uses the count value as a read address, and the data signal D (0), D (1), D (2)... D (n / 2-2), D (n / 2 -1) is read and output, and the line buffer 128-2 receives the data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2 ), D (n-1) is read and output.
  • the Rd address comparison unit 130 causes only the Data Enable A signal to transition from Low to High.
  • the OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output.
  • the data signals D (0), D (1), D (2)... D (n / 2-2), D (n / 2-1) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
  • the Wr address comparison unit 127 When the count value reaches n / 2-1 at time t52, the Wr address comparison unit 127 outputs a clear signal to the address counter 126, and the address counter 126 returns the count value to 0.
  • the Rd address comparison unit 130 causes the Data Enable A signal to transition from High to Low, and causes the Data Enable B signal to transition from Low to High.
  • the OR circuit 124-2 causes the signal to the multiplexer 132-1 when the Data Enable A signal transitions to Low. Stop output.
  • the multiplexer 132-1 sets the output destination of the Data signal stored in the line buffer 128-2 as the multiplexer 132-1, and is output from the line buffer 128-2.
  • Data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300.
  • OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal or Data Enable B signal transitions to High. By transitioning the Data Enable Out signal to High, the Data signal of the video area 20 for one line input from the multiplexer 132-2 is treated as a valid signal, and the video signal of the video area 20 for one line is combined. And output to the digital cinema processing circuit 300.
  • the Rd address comparison unit 130 causes the Data Enable A signal and the Data Enable B signal to simultaneously transition from Low to High.
  • the multiplexer 132-2 receives a data left signal that combines the left-eye video signal stored in the line buffer 128-1 and the ancillary data stored in the ancillary buffer 122-1, and the multiplexer 132-3.
  • the data right signal which is a combination of the right-eye video signal stored in the line buffer 128-2 and the ancillary data stored in the ancillary buffer 122-2, is output to the digital cinema processing circuit 300 in parallel.
  • the Rd address comparison unit 130 first transitions the Data Enable A signal and then the Data Enable B signal from Low to High. In this case, the data signal stored in each line buffer is output to the multiplexer 132-2 in the order of the line buffers 128-1 and 128-2, and combined with the ancillary data stored in the ancillary buffer 122-1. It is output to the cinema processing circuit 300.
  • the multiplexer 132-2 adds the ancillary data stored in the ancillary buffer 122-1 to the video signal stored in the line buffers 128-1 and 128-2 in response to the output of the insert ancillary signal. And output to the digital cinema processing circuit 300. That is, the multiplexer 132-2 combines the video signal stored in the line buffers 128-1 and 128-2 and the Ancillary Data stored in the Ancillary buffer 122-1, and performs digital cinema processing as a third output signal. Output to the circuit 300.
  • Ancillary data is added in the same manner as the operation described with reference to FIG.
  • the signal processing circuit 100 includes the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2, and the video signal is a 3D video signal.
  • the Ancillary Data added to the left-eye video signal is stored in the Ancillary buffer 122-1
  • the Ancillary Data added to the right-eye video signal is stored in the Ancillary buffer 122-2
  • the left-eye video signal is stored in the line buffer 128.
  • the right eye video signal is stored in the line buffer 128-2
  • the Ancillary Data stored in the Ancillary buffer 122-1 is combined with the left eye video signal stored in the line buffer 128-1.
  • Data Left signal and Ancillary Data stored in the Ancillary buffer 122-2 and Line buffer 128-2 And Data Right signal combining the right-eye image signal are, in parallel and outputs the digital cinema processing circuit 300.
  • the signal processing circuit 100 stores the Ancillary Data in the Ancillary buffer 122-1, when the video signal is not a 3D video signal, and the video of the video area 20 for one line. Signals are sequentially stored in the line buffers 128-1 and 128-2, and a signal obtained by combining the Ancillary Data stored in the Ancillary buffer 122-1 and the video signal stored in the line buffers 128-1 and 128-2. Is output to the digital cinema processing circuit 300.
  • an image signal with ancillary data is output to the digital cinema processing circuit 300 regardless of whether the video signal is a 3D video signal or not a 3D video signal while suppressing an increase in circuit scale. Can do.
  • the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2 are described as examples of independent buffers.
  • the present invention is not limited to this. It is not a thing.
  • the signal processing circuit 100 may include a buffer including a plurality of buffers among the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

Le circuit de traitement de signal de la présente invention comporte : des premier à quatrième tampons; une unité de sortie pour entrer une sortie à partir des premier à quatrième tampons ; une première unité de commande d'écriture pour stocker, dans les premier et deuxième tampons, chaque moitié d'un signal vidéo provenant d'une unique ligne horizontale ; une seconde unité de commande d'écriture pour stocker des premières données auxiliaires dans le quatrième tampon dans un cas dans lequel le signal vidéo est un signal vidéo tridimensionnel, et pour stocker des troisième données auxiliaires dans le troisième tampon dans un cas dans lequel le signal vidéo n'est pas un signal vidéo tridimensionnel ; et une unité de commande de lecture pour émettre, en parallèle, un signal combinant les premières données auxiliaires avec le signal vidéo stocké dans le premier tampon, et un signal combinant les deuxièmes données auxiliaires avec le signal vidéo stocké dans le deuxième tampon, dans un cas dans lequel les signaux vidéo sont des signaux vidéo tridimensionnels, et pour émettre un signal combinant les troisièmes données auxiliaires avec les signaux vidéo stockés dans les premier et deuxième tampons dans un cas dans lequel les signaux vidéo ne sont pas des signaux vidéo tridimensionnels.
PCT/JP2010/072093 2010-12-09 2010-12-09 Circuit de traitement de signal et son procédé de commande WO2012077208A1 (fr)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010008012A1 (fr) * 2008-07-16 2010-01-21 ソニー株式会社 Émetteur, procédé d'émission de données d'image tridimensionnelle, récepteur, et procédé de réception de données d'image tridimensionnelle

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010008012A1 (fr) * 2008-07-16 2010-01-21 ソニー株式会社 Émetteur, procédé d'émission de données d'image tridimensionnelle, récepteur, et procédé de réception de données d'image tridimensionnelle

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