WO2012077208A1 - Signal processing circuit and control method thereof - Google Patents

Signal processing circuit and control method thereof Download PDF

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Publication number
WO2012077208A1
WO2012077208A1 PCT/JP2010/072093 JP2010072093W WO2012077208A1 WO 2012077208 A1 WO2012077208 A1 WO 2012077208A1 JP 2010072093 W JP2010072093 W JP 2010072093W WO 2012077208 A1 WO2012077208 A1 WO 2012077208A1
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Prior art keywords
output
signal
buffer
video signal
data
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PCT/JP2010/072093
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French (fr)
Japanese (ja)
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濱村　繁男
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Ｎｅｃディスプレイソリューションズ株式会社
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Priority to PCT/JP2010/072093 priority Critical patent/WO2012077208A1/en
Publication of WO2012077208A1 publication Critical patent/WO2012077208A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
    • H04N13/106—Processing image signals
    • H04N13/161—Encoding, multiplexing or demultiplexing different image signal components

Definitions

  • the present invention relates to a signal processing circuit that outputs a video signal and a control method thereof.
  • the video shown in the video signal of the digital cinema is composed of a plurality of horizontal lines (hereinafter referred to as lines), and a blanking area 10 and a blanking area where black images are continuous from the outer edge of the video. And a video area 20 that is an area other than 10.
  • the total number of lines per frame is Y
  • the top line of the video area 20 is the top line M
  • the end line is the end line N.
  • auxiliary data necessary for processing a video signal called Ancillary Data is added to the video signal.
  • the digital cinema processing circuit processes the video signal using the Ancillary Data added to the video signal and drives, for example, a display device that displays the video indicated by the video signal.
  • FIG. 2 is a diagram showing a video signal to which Ancillary Data is added.
  • the ancillary data is added to the video signal by inserting the ancillary data into the line M-1 that is the line immediately before the head line M. Since the line M-1 is included in the blanking area 10, even if ancillary data is added, the total number of lines Y per frame, the first line M and the end line N of the video area 20 are not changed.
  • Ancillary data is added by a signal processing circuit that outputs a video signal to the digital cinema processing circuit.
  • the configuration of such a signal processing circuit is shown in FIG.
  • 3 includes an input unit 210 and an ancillary data adding unit 220.
  • the Ancillary Data adding unit 220 includes an Ancillary Data extracting unit 221, an Ancillary buffer 222, an en delay unit 223, OR circuits 224-1 and 224-2, an address counter 225, a line buffer 226, and a head line. It has a detection unit 227, a multiplexer 228, and a V Sync delay unit 229.
  • the video signal given from the signal source is input to the input unit 210.
  • the input unit 210 When the video signal is input, the input unit 210 inputs the Data signal to the Ancillary Data extraction unit 221 and the line buffer 226, and sends the Data Enable signal to the en delay unit 223, the OR circuit 224-1, the line buffer 226, and the head. Input to the line detection unit 227, input the H Sync signal to the leading line detection unit 227, and input the V Sync signal to the V Sync delay unit 229.
  • the Data signal is a signal obtained by reading the video signal for each line from the left to the right in order from the line 1 shown in FIG.
  • the Data Enable signal is a signal indicating whether or not the Data signal is a video signal of the video area 20.
  • the H Sync signal is a signal indicating the start timing of the line.
  • the V Sync signal is a signal indicating the start timing of the frame.
  • the input unit 210 inputs the 3D Left Right signal and the interlace Odd Even signal to the Ancillary Data extraction unit 221.
  • the 3D Left Right signal is a signal for discriminating between a left-eye image and a right-eye image having binocular parallax for displaying a 3D image.
  • the interlace Odd Even signal is a signal for identifying the odd-numbered and even-numbered video signals when the video signal is divided into odd-numbered lines and even-numbered lines and output to the digital cinema processing circuit 300.
  • the Ancillary Data extraction unit 221 extracts Ancillary Data from the input signal and outputs it to the Ancillary buffer 222.
  • Specific examples of Ancillary Data include 3D Left Right signal, interlace Odd Even signal, key code used to decrypt the encrypted video signal, and time code related to the frame display time. There is.
  • the Ancillary buffer 222 stores the Ancillary Data output from the Ancillary Data extraction unit 221 and outputs it to the multiplexer 228.
  • the en delay unit 223 delays the input Data Enable signal by one line and outputs it to the OR circuits 224-1 and 224-2 as Delayed Data Enable signals.
  • OR circuit 224-1 outputs a signal to address counter 225 in response to the input of Data Enable signal or Delayed Data Enable signal.
  • the address counter 225 starts counting from 0 in response to the signal output from the OR circuit 224-1 and outputs the count value to the line buffer 226.
  • the line buffer 226 writes a Data signal using the count value output from the address counter 225 as a write address.
  • the line buffer 226 reads the written Data signal using the count value output from the address counter 225 as a read address, and outputs the read Data signal to the multiplexer 228.
  • the Insert Ancillary signal indicating that the Ancillary Data is to be inserted is sent to the multiplexer 228 and the OR circuit 224- Output to 2.
  • the multiplexer 228 receives the output of the Ancillary buffer 222 and the output of the line buffer 226 as inputs, and selectively outputs either to the digital cinema processing circuit 300 as a Data Out signal according to the input of the Insert Ancillary signal.
  • the V Sync delay unit 229 delays the input V Sync signal by one line and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
  • the OR circuit 224-2 indicates whether the Data Out signal is a valid signal according to the input of the Delayed Data Enable signal or the Insert Ancillary signal, that is, whether it is the Ancillary Data or the video signal of the video area 20.
  • Data Enable Out signal is output to the digital cinema processing circuit 300.
  • FIG. 4 is a timing chart of each signal shown in FIG.
  • Ancillary Data is stored in the Ancillary buffer 222.
  • the input unit 210 causes the V Sync signal to transition from Low to High.
  • the input unit 210 changes the H Sync signal from High to Low, then changes from Low to High, and in order from line 1, the video signal for each line goes from left to right. Read out and input as Data signal. Since the line 1 to the line M-1 are the blanking area 10, the Data Enable signal remains Low.
  • the V Sync delay unit 229 transitions the V Sync Out signal from Low to High at time t12 when one line has elapsed from time t11.
  • the input unit 210 keeps the Data Enable signal Low while the video signal of the blanking area 10 is being input, and when the input of the video signal of the video area 20 is started at time t14, the Data Enable signal. Is transitioned from Low to High.
  • the input unit 201 transitions the Data Enable signal from High to Low.
  • the video signal of the video area 20 for one line (line X) is referred to as Data X.
  • the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 counts from 0 every clock according to the signal output. Is output to the line buffer 226.
  • the Write Enable signal indicating write permission transitions from Low to High
  • the line buffer 226 writes the Data signal using the count value output from the address counter 225 as the write address.
  • the video area 20 for one line is n pixels, and a video signal for one pixel is input from the input unit 210 as a Data signal every clock.
  • the address counter 225 While the video signal of the video area 20 is being input, the Data Enable signal is High, and the address counter 225 outputs the counter value. Therefore, the address counter 225 outputs a count value from 0 to n ⁇ 1, and the line buffer 226 writes the video signal of each pixel using the count value as a write address.
  • the head line detection unit 227 starts from the time t14 when the Data Enable signal transitions from Low to High for the first time, and then the Data Enable signal transitions from High to Low. Until the transition time t15, the Insert Ancillary signal is transitioned from Low to High.
  • the multiplexer 228 selects the Ancillary buffer 222 as the output source of the Data Out signal, and the digital cinema processing circuit 300 uses the Ancillary Data stored in the Ancillary buffer 222 as the Data Out signal. Output to.
  • the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal.
  • the en delay unit 223 transitions the Delayed Data Enable signal from Low to High.
  • the time from time t16 to time 17 is the same as the time from time t14 to time t15.
  • the OR circuit 224-1 When the Delayed Data Enable signal transitions to High, the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 outputs a count value from 0 to the line buffer 226 according to the signal output.
  • the address counter 225 outputs a count value from 0, and the line buffer 226 reads the written Data signal (Data M) using the count value as a read address and outputs it to the multiplexer 228.
  • Data M + 1 is input as the Data signal between time t16 and time t17.
  • the line buffer 226 reads Data M, outputs it to the multiplexer 228, and writes Data M + 1.
  • the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal
  • the Data M output from the line buffer 226 is digitally output as the Data Out signal. It is output to the cinema processing circuit 300.
  • Data M is output as a Data Out signal at time t16 delayed by one line after input is started at time t14.
  • V Sync signal is delayed by one line, the video signal with ancillary data added to the digital cinema without changing the total number of lines Y per frame, the top line M and the end line N of the video area 20 It can be output to the processing circuit 300.
  • Patent Document 1 Japanese Patent Laid-Open No. 2010-68309 discloses a technique for displaying a three-dimensional image by combining and displaying a left-eye image and a right-eye image.
  • a video signal for displaying a 3D video as described above the video area 20 is divided into a left area 21 and a right area 22 as shown in FIG.
  • a so-called side-by-side video signal is disclosed in which a left-eye video signal indicating a left-eye video is stored and a right-eye video signal indicating a right-eye video is stored in the right area 22.
  • a side-by-side video signal is referred to as a 3D video signal.
  • FIG. 9 shows an outline of the configuration of the signal processing circuit for separating the video signal and adding the ancillary data described above.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
  • the signal processing circuit 400 shown in FIG. 9 has an input unit 210, a separation unit 410, and two ancillary data addition units 220-1 and 220-2.
  • the separation unit 410 separates the left-eye video signal and the right-eye video signal, outputs the left-eye video signal to the Ancillary Data adding unit 220-1, and outputs the right-eye video signal. Output to Ancillary Data adder 220-2.
  • the Ancillary Data adding unit 220-1 adds the Ancillary Data necessary for processing the left-eye video signal to the left-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
  • the Ancillary Data adding unit 220-2 adds the Ancillary Data necessary for processing the right-eye video signal to the right-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
  • FIG. 10 is a block diagram showing a configuration of the separation unit 410.
  • 10 includes an address counter 411, an address comparison unit 412, and a line buffer 413.
  • the video signal given from the signal source is input to the input unit 210.
  • the input unit 210 inputs the Data signal to the line buffer 413, and sends the Data Enable signal to the address counter 411 and the address comparison unit. 412. Further, the Data signal is output as it is to the Ancillary Data adding unit 220-2 as a Data Right signal.
  • the address counter 411 starts counting from 0 and outputs the count value to the address comparison unit 412 and the line buffer 413.
  • the address comparison unit 412 When the count value output from the address counter 411 reaches a predetermined value, the address comparison unit 412 outputs a clear signal for returning the count value to 0 to the address counter 411.
  • the address comparison unit 412 outputs a Write Enable signal to the line buffer 413 and outputs a Data Enable Out signal to the Ancillary Data adding units 220-1 and 220-2.
  • the line buffer 413 When the Write Enable signal is output from the address comparison unit 412, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. Also, the line buffer 413 reads the written Data signal using the count value output from the address counter 411 as a read address, and outputs it to the Ancillary Data adding unit 220-1 as a Data Left signal.
  • FIG. 11 is a timing chart of each signal shown in FIG.
  • the left-eye video and the right-eye video for one line are each n pixels, and the left-eye video signal is L (0), L (1), L (2)... L (n-2), L ( n-1), and the right-eye video signals are R (0), R (1), R (2)... R (n-2), R (n-1).
  • the address counter 411 When the Data Enable signal transitions to High, the address counter 411 outputs a count value from 0 to the address comparison unit 412 and the line buffer 413 every clock. Further, the address comparison unit 412 changes the Write Enable signal from Low to High. Note that the Data Enable Out signal remains Low.
  • the line buffer 413 When the Write Enable signal transitions to High, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. As described above, the Data signal is output as the Data Right signal to the Ancillary Data adding unit 220-2. However, since the Data Enable Out signal is Low, it is not handled as an effective signal.
  • the address comparison unit 412 outputs a clear signal when the count value reaches a predetermined value n-1. Therefore, by the time the count value reaches n-1, the left-eye video signals L (0), L (1), L (2)... L (n-2), L (n-1) 413 is written.
  • the address comparison unit 412 When the count value reaches the predetermined value n ⁇ 1 at time t22, the address comparison unit 412 outputs a clear signal to the address counter 411, transitions the Write Enable signal from High to Low, and sets the Data Enable Out signal to Low. Transition from to High.
  • the address counter 411 returns the count value to zero.
  • the line buffer 413 uses the count value output from the address comparison unit 412 as a read address, and writes the left-eye video signals L (0), L (1), and L (2) that have been written. ... L (n-2) and L (n-1) are read and output to the Ancillary Data adder 220-1 as Data Left signals.
  • the Data signal is output as is to the Ancillary Data adding unit 220-2 as a Data Right signal.
  • right eye video signals R (0), R (1), R (2)... R (n-2), R (n-1) are input, so ancillary data is added.
  • the right eye video signal is output as a Data Right signal to the unit 220-2.
  • the separating unit 410 can separate the left-eye video signal and the right-eye video signal and output them to the Ancillary Data adding units 220-1 and 220-2.
  • the signal processing circuit of the present invention comprises: First and second buffers for storing half the video signal for one horizontal line; Third and fourth buffers for storing auxiliary data necessary for processing the video signals stored in the first and second buffers; An output unit for inputting the outputs of the first to fourth buffers and outputting different signals according to the content of the video signal; A first write control unit for sequentially storing the video signal for one horizontal line in the first and second buffers;
  • the video signal is a three-dimensional video signal indicating a left-eye video and a right-eye video for displaying a three-dimensional video
  • a first required for processing the left-eye video signal indicating the left-eye video Auxiliary data is stored in the third buffer
  • second auxiliary data required for processing a right-eye video signal indicating the right-eye video is stored in the fourth buffer
  • the video signal is stored in the three-dimensional
  • a second write control unit for storing, in the third buffer, third auxiliary data necessary for processing the video signal when it is not a video signal
  • the output unit in parallel with the output signal and a second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer And when the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the video signal stored in the first and second buffers A third output signal combining the above is output to the output unit.
  • a method for controlling a signal processing circuit of the present invention includes: First and second buffers for storing half the video signal for one horizontal line, and third data for storing auxiliary data required when processing the video signals stored in the first and second buffers And a fourth buffer, and a control method of a signal processing circuit having an output unit that inputs the output of the first to fourth buffers and outputs a different signal according to the content of the video signal,
  • the first writing control unit sequentially stores the video signal for one horizontal line in the first and second buffers, When the video signal is a 3D video signal indicating a left-eye video and a right-eye video for displaying a 3D video, the second writing control unit processes the left-eye video signal indicating the left-eye video.
  • First auxiliary data required at the time is stored in the third buffer, and second auxiliary data required in processing the right-eye video signal indicating the right-eye video is stored in the fourth buffer.
  • the third auxiliary data required for processing the video signal is stored in the third buffer.
  • the read control unit obtains the first auxiliary data stored in the third buffer and the video signal stored in the first buffer.
  • the combined first output signal and the second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer are parallel to each other.
  • the third auxiliary data stored in the third buffer and the first and second buffers are stored.
  • a third output signal combined with the video signal being output is output to the output unit.
  • the present invention it is possible to process a video signal to which ancillary data is added, regardless of whether the video signal is a 3D video signal or not, while suppressing an increase in the circuit scale of the signal processing circuit. Can be output to the circuit.
  • FIG. 3 It is a figure which shows the video signal of a digital cinema. It is a figure which shows the video signal in the state where Ancillary Data was added. It is a figure which shows the structure of the related signal processing circuit. 4 is a timing chart showing an operation of the signal processing circuit shown in FIG. 3. 4 is a timing chart showing a write operation to the line buffer shown in FIG. 3. FIG. 4 is a timing chart showing a read operation from the line buffer shown in FIG. 3.
  • FIG. It is a figure which shows a three-dimensional video signal. It is a figure which shows the state which isolate
  • FIG. 13 is a timing chart showing a write operation to the line buffer shown in FIG. 12.
  • FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12.
  • FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12.
  • FIG. 12 is a block diagram showing a configuration of the signal processing circuit 100 according to the embodiment of the present invention.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
  • the signal processing circuit 100 of this embodiment includes an input unit 110 and an ancillary data adding unit 120.
  • the Ancillary Data adding unit 120 includes an Ancillary Data extraction unit 121, Ancillary buffers 122-1 and 122-2, an en delay unit 123, OR circuits 124-1 to 124-3, a write control unit 125, Line buffers 128-1 and 128-2, a read control unit 129, an output unit 132, and a V Sync delay unit 133.
  • the write control unit 125 includes an address counter 126 and a Wr address comparison unit 127.
  • the read control unit 129 includes an Rd address comparison unit 130 and a head line detection unit 131.
  • the output unit 132 includes multiplexers 132-1 to 132-3.
  • the Ancillary Data extraction unit 121 is an example of a second write control unit
  • the Ancillary buffer 122-1 is an example of a third buffer
  • the Ancillary buffer 122-2 is an example of a fourth buffer.
  • the write control unit 125 is an example of a first write control unit
  • the line buffer 128-1 is an example of a first buffer
  • the line buffer 128-2 is an example of a second buffer
  • the multiplexer 132-1 is an example of a third multiplexer
  • the multiplexer 132-2 is an example of a first multiplexer
  • the multiplexer 132-3 is an example of a second multiplexer.
  • the video signal given from the signal source is input to the input unit 110.
  • the input unit 110 When the video signal is input, the input unit 110 inputs the Data signal to the Ancillary Data extraction unit 121 and the line buffers 128-1 and 128-2, and sends the Data Enable signal to the en delay unit 123 and the OR circuit 124-1. And the first line detection unit 131, the H Sync signal is input to the first line detection unit 131, the V Sync signal is input to the V Sync delay unit 133, and the 3D Left Right signal and the interlace Odd Even signal are extracted from the Ancillary Data. Input to the unit 121.
  • the input unit 110 determines whether or not the input video signal is a 3D video signal, and outputs a 3D signal indicating the determination result to the Rd address comparison unit 130, the head line detection unit 131, and the OR circuit 124-2. To enter.
  • the Ancillary Data extraction unit 121 extracts the Ancillary Data from the input signal and outputs the extracted Ancillary Data to the Ancillary buffers 122-1 and 122-2. If the input video signal is a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data necessary for processing the left-eye video signal to the Ancillary buffer 122-1, so that the right-eye video signal is output. The Ancillary Data necessary for the processing is output to the Ancillary buffer 122-2. Further, if the input video signal is not a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data to the Ancillary buffer 122-1.
  • the Ancillary buffer 122-1 stores the Ancillary Data output from the Ancillary Data extraction unit 121, and outputs it to the multiplexer 132-2.
  • the Ancillary buffer 122-2 stores the Ancillary Data output from the Ancillary Data extraction unit 121 and outputs it to the multiplexer 132-3.
  • the en delay unit 123 delays the input Data Enable signal by one line, and outputs it to the OR circuit 124-1 and the Rd address comparison unit 130 as a Delayed Data Enable signal.
  • the OR circuit 124-1 outputs a signal to the address counter 126 in response to the input of the Data Enable signal or the Delayed Data Enable signal.
  • the write controller 125 controls writing of the Data signal to the line buffers 128-1 and 128-2.
  • the address counter 126 starts counting from 0 in response to the signal output from the OR circuit 124-1, and sets the count value to the Wr address comparison unit 127, the Rd address comparison unit 130, and the line buffers 128-1 and 128-2. Output to.
  • the Wr address comparator 127 outputs a clear signal to the address counter 126 when the count value output from the address counter 126 reaches a predetermined value.
  • the Wr address comparison unit 127 outputs a Write Enable A signal indicating permission for writing to the line buffer 128-1, and outputs a Write Enable B signal indicating permission for writing to the line buffer 128-2. Output to.
  • the line buffer 128-1 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-1 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1.
  • the line buffer 128-2 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-2 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1 or the line buffer 132-3.
  • the line buffers 128-1 and 128-2 each store half of the video signal of the video area 20 for one line.
  • Read control unit 129 controls the output state of the signal from output unit 132.
  • the Rd address comparison unit 130 When the Delayed Data Enable signal is output from the en delay unit 123, the Rd address comparison unit 130 outputs the Data Enable A signal to the OR circuits 124-2 and 124-3, and the Data Enable B signal to the OR circuit 124-3. Output to.
  • the head line detection unit 131 When the video signal of the head line M is input as the Data signal, the head line detection unit 131 inputs the Insert Ancillary signal to the multiplexers 132-2 and 132-3 and the OR circuit 124-3.
  • OR circuit 124-2 outputs a signal to multiplexer 132-1 in response to the input of 3D signal or Data Enable A signal.
  • the output unit 132 combines the auxiliary data stored in the Ancillary buffers 122-1 and 122-2 and the video signal stored in the line buffers 128-1 and 128-2 in accordance with the control of the read control unit 129. , Data Left signal and Data Right signal are output.
  • the multiplexer 132-1 receives the outputs of the line buffers 128-1 and 128-2 as inputs, and selectively outputs one according to the signal output from the OR circuit 124-2.
  • the multiplexer 132-2 receives the output of the ancillary buffer 122-1 and the output of the multiplexer 132-1 as input, and selectively selects one of the data left signals according to the input of the insert ancillary signal from the head line detector 131. To the digital cinema processing circuit 300.
  • the multiplexer 132-3 receives the output of the Ancillary buffer 122-2 and the output of the line buffer 128-2 as input, and selectively selects either Data Right according to the Insert Ancillary signal input from the head line detection unit 131.
  • the signal is output to the digital cinema processing circuit 300 as a signal.
  • the OR circuit 124-3 performs digital cinema processing on the Data Enable Out signal indicating that the Data Left signal and Data Right signal are valid signals in response to the input of the Data Enable A signal, Data Enable B signal, or Insert Ancillary signal. Output to the circuit 300.
  • the V Sync delay unit 133 delays the V Sync signal input from the input unit 110 by one line, and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
  • the input unit 110 changes the Data Enable signal from Low to High.
  • the OR circuit 124-1 When the Data Enable signal transitions to High, the OR circuit 124-1 outputs a signal to the address counter 126, and the address counter 126 outputs a count value from 0 every clock according to the signal output.
  • the Wr address comparison unit 127 causes the Write Enable A signal to transition to High.
  • the line buffer 128-1 When the Write Enable A signal transitions to High, the line buffer 128-1 writes the Data signal using the count value output from the address counter 126 as the write address.
  • the Wr address comparison unit 127 outputs a clear signal to the address counter 126.
  • a data signal for one pixel is output for each clock, and the data signal is written. Therefore, between time t31 and time t32, data signals for n / 2 pixels, that is, left-eye video signals L (0), L (1), L (2)... L (n / 2-2 ), L (n / 2-1) are written into the line buffer 128-1.
  • the Wr address comparison unit 127 causes the Write Enable A signal to transition from High to Low and causes the Data Enable B signal to transition from Low to High.
  • the Write Enable A signal transitions to Low, writing to the line buffer 128-1 is completed, and when the Write Enable B signal transitions to High, writing to the line buffer 128-2 is started.
  • the address counter 126 When the clear signal is output, the address counter 126 returns the count value to zero.
  • the line buffer 128-2 When the Write Enable B signal transitions to High, the line buffer 128-2 writes the input Data signal using the count value output from the address counter 126 as a write address.
  • the video signal R (0) is output as the Data signal. Therefore, the right-eye video signals R (0), R (1), L (2)... R (n / 2-2), R (n / 2-1) are sequentially written in the line buffer 128-2. It is.
  • the Wr address comparison unit 127 When the count value reaches the predetermined value n / 2-1 again at time t33, the Wr address comparison unit 127 outputs a clear signal to the address counter 126 and changes the Write Enable B signal from Low to High. When the Write Enable B signal transitions to Low, writing to the line buffer 128-2 is completed.
  • FIG. 14 is a timing chart of each signal when the Data signal is read when the video signal is a 3D video signal.
  • the left-eye video signals L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1) are lines as the Data signal.
  • the right-eye video signals R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1) are written into the buffer 128-1, and the line buffer 128- 2 is written.
  • the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the line buffer 128-1 uses the count value as a read address, and the data buffer (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) is read and output, and the line buffer 128-2 outputs the data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1)) is read and output.
  • the Rd address comparison unit 130 simultaneously transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output.
  • the data signals (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
  • the multiplexer 132-3 also outputs the Data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / n) output from the line buffer 128-2. 2-1)) is output to the digital cinema processing circuit 300 as a Data Right signal.
  • OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal and Data Enable B signal transition to High.
  • the Data Enable Out signal transitions to High, the Data Left signal and Data Right signal output from the multiplexers 132-1 and 132-2 are treated as valid signals, and the left-eye video signals L (0), L ( 1), L (2) ... L (n / 2-2), L (n / 2-1) and right-eye video signal R (0), R (1), R (2) ... R ( n / 2-2) and R (n / 2-1) are separated and output to the digital cinema processing circuit 300.
  • the multiplexer 132-2 adds the Ancillary Data stored in the Ancillary buffer 122-1 to the left-eye video signal and outputs it to the digital cinema processing circuit 300 in response to the input of the Insert Ancillary signal. That is, the multiplexer 132-2 combines the left eye video signal stored in the line buffer 128-1 and the Ancillary Data stored in the Ancillary buffer 122-1, and digitally converts the Data Left signal as the first output signal. Output to the cinema processing circuit 300.
  • the multiplexer 132-3 adds the Ancillary Data stored in the Ancillary buffer 122-2 to the right-eye video signal in response to the input of the Insert Ancillary signal, and outputs it to the digital cinema processing circuit 300. That is, the multiplexer 132-3 combines the right eye video signal stored in the line buffer 128-2 and the Ancillary Data stored in the Ancillary buffer 122-2, and digitally converts the Data Right signal as the second output signal. Output to the cinema processing circuit 300.
  • Ancillary data is added in the same manner as the operation described with reference to FIG.
  • FIG. 15 is a timing chart of each signal when the Data signal is read when the video signal is not a 3D video signal.
  • the line buffer 128-1 includes data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1). Is written.
  • the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High.
  • the line buffer 128-1 uses the count value as a read address, and the data signal D (0), D (1), D (2)... D (n / 2-2), D (n / 2 -1) is read and output, and the line buffer 128-2 receives the data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2 ), D (n-1) is read and output.
  • the Rd address comparison unit 130 causes only the Data Enable A signal to transition from Low to High.
  • the OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output.
  • the data signals D (0), D (1), D (2)... D (n / 2-2), D (n / 2-1) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
  • the Wr address comparison unit 127 When the count value reaches n / 2-1 at time t52, the Wr address comparison unit 127 outputs a clear signal to the address counter 126, and the address counter 126 returns the count value to 0.
  • the Rd address comparison unit 130 causes the Data Enable A signal to transition from High to Low, and causes the Data Enable B signal to transition from Low to High.
  • the OR circuit 124-2 causes the signal to the multiplexer 132-1 when the Data Enable A signal transitions to Low. Stop output.
  • the multiplexer 132-1 sets the output destination of the Data signal stored in the line buffer 128-2 as the multiplexer 132-1, and is output from the line buffer 128-2.
  • Data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1) are output to the multiplexer 132-2.
  • the multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300.
  • OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal or Data Enable B signal transitions to High. By transitioning the Data Enable Out signal to High, the Data signal of the video area 20 for one line input from the multiplexer 132-2 is treated as a valid signal, and the video signal of the video area 20 for one line is combined. And output to the digital cinema processing circuit 300.
  • the Rd address comparison unit 130 causes the Data Enable A signal and the Data Enable B signal to simultaneously transition from Low to High.
  • the multiplexer 132-2 receives a data left signal that combines the left-eye video signal stored in the line buffer 128-1 and the ancillary data stored in the ancillary buffer 122-1, and the multiplexer 132-3.
  • the data right signal which is a combination of the right-eye video signal stored in the line buffer 128-2 and the ancillary data stored in the ancillary buffer 122-2, is output to the digital cinema processing circuit 300 in parallel.
  • the Rd address comparison unit 130 first transitions the Data Enable A signal and then the Data Enable B signal from Low to High. In this case, the data signal stored in each line buffer is output to the multiplexer 132-2 in the order of the line buffers 128-1 and 128-2, and combined with the ancillary data stored in the ancillary buffer 122-1. It is output to the cinema processing circuit 300.
  • the multiplexer 132-2 adds the ancillary data stored in the ancillary buffer 122-1 to the video signal stored in the line buffers 128-1 and 128-2 in response to the output of the insert ancillary signal. And output to the digital cinema processing circuit 300. That is, the multiplexer 132-2 combines the video signal stored in the line buffers 128-1 and 128-2 and the Ancillary Data stored in the Ancillary buffer 122-1, and performs digital cinema processing as a third output signal. Output to the circuit 300.
  • Ancillary data is added in the same manner as the operation described with reference to FIG.
  • the signal processing circuit 100 includes the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2, and the video signal is a 3D video signal.
  • the Ancillary Data added to the left-eye video signal is stored in the Ancillary buffer 122-1
  • the Ancillary Data added to the right-eye video signal is stored in the Ancillary buffer 122-2
  • the left-eye video signal is stored in the line buffer 128.
  • the right eye video signal is stored in the line buffer 128-2
  • the Ancillary Data stored in the Ancillary buffer 122-1 is combined with the left eye video signal stored in the line buffer 128-1.
  • Data Left signal and Ancillary Data stored in the Ancillary buffer 122-2 and Line buffer 128-2 And Data Right signal combining the right-eye image signal are, in parallel and outputs the digital cinema processing circuit 300.
  • the signal processing circuit 100 stores the Ancillary Data in the Ancillary buffer 122-1, when the video signal is not a 3D video signal, and the video of the video area 20 for one line. Signals are sequentially stored in the line buffers 128-1 and 128-2, and a signal obtained by combining the Ancillary Data stored in the Ancillary buffer 122-1 and the video signal stored in the line buffers 128-1 and 128-2. Is output to the digital cinema processing circuit 300.
  • an image signal with ancillary data is output to the digital cinema processing circuit 300 regardless of whether the video signal is a 3D video signal or not a 3D video signal while suppressing an increase in circuit scale. Can do.
  • the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2 are described as examples of independent buffers.
  • the present invention is not limited to this. It is not a thing.
  • the signal processing circuit 100 may include a buffer including a plurality of buffers among the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2.

Abstract

This signal processing circuit has: first to fourth buffers; an output unit for inputting output from the first through fourth buffers; a first write control unit for storing, in the first and second buffers, half each of a video signal from a single horizontal line; a second write control unit for storing first ancillary data in the fourth buffer in a case in which the video signal is a three-dimensional video signal, and for storing third ancillary data in the third buffer in a case in which the video signal is not a three-dimensional video signal; and a read control unit for outputting, in parallel, a signal combining the first ancillary data with the video signal stored in the first buffer, and a signal combining the second ancillary data with the video signal stored in the second buffer, in a case in which the video signals are three-dimensional video signals, and for outputting a signal combining the third ancillary data with the video signals stored in the first and second buffers in a case in which the video signals are not three-dimensional video signals.

Description

信号処理回路およびその制御方法Signal processing circuit and control method thereof
　本発明は、映像信号を出力する信号処理回路およびその制御方法に関する。 The present invention relates to a signal processing circuit that outputs a video signal and a control method thereof.
　近年、デジタル形式で映像信号を記録し、その映像信号に示される映像を表示する、いわゆるデジタルシネマが普及している。 In recent years, a so-called digital cinema that records a video signal in a digital format and displays a video indicated by the video signal has become widespread.
　デジタルシネマの映像信号に示される映像は、図１に示すように、複数の水平ライン（以下、ラインと称する）からなり、映像の外縁部から黒画像が連続するブランキングエリア１０とブランキングエリア１０以外の領域である映像エリア２０とを含む。なお、以下では、１フレームあたりの総ライン数をＹとし、映像エリア２０の先頭ラインを先頭ラインＭとし、終了ラインを終了ラインＮとする。 As shown in FIG. 1, the video shown in the video signal of the digital cinema is composed of a plurality of horizontal lines (hereinafter referred to as lines), and a blanking area 10 and a blanking area where black images are continuous from the outer edge of the video. And a video area 20 that is an area other than 10. In the following, the total number of lines per frame is Y, the top line of the video area 20 is the top line M, and the end line is the end line N.
　デジタルシネマの表示などの処理を行うデジタルシネマ処理回路に映像信号を出力する場合には、Ancillary　Dataと称される映像信号を処理する際に必要となる補助データが映像信号に付加される。デジタルシネマ処理回路は、映像信号に付加されたAncillary　Dataを用いて、その映像信号を処理し、例えば、映像信号に示される映像を表示する表示装置を駆動する。 When outputting a video signal to a digital cinema processing circuit that performs processing such as display of a digital cinema, auxiliary data necessary for processing a video signal called Ancillary Data is added to the video signal. The digital cinema processing circuit processes the video signal using the Ancillary Data added to the video signal and drives, for example, a display device that displays the video indicated by the video signal.
　図２は、Ancillary　Dataが付加された映像信号を示す図である。 FIG. 2 is a diagram showing a video signal to which Ancillary Data is added.
　図２に示すように、先頭ラインＭの１つ前のラインであるラインＭ－１にAncillary　Dataが挿入されることで、映像信号にAncillary　Dataが付加される。なお、ラインＭ－１は、ブランキングエリア１０に含まれるため、Ancillary　Dataが付加されても、１フレームあたりの総ライン数Ｙ、映像エリア２０の先頭ラインＭおよび終了ラインＮに変更はない。 As shown in FIG. 2, the ancillary data is added to the video signal by inserting the ancillary data into the line M-1 that is the line immediately before the head line M. Since the line M-1 is included in the blanking area 10, even if ancillary data is added, the total number of lines Y per frame, the first line M and the end line N of the video area 20 are not changed.
　Ancillary　Dataの付加は、デジタルシネマ処理回路に映像信号を出力する信号処理回路により行われる。このような信号処理回路の構成を図３に示す。 Ancillary data is added by a signal processing circuit that outputs a video signal to the digital cinema processing circuit. The configuration of such a signal processing circuit is shown in FIG.
　図３に示す信号処理回路２００は、入力部２１０と、Ancillary　Data付加部２２０と、を有する。 3 includes an input unit 210 and an ancillary data adding unit 220.
　また、Ancillary　Data付加部２２０は、Ancillary　Data抽出部２２１と、Ancillaryバッファ２２２と、en遅延部２２３と、OR回路２２４－１，２２４－２と、アドレスカウンタ２２５と、ラインバッファ２２６と、先頭ライン検出部２２７と、マルチプレクサ２２８と、V　Sync遅延部２２９と、を有する。 The Ancillary Data adding unit 220 includes an Ancillary Data extracting unit 221, an Ancillary buffer 222, an en delay unit 223, OR circuits 224-1 and 224-2, an address counter 225, a line buffer 226, and a head line. It has a detection unit 227, a multiplexer 228, and a V Sync delay unit 229.
　信号源から与えられた映像信号は、入力部２１０に入力される。 The video signal given from the signal source is input to the input unit 210.
　入力部２１０は、映像信号が入力されると、Data信号をAncillary　Data抽出部２２１とラインバッファ２２６とに入力し、Data　Enable信号をen遅延部２２３とOR回路２２４－１とラインバッファ２２６と先頭ライン検出部２２７とに入力し、H　Sync信号を先頭ライン検出部２２７に入力し、V　Sync信号をV　Sync遅延部２２９に入力する。 When the video signal is input, the input unit 210 inputs the Data signal to the Ancillary Data extraction unit 221 and the line buffer 226, and sends the Data Enable signal to the en delay unit 223, the OR circuit 224-1, the line buffer 226, and the head. Input to the line detection unit 227, input the H Sync signal to the leading line detection unit 227, and input the V Sync signal to the V Sync delay unit 229.
　なお、Data信号は、図１に示すライン１から順に、ライン毎の映像信号を左から右に読み出した信号である。また、Data　Enable信号は、Data信号が映像エリア２０の映像信号であるか否かを示す信号である。また、H　Sync信号は、ラインの開始タイミングを示す信号である。また、V　Sync信号は、フレームの開始タイミングを示す信号である。 The Data signal is a signal obtained by reading the video signal for each line from the left to the right in order from the line 1 shown in FIG. The Data Enable signal is a signal indicating whether or not the Data signal is a video signal of the video area 20. The H Sync signal is a signal indicating the start timing of the line. The V Sync signal is a signal indicating the start timing of the frame.
　また、入力部２１０は、3D　Left　Right信号とinterlace　Odd　Even信号とをAncillary　Data抽出部２２１に入力する。なお、3D　Left　Right信号は、三次元映像を表示するための、両眼視差を有する左目映像と右目映像とを識別するための信号である。また、interlace　Odd　Even信号は、映像信号を奇数ラインと偶数ラインとに分けてデジタルシネマ処理回路３００に出力する際に、奇数ラインおよび偶数ラインの映像信号を識別するための信号である。 Also, the input unit 210 inputs the 3D Left Right signal and the interlace Odd Even signal to the Ancillary Data extraction unit 221. The 3D Left Right signal is a signal for discriminating between a left-eye image and a right-eye image having binocular parallax for displaying a 3D image. The interlace Odd Even signal is a signal for identifying the odd-numbered and even-numbered video signals when the video signal is divided into odd-numbered lines and even-numbered lines and output to the digital cinema processing circuit 300.
　Ancillary　Data抽出部２２１は、入力された信号からAncillary　Dataを抽出し、Ancillaryバッファ２２２に出力する。なお、Ancillary　Dataの具体例としては、3D　Left　Right信号、interlace　Odd　Even信号、暗号化された映像信号の復号に用いられるキーコード（Key　Code）、フレームの表示時刻に関するタイムコード（Time　Code）などがある。 The Ancillary Data extraction unit 221 extracts Ancillary Data from the input signal and outputs it to the Ancillary buffer 222. Specific examples of Ancillary Data include 3D Left Right signal, interlace Odd Even signal, key code used to decrypt the encrypted video signal, and time code related to the frame display time. There is.
　Ancillaryバッファ２２２は、Ancillary　Data抽出部２２１から出力されたAncillary　Dataを記憶し、マルチプレクサ２２８に出力する。 The Ancillary buffer 222 stores the Ancillary Data output from the Ancillary Data extraction unit 221 and outputs it to the multiplexer 228.
　en遅延部２２３は、入力されたData　Enable信号を１ライン分遅延させ、Delayed　Data　Enable信号としてOR回路２２４－１，２２４－２に出力する。 The en delay unit 223 delays the input Data Enable signal by one line and outputs it to the OR circuits 224-1 and 224-2 as Delayed Data Enable signals.
　OR回路２２４－１は、Data　Enable信号またはDelayed　Data　Enable信号の入力に応じて、アドレスカウンタ２２５に信号を出力する。 OR circuit 224-1 outputs a signal to address counter 225 in response to the input of Data Enable signal or Delayed Data Enable signal.
　アドレスカウンタ２２５は、OR回路２２４－１からの信号出力に応じて、０からカウントを開始し、カウント値をラインバッファ２２６に出力する。 The address counter 225 starts counting from 0 in response to the signal output from the OR circuit 224-1 and outputs the count value to the line buffer 226.
　ラインバッファ２２６は、アドレスカウンタ２２５から出力されたカウント値を書き込みアドレスとしてData信号の書き込みを行う。また、ラインバッファ２２６は、アドレスカウンタ２２５から出力されたカウント値を読み出しアドレスとして、書き込んだData信号を読み出し、マルチプレクサ２２８に出力する。 The line buffer 226 writes a Data signal using the count value output from the address counter 225 as a write address. The line buffer 226 reads the written Data signal using the count value output from the address counter 225 as a read address, and outputs the read Data signal to the multiplexer 228.
　先頭ライン検出部２２７は、Data　Enable信号とH　Sync信号とに応じて、先頭ラインＭの映像信号の入力を検出すると、Ancillary　Dataを挿入する旨を示すInsert　Ancillary信号をマルチプレクサ２２８およびOR回路２２４－２に出力する。 When the start line detection unit 227 detects the input of the video signal of the start line M according to the Data Enable signal and the H Sync signal, the Insert Ancillary signal indicating that the Ancillary Data is to be inserted is sent to the multiplexer 228 and the OR circuit 224- Output to 2.
　マルチプレクサ２２８は、Ancillaryバッファ２２２の出力とラインバッファ２２６の出力とを入力とし、Insert　Ancillary信号の入力に応じて、いずれかを選択的にData　Out信号としてデジタルシネマ処理回路３００に出力する。 The multiplexer 228 receives the output of the Ancillary buffer 222 and the output of the line buffer 226 as inputs, and selectively outputs either to the digital cinema processing circuit 300 as a Data Out signal according to the input of the Insert Ancillary signal.
　V　Sync遅延部２２９は、入力されたV　Sync信号を１ライン分遅延させ、V　Sync　Out信号としてデジタルシネマ処理回路３００に出力する。 The V Sync delay unit 229 delays the input V Sync signal by one line and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
　OR回路２２４－２は、Delayed　Data　Enable信号またはInsert　Ancillary信号の入力に応じて、Data　Out信号が有効な信号であるか、すなわち、Ancillary　Dataまたは映像エリア２０の映像信号であるか否かを示すData　Enable　Out信号をデジタルシネマ処理回路３００に出力する。 The OR circuit 224-2 indicates whether the Data Out signal is a valid signal according to the input of the Delayed Data Enable signal or the Insert Ancillary signal, that is, whether it is the Ancillary Data or the video signal of the video area 20. Data Enable Out signal is output to the digital cinema processing circuit 300.
　次に、信号処理回路２００の動作について説明する。 Next, the operation of the signal processing circuit 200 will be described.
　図４は、図３に示す各信号のタイミングチャートである。 FIG. 4 is a timing chart of each signal shown in FIG.
　なお、Ancillary　Dataが、Ancillaryバッファ２２２に記憶されているものとする。 It is assumed that Ancillary Data is stored in the Ancillary buffer 222.
　時刻ｔ１１において、フレーム開始タイミングになると、入力部２１０は、V　Sync信号をＬｏｗからＨｉｇｈに遷移させる。 At time t11, when the frame start timing comes, the input unit 210 causes the V Sync signal to transition from Low to High.
　また、ライン開始タイミングになると、入力部２１０は、H　Sync信号をＨｉｇｈからＬｏｗに遷移させた後、ＬｏｗからＨｉｇｈに遷移させるとともに、ライン１から順に、ライン毎の映像信号を左から右に向かって読み出し、Data信号として入力する。なお、ライン１からラインＭ－１まではブランキングエリア１０であるため、Data　Enable信号はＬｏｗのままである。 Also, at the line start timing, the input unit 210 changes the H Sync signal from High to Low, then changes from Low to High, and in order from line 1, the video signal for each line goes from left to right. Read out and input as Data signal. Since the line 1 to the line M-1 are the blanking area 10, the Data Enable signal remains Low.
　V　Sync遅延部２２９は、時刻ｔ１１から１ライン分経過した時刻ｔ１２において、V　Sync　Out信号をＬｏｗからＨｉｇｈに遷移させる。 The V Sync delay unit 229 transitions the V Sync Out signal from Low to High at time t12 when one line has elapsed from time t11.
　時刻ｔ１３において、先頭ラインＭの映像信号がData信号として入力されたとする。ここで、図１に示すように、先頭ラインＭの映像エリア２０の左右にはブランキングエリア１０が存在する。したがって、入力部２１０は、ブランキングエリア１０の映像信号を入力している間は、Data　Enable信号をＬｏｗのままにし、時刻ｔ１４において、映像エリア２０の映像信号の入力を開始すると、Data　Enable信号をＬｏｗからＨｉｇｈに遷移させる。また、入力部２０１は、時刻ｔ１５において、映像エリア２０の映像信号の入力が終了し、再び、ブランキングエリア１０の映像信号の入力を開始すると、Data　Enable信号をＨｉｇｈからＬｏｗに遷移させる。なお、以下では、１ライン（ラインＸ）分の映像エリア２０の映像信号をData　Xとする。 Assume that the video signal of the leading line M is input as a Data signal at time t13. Here, as shown in FIG. 1, there are blanking areas 10 on the left and right of the video area 20 of the leading line M. Therefore, the input unit 210 keeps the Data Enable signal Low while the video signal of the blanking area 10 is being input, and when the input of the video signal of the video area 20 is started at time t14, the Data Enable signal. Is transitioned from Low to High. In addition, when the input of the video signal in the video area 20 is finished and the input of the video signal in the blanking area 10 is started again at time t15, the input unit 201 transitions the Data Enable signal from High to Low. In the following, the video signal of the video area 20 for one line (line X) is referred to as Data X.
　時刻ｔ１４において、Data　Enable信号がＨｉｇｈに遷移すると、ラインバッファ２２６へのData　Mの書き込みが行われる。この書き込み動作について図５を参照して説明する。なお、図５において、図４と同時刻については同じ符号を付す。 When the Data Enable signal transitions to High at time t14, Data M is written to the line buffer 226. This write operation will be described with reference to FIG. In FIG. 5, the same reference numerals are assigned to the same times as in FIG.
　時刻ｔ１４において、Data　Enable信号がＨｉｇｈに遷移すると、OR回路２２４－１は、アドレスカウンタ２２５に信号を出力し、アドレスカウンタ２２５は、その信号出力に応じて、１クロック毎に、０からカウント値をラインバッファ２２６に出力する。 At time t14, when the Data Enable signal transitions to High, the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 counts from 0 every clock according to the signal output. Is output to the line buffer 226.
　Data　Enable信号がＨｉｇｈに遷移すると、書き込み許可を示すWrite　Enable信号がＬｏｗからＨｉｇｈに遷移し、ラインバッファ２２６は、アドレスカウンタ２２５から出力されたカウント値を書き込みアドレスとして、Data信号の書き込みを行う。 When the Data Enable signal transitions to High, the Write Enable signal indicating write permission transitions from Low to High, and the line buffer 226 writes the Data signal using the count value output from the address counter 225 as the write address.
　ここで、１ライン分の映像エリア２０がｎピクセルであるとし、入力部２１０からは、１クロック毎に１ピクセル分の映像信号がData信号として入力されるとする。 Here, it is assumed that the video area 20 for one line is n pixels, and a video signal for one pixel is input from the input unit 210 as a Data signal every clock.
　映像エリア２０の映像信号が入力されている間、Data　Enable信号はＨｉｇｈとなり、アドレスカウンタ２２５は、カウンタ値を出力する。したがって、アドレスカウンタ２２５は、０からｎ－１までカウント値を出力し、ラインバッファ２２６は、そのカウント値を書き込みアドレスとして、各ピクセルの映像信号の書き込みを行う。 While the video signal of the video area 20 is being input, the Data Enable signal is High, and the address counter 225 outputs the counter value. Therefore, the address counter 225 outputs a count value from 0 to n−1, and the line buffer 226 writes the video signal of each pixel using the count value as a write address.
　時刻ｔ１５において、先頭ラインＭの映像エリア２０の映像信号の入力が終了し、Data　Enable信号がＨｉｇｈからＬｏｗに遷移すると、Write　Enable信号もＬｏｗに遷移し、Data信号の書き込みが終了する。 At time t15, when the input of the video signal of the video area 20 of the first line M is completed and the Data Enable signal transitions from High to Low, the Write Enable signal also transitions to Low, and the writing of the Data signal is completed.
　再び、図４を参照すると、先頭ライン検出部２２７は、V　Sync信号がＨｉｇｈに遷移した後、初めてData　Enable信号がＬｏｗからＨｉｇｈに遷移した時刻ｔ１４から、次にData　Enable信号がＨｉｇｈからＬｏｗに遷移する時刻ｔ１５までの間、Insert　Ancillary信号をＬｏｗからＨｉｇｈに遷移させる。 Referring to FIG. 4 again, after the V Sync signal transitions to High, the head line detection unit 227 starts from the time t14 when the Data Enable signal transitions from Low to High for the first time, and then the Data Enable signal transitions from High to Low. Until the transition time t15, the Insert Ancillary signal is transitioned from Low to High.
　Insert　Ancillary信号がＨｉｇｈに遷移している間、マルチプレクサ２２８は、Ancillaryバッファ２２２をData　Out信号の出力元として選択し、Ancillaryバッファ２２２に記憶されているAncillary　DataをData　Out信号としてデジタルシネマ処理回路３００に出力する。 While the Insert Ancillary signal transitions to High, the multiplexer 228 selects the Ancillary buffer 222 as the output source of the Data Out signal, and the digital cinema processing circuit 300 uses the Ancillary Data stored in the Ancillary buffer 222 as the Data Out signal. Output to.
　時刻ｔ１５において、Insert　Ancillary信号がＬｏｗに遷移すると、マルチプレクサ２２８は、ラインバッファ２２６をData　Out信号の出力元として選択する。 When the Insert Ancillary signal transitions to Low at time t15, the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal.
　時刻ｔ１４から１ライン分経過後の時刻ｔ１６から時刻ｔ１７までの間、en遅延部２２３は、Delayed　Data　Enable信号をＬｏｗからＨｉｇｈに遷移させる。なお、時刻ｔ１６から時刻１７までの時間は、時刻ｔ１４から時刻ｔ１５までの時間と同じである。 From time t16 to time t17 after the elapse of one line from time t14, the en delay unit 223 transitions the Delayed Data Enable signal from Low to High. The time from time t16 to time 17 is the same as the time from time t14 to time t15.
　Delayed　Data　Enable信号がＨｉｇｈに遷移すると、OR回路２２４－１は、アドレスカウンタ２２５に信号を出力し、アドレスカウンタ２２５は、その信号出力に応じて、０からカウント値をラインバッファ２２６に出力する。 When the Delayed Data Enable signal transitions to High, the OR circuit 224-1 outputs a signal to the address counter 225, and the address counter 225 outputs a count value from 0 to the line buffer 226 according to the signal output.
　カウント値が出力されると、ラインバッファ２２６に書き込まれたData信号の読み出しが行われる。この読み出し動作について図６を参照して説明する。なお。図６において、図４と同時刻については同じ符号を付す。 When the count value is output, the Data signal written in the line buffer 226 is read. This read operation will be described with reference to FIG. Note that. In FIG. 6, the same reference numerals are assigned to the same times as in FIG.
　アドレスカウンタ２２５は、０からカウント値を出力し、ラインバッファ２２６は、そのカウント値を読み出しアドレスとして、書き込んだData信号（Data　M）を読み出し、マルチプレクサ２２８に出力する。 The address counter 225 outputs a count value from 0, and the line buffer 226 reads the written Data signal (Data M) using the count value as a read address and outputs it to the multiplexer 228.
　なお、時刻ｔ１６から時刻ｔ１７までの間には、Data信号としてData　M+1が入力される。ラインバッファ２２６は、Data　Mを読み出して、マルチプレクサ２２８に出力するとともに、Data　M+1の書き込みを行う。 Note that Data M + 1 is input as the Data signal between time t16 and time t17. The line buffer 226 reads Data M, outputs it to the multiplexer 228, and writes Data M + 1.
　再び、図４を参照すると、上述したように、マルチプレクサ２２８は、ラインバッファ２２６をData　Out信号の出力元として選択しているので、ラインバッファ２２６から出力されたData　Mは、Data　Out信号としてデジタルシネマ処理回路３００に出力される。 Referring to FIG. 4 again, as described above, since the multiplexer 228 selects the line buffer 226 as the output source of the Data Out signal, the Data M output from the line buffer 226 is digitally output as the Data Out signal. It is output to the cinema processing circuit 300.
　Data　Mは、時刻ｔ１４で入力が開始された後、１ライン分遅延した時刻ｔ１６において、Data　Out信号として出力されている。しかし、V　Sync信号が１ライン分遅延されているので、１フレームの総ライン数Ｙ、映像エリア２０の先頭ラインＭ、終了ラインＮを変更することなく、Ancillary　Dataを付加した映像信号をデジタルシネマ処理回路３００に出力することができる。 Data M is output as a Data Out signal at time t16 delayed by one line after input is started at time t14. However, since the V Sync signal is delayed by one line, the video signal with ancillary data added to the digital cinema without changing the total number of lines Y per frame, the top line M and the end line N of the video area 20 It can be output to the processing circuit 300.
　ところで、特許文献１（特開２０１０－６８３０９号公報）には、左目映像と右目映像とを合成して表示することで、三次元映像を表示する技術が開示されている。また、特許文献１には、上述したような三次元映像を表示するための映像信号として、図７に示すように、映像エリア２０を左側エリア２１と右側エリア２２とに分け、左側エリア２１に左目映像を示す左目映像信号を格納し、右側エリア２２に右目映像を示す右目映像信号を格納した、いわゆる、サイド・バイ・サイド方式の映像信号が開示されている。以下では、サイド・バイ・サイド方式の映像信号を、三次元映像信号と称する。 Incidentally, Patent Document 1 (Japanese Patent Laid-Open No. 2010-68309) discloses a technique for displaying a three-dimensional image by combining and displaying a left-eye image and a right-eye image. In Patent Document 1, as a video signal for displaying a 3D video as described above, the video area 20 is divided into a left area 21 and a right area 22 as shown in FIG. A so-called side-by-side video signal is disclosed in which a left-eye video signal indicating a left-eye video is stored and a right-eye video signal indicating a right-eye video is stored in the right area 22. Hereinafter, a side-by-side video signal is referred to as a 3D video signal.
　三次元映像信号をデジタルシネマ処理回路に入力する場合には、図８に示すように、左目映像信号と右目映像信号とを分離し、分離したそれぞれの映像信号にAncillary　Dataを付加する必要がある。上述した、映像信号の分離、および、Ancillary　Dataの付加を行う信号処理回路の構成の概略を図９に示す。なお、図９において、図３と同様の構成については同じ符号を付し、説明を省略する。 When inputting a 3D video signal to the digital cinema processing circuit, as shown in FIG. 8, it is necessary to separate the left-eye video signal and the right-eye video signal and add ancillary data to each separated video signal. . FIG. 9 shows an outline of the configuration of the signal processing circuit for separating the video signal and adding the ancillary data described above. In FIG. 9, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
　図９に示す信号処理回路４００は、入力部２１０、分離部４１０と、２つのAncillary　Data付加部２２０－１，２２０－２と、を有する。 The signal processing circuit 400 shown in FIG. 9 has an input unit 210, a separation unit 410, and two ancillary data addition units 220-1 and 220-2.
　分離部４１０は、入力部２１０から三次元映像信号が入力されると、左目映像信号と右目映像信号とに分離し、左目映像信号をAncillary　Data付加部２２０－１に出力し、右目映像信号をAncillary　Data付加部２２０－２に出力する。 When the 3D video signal is input from the input unit 210, the separation unit 410 separates the left-eye video signal and the right-eye video signal, outputs the left-eye video signal to the Ancillary Data adding unit 220-1, and outputs the right-eye video signal. Output to Ancillary Data adder 220-2.
　Ancillary　Data付加部２２０－１は、分離部４１０から出力された左目映像信号に、その左目映像信号を処理する際に必要となるAncillary　Dataを付加し、デジタルシネマ処理回路３００に出力する。 The Ancillary Data adding unit 220-1 adds the Ancillary Data necessary for processing the left-eye video signal to the left-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
　また、Ancillary　Data付加部２２０－２は、分離部４１０から出力された右目映像信号に、その右目映像信号を処理する際に必要となるAncillary　Dataを付加し、デジタルシネマ処理回路３００に出力する。 Also, the Ancillary Data adding unit 220-2 adds the Ancillary Data necessary for processing the right-eye video signal to the right-eye video signal output from the separation unit 410, and outputs it to the digital cinema processing circuit 300.
　次に、分離部４１０の構成について説明する。 Next, the configuration of the separation unit 410 will be described.
　図１０は、分離部４１０の構成を示すブロック図である。 FIG. 10 is a block diagram showing a configuration of the separation unit 410.
　図１０に示す分離部４１０は、アドレスカウンタ４１１と、アドレス比較部４１２と、ラインバッファ４１３と、を有する。 10 includes an address counter 411, an address comparison unit 412, and a line buffer 413.
　信号源から与えられた映像信号が入力部２１０に入力され、入力部２１０は、映像信号が入力されると、Data信号をラインバッファ４１３に入力し、Data　Enable信号をアドレスカウンタ４１１とアドレス比較部４１２とに入力する。また、Data信号はそのまま、Data　Right信号として、Ancillary　Data付加部２２０－２に出力される。 The video signal given from the signal source is input to the input unit 210. When the video signal is input, the input unit 210 inputs the Data signal to the line buffer 413, and sends the Data Enable signal to the address counter 411 and the address comparison unit. 412. Further, the Data signal is output as it is to the Ancillary Data adding unit 220-2 as a Data Right signal.
　アドレスカウンタ４１１は、Data　Enable信号が入力されると、０からカウントを開始し、カウント値をアドレス比較部４１２およびラインバッファ４１３に出力する。 When the Data Enable signal is input, the address counter 411 starts counting from 0 and outputs the count value to the address comparison unit 412 and the line buffer 413.
　アドレス比較部４１２は、アドレスカウンタ４１１から出力されたカウント値が所定値に達すると、カウント値を０に戻すclear信号をアドレスカウンタ４１１に出力する。 When the count value output from the address counter 411 reaches a predetermined value, the address comparison unit 412 outputs a clear signal for returning the count value to 0 to the address counter 411.
　また、アドレス比較部４１２は、Data　Enable信号が入力されると、Write　Enable信号をラインバッファ４１３に出力し、Data　Enable　Out信号をAncillary　Data付加部２２０－１，２２０－２に出力する。 In addition, when the Data Enable signal is input, the address comparison unit 412 outputs a Write Enable signal to the line buffer 413 and outputs a Data Enable Out signal to the Ancillary Data adding units 220-1 and 220-2.
　ラインバッファ４１３は、アドレス比較部４１２からWrite　Enable信号が出力されると、アドレスカウンタ４１１から出力されたカウント値を書き込みアドレスとしてData信号の書き込みを行う。また、ラインバッファ４１３は、アドレスカウンタ４１１から出力されたカウント値を読み出しアドレスとして、書き込んだData信号を読み出し、Data　Left信号としてAncillary　Data付加部２２０－１に出力する。 When the Write Enable signal is output from the address comparison unit 412, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. Also, the line buffer 413 reads the written Data signal using the count value output from the address counter 411 as a read address, and outputs it to the Ancillary Data adding unit 220-1 as a Data Left signal.
　次に、分離部４１０の動作について説明する。 Next, the operation of the separation unit 410 will be described.
　図１１は、図１０に示す各信号のタイミングチャートである。 FIG. 11 is a timing chart of each signal shown in FIG.
　なお、以下では、１ライン分の左目映像および右目映像をそれぞれｎピクセルとし、左目映像信号をL(0),L(1),L(2)・・・L(n-2),L(n-1)とし、右目映像信号をR(0),R(1),R(2)・・・R(n-2),R(n-1)とする。 In the following, the left-eye video and the right-eye video for one line are each n pixels, and the left-eye video signal is L (0), L (1), L (2)... L (n-2), L ( n-1), and the right-eye video signals are R (0), R (1), R (2)... R (n-2), R (n-1).
　時刻ｔ２１において、入力部２１０は、映像エリア２０の映像信号の入力を開始すると、１ライン分の左目映像信号L(0),L(1),L(2)・・・L(n-2),L(n-1)および右目映像信号R(0),R(1),R(2)・・・R(n-2),R(n-1)を順に、１クロック毎に、１ピクセル分ずつ、Data信号として出力するとともに、Data　Enable信号をＬｏｗからＨｉｇｈに遷移させる。 At time t21, when the input unit 210 starts to input the video signal of the video area 20, the left-eye video signals L (0), L (1), L (2)... L (n−2) for one line. ), L (n-1) and right-eye video signals R (0), R (1), R (2) ... R (n-2), R (n-1) in order, every clock, Each pixel is output as a Data signal, and the Data Enable signal is changed from Low to High.
　Data　Enable信号がＨｉｇｈに遷移すると、アドレスカウンタ４１１は、１クロック毎に、０からカウント値をアドレス比較部４１２およびラインバッファ４１３に出力する。また、アドレス比較部４１２は、Write　Enable信号をＬｏｗからＨｉｇｈに遷移させる。なお、Data　Enable　Out信号はＬｏｗのままである。 When the Data Enable signal transitions to High, the address counter 411 outputs a count value from 0 to the address comparison unit 412 and the line buffer 413 every clock. Further, the address comparison unit 412 changes the Write Enable signal from Low to High. Note that the Data Enable Out signal remains Low.
　Write　Enable信号がＨｉｇｈに遷移すると、ラインバッファ４１３は、アドレスカウンタ４１１から出力されたカウント値を書き込みアドレスとして、Data信号の書き込みを行う。なお、上述したように、Data信号がData　Right信号としてAncillary　Data付加部２２０－２に出力されるが、Data　Enable　Out信号がＬｏｗであるので、有効な信号としては取り扱われない。 When the Write Enable signal transitions to High, the line buffer 413 writes the Data signal using the count value output from the address counter 411 as the write address. As described above, the Data signal is output as the Data Right signal to the Ancillary Data adding unit 220-2. However, since the Data Enable Out signal is Low, it is not handled as an effective signal.
　アドレス比較部４１２は、カウント値が所定値ｎ－１に達すると、clear信号を出力する。したがって、カウント値がｎ－１に達するまでに、左目映像信号L(0),L(1),L(2)・・・L(n-2),L(n-1)が、ラインバッファ４１３に書き込まれる。 The address comparison unit 412 outputs a clear signal when the count value reaches a predetermined value n-1. Therefore, by the time the count value reaches n-1, the left-eye video signals L (0), L (1), L (2)... L (n-2), L (n-1) 413 is written.
　時刻ｔ２２において、カウント値が所定値ｎ－１に達すると、アドレス比較部４１２は、clear信号をアドレスカウンタ４１１に出力するとともに、Write　Enable信号をＨｉｇｈからＬｏｗに遷移させ、Data　Enable　Out信号をＬｏｗからＨｉｇｈに遷移させる。 When the count value reaches the predetermined value n−1 at time t22, the address comparison unit 412 outputs a clear signal to the address counter 411, transitions the Write Enable signal from High to Low, and sets the Data Enable Out signal to Low. Transition from to High.
　clear信号が出力されると、アドレスカウンタ４１１は、カウント値を０に戻す。 When the clear signal is output, the address counter 411 returns the count value to zero.
　Write　Enable信号がＬｏｗに遷移すると、ラインバッファ４１３は、アドレス比較部４１２から出力されたカウント値を読み出しアドレスとして、書き込みを行った左目映像信号L(0),L(1),L(2)・・・L(n-2),L(n-1)を読み出し、Data　Left信号としてAncillary　Data付加部２２０－１に出力する。 When the Write Enable signal transitions to Low, the line buffer 413 uses the count value output from the address comparison unit 412 as a read address, and writes the left-eye video signals L (0), L (1), and L (2) that have been written. ... L (n-2) and L (n-1) are read and output to the Ancillary Data adder 220-1 as Data Left signals.
　また、Ancillary　Data付加部２２０－２には、Data信号がそのままData　Right信号として出力される。ここで、時刻ｔ２２からは、右目映像信号R(0),R(1),R(2)・・・R(n-2),R(n-1)が入力されるので、Ancillary　Data付加部２２０－２には、右目映像信号がData　Right信号として出力される。 Also, the Data signal is output as is to the Ancillary Data adding unit 220-2 as a Data Right signal. Here, from time t22, right eye video signals R (0), R (1), R (2)... R (n-2), R (n-1) are input, so ancillary data is added. The right eye video signal is output as a Data Right signal to the unit 220-2.
　上述したように、Data　Enable　Out信号はＨｉｇｈに遷移しているので、Data　Left信号として出力された左目映像信号およびData　Right信号として出力された右目映像信号は、有効な信号として取り扱われる。したがって、分離部４１０によれば、左目映像信号と右目映像信号とを分離して、Ancillary　Data付加部２２０－１，２２０－２に出力することができる。 As described above, since the Data Enable Out signal transitions to High, the left-eye video signal output as the Data Left signal and the right-eye video signal output as the Data Right signal are handled as valid signals. Therefore, the separating unit 410 can separate the left-eye video signal and the right-eye video signal and output them to the Ancillary Data adding units 220-1 and 220-2.
特開２０１０－６８３０９号公報JP 2010-68309 A
　しかしながら、図６に示す信号処理回路４００においては、三次元映像信号をデジタルシネマ処理回路３００に出力するために、分離部４１０と２つのAncillary　Data付加部２２０－１，２２０－２とが必要となり、回路規模が増大するという課題がある。 However, in the signal processing circuit 400 shown in FIG. 6, in order to output the 3D video signal to the digital cinema processing circuit 300, the separation unit 410 and the two Ancillary Data addition units 220-1 and 220-2 are required. There is a problem that the circuit scale increases.
　本発明は、上述した課題を解決することができる信号処理回路およびその制御方法を提供することにある。 It is an object of the present invention to provide a signal processing circuit and a control method thereof that can solve the above-described problems.
　上記目的を達成するために本発明の信号処理回路は、
　１水平ライン分の半分の映像信号を記憶する第１および第２のバッファと、
　前記第１および第２のバッファに記憶された映像信号を処理する際に必要となる補助データを記憶する第３および第４のバッファと、
　前記第１乃至第４のバッファの出力を入力し、映像信号の内容に応じて異なる信号を出力する出力部と、
　１水平ライン分の前記映像信号を前記第１および第２のバッファに順次記憶させる第１の書き込み制御部と、
　前記映像信号が、三次元映像を表示するための左目映像と右目映像とを示す三次元映像信号である場合には、前記左目映像を示す左目映像信号を処理する際に必要となる第１の補助データを前記第３のバッファに記憶させ、前記右目映像を示す右目映像信号を処理する際に必要となる第２の補助データを前記第４のバッファに記憶させ、前記映像信号が前記三次元映像信号でない場合には、前記映像信号を処理する際に必要となる第３の補助データを前記第３のバッファに記憶させる第２の書き込み制御部と、
　前記出力部の出力状態を制御する読み出し制御部と、を有し、
　前記読み出し制御部は、
　前記映像信号が前記三次元映像信号である場合には、前記第３のバッファに記憶されている第１の補助データと前記第１のバッファに記憶されている映像信号とを組み合わせた第１の出力信号と、前記第４のバッファに記憶されている第２の補助データと前記第２のバッファに記憶されている映像信号とを組み合わせた第２の出力信号と、を並行して前記出力部に出力させ、前記映像信号が前記三次元映像信号でない場合には、前記第３のバッファに記憶されている第３の補助データと前記第１および第２のバッファに記憶されている映像信号とを組み合わせた第３の出力信号を前記出力部に出力させる。 In order to achieve the above object, the signal processing circuit of the present invention comprises:
First and second buffers for storing half the video signal for one horizontal line;
Third and fourth buffers for storing auxiliary data necessary for processing the video signals stored in the first and second buffers;
An output unit for inputting the outputs of the first to fourth buffers and outputting different signals according to the content of the video signal;
A first write control unit for sequentially storing the video signal for one horizontal line in the first and second buffers;
When the video signal is a three-dimensional video signal indicating a left-eye video and a right-eye video for displaying a three-dimensional video, a first required for processing the left-eye video signal indicating the left-eye video Auxiliary data is stored in the third buffer, second auxiliary data required for processing a right-eye video signal indicating the right-eye video is stored in the fourth buffer, and the video signal is stored in the three-dimensional A second write control unit for storing, in the third buffer, third auxiliary data necessary for processing the video signal when it is not a video signal;
A read control unit for controlling the output state of the output unit,
The read control unit
When the video signal is the 3D video signal, a first combination of the first auxiliary data stored in the third buffer and the video signal stored in the first buffer is used. The output unit in parallel with the output signal and a second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer And when the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the video signal stored in the first and second buffers A third output signal combining the above is output to the output unit.
　上記目的を達成するために本発明の信号処理回路の制御方法は、
　１水平ライン分の半分の映像信号を記憶する第１および第２のバッファと、前記第１および第２のバッファに記憶された映像信号を処理する際に必要となる補助データを記憶する第３および第４のバッファと、前記第１乃至第４のバッファの出力を入力し、映像信号の内容に応じて異なる信号を出力する出力部と、を有する信号処理回路の制御方法であって、
　第１の書き込み制御部が、１水平ライン分の前記映像信号を前記第１および第２のバッファに順次記憶させ、
　第２の書き込み制御部が、前記映像信号が、三次元映像を表示するための左目映像と右目映像とを示す三次元映像信号である場合には、前記左目映像を示す左目映像信号を処理する際に必要となる第１の補助データを前記第３のバッファに記憶させ、前記右目映像を示す右目映像信号を処理する際に必要となる第２の補助データを前記第４のバッファに記憶させ、前記映像信号が前記三次元映像信号でない場合には、前記映像信号を処理する際に必要となる第３の補助データを前記第３のバッファに記憶させ、
　読み出し制御部が、前記映像信号が前記三次元映像信号である場合には、前記第３のバッファに記憶されている第１の補助データと前記第１のバッファに記憶されている映像信号とを組み合わせた第１の出力信号と、前記第４のバッファに記憶されている第２の補助データと前記第２のバッファに記憶されている映像信号とを組み合わせた第２の出力信号と、を並行して前記出力部に出力させ、前記映像信号が前記三次元映像信号でない場合には、前記第３のバッファに記憶されている第３の補助データと前記第１および第２のバッファに記憶されている映像信号とを組み合わせた第３の出力信号を前記出力部に出力させる。 In order to achieve the above object, a method for controlling a signal processing circuit of the present invention includes:
First and second buffers for storing half the video signal for one horizontal line, and third data for storing auxiliary data required when processing the video signals stored in the first and second buffers And a fourth buffer, and a control method of a signal processing circuit having an output unit that inputs the output of the first to fourth buffers and outputs a different signal according to the content of the video signal,
The first writing control unit sequentially stores the video signal for one horizontal line in the first and second buffers,
When the video signal is a 3D video signal indicating a left-eye video and a right-eye video for displaying a 3D video, the second writing control unit processes the left-eye video signal indicating the left-eye video. First auxiliary data required at the time is stored in the third buffer, and second auxiliary data required in processing the right-eye video signal indicating the right-eye video is stored in the fourth buffer. , If the video signal is not the 3D video signal, the third auxiliary data required for processing the video signal is stored in the third buffer,
When the video signal is the 3D video signal, the read control unit obtains the first auxiliary data stored in the third buffer and the video signal stored in the first buffer. The combined first output signal and the second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer are parallel to each other. When the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the first and second buffers are stored. A third output signal combined with the video signal being output is output to the output unit.
　本発明によれば、信号処理回路の回路規模の増大を抑制しつつ、映像信号が三次元映像信号である場合にも、三次元映像信号でない場合にも、Ancillary　Dataを付加した映像信号を処理回路に出力することができる。 According to the present invention, it is possible to process a video signal to which ancillary data is added, regardless of whether the video signal is a 3D video signal or not, while suppressing an increase in the circuit scale of the signal processing circuit. Can be output to the circuit.
デジタルシネマの映像信号を示す図である。It is a figure which shows the video signal of a digital cinema. Ancillary　Dataが付加された状態の映像信号を示す図である。It is a figure which shows the video signal in the state where Ancillary Data was added. 関連する信号処理回路の構成を示す図である。It is a figure which shows the structure of the related signal processing circuit. 図３に示す信号処理回路の動作を示すタイミングチャートである。4 is a timing chart showing an operation of the signal processing circuit shown in FIG. 3. 図３に示すラインバッファへの書き込み動作を示すタイミングチャートである。4 is a timing chart showing a write operation to the line buffer shown in FIG. 3. 図３に示すラインバッファからの読み出し動作を示すタイミングチャートである。FIG. 4 is a timing chart showing a read operation from the line buffer shown in FIG. 3. FIG. 三次元映像信号を示す図である。It is a figure which shows a three-dimensional video signal. 三次元映像信号を分離した状態を示す図である。It is a figure which shows the state which isolate | separated the three-dimensional video signal. 関連する信号処理回路の他の構成の概略を示す図である。It is a figure which shows the outline of the other structure of the related signal processing circuit. 図９に示す分離部の構成を示すブロック図である。It is a block diagram which shows the structure of the isolation | separation part shown in FIG. 図１０に示す分離部の動作を示すタイミングチャートである。It is a timing chart which shows operation | movement of the isolation | separation part shown in FIG. 本発明の一実施形態の信号処理回路の構成を示すブロック図である。It is a block diagram which shows the structure of the signal processing circuit of one Embodiment of this invention. 図１２に示すラインバッファへの書き込み動作を示すタイミングチャートである。13 is a timing chart showing a write operation to the line buffer shown in FIG. 12. 図１２に示すラインバッファからの読み出し動作を示すタイミングチャートである。FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12. 図１２に示すラインバッファからの読み出し動作を示すタイミングチャートである。FIG. 13 is a timing chart showing a read operation from the line buffer shown in FIG. 12.
　以下に、本発明を実施するための形態について図面を参照して説明する。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
　図１２は、本発明の一実施形態の信号処理回路１００の構成を示すブロック図である。なお、図１２において、図３と同様の構成については同じ符号を付し、説明を省略する。 FIG. 12 is a block diagram showing a configuration of the signal processing circuit 100 according to the embodiment of the present invention. In FIG. 12, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
　図１２に示すように、本実施形態の信号処理回路１００は、入力部１１０と、Ancillary　Data付加部１２０と、を有する。 As shown in FIG. 12, the signal processing circuit 100 of this embodiment includes an input unit 110 and an ancillary data adding unit 120.
　また、Ancillary　Data付加部１２０は、Ancillary　Data抽出部１２１と、Ancillaryバッファ１２２－１，１２２－２と、en遅延部１２３と、OR回路１２４－１～１２４－３と、書き込み制御部１２５と、ラインバッファ１２８－１，１２８－２と、読み出し制御部１２９と、出力部１３２と、V　Sync遅延部１３３と、を有する。 The Ancillary Data adding unit 120 includes an Ancillary Data extraction unit 121, Ancillary buffers 122-1 and 122-2, an en delay unit 123, OR circuits 124-1 to 124-3, a write control unit 125, Line buffers 128-1 and 128-2, a read control unit 129, an output unit 132, and a V Sync delay unit 133.
　また、書き込み制御部１２５は、アドレスカウンタ１２６と、Wrアドレス比較部１２７と、を有する。 In addition, the write control unit 125 includes an address counter 126 and a Wr address comparison unit 127.
　また、読み出し制御部１２９は、Rdアドレス比較部１３０と、先頭ライン検出部１３１と、を有する。 In addition, the read control unit 129 includes an Rd address comparison unit 130 and a head line detection unit 131.
　また、出力部１３２は、マルチプレクサ１３２－１～１３２－３を有する。 The output unit 132 includes multiplexers 132-1 to 132-3.
　なお、Ancillary　Data抽出部１２１は、第２の書き込み制御部の一例であり、Ancillaryバッファ１２２－１は、第３のバッファの一例であり、Ancillaryバッファ１２２－２は、第４のバッファ一例であり、書き込み制御部１２５は、第１の書き込み制御部の一例であり、ラインバッファ１２８－１は、第１のバッファの一例であり、ラインバッファ１２８－２は、第２のバッファの一例であり、マルチプレクサ１３２－１は、第３のマルチプレクサの一例であり、マルチプレクサ１３２－２は、第１のマルチプレクサの一例であり、マルチプレクサ１３２－３は、第２のマルチプレクサの一例である。 The Ancillary Data extraction unit 121 is an example of a second write control unit, the Ancillary buffer 122-1 is an example of a third buffer, and the Ancillary buffer 122-2 is an example of a fourth buffer. The write control unit 125 is an example of a first write control unit, the line buffer 128-1 is an example of a first buffer, the line buffer 128-2 is an example of a second buffer, The multiplexer 132-1 is an example of a third multiplexer, the multiplexer 132-2 is an example of a first multiplexer, and the multiplexer 132-3 is an example of a second multiplexer.
　信号源から与えられる映像信号は、入力部１１０に入力される。 The video signal given from the signal source is input to the input unit 110.
　入力部１１０は、映像信号が入力されると、Data信号をAncillary　Data抽出部１２１とラインバッファ１２８－１，１２８－２とに入力し、Data　Enable信号をen遅延部１２３とOR回路１２４－１と先頭ライン検出部１３１とに入力し、H　Sync信号を先頭ライン検出部１３１に入力し、V　Sync信号をV　Sync遅延部１３３に入力し、3D　Left　Right信号およびinterlace　Odd　Even信号をAncillary　Data抽出部１２１に入力する。 When the video signal is input, the input unit 110 inputs the Data signal to the Ancillary Data extraction unit 121 and the line buffers 128-1 and 128-2, and sends the Data Enable signal to the en delay unit 123 and the OR circuit 124-1. And the first line detection unit 131, the H Sync signal is input to the first line detection unit 131, the V Sync signal is input to the V Sync delay unit 133, and the 3D Left Right signal and the interlace Odd Even signal are extracted from the Ancillary Data. Input to the unit 121.
　また、入力部１１０は、入力する映像信号が三次元映像信号であるか否かを判定し、判定結果を示す3D信号をRdアドレス比較部１３０と先頭ライン検出部１３１とOR回路１２４－２とに入力する。 Further, the input unit 110 determines whether or not the input video signal is a 3D video signal, and outputs a 3D signal indicating the determination result to the Rd address comparison unit 130, the head line detection unit 131, and the OR circuit 124-2. To enter.
　Ancillary　Data抽出部１２１は、入力された信号からAncillary　Dataを抽出し、抽出したAncillary　DataをAncillaryバッファ１２２－１，１２２－２に出力する。なお、Ancillary　Data抽出部１２１は、入力する映像信号が三次元映像信号である場合には、左目映像信号を処理する際に必要となるAncillary　DataをAncillaryバッファ１２２－１に出力し、右目映像信号の処理する際に必要となるAncillary　DataをAncillaryバッファ１２２－２に出力する。また、Ancillary　Data抽出部１２１は、入力する映像信号が三次元映像信号でない場合には、Ancillary　DataをAncillaryバッファ１２２－１に出力する。 The Ancillary Data extraction unit 121 extracts the Ancillary Data from the input signal and outputs the extracted Ancillary Data to the Ancillary buffers 122-1 and 122-2. If the input video signal is a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data necessary for processing the left-eye video signal to the Ancillary buffer 122-1, so that the right-eye video signal is output. The Ancillary Data necessary for the processing is output to the Ancillary buffer 122-2. Further, if the input video signal is not a 3D video signal, the Ancillary Data extraction unit 121 outputs the Ancillary Data to the Ancillary buffer 122-1.
　Ancillaryバッファ１２２－１は、Ancillary　Data抽出部１２１から出力されたAncillary　Dataを記憶し、マルチプレクサ１３２－２に出力する。 The Ancillary buffer 122-1 stores the Ancillary Data output from the Ancillary Data extraction unit 121, and outputs it to the multiplexer 132-2.
　Ancillaryバッファ１２２－２は、Ancillary　Data抽出部１２１から出力されたAncillary　Dataを記憶し、マルチプレクサ１３２－３に出力する。 The Ancillary buffer 122-2 stores the Ancillary Data output from the Ancillary Data extraction unit 121 and outputs it to the multiplexer 132-3.
　en遅延部１２３は、入力されたData　Enable信号を１ライン分遅延させ、Delayed　Data　Enable信号としてOR回路１２４－１およびRdアドレス比較部１３０に出力する。 The en delay unit 123 delays the input Data Enable signal by one line, and outputs it to the OR circuit 124-1 and the Rd address comparison unit 130 as a Delayed Data Enable signal.
　OR回路１２４－１は、Data　Enable信号またはDelayed　Data　Enable信号の入力に応じて、アドレスカウンタ１２６に信号を出力する。 The OR circuit 124-1 outputs a signal to the address counter 126 in response to the input of the Data Enable signal or the Delayed Data Enable signal.
　書き込み制御部１２５は、ラインバッファ１２８－１，１２８－２へのData信号の書き込みを制御する。 The write controller 125 controls writing of the Data signal to the line buffers 128-1 and 128-2.
　アドレスカウンタ１２６は、OR回路１２４－１からの信号出力に応じて、０からカウントを開始し、カウント値をWrアドレス比較部１２７とRdアドレス比較部１３０とラインバッファ１２８－１，１２８－２とに出力する。 The address counter 126 starts counting from 0 in response to the signal output from the OR circuit 124-1, and sets the count value to the Wr address comparison unit 127, the Rd address comparison unit 130, and the line buffers 128-1 and 128-2. Output to.
　Wrアドレス比較部１２７は、アドレスカウンタ１２６から出力されたカウント値が所定値に達すると、clear信号をアドレスカウンタ１２６に出力する。また、Wrアドレス比較部１２７は、Data　Enable信号が入力されると、書き込み許可を示すWrite　Enable　A信号をラインバッファ１２８－１に出力し、書き込み許可を示すWrite　Enable　B信号をラインバッファ１２８－２に出力する。 The Wr address comparator 127 outputs a clear signal to the address counter 126 when the count value output from the address counter 126 reaches a predetermined value. In addition, when the Data Enable signal is input, the Wr address comparison unit 127 outputs a Write Enable A signal indicating permission for writing to the line buffer 128-1, and outputs a Write Enable B signal indicating permission for writing to the line buffer 128-2. Output to.
　ラインバッファ１２８－１は、アドレスカウンタ１２６から出力されたカウント値を書き込みアドレスとしてData信号の書き込みを行う。また、ラインバッファ１２８－１は、アドレスカウンタ１２６から出力されたカウント値を読み出しアドレスとして、書き込みを行ったData信号を読み出し、マルチプレクサ１３２－１に出力する。 The line buffer 128-1 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-1 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1.
　ラインバッファ１２８－２は、アドレスカウンタ１２６から出力されたカウント値を書き込みアドレスとしてData信号の書き込みを行う。また、ラインバッファ１２８－２は、アドレスカウンタ１２６から出力されたカウント値を読み出しアドレスとして、書き込みを行ったData信号を読み出し、マルチプレクサ１３２－１またはラインバッファ１３２－３に出力する。 The line buffer 128-2 writes a Data signal using the count value output from the address counter 126 as a write address. Further, the line buffer 128-2 reads the written Data signal using the count value output from the address counter 126 as a read address, and outputs it to the multiplexer 132-1 or the line buffer 132-3.
　なお、ラインバッファ１２８－１，１２８－２はそれぞれ、１ライン分の映像エリア２０の映像信号の半分を記憶する。 The line buffers 128-1 and 128-2 each store half of the video signal of the video area 20 for one line.
　読み出し制御部１２９は、出力部１３２からの信号の出力状態を制御する。 Read control unit 129 controls the output state of the signal from output unit 132.
　Rdアドレス比較部１３０は、en遅延部１２３からDelayed　Data　Enable信号が出力されると、Data　Enable　A信号をOR回路１２４－２，１２４－３に出力し、Data　Enable　B信号をOR回路１２４－３に出力する。 When the Delayed Data Enable signal is output from the en delay unit 123, the Rd address comparison unit 130 outputs the Data Enable A signal to the OR circuits 124-2 and 124-3, and the Data Enable B signal to the OR circuit 124-3. Output to.
　先頭ライン検出部１３１は、Data信号として先頭ラインＭの映像信号が入力されると、Insert　Ancillary信号をマルチプレクサ１３２－２，１３２－３とOR回路１２４－３とに入力する。 When the video signal of the head line M is input as the Data signal, the head line detection unit 131 inputs the Insert Ancillary signal to the multiplexers 132-2 and 132-3 and the OR circuit 124-3.
　OR回路１２４－２は、3D信号またはData　Enable　A信号の入力に応じて、マルチプレクサ１３２－１に信号を出力する。 OR circuit 124-2 outputs a signal to multiplexer 132-1 in response to the input of 3D signal or Data Enable A signal.
　出力部１３２は、読み出し制御部１２９の制御に従い、Ancillaryバッファ１２２－１，１２２－２に記憶されている補助データとラインバッファ１２８－１，１２８－２に記憶されている映像信号とを組み合わせて、Data　Left信号およびData　Right信号を出力する。 The output unit 132 combines the auxiliary data stored in the Ancillary buffers 122-1 and 122-2 and the video signal stored in the line buffers 128-1 and 128-2 in accordance with the control of the read control unit 129. , Data Left signal and Data Right signal are output.
　マルチプレクサ１３２－１は、ラインバッファ１２８－１，１２８－２の出力を入力とし、OR回路１２４－２からの信号出力に応じて、いずれかを選択的に出力する。 The multiplexer 132-1 receives the outputs of the line buffers 128-1 and 128-2 as inputs, and selectively outputs one according to the signal output from the OR circuit 124-2.
　マルチプレクサ１３２－２は、Ancillaryバッファ１２２－１の出力とマルチプレクサ１３２－１の出力とを入力とし、先頭ライン検出部１３１からのInsert　Ancillary信号の入力に応じて、いずれかを選択的にData　Left信号としてデジタルシネマ処理回路３００に出力する。 The multiplexer 132-2 receives the output of the ancillary buffer 122-1 and the output of the multiplexer 132-1 as input, and selectively selects one of the data left signals according to the input of the insert ancillary signal from the head line detector 131. To the digital cinema processing circuit 300.
　マルチプレクサ１３２－３は、Ancillaryバッファ１２２－２の出力とラインバッファ１２８－２の出力とを入力とし、先頭ライン検出部１３１からのInsert　Ancillary信号の入力に応じて、いずれかを選択的にData　Right信号としてデジタルシネマ処理回路３００に出力する。 The multiplexer 132-3 receives the output of the Ancillary buffer 122-2 and the output of the line buffer 128-2 as input, and selectively selects either Data Right according to the Insert Ancillary signal input from the head line detection unit 131. The signal is output to the digital cinema processing circuit 300 as a signal.
　OR回路１２４－３は、Data　Enable　A信号、Data　Enable　B信号またはInsert　Ancillary信号の入力に応じて、Data　Left信号およびData　Right信号が有効な信号であることを示すData　Enable　Out信号をデジタルシネマ処理回路３００に出力する。 The OR circuit 124-3 performs digital cinema processing on the Data Enable Out signal indicating that the Data Left signal and Data Right signal are valid signals in response to the input of the Data Enable A signal, Data Enable B signal, or Insert Ancillary signal. Output to the circuit 300.
　V　Sync遅延部１３３は、入力部１１０から入力されたV　Sync信号を１ライン分だけ遅延させ、V　Sync　Out信号としてデジタルシネマ処理回路３００に出力する。 The V Sync delay unit 133 delays the V Sync signal input from the input unit 110 by one line, and outputs it to the digital cinema processing circuit 300 as a V Sync Out signal.
　次に、本実施形態の信号処理回路１００の動作について説明する。 Next, the operation of the signal processing circuit 100 of this embodiment will be described.
　まず、ラインバッファ１２８－１，１２８－２へのData信号の書き込み動作について図１３に示す各信号のタイミングチャートを参照して説明する。 First, a data signal writing operation to the line buffers 128-1 and 128-2 will be described with reference to a timing chart of each signal shown in FIG.
　なお、以下では、三次元映像信号がData信号として入力され、１ライン分の左目映像および右目映像のピクセル数がｎ／２であるとする。したがって、左目映像信号L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)および右目映像信号R(0),R(1),L(2)・・・R(n/2-2),R(n/2-1)が順に、１クロック毎に、１ピクセル分ずつ、Data信号D(0),D(1),D(2)…D(n-2),D(n-1)として入力される。 In the following, it is assumed that a 3D video signal is input as a Data signal, and the number of pixels of the left-eye video and the right-eye video for one line is n / 2. Therefore, left eye video signals L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1) and right eye video signals R (0), R ( 1), L (2)... R (n / 2-2), R (n / 2-1) in turn, one pixel at a time, one data signal D (0), D (1 ), D (2)... D (n-2), D (n-1).
　時刻ｔ３１において、入力部１１０は、Data信号として映像エリア２０の映像信号の入力を開始すると、Data　Enable信号をＬｏｗからＨｉｇｈに遷移させる。 At time t31, when the input unit 110 starts inputting the video signal of the video area 20 as the Data signal, the input unit 110 changes the Data Enable signal from Low to High.
　Data　Enable信号がＨｉｇｈに遷移すると、OR回路１２４－１は、アドレスカウンタ１２６に信号を出力し、アドレスカウンタ１２６は、その信号出力に応じて、１クロック毎に、０からカウント値を出力する。また、Wrアドレス比較部１２７は、Write　Enable　A信号をＨｉｇｈに遷移させる。Write　Enable　A信号がＨｉｇｈに遷移すると、ラインバッファ１２８－１は、アドレスカウンタ１２６から出力されたカウント値を書き込みアドレスとして、Data信号の書き込みを行う。 When the Data Enable signal transitions to High, the OR circuit 124-1 outputs a signal to the address counter 126, and the address counter 126 outputs a count value from 0 every clock according to the signal output. In addition, the Wr address comparison unit 127 causes the Write Enable A signal to transition to High. When the Write Enable A signal transitions to High, the line buffer 128-1 writes the Data signal using the count value output from the address counter 126 as the write address.
　時刻ｔ３２において、カウント値が所定値ｎ／２－１に達すると、Wrアドレス比較部１２７は、clear信号をアドレスカウンタ１２６に出力する。 At time t32, when the count value reaches the predetermined value n / 2-1, the Wr address comparison unit 127 outputs a clear signal to the address counter 126.
　上述したように、１クロック毎に１ピクセル分のData信号が出力されるとともに、そのData信号の書き込みが行われる。したがって、時刻ｔ３１から時刻ｔ３２までの間に、ｎ／２ピクセル分のData信号、すなわち、左目映像信号L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)が、ラインバッファ１２８－１に書き込まれる。 As described above, a data signal for one pixel is output for each clock, and the data signal is written. Therefore, between time t31 and time t32, data signals for n / 2 pixels, that is, left-eye video signals L (0), L (1), L (2)... L (n / 2-2 ), L (n / 2-1) are written into the line buffer 128-1.
　また、カウント値がｎ／２－１に達すると、Wrアドレス比較部１２７は、Write　Enable　A信号をＨｉｇｈからＬｏｗに遷移させるとともに、Data　Enable　B信号をＬｏｗからＨｉｇｈに遷移させる。Write　Enable　A信号がＬｏｗに遷移すると、ラインバッファ１２８－１への書き込みが終了し、Write　Enable　B信号がＨｉｇｈに遷移すると、ラインバッファ１２８－２への書き込みが開始される。 When the count value reaches n / 2-1, the Wr address comparison unit 127 causes the Write Enable A signal to transition from High to Low and causes the Data Enable B signal to transition from Low to High. When the Write Enable A signal transitions to Low, writing to the line buffer 128-1 is completed, and when the Write Enable B signal transitions to High, writing to the line buffer 128-2 is started.
　clear信号が出力されると、アドレスカウンタ１２６は、カウント値を０に戻す。 When the clear signal is output, the address counter 126 returns the count value to zero.
　Write　Enable　B信号がＨｉｇｈに遷移すると、ラインバッファ１２８－２は、アドレスカウンタ１２６から出力されたカウント値を書き込みアドレスとして、入力されたData信号の書き込みを行う。ここで、時刻ｔ３２においては、Data信号として映像信号R(0)が出力される。したがって、ラインバッファ１２８－２には、右目映像信号R(0),R(1),L(2)・・・R(n/2-2),R(n/2-1)が順に書き込まれる。 When the Write Enable B signal transitions to High, the line buffer 128-2 writes the input Data signal using the count value output from the address counter 126 as a write address. Here, at time t32, the video signal R (0) is output as the Data signal. Therefore, the right-eye video signals R (0), R (1), L (2)... R (n / 2-2), R (n / 2-1) are sequentially written in the line buffer 128-2. It is.
　時刻ｔ３３において、再び、カウント値が所定値ｎ／２－１に達すると、Wrアドレス比較部１２７は、clear信号をアドレスカウンタ１２６に出力するとともに、Write　Enable　B信号をＬｏｗからＨｉｇｈに遷移させる。Write　Enable　B信号がＬｏｗに遷移すると、ラインバッファ１２８－２への書き込みが終了する。 When the count value reaches the predetermined value n / 2-1 again at time t33, the Wr address comparison unit 127 outputs a clear signal to the address counter 126 and changes the Write Enable B signal from Low to High. When the Write Enable B signal transitions to Low, writing to the line buffer 128-2 is completed.
　なお、三次元映像信号ではない映像信号が入力された場合には、入力部１１０から入力された順に、１ライン分の映像エリア２０の映像信号の半分がラインバッファ１２８－１に書き込まれ、残り半分がラインバッファ１２８－２に書き込まれる。 When a video signal that is not a 3D video signal is input, half of the video signal of the video area 20 for one line is written in the line buffer 128-1 in the order of input from the input unit 110, and the rest Half is written to the line buffer 128-2.
　次に、ラインバッファ１２８－１，１２８－２からのData信号の読み出し動作について説明する。 Next, a data signal read operation from the line buffers 128-1 and 128-2 will be described.
　図１４は、映像信号が三次元映像信号である場合の、Data信号の読み出し時の各信号のタイミングチャートである。 FIG. 14 is a timing chart of each signal when the Data signal is read when the video signal is a 3D video signal.
　なお、図１４においては、Data信号として、左目映像信号L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)がラインバッファ１２８－１に書き込まれ、右目映像信号R(0),R(1),R(2)・・・R(n/2-2),R(n/2-1)がラインバッファ１２８－２に書き込まれているものとする。 In FIG. 14, the left-eye video signals L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1) are lines as the Data signal. The right-eye video signals R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1) are written into the buffer 128-1, and the line buffer 128- 2 is written.
　時刻ｔ４１において、アドレスカウンタ１２６からカウント値が出力されると、Rdアドレス比較部１３０は、Data　Enable　A信号およびData　Enable　B信号をＬｏｗからＨｉｇｈに遷移させる。また、そのカウント値を読み出しアドレスとして、ラインバッファ１２８－１は、Data信号（L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)）を読み出して出力し、ラインバッファ１２８－２は、Data信号（R(0),R(1),R(2)・・・R(n/2-2),R(n/2-1)）を読み出して出力する。 When the count value is output from the address counter 126 at time t41, the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High. The line buffer 128-1 uses the count value as a read address, and the data buffer (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) is read and output, and the line buffer 128-2 outputs the data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / 2-1)) is read and output.
　上述したように、入力される映像信号は三次元映像信号であるので、映像信号が三次元映像信号である旨を示す3D信号が入力される。この場合、Rdアドレス比較部１３０は、Data　Enable　A信号およびData　Enable　B信号を同時にＬｏｗからＨｉｇｈに遷移させる。 As described above, since the input video signal is a 3D video signal, a 3D signal indicating that the video signal is a 3D video signal is input. In this case, the Rd address comparison unit 130 simultaneously transitions the Data Enable A signal and the Data Enable B signal from Low to High.
　OR回路１２４－２は、Data　Enable　A信号のＨｉｇｈへの遷移に応じて、マルチプレクサ１３２－１に信号を出力し、マルチプレクサ１３２－１は、その信号出力に応じて、ラインバッファ１２８－１から出力されたData信号（L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)）をマルチプレクサ１３２－２に出力する。マルチプレクサ１３２－２は、そのData信号をData　Left信号としてデジタルシネマ処理回路３００に出力する。 The OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output. The data signals (L (0), L (1), L (2)... L (n / 2-2), L (n / 2-1)) are output to the multiplexer 132-2. The multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
　また、マルチプレクサ１３２－３は、ラインバッファ１２８－２から出力されたData信号（R(0),R(1),R(2)・・・R(n/2-2),R(n/2-1)）をData　Right信号としてデジタルシネマ処理回路３００に出力する。 The multiplexer 132-3 also outputs the Data signals (R (0), R (1), R (2)... R (n / 2-2), R (n / n) output from the line buffer 128-2. 2-1)) is output to the digital cinema processing circuit 300 as a Data Right signal.
　OR回路１２４－３は、Data　Enable　A信号およびData　Enable　B信号がＨｉｇｈに遷移すると、Data　Enable　Out信号をＨｉｇｈに遷移させる。Data　Enable　Out信号がＨｉｇｈに遷移することで、マルチプレクサ１３２－１，１３２－２から出力されたData　Left信号およびData　Right信号が、有効な信号として取り扱われ、左目映像信号L(0),L(1),L(2)・・・L(n/2-2),L(n/2-1)と右目映像信号R(0),R(1),R(2)・・・R(n/2-2),R(n/2-1)とが分離されて、デジタルシネマ処理回路３００に出力される。 OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal and Data Enable B signal transition to High. When the Data Enable Out signal transitions to High, the Data Left signal and Data Right signal output from the multiplexers 132-1 and 132-2 are treated as valid signals, and the left-eye video signals L (0), L ( 1), L (2) ... L (n / 2-2), L (n / 2-1) and right-eye video signal R (0), R (1), R (2) ... R ( n / 2-2) and R (n / 2-1) are separated and output to the digital cinema processing circuit 300.
　なお、マルチプレクサ１３２－２は、Insert　Ancillary信号の入力に応じて、左目映像信号にAncillaryバッファ１２２－１に記憶されているAncillary　Dataを付加してデジタルシネマ処理回路３００に出力する。すなわち、マルチプレクサ１３２－２は、ラインバッファ１２８－１に記憶されている左目映像信号とAncillaryバッファ１２２－１に記憶されているAncillary　Dataとを組み合わせ、第１の出力信号であるData　Left信号をデジタルシネマ処理回路３００に出力する。 Note that the multiplexer 132-2 adds the Ancillary Data stored in the Ancillary buffer 122-1 to the left-eye video signal and outputs it to the digital cinema processing circuit 300 in response to the input of the Insert Ancillary signal. That is, the multiplexer 132-2 combines the left eye video signal stored in the line buffer 128-1 and the Ancillary Data stored in the Ancillary buffer 122-1, and digitally converts the Data Left signal as the first output signal. Output to the cinema processing circuit 300.
　また、マルチプレクサ１３２－３は、Insert　Ancillary信号の入力に応じて、右目映像信号にAncillaryバッファ１２２－２に記憶されているAncillary　Dataを付加してデジタルシネマ処理回路３００に出力する。すなわち、マルチプレクサ１３２－３は、ラインバッファ１２８－２に記憶されている右目映像信号とAncillaryバッファ１２２－２に記憶されているAncillary　Dataとを組み合わせ、第２の出力信号であるData　Right信号をデジタルシネマ処理回路３００に出力する。 In addition, the multiplexer 132-3 adds the Ancillary Data stored in the Ancillary buffer 122-2 to the right-eye video signal in response to the input of the Insert Ancillary signal, and outputs it to the digital cinema processing circuit 300. That is, the multiplexer 132-3 combines the right eye video signal stored in the line buffer 128-2 and the Ancillary Data stored in the Ancillary buffer 122-2, and digitally converts the Data Right signal as the second output signal. Output to the cinema processing circuit 300.
　なお、Ancillary　Dataの付加は、図４を参照して説明した動作と同様に行われるので説明を省略する。 Ancillary data is added in the same manner as the operation described with reference to FIG.
　図１５は、映像信号が三次元映像信号でない場合の、Data信号の読み出し時の各信号のタイミングチャートである。 FIG. 15 is a timing chart of each signal when the Data signal is read when the video signal is not a 3D video signal.
　なお、図１５においては、入力部１１０から入力された順に、１ライン分の映像エリア２０の映像信号の半分がラインバッファ１２８－１に書き込まれ、残り半分がラインバッファ１２８－２に書き込まれているとする。したがって、ラインバッファ１２８－１には、Data信号D(0),D(1),D(2)・・・D(n/2-2),D(n/2-1)が書き込まれ、ラインバッファ１２８－２には、Data信号D(n/2),D(n/2+1),D(n/2+2)・・・D(n-2),D(n-1)が書き込まれているとする。 In FIG. 15, half of the video signal of the video area 20 for one line is written to the line buffer 128-1 and the other half is written to the line buffer 128-2 in the order input from the input unit 110. Suppose that Therefore, the data signals D (0), D (1), D (2)... D (n / 2-2), D (n / 2-1) are written in the line buffer 128-1. The line buffer 128-2 includes data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1). Is written.
　時刻ｔ５１において、アドレスカウンタ１２６からカウント値が出力されると、Rdアドレス比較部１３０は、Data　Enable　A信号およびData　Enable　B信号をＬｏｗからＨｉｇｈに遷移させる。また、そのカウント値を読み出しアドレスとして、ラインバッファ１２８－１は、Data信号D(0),D(1),D(2)・・・D(n/2-2),D(n/2-1)を読み出して出力し、ラインバッファ１２８－２は、Data信号D(n/2),D(n/2+1),D(n/2+2)・・・D(n-2),D(n-1)を読み出して出力する。 When the count value is output from the address counter 126 at time t51, the Rd address comparison unit 130 transitions the Data Enable A signal and the Data Enable B signal from Low to High. The line buffer 128-1 uses the count value as a read address, and the data signal D (0), D (1), D (2)... D (n / 2-2), D (n / 2 -1) is read and output, and the line buffer 128-2 receives the data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2 ), D (n-1) is read and output.
　上述したように、入力される映像信号は三次元映像信号ではないので、映像信号が三次元映像信号ではない旨を示す3D信号が入力される。この場合、Rdアドレス比較部１３０は、Data　Enable　A信号のみをＬｏｗからＨｉｇｈに遷移させる。 As described above, since the input video signal is not a 3D video signal, a 3D signal indicating that the video signal is not a 3D video signal is input. In this case, the Rd address comparison unit 130 causes only the Data Enable A signal to transition from Low to High.
　OR回路１２４－２は、Data　Enable　A信号のＨｉｇｈへの遷移に応じて、マルチプレクサ１３２－１に信号を出力し、マルチプレクサ１３２－１は、その信号出力に応じて、ラインバッファ１２８－１から出力されたData信号D(0),D(1),D(2)・・・D(n/2-2),D(n/2-1)をマルチプレクサ１３２－２に出力する。マルチプレクサ１３２－２は、そのData信号をData　Left信号としてデジタルシネマ処理回路３００に出力する。 The OR circuit 124-2 outputs a signal to the multiplexer 132-1 according to the transition of the Data Enable A signal to High, and the multiplexer 132-1 outputs from the line buffer 128-1 according to the signal output. The data signals D (0), D (1), D (2)... D (n / 2-2), D (n / 2-1) are output to the multiplexer 132-2. The multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300 as a Data Left signal.
　時刻ｔ５２において、カウント値がｎ／２－１に達すると、Wrアドレス比較部１２７は、clear信号をアドレスカウンタ１２６に出力し、アドレスカウンタ１２６は、カウント値を０に戻す。 When the count value reaches n / 2-1 at time t52, the Wr address comparison unit 127 outputs a clear signal to the address counter 126, and the address counter 126 returns the count value to 0.
　カウント値が０になると、Rdアドレス比較部１３０は、Data　Enable　A信号をＨｉｇｈからＬｏｗに遷移させるとともに、Data　Enable　B信号をＬｏｗからＨｉｇｈに遷移させる。 When the count value becomes 0, the Rd address comparison unit 130 causes the Data Enable A signal to transition from High to Low, and causes the Data Enable B signal to transition from Low to High.
　上述したように、映像信号が三次元映像信号ではない旨を示す3D信号が入力されているので、OR回路１２４－２は、Data　Enable　A信号がＬｏｗに遷移すると、マルチプレクサ１３２－１への信号出力を停止する。 As described above, since the 3D signal indicating that the video signal is not a 3D video signal is input, the OR circuit 124-2 causes the signal to the multiplexer 132-1 when the Data Enable A signal transitions to Low. Stop output.
　OR回路１２４－２からの信号出力が停止すると、マルチプレクサ１３２－１は、ラインバッファ１２８－２に記憶されているData信号の出力先をマルチプレクサ１３２－１とし、ラインバッファ１２８－２から出力されたData信号D(n/2),D(n/2+1),D(n/2+2)・・・D(n-2),D(n-1)をマルチプレクサ１３２－２に出力する。マルチプレクサ１３２－２は、そのData信号をデジタルシネマ処理回路３００に出力する。 When the signal output from the OR circuit 124-2 is stopped, the multiplexer 132-1 sets the output destination of the Data signal stored in the line buffer 128-2 as the multiplexer 132-1, and is output from the line buffer 128-2. Data signals D (n / 2), D (n / 2 + 1), D (n / 2 + 2)... D (n-2), D (n-1) are output to the multiplexer 132-2. . The multiplexer 132-2 outputs the Data signal to the digital cinema processing circuit 300.
　OR回路１２４－３は、Data　Enable　A信号またはData　Enable　B信号がＨｉｇｈに遷移すると、Data　Enable　Out信号をＨｉｇｈに遷移させる。Data　Enable　Out信号をＨｉｇｈに遷移させることで、マルチプレクサ１３２－２から入力された１ライン分の映像エリア２０のData信号が有効な信号として取り扱われ、１ライン分の映像エリア２０の映像信号が結合されて、デジタルシネマ処理回路３００に出力される。 OR circuit 124-3 transitions Data Enable Out signal to High when Data Enable A signal or Data Enable B signal transitions to High. By transitioning the Data Enable Out signal to High, the Data signal of the video area 20 for one line input from the multiplexer 132-2 is treated as a valid signal, and the video signal of the video area 20 for one line is combined. And output to the digital cinema processing circuit 300.
　なお、上述したように、映像信号が三次元映像信号である場合には、Rdアドレス比較部１３０は、Data　Enable　A信号およびData　Enable　B信号を同時にＬｏｗからＨｉｇｈに遷移させる。この場合、マルチプレクサ１３２－２からはラインバッファ１２８－１に記憶されている左目映像信号とAncillaryバッファ１２２－１に記憶されているAncillary　Dataとを組み合わせたData　Left信号が、また、マルチプレクサ１３２－３からはラインバッファ１２８－２に記憶されている右目映像信号とAncillaryバッファ１２２－２に記憶されているAncillary　Dataとを組み合わせたData　Right信号が、並行してデジタルシネマ処理回路３００に出力される。 As described above, when the video signal is a 3D video signal, the Rd address comparison unit 130 causes the Data Enable A signal and the Data Enable B signal to simultaneously transition from Low to High. In this case, the multiplexer 132-2 receives a data left signal that combines the left-eye video signal stored in the line buffer 128-1 and the ancillary data stored in the ancillary buffer 122-1, and the multiplexer 132-3. The data right signal, which is a combination of the right-eye video signal stored in the line buffer 128-2 and the ancillary data stored in the ancillary buffer 122-2, is output to the digital cinema processing circuit 300 in parallel.
　一方、映像信号が三次元映像信号でない場合には、Rdアドレス比較部１３０は、まずData　Enable　A信号を、次に、Data　Enable　B信号を、ＬｏｗからＨｉｇｈに遷移させる。この場合、ラインバッファ１２８－１，１２８－２の順に、各ラインバッファに記憶されたData信号がマルチプレクサ１３２－２に出力され、Ancillaryバッファ１２２－１に記憶されているAncillary　Dataと組み合わされてデジタルシネマ処理回路３００に出力される。 On the other hand, if the video signal is not a 3D video signal, the Rd address comparison unit 130 first transitions the Data Enable A signal and then the Data Enable B signal from Low to High. In this case, the data signal stored in each line buffer is output to the multiplexer 132-2 in the order of the line buffers 128-1 and 128-2, and combined with the ancillary data stored in the ancillary buffer 122-1. It is output to the cinema processing circuit 300.
　なお、マルチプレクサ１３２－２は、Insert　Ancillary信号の出力に応じて、ラインバッファ１２８－１，１２８－２に記憶されている映像信号にAncillaryバッファ１２２－１に記憶されているAncillary　Dataを付加して、デジタルシネマ処理回路３００に出力する。すなわち、マルチプレクサ１３２－２は、ラインバッファ１２８－１，１２８－２に記憶されている映像信号とAncillaryバッファ１２２－１に記憶されているAncillary　Dataとを組み合わせ、第３の出力信号としてデジタルシネマ処理回路３００に出力する。 The multiplexer 132-2 adds the ancillary data stored in the ancillary buffer 122-1 to the video signal stored in the line buffers 128-1 and 128-2 in response to the output of the insert ancillary signal. And output to the digital cinema processing circuit 300. That is, the multiplexer 132-2 combines the video signal stored in the line buffers 128-1 and 128-2 and the Ancillary Data stored in the Ancillary buffer 122-1, and performs digital cinema processing as a third output signal. Output to the circuit 300.
　なお、Ancillary　Dataの付加は、図４を参照して説明した動作と同様に行われるので説明を省略する。 Ancillary data is added in the same manner as the operation described with reference to FIG.
　このように、本実施形態によれは、信号処理回路１００は、Ancillaryバッファ１２２－１，１２２－２と、ラインバッファ１２８－１，１２８－２と、を備え、映像信号が三次元映像信号である場合には、左目映像信号に付加するAncillary　DataをAncillaryバッファ１２２－１に記憶させ、右目映像信号に付加するAncillary　DataをAncillaryバッファ１２２－２に記憶させ、また、左目映像信号をラインバッファ１２８－１に記憶させ、右目映像信号をラインバッファ１２８－２に記憶させ、Ancillaryバッファ１２２－１に記憶されているAncillary　Dataとラインバッファ１２８－１に記憶に記憶されている左目映像信号とを組み合わせたData　Left信号と、Ancillaryバッファ１２２－２に記憶されているAncillary　Dataとラインバッファ１２８－２に記憶に記憶されている右目映像信号とを組み合わせたData　Right信号と、を並行してデジタルシネマ処理回路３００に出力する。 As described above, according to the present embodiment, the signal processing circuit 100 includes the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2, and the video signal is a 3D video signal. In some cases, the Ancillary Data added to the left-eye video signal is stored in the Ancillary buffer 122-1, the Ancillary Data added to the right-eye video signal is stored in the Ancillary buffer 122-2, and the left-eye video signal is stored in the line buffer 128. −1, the right eye video signal is stored in the line buffer 128-2, and the Ancillary Data stored in the Ancillary buffer 122-1 is combined with the left eye video signal stored in the line buffer 128-1. Data Left signal and Ancillary Data stored in the Ancillary buffer 122-2 and Line buffer 128-2 And Data Right signal combining the right-eye image signal are, in parallel and outputs the digital cinema processing circuit 300.
　また、本実施形態によれば、信号処理回路１００は、映像信号が三次元映像信号でない場合には、Ancillary　DataをAncillaryバッファ１２２－１に記憶させ、また、１ライン分の映像エリア２０の映像信号をラインバッファ１２８－１，１２８－２に順次記憶させ、Ancillaryバッファ１２２－１に記憶されているAncillary　Dataとラインバッファ１２８－１，１２８－２に記憶されている映像信号とを組み合わせた信号をデジタルシネマ処理回路３００に出力する。 Further, according to the present embodiment, the signal processing circuit 100 stores the Ancillary Data in the Ancillary buffer 122-1, when the video signal is not a 3D video signal, and the video of the video area 20 for one line. Signals are sequentially stored in the line buffers 128-1 and 128-2, and a signal obtained by combining the Ancillary Data stored in the Ancillary buffer 122-1 and the video signal stored in the line buffers 128-1 and 128-2. Is output to the digital cinema processing circuit 300.
　そのため、回路規模の増大を抑制しつつ、映像信号が三次元映像信号である場合にも、三次元映像信号でない場合にも、Ancillary　Dataを付加した映像信号をデジタルシネマ処理回路３００に出力することができる。 Therefore, an image signal with ancillary data is output to the digital cinema processing circuit 300 regardless of whether the video signal is a 3D video signal or not a 3D video signal while suppressing an increase in circuit scale. Can do.
　なお、本実施形態においては、Ancillaryバッファ１２２－１，１２２－２およびラインバッファ１２８－１，１２８－２がそれぞれ、独立したバッファである例を用いて説明したが、本発明はこれに限られるものではない。例えば、Ancillaryバッファ１２２－１，１２２－２およびラインバッファ１２８－１，１２８－２のうち、複数のバッファを含むバッファを信号処理回路１００が有するようにしてもよい。 In the present embodiment, the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2 are described as examples of independent buffers. However, the present invention is not limited to this. It is not a thing. For example, the signal processing circuit 100 may include a buffer including a plurality of buffers among the ancillary buffers 122-1 and 122-2 and the line buffers 128-1 and 128-2.
　以上、実施形態を参照して本願発明を説明したが、本発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明の範囲内で当業者が理解し得る様々な変更をすることができる。 As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to the said embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

Claims (5)

  1. 　１水平ライン分の半分の映像信号を記憶する第１および第２のバッファと、
    　前記第１および第２のバッファに記憶された映像信号を処理する際に必要となる補助データを記憶する第３および第４のバッファと、
    　前記第１乃至第４のバッファの出力を入力し、映像信号の内容に応じて異なる信号を出力する出力部と、
    　１水平ライン分の前記映像信号を前記第１および第２のバッファに順次記憶させる第１の書き込み制御部と、
    　前記映像信号が、三次元映像を表示するための左目映像と右目映像とを示す三次元映像信号である場合には、前記左目映像を示す左目映像信号を処理する際に必要となる第１の補助データを前記第３のバッファに記憶させ、前記右目映像を示す右目映像信号を処理する際に必要となる第２の補助データを前記第４のバッファに記憶させ、前記映像信号が前記三次元映像信号でない場合には、前記映像信号を処理する際に必要となる第３の補助データを前記第３のバッファに記憶させる第２の書き込み制御部と、
    　前記出力部の出力状態を制御する読み出し制御部と、を有し、
    　前記読み出し制御部は、
    　前記映像信号が前記三次元映像信号である場合には、前記第３のバッファに記憶されている第１の補助データと前記第１のバッファに記憶されている映像信号とを組み合わせた第１の出力信号と、前記第４のバッファに記憶されている第２の補助データと前記第２のバッファに記憶されている映像信号とを組み合わせた第２の出力信号と、を並行して前記出力部に出力させ、前記映像信号が前記三次元映像信号でない場合には、前記第３のバッファに記憶されている第３の補助データと前記第１および第２のバッファに記憶されている映像信号とを組み合わせた第３の出力信号を前記出力部に出力させることを特徴とする信号処理回路。     First and second buffers for storing half the video signal for one horizontal line;
    Third and fourth buffers for storing auxiliary data necessary for processing the video signals stored in the first and second buffers;
    An output unit for inputting the outputs of the first to fourth buffers and outputting different signals according to the content of the video signal;
    A first write control unit for sequentially storing the video signal for one horizontal line in the first and second buffers;
    When the video signal is a three-dimensional video signal indicating a left-eye video and a right-eye video for displaying a three-dimensional video, a first required for processing the left-eye video signal indicating the left-eye video Auxiliary data is stored in the third buffer, second auxiliary data required for processing a right-eye video signal indicating the right-eye video is stored in the fourth buffer, and the video signal is stored in the three-dimensional A second write control unit for storing, in the third buffer, third auxiliary data necessary for processing the video signal when it is not a video signal;
    A read control unit for controlling the output state of the output unit,
    The read control unit
    When the video signal is the 3D video signal, a first combination of the first auxiliary data stored in the third buffer and the video signal stored in the first buffer is used. The output unit in parallel with the output signal and a second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer And when the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the video signal stored in the first and second buffers A signal processing circuit characterized by causing the output unit to output a third output signal obtained by combining the above.
  2. 　請求項１記載の信号処理回路において、
    　前記出力部は、第１乃至第３のマルチプレクサにより構成され、
    　前記第１のマルチプレクサは、前記第３のバッファの出力と前記第３のマルチプレクサの出力とを入力し、いずれかを選択的に出力し、
    　前記第２のマルチプレクサは、前記第４のバッファの出力と前記第２のバッファの出力とを入力し、いずれかを選択的に出力し、
    　前記第３のマルチプレクサは、前記第１のバッファの出力と前記第２のバッファの出力とを入力し、いずれかを選択的に出力し、
    　前記読み出し制御部は、
    　前記映像信号が前記三次元映像信号である場合、前記第３のマルチプレクサには前記第１のバッファの出力を選択させ、前記第１のマルチプレクサには前記第３のバッファの出力を選択させた後に前記第３のマルチプレクサの出力を選択させ、前記第２のマルチプレクサには前記第４のバッファの出力を選択させた後に前記第２のバッファの出力を選択させ、
    　前記映像信号が前記三次元映像信号でない場合には、前記第３のマルチプレクサには前記第１のバッファの出力を選択させた後に前記第２のバッファの出力を選択させ、前記第１のマルチプレクサには、前記第３のバッファの出力を選択させた後に前記第３のマルチプレクサの出力を選択させることを特徴とする信号処理回路。     The signal processing circuit according to claim 1,
    The output unit includes first to third multiplexers,
    The first multiplexer inputs the output of the third buffer and the output of the third multiplexer, and selectively outputs one of them,
    The second multiplexer inputs the output of the fourth buffer and the output of the second buffer, selectively outputs one of them,
    The third multiplexer inputs the output of the first buffer and the output of the second buffer, selectively outputs one of them,
    The read control unit
    When the video signal is the 3D video signal, after the third multiplexer selects the output of the first buffer and the first multiplexer selects the output of the third buffer Selecting the output of the third multiplexer, causing the second multiplexer to select the output of the fourth buffer and then selecting the output of the second buffer;
    If the video signal is not the 3D video signal, the third multiplexer selects the output of the first buffer after selecting the output of the first buffer, and then the first multiplexer selects the output of the second buffer. And selecting the output of the third multiplexer after selecting the output of the third buffer.
  3. 　請求項１または請求項２に記載の信号処理回路において、
    　前記第１乃至第４のバッファを複数含むバッファを有することを特徴とする信号処理回路。     The signal processing circuit according to claim 1 or 2,
    A signal processing circuit comprising a buffer including a plurality of the first to fourth buffers.
  4. 　１水平ライン分の半分の映像信号を記憶する第１および第２のバッファと、前記第１および第２のバッファに記憶された映像信号を処理する際に必要となる補助データを記憶する第３および第４のバッファと、前記第１乃至第４のバッファの出力を入力し、映像信号の内容に応じて異なる信号を出力する出力部と、を有する信号処理回路の制御方法であって、
    　第１の書き込み制御部が、１水平ライン分の前記映像信号を前記第１および第２のバッファに順次記憶させ、
    　第２の書き込み制御部が、前記映像信号が、三次元映像を表示するための左目映像と右目映像とを示す三次元映像信号である場合には、前記左目映像を示す左目映像信号を処理する際に必要となる第１の補助データを前記第３のバッファに記憶させ、前記右目映像を示す右目映像信号を処理する際に必要となる第２の補助データを前記第４のバッファに記憶させ、前記映像信号が前記三次元映像信号でない場合には、前記映像信号を処理する際に必要となる第３の補助データを前記第３のバッファに記憶させ、
    　読み出し制御部が、前記映像信号が前記三次元映像信号である場合には、前記第３のバッファに記憶されている第１の補助データと前記第１のバッファに記憶されている映像信号とを組み合わせた第１の出力信号と、前記第４のバッファに記憶されている第２の補助データと前記第２のバッファに記憶されている映像信号とを組み合わせた第２の出力信号と、を並行して前記出力部に出力させ、前記映像信号が前記三次元映像信号でない場合には、前記第３のバッファに記憶されている第３の補助データと前記第１および第２のバッファに記憶されている映像信号とを組み合わせた第３の出力信号を前記出力部に出力させることを特徴とする信号処理回路の制御方法。     First and second buffers for storing half the video signal for one horizontal line, and third data for storing auxiliary data required when processing the video signals stored in the first and second buffers And a fourth buffer, and a control method of a signal processing circuit having an output unit that inputs the output of the first to fourth buffers and outputs a different signal according to the content of the video signal,
    The first writing control unit sequentially stores the video signal for one horizontal line in the first and second buffers,
    When the video signal is a 3D video signal indicating a left-eye video and a right-eye video for displaying a 3D video, the second writing control unit processes the left-eye video signal indicating the left-eye video. First auxiliary data required at the time is stored in the third buffer, and second auxiliary data required in processing the right-eye video signal indicating the right-eye video is stored in the fourth buffer. , If the video signal is not the 3D video signal, the third auxiliary data required for processing the video signal is stored in the third buffer,
    When the video signal is the 3D video signal, the read control unit obtains the first auxiliary data stored in the third buffer and the video signal stored in the first buffer. The combined first output signal and the second output signal obtained by combining the second auxiliary data stored in the fourth buffer and the video signal stored in the second buffer are parallel to each other. When the video signal is not the 3D video signal, the third auxiliary data stored in the third buffer and the first and second buffers are stored. A control method for a signal processing circuit, comprising: causing the output unit to output a third output signal combined with a video signal being output.
  5. 　請求項４記載の信号処理回路の制御方法において、
    　前記出力部は、第１乃至第３のマルチプレクサにより構成され、
    　前記第１のマルチプレクサは、前記第３のバッファの出力と前記第３のマルチプレクサの出力とを入力し、いずれかを選択的に出力し、
    　前記第２のマルチプレクサは、前記第４のバッファの出力と前記第２のバッファの出力とを入力し、いずれかを選択的に出力し、
    　前記第３のマルチプレクサは、前記第１のバッファの出力と前記第２のバッファの出力とを入力し、いずれかを選択的に出力し、
    　前記読み出し制御部が、
    　前記映像信号が前記三次元映像信号である場合、前記第３のマルチプレクサには前記第１のバッファの出力を選択させ、前記第１のマルチプレクサには前記第３のバッファの出力を選択させた後に前記第３のマルチプレクサの出力を選択させ、前記第２のマルチプレクサには前記第４のバッファの出力を選択させた後に前記第２のバッファの出力を選択させ、
    　前記映像信号が前記三次元映像信号でない場合には、前記第３のマルチプレクサには前記第１のバッファの出力を選択させた後に前記第２のバッファの出力を選択させ、前記第１のマルチプレクサには、前記第３のバッファの出力を選択させた後に前記第３のマルチプレクサの出力を選択させることを特徴とする信号処理回路。     In the control method of the signal processing circuit according to claim 4,
    The output unit includes first to third multiplexers,
    The first multiplexer inputs the output of the third buffer and the output of the third multiplexer, and selectively outputs one of them,
    The second multiplexer inputs the output of the fourth buffer and the output of the second buffer, selectively outputs one of them,
    The third multiplexer inputs the output of the first buffer and the output of the second buffer, selectively outputs one of them,
    The read controller is
    When the video signal is the 3D video signal, after the third multiplexer selects the output of the first buffer and the first multiplexer selects the output of the third buffer Selecting the output of the third multiplexer, causing the second multiplexer to select the output of the fourth buffer and then selecting the output of the second buffer;
    If the video signal is not the 3D video signal, the third multiplexer selects the output of the first buffer after selecting the output of the first buffer, and then the first multiplexer selects the output of the second buffer. And selecting the output of the third multiplexer after selecting the output of the third buffer.
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