WO2012074176A1 - Solar cell and a production method therefor - Google Patents

Solar cell and a production method therefor Download PDF

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Publication number
WO2012074176A1
WO2012074176A1 PCT/KR2011/004399 KR2011004399W WO2012074176A1 WO 2012074176 A1 WO2012074176 A1 WO 2012074176A1 KR 2011004399 W KR2011004399 W KR 2011004399W WO 2012074176 A1 WO2012074176 A1 WO 2012074176A1
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Prior art keywords
semiconductor layer
conductive
conductive semiconductor
trenches
solar cell
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PCT/KR2011/004399
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French (fr)
Korean (ko)
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한석빈
최용규
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주식회사 선반도체
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Publication of WO2012074176A1 publication Critical patent/WO2012074176A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281Shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0236Special surface textures
    • H01L31/02363Special surface textures of the semiconductor body itself, e.g. textured active layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell, and more particularly, to a solar cell and a method for manufacturing the same, which can maximize the light efficiency, and can reduce the implementation and cost of the process.
  • Such solar energy is a renewable energy source that can be converted into other forms of energy such as heat and electricity.
  • the major drawback is the low efficiency in converting light energy into heat or electricity, and the solar energy at different times of the day and month of the year. Deviation.
  • PV cells based on the principle of converting optical energy into electrical energy are used to convert solar energy into electrical energy.
  • Systems using such PV cells can have a conversion efficiency between 10 and 20%.
  • Such solar cells are devices that utilize the photoelectric effect of converting light into electrical energy, and the PV cells provide power to satellite and space shuttles, provide electricity to residential and commercial properties, and provide automotive batteries and other navigational devices. It can be used for a wide range of applications such as filling.
  • the second conductive semiconductor layer 12 serving as an emitter is stacked on the first conductive semiconductor layer 11 serving as a base, and the second conductive semiconductor layer 12 is stacked.
  • a protective film 13 which is an antireflection film, is formed on the conductive semiconductor layer 12, and the first contact layer 14 is formed on both sides of the first conductive semiconductor layer 11, and the first conductive type is formed.
  • the second contact layer 15 is formed on the bottom surface of the semiconductor layer 11.
  • there is a driving battery 16 having both ends connected to the first and second contact layers 14 and 15.
  • the first conductivity type is a P type impurity
  • the second conductivity type is an N type impurity
  • the surface is doped with N-type impurities, and then the anode contact layer, that is, the first First and second contact layers 14 and 15 are formed, and the driving battery 16 is mounted.
  • a protective film and a reflective protective film are mounted on the second conductive semiconductor layer 11 to be used.
  • the conventional solar cell uses a method of maximizing the amount of incident light even if the electrode area is reduced by forming an electrode by digging a contact hole deeply in order to prevent the incident amount of sunlight from decreasing.
  • the conventional solar cell has a problem in that the incident light enters the reaction region in the PN junction region when the reaction distance is far and the recombination is large, the electrical extraction efficiency is reduced.
  • the present invention has been proposed to solve the problems according to the prior art, a solar cell and a method for manufacturing the same, which can increase the light utilization efficiency of the solar cell, and reduce the implementation and cost of the process by using the inkjet method.
  • the purpose is to provide.
  • the solar cell of the present invention for achieving the above object is a first conductive semiconductor layer surface-treated; A first conductive high concentration semiconductor layer formed in a surface of the first conductive semiconductor layer; First and second oxide films formed on textured top and bottom surfaces of the first conductive semiconductor layer, respectively; A plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer; A third oxide film formed on the upper side of the first trench; First and second conductive impurity regions formed in the first conductive semiconductor layer under the adjacent first trenches with different conductivity types; And first and second metal electrodes formed in the first trenches corresponding to the first and second conductive impurity regions, respectively.
  • the manufacturing method of the solar cell of the present invention having the above configuration comprises the steps of texturing the surface of the first conductive semiconductor layer; Forming a first conductive high concentration semiconductor layer on a surface of the first conductive semiconductor layer; Forming first and second oxide films on the top and bottom surfaces of the first conductive semiconductor layer, respectively; Forming a plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer; Forming a third oxide film on a surface of the first trench; Removing the third oxide layer so that the bottom and bottom sides of the first trench are exposed; Forming first and second conductive impurity regions having different conductivity types in the first conductive semiconductor layer under the adjacent first trenches; The first and second metal electrodes may be formed in the first trenches corresponding to the first and second conductive impurity regions, respectively.
  • the solar cell and a method of manufacturing the same according to the present invention described above have the following effects.
  • a plurality of spaced trenches are formed on a substrate, that is, a back surface of the first conductive semiconductor layer to have a depth capable of forming a PN junction, and P-type and N-type junctions are formed below the spaced trenches to form PN.
  • the trench may be formed in a dot shape, the light efficiency may be increased, and the trench may be formed deeper by using dry etch. If the trench is formed deeper as described above, the pattern may be densely formed because the probability of forming the side doping material and the PN junction may be increased and the side diffusion may be reduced. In addition, by reducing the distance that the light is transmitted to reach the back surface junction, it is possible to increase the light efficiency without recombination (recombination).
  • the formation of the first and second conductive impurity regions and the first and second metal electrodes can be formed by an inkjet method, the implementation and the cost of the process can be reduced.
  • FIG. 1 is a structural cross-sectional view of a solar cell according to the prior art.
  • FIG. 2 is a view for explaining the flow of electricity of a conventional solar cell.
  • FIG 3 is a structural cross-sectional view of a solar cell according to an embodiment of the present invention.
  • FIG. 4 is a view for explaining the flow of electricity of the solar cell according to an embodiment of the present invention.
  • 5A through 5I are cross-sectional views illustrating a method of manufacturing a solar cell according to an exemplary embodiment of the present invention.
  • the first conductivity type will be described as defined as P type, and the second conductivity type will be described as defined as N type.
  • the solar cell according to the embodiment of the present invention includes a first conductive semiconductor layer 51 having a textured surface, and a surface of the first conductive semiconductor layer 51.
  • the first conductive high concentration semiconductor layer 52 is formed therein, and the first and second oxide films 53 and 54 are formed on the textured upper and rear surfaces of the first conductive semiconductor layer 51, respectively.
  • a plurality of first trenches 55 spaced apart from each other may be formed on the rear surface of the first conductive semiconductor layer 51.
  • the first trenches 55 may be formed in the form of a plurality of dots spaced apart from each other at predetermined intervals, or may be formed in a line shape.
  • the third oxide layer is formed only on the upper side of the first trench 55 so that the lower and lower side surfaces of the first trench 55 are exposed.
  • the first conductive semiconductor layer 51 exposed to the lower portions of the adjacent first trenches 55 may have a first conductivity type impurity region 57a and a second conductivity type impurity region 58a having different conductivity types. This is formed adjacent to.
  • the first conductive impurity region 57a and the second conductive impurity region 58a are heavily doped, and the first conductive impurity region 57a is doped with boric acid (B 2 O 3) -based impurities.
  • the second conductive impurity region 58a is doped with an impurity of the phosphoric acid (P 2 O 5) series.
  • the first and second conductive droplets 57 and 58 having first and second conductive droplets 57 and 58 formed thereon to prevent cross diffusion of the first and second conductive impurity regions 57a and 58a into the adjacent first trench 55.
  • a capping material such as SOG may be further applied. In this way, if a capping material such as SOG is further applied, it is possible to prevent the doping of the side doping portion.
  • the first and second metals may be filled in the first trenches 55 corresponding to the first conductive impurity region 57a and the second conductive impurity region 58a, respectively. Electrodes 59 and 60 are formed. The first and second metal electrodes 59 and 60 serve as a plurality of contact layers for contact with the driving battery.
  • the surface of the first conductive semiconductor layer 51 serving as a substrate is textured to improve the efficiency of the solar cell. Process.
  • Texturing is to prevent the phenomenon of deterioration due to the optical loss caused by the reflection of light incident on the substrate surface of the solar cell, and to roughen the surface of the substrate used in the solar cell, that is, the uneven surface of the substrate To form a pattern of shapes. If the surface of the substrate is roughened by texturing, the light reflected once is reflected back to decrease the reflectance of the incident light, thereby increasing the amount of light trapped, thereby reducing the optical loss.
  • the first conductive high concentration semiconductor layer 52 is formed by injecting a high concentration of the first conductive type impurity into the surface of the textured first conductive semiconductor layer 51.
  • a high concentration of P + impurity which is a first conductivity type impurity, is implanted.
  • an N-type solar cell it may be formed by implanting an N-type high concentration impurity.
  • a first oxide film 53 is formed on the textured upper surface by performing a double-sided thermal oxidation process, and a second oxide film 54 is formed on the rear surface of the first conductive semiconductor layer 51. To form.
  • the second oxide film 54 and the first conductive semiconductor layer 51 on the back surface of the first conductive semiconductor layer 51 are sequentially formed using a photomask (not shown). Etching is performed to form a plurality of first trenches 55 spaced apart from each other.
  • the first trenches 55 may be formed in the form of a plurality of spaced apart dots, or may be formed in the form of a plurality of spaced apart lines.
  • a thermal oxidation process is performed on the structure to form a third oxide film 56 on the surface of the first trench 55.
  • the structure is turned upside down so that the first trench 55 is brought up.
  • an oxide film removing solution is dropped into the first trench 55 by using an inkjet device to remove a portion of the third oxide film 56 formed on the surface of the first trench 55. Drops in the form of water droplets). In this process, the third oxide film 56 on the lower surface and the lower side of the first trench 55 is removed, and the first conductive semiconductor layer 51 on the lower surface and the lower side of the first trench 55 is exposed. do.
  • a hydrofluoric acid (HF) -containing solution may be used as the oxide film removal solution.
  • the first conductive droplet 57 and the second conductive droplet 57 may be disposed on the exposed first conductive semiconductor layer 51 of the first trench 55 spaced apart from each other. 58) drop.
  • the first conductive droplet 57 mainly uses boric acid (B 2 O 3) series as a P-type droplet
  • the second conductive droplet 58 mainly uses phosphoric acid (P 2 O 5) series as an N-type droplet.
  • a diffusion process is performed on the first conductive droplets 57 and the second conductive droplets 58 dropped on the spaced apart first trenches 55.
  • the first conductive impurity region 57a and the second conductive impurity region 58a spaced apart from the first conductive semiconductor layer 51 in contact with the first trenches 55 are formed.
  • the first conductive impurity region 57a and the second conductive impurity region 58a are heavily doped.
  • a capping material such as SOG is further applied to the first trench 55 in which the first and second conductive droplets 57 and 58 are formed to prevent cross diffusion into the adjacent first trench 55.
  • a liquefied metal material that is, a metal liquid
  • a metal liquid is formed in the first trench 55 corresponding to a region where the first conductive impurity region 57a and the second conductive impurity region 58a are formed.
  • first and second metal electrodes 59 and 60 are formed to fill the spaced inside of the first trench 55, respectively.
  • a plurality of first trenches 55 spaced apart from each other are formed on the rear surface of the first conductive semiconductor layer 51 to have a depth capable of forming a PN junction.
  • P-type and N-type junctions are formed below the first trench 55 spaced apart to reduce the area distance between the PNs, and the sidewalls of the first trench 55 are protected by the third oxide layer 56 to be recombined. Therefore, the light efficiency can be prevented from being reduced, thereby maximizing the light efficiency.
  • the first trench 55 may be formed in a dot shape, light efficiency may be increased, and the first trench 55 may be formed deeper by using a dry etch. If the first trench is formed deeper as described above, the pattern may be densely formed because the probability of forming the side doping material and the PN junction may be increased and the side diffusion may be reduced. In addition, by reducing the distance that the light is transmitted to reach the back surface junction, it is possible to increase the light efficiency without recombination (recombination). Then, the position of the pattern and the depth of the trench are determined so that each metal contact is within the average charge movement distance in the wafer (carrier life time), so that the metal contact can be etched to 1/2 of the wafer thickness.
  • first conductive semiconductor layer 52 first conductive semiconductor layer
  • first conductive droplet 58 second conductive droplet
  • first conductive impurity region 58a second conductive impurity region
  • first metal electrode 60 second metal electrode

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Abstract

The object of the present invention is to provide a solar cell which can maximize light efficiency and can economize on process implementation and cost, and also to provide a production method for the solar cell. The solar cell of the present invention includes articles comprising: a surface-textured first electrically conductive semiconductor layer; a first electrically conductive high-density semiconductor layer which is formed within the surface of the first electrically conductive semiconductor layer; a first and a second oxide film respectively formed on the textured upper surface and back surface of the first electrically conductive semiconductor layer; a plurality of first trenches which are formed at intervals on the back surface of the first electrically conductive semiconductor layer; a third oxide film which is formed on the top-side surfaces of the first trenches; first and second electrically conductive impurity regions which are formed so as to have mutually different forms of electrical conductivity in the first electrically conductive semiconductor layer underneath neighbouring first trenches; and first and second metal electrodes which are formed within each of the first trenches, corresponding to the first and second electrically conductive impurity regions. The present invention is advantageous in that it can maximize the light efficiency of solar cells and can exploit inkjet technology to economize on process implementation and cost.

Description

태양전지 및 그의 제조방법Solar cell and manufacturing method thereof
본 발명은 태양전지에 관한 것으로서, 특히 광효율을 극대화시킬 수 있고, 공정의 구현 및 비용을 절감시킬 수 있는 태양전지 및 그의 제조방법에 관한 것이다. The present invention relates to a solar cell, and more particularly, to a solar cell and a method for manufacturing the same, which can maximize the light efficiency, and can reduce the implementation and cost of the process.
일반적으로 태양전지 기술은 근래에 화석 연료의 고갈화나 지구 온난화 등의 에너지, 환경 문제에 대한 해결책으로 제시된 것으로, 이와 같이 태양에너지 등의 자연 에너지를 이용하는 기술의 개발이 급속도로 진행되고 있다.In general, solar cell technology has recently been proposed as a solution to energy and environmental problems such as depletion of fossil fuels, global warming, and the like. Thus, the development of technology using natural energy such as solar energy is rapidly progressing.
상기와 같은 태양 에너지는 열 및 전기 등과 같은 다른 형태의 에너지로 변환될 수 있는 재생 가능한 에너지 공급원이다. 이와 같은 재생 가능한 에너지의 신뢰성 있는 공급원으로서 태양 에너지를 이용함에 있어서, 주된 결점은 광 에너지를 열이나 전기로 변환시키는 데 있어서의 낮은 효율, 그리고 하루 중의 시간 및 한 해의 월에 따라 태양 에너지에서의 편차이다. Such solar energy is a renewable energy source that can be converted into other forms of energy such as heat and electricity. In using solar energy as a reliable source of such renewable energy, the major drawback is the low efficiency in converting light energy into heat or electricity, and the solar energy at different times of the day and month of the year. Deviation.
광 에너지를 전기 에너지로 변환시키는 원리에 기초한 광기전력(PV: Photovoltaic) 전지는 태양 에너지를 전기 에너지로 변환시켜서 이용되는 것이다. 상기 PV 전지를 이용하는 시스템은 10 내지 20% 사이의 변환 효율을 지닐 수 있다.Photovoltaic (PV) cells based on the principle of converting optical energy into electrical energy are used to convert solar energy into electrical energy. Systems using such PV cells can have a conversion efficiency between 10 and 20%.
이와 같은 태양전지는 광을 전기에너지로 변환시키는 광전효과를 이용하는 소자이며, 상기 PV 전지는 위성 및 우주 왕복선에 전력을 제공하고, 전기를 주거 및 상업적 속성에 제공하며, 자동차 배터리 및 기타 네비게이션 기구를 충전시키는 등의 광범위한 용도에 이용될 수 있다. Such solar cells are devices that utilize the photoelectric effect of converting light into electrical energy, and the PV cells provide power to satellite and space shuttles, provide electricity to residential and commercial properties, and provide automotive batteries and other navigational devices. It can be used for a wide range of applications such as filling.
그러나, 이런 광범위한 활용도에도 불구하고 이론적으로 실리콘 태양전지의 광효율은 28%가 최대치이며, 현재에는 22%정도에서 한계를 나타내고 있다. However, in spite of this wide range of applications, theoretically, photovoltaic efficiency of silicon solar cells is the highest at 28%, and is currently limited at 22%.
이하, 첨부 도면을 참조하여 종래의 태양전지에 대하여 간략히 설명하면 다음과 같다. Hereinafter, a brief description of a conventional solar cell with reference to the accompanying drawings.
종래의 태양전지는 도 1에 도시한 바와 같이, 베이스 역할을 하는 제1도전형 반도체층(11)의 상부에 에미터 역할을 하는 제2도전형 반도체층(12)이 적층되어 있고, 제2도전형 반도체층(12) 상부에 반사 방지막인 보호막(13)이 형성되어 있고, 제1도전형 반도체층(11)의 양측 상부에 제1콘택층(14)이 형성되어 있고, 제1도전형 반도체층(11)의 하면에 제2콘택층(15)이 형성되어 있다. 그리고, 상기 제1, 제2콘택층(14, 15)에 양단이 연결되어 있는 구동전지(16)가 있다. In the conventional solar cell, as illustrated in FIG. 1, the second conductive semiconductor layer 12 serving as an emitter is stacked on the first conductive semiconductor layer 11 serving as a base, and the second conductive semiconductor layer 12 is stacked. A protective film 13, which is an antireflection film, is formed on the conductive semiconductor layer 12, and the first contact layer 14 is formed on both sides of the first conductive semiconductor layer 11, and the first conductive type is formed. The second contact layer 15 is formed on the bottom surface of the semiconductor layer 11. In addition, there is a driving battery 16 having both ends connected to the first and second contact layers 14 and 15.
이때, 제1도전형은 P형 불순물이고, 제2도전형은 N형 불순물이다. At this time, the first conductivity type is a P type impurity, and the second conductivity type is an N type impurity.
이와 같은 종래의 태양전지는 도 2에 도시한 바와 같이, 태양광을 입사 받으면 제1도전형 반도체층(11)과 제2도전형 반도체층(12)에 활성화된 전자(-)와 홀(+)이 발생하고, 전자(-)는 제2도전형 반도체층(12)으로 이동하고, 홀(+)은 제1도전형 반도체층(11)으로 이동하여 각각 제1, 제2콘택층(14, 15)으로 이동하여 각각의 콘택층을 통해서 구동전지(16)로 들어간다. 이와 같이 제1, 제2콘택층(14, 15)으로 전자(-)와 홀(+)이 들어가서 전기가 흐르게 된다. In the conventional solar cell as shown in FIG. 2, when sunlight is incident, electrons (−) and holes (+) activated in the first conductive semiconductor layer 11 and the second conductive semiconductor layer 12 are positive. ), Electrons (-) move to the second conductive semiconductor layer 12, holes (+) move to the first conductive semiconductor layer 11, and the first and second contact layers 14, respectively. 15, and enters the driving battery 16 through each contact layer. As such, electrons (−) and holes (+) enter the first and second contact layers 14 and 15 so that electricity flows.
상기와 같은 종래의 태양전지의 경우 일반적으로 P형 불순물로 구성된 제1도전형 반도체층(11)에 텍스쳐링을 형성한 후에 표면을 N형 불순물로 도핑 후, 그 양측 상부에 양극 콘택층 즉, 제1, 제2콘택층(14, 15)을 형성하고, 구동전지(16)를 장착하여 형성한다. 그리고, 제2도전형 반도체층(11) 상부에 보호막과 반사 보호막을 장착하여 사용하고 있다.In the case of the conventional solar cell as described above, after texturing is formed on the first conductive semiconductor layer 11 composed of P-type impurities, the surface is doped with N-type impurities, and then the anode contact layer, that is, the first First and second contact layers 14 and 15 are formed, and the driving battery 16 is mounted. A protective film and a reflective protective film are mounted on the second conductive semiconductor layer 11 to be used.
이와 같은 종래의 태양전지는 태양광의 입사량이 줄어드는 것을 방지하기 위해서 콘택홀(CONTACT HOLE)을 깊게 파서 전극을 형성하므로써, 전극의 면적을 줄여주어도 입사광량을 극대화 시키는 방법을 사용하였다. The conventional solar cell uses a method of maximizing the amount of incident light even if the electrode area is reduced by forming an electrode by digging a contact hole deeply in order to prevent the incident amount of sunlight from decreasing.
그러나, 이와 같은 종래에 따른 태양전지는 입사광이 들어와서 PN 접합영역에서 반응시 거리가 멀고 재결합되는 영역이 넓어 전기 추출 효율이 떨어진다는 문제가 있다. However, the conventional solar cell has a problem in that the incident light enters the reaction region in the PN junction region when the reaction distance is far and the recombination is large, the electrical extraction efficiency is reduced.
본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위해 제안된 것으로서, 태양전지의 광이용 효율을 증대시키고, 잉크젯방식을 활용하여 공정의 구현 및 비용을 절감시킬 수 있는 태양전지 및 그의 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the problems according to the prior art, a solar cell and a method for manufacturing the same, which can increase the light utilization efficiency of the solar cell, and reduce the implementation and cost of the process by using the inkjet method. The purpose is to provide.
상기 목적을 달성하기 위한 본 발명의 태양전지는 표면이 텍스쳐링 처리된 제1도전형 반도체층과; 상기 제1도전형 반도체층의 표면내에 형성된 제1도전형 고농도 반도체층과; 상기 제1도전형 반도체층의 텍스쳐링된 상면과 배면에 각각 형성된 제1, 제2산화막과; 상기 제1도전형 반도체층의 배면에 이격 형성된 복수개의 제1트렌치들과; 상기 제1트렌치의 상측면에 형성된 제3산화막과; 인접한 상기 제1트렌치들 하부의 상기 제1도전형 반도체층에 서로 다른 도전형을 갖고 형성된 제1, 제2도전형 불순물영역과; 상기 제1, 제2도전형 불순물영역에 대응되는 상기 각각 제1트렌치내에 형성된 제1, 제2금속전극으로 구성된 것을 특징으로 한다. The solar cell of the present invention for achieving the above object is a first conductive semiconductor layer surface-treated; A first conductive high concentration semiconductor layer formed in a surface of the first conductive semiconductor layer; First and second oxide films formed on textured top and bottom surfaces of the first conductive semiconductor layer, respectively; A plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer; A third oxide film formed on the upper side of the first trench; First and second conductive impurity regions formed in the first conductive semiconductor layer under the adjacent first trenches with different conductivity types; And first and second metal electrodes formed in the first trenches corresponding to the first and second conductive impurity regions, respectively.
그리고, 상기 구성을 갖는 본 발명의 태양전지의 제조방법은 제1도전형 반도체층의 표면을 텍스쳐링 처리하는 단계; 상기 제1도전형 반도체층의 표면내에 제1도전형 고농도 반도체층을 형성하는 단계; 상기 제1도전형 반도체층의 상면과 배면에 각각 제1, 제2산화막을 형성하는 단계; 상기 제1도전형 반도체층의 배면에 이격된 복수개의 제1트렌치들을 형성하는 단계; 상기 제1트렌치의 표면에 제3산화막을 형성하는 단계; 상기 제1트렌치의 하면 및 하부측면이 드러나도록 상기 제3산화막을 제거하는 단계; 인접한 상기 제1트렌치들 하부의 상기 제1도전형 반도체층에 서로 다른 도전형을 갖는 제1, 제2도전형 불순물영역을 형성하는 단계; 상기 제1, 제2도전형 불순물영역에 대응되는 상기 제1트렌치 내에 각각 제1, 제2금속전극을 형성하는 것을 특징으로 한다.In addition, the manufacturing method of the solar cell of the present invention having the above configuration comprises the steps of texturing the surface of the first conductive semiconductor layer; Forming a first conductive high concentration semiconductor layer on a surface of the first conductive semiconductor layer; Forming first and second oxide films on the top and bottom surfaces of the first conductive semiconductor layer, respectively; Forming a plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer; Forming a third oxide film on a surface of the first trench; Removing the third oxide layer so that the bottom and bottom sides of the first trench are exposed; Forming first and second conductive impurity regions having different conductivity types in the first conductive semiconductor layer under the adjacent first trenches; The first and second metal electrodes may be formed in the first trenches corresponding to the first and second conductive impurity regions, respectively.
상술한 본 발명에 따른 태양전지 및 그의 제조방법은 다음과 같은 효과가 있다. The solar cell and a method of manufacturing the same according to the present invention described above have the following effects.
첫째, 기판 즉, 제1도전형 반도체층의 배면에 PN 접합을 형성할 수 있는 깊이를 갖도록 복수개의 이격된 트렌치가 형성되어 있고, 이격된 트렌치 하부에 각각 P형과 N형 정션을 형성하여 PN간의 영역 거리를 축소시키고, 트렌치의 측벽을 산화막으로 보호하여 재결합(recombination)으로 인해 광효율이 감소되는 것을 방지할 수 있으므로, 태양전지의 광효율을 극대화할 수 있다. First, a plurality of spaced trenches are formed on a substrate, that is, a back surface of the first conductive semiconductor layer to have a depth capable of forming a PN junction, and P-type and N-type junctions are formed below the spaced trenches to form PN. By reducing the area distance between the gaps and protecting the sidewalls of the trenches with an oxide film, it is possible to prevent the light efficiency from decreasing due to recombination, thereby maximizing the light efficiency of the solar cell.
둘째, 기판 즉, 제1도전형 반도체층의 표면에 텍스쳐링 처리를 하므로써, 종래의 EVA 없이도 반사방지 필름으로 대체하여 광효율을 증대시킬 수 있다. Second, by texturing the substrate, that is, the surface of the first conductive semiconductor layer, it is possible to increase the light efficiency by replacing the anti-reflection film without conventional EVA.
셋째, 트렌치를 도트(dot)형으로 형성하는 것도 가능하므로 광효율이 증가하며, 드라이 에치(dry etch)를 활용하여 트렌치를 더 깊게 형성할 수도 있다. 이와 같이 트렌치를 더 깊게 형성하면, 옆 도핑물질과 PN 정션을 형성하기 위한 확률을 높이고 측면 확산을 적게해도 되므로 패턴을 조밀하게 형성할 수 있다. 또한, 빛이 투과되어 백면 정션까지 도달하는 거리를 줄여줌으로써, 재결합(recombination) 없이 광효율이 증대될 수 있도록 할 수 있다. Third, since the trench may be formed in a dot shape, the light efficiency may be increased, and the trench may be formed deeper by using dry etch. If the trench is formed deeper as described above, the pattern may be densely formed because the probability of forming the side doping material and the PN junction may be increased and the side diffusion may be reduced. In addition, by reducing the distance that the light is transmitted to reach the back surface junction, it is possible to increase the light efficiency without recombination (recombination).
넷째, 제1, 제2도전형 불순물영역과 제1, 제2금속전극의 형성을 잉크젯 방식으로 형성할 수 있으므로, 공정의 구현 및 비용을 절감시킬 수 있다. Fourth, since the formation of the first and second conductive impurity regions and the first and second metal electrodes can be formed by an inkjet method, the implementation and the cost of the process can be reduced.
도 1은 종래기술에 따른 태양전지의 구조단면도이다.1 is a structural cross-sectional view of a solar cell according to the prior art.
도 2는 종래의 태양전지의 전기의 흐름을 설명하는 도면이다. 2 is a view for explaining the flow of electricity of a conventional solar cell.
도 3은 본 발명의 실시예에 따른 태양전지의 구조단면도이다. 3 is a structural cross-sectional view of a solar cell according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 태양전지의 전기의 흐름을 설명하는 도면이다. 4 is a view for explaining the flow of electricity of the solar cell according to an embodiment of the present invention.
도 5a 내지 도 5i는 본 발명의 실시예에 따른 태양전지의 제조방법을 나타낸 공정단면도이다. 5A through 5I are cross-sectional views illustrating a method of manufacturing a solar cell according to an exemplary embodiment of the present invention.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
본 발명에 따른 실시예를 설명하기에 앞서서, 제1도전형은 P형으로 정의하여 설명하고, 제2도전형은 N형으로 정의하여 설명하기로 한다. Prior to describing an embodiment according to the present invention, the first conductivity type will be described as defined as P type, and the second conductivity type will be described as defined as N type.
먼저, 본 발명의 실시예에 따른 태양전지는, 도 2에 도시한 바와 같이, 표면이 텍스쳐링 처리된 제1도전형 반도체층(51)이 있고, 상기 제1도전형 반도체층(51)의 표면내에 제1도전형 고농도 반도체층(52)이 형성되어 있고, 제1도전형 반도체층(51)의 텍스쳐링된 상면과 배면에 각각 제1, 제2산화막(53, 54)이 형성되어 있고, 제1도전형 반도체층(51)의 배면에 이격된 복수개의 제1트렌치(55)들이 형성되어 있다. First, as shown in FIG. 2, the solar cell according to the embodiment of the present invention includes a first conductive semiconductor layer 51 having a textured surface, and a surface of the first conductive semiconductor layer 51. The first conductive high concentration semiconductor layer 52 is formed therein, and the first and second oxide films 53 and 54 are formed on the textured upper and rear surfaces of the first conductive semiconductor layer 51, respectively. A plurality of first trenches 55 spaced apart from each other may be formed on the rear surface of the first conductive semiconductor layer 51.
이때, 제1트렌치(55)들은 일정간격을 갖고 이격된 복수개의 도트(dot) 형태로 구성될 수도 있고, 라인(line) 형상으로 형성될 수도 있다. In this case, the first trenches 55 may be formed in the form of a plurality of dots spaced apart from each other at predetermined intervals, or may be formed in a line shape.
그리고, 상기 제1트렌치(55)의 하면 및 하부측면이 노출되도록 즉, 제1트렌치(55)의 상부 측면에만 제3산화막이 형성되어 있다. The third oxide layer is formed only on the upper side of the first trench 55 so that the lower and lower side surfaces of the first trench 55 are exposed.
그리고, 인접한 제1트렌치(55)들의 하측 부분에 노출된 제1도전형 반도체층(51)에는 서로 다른 도전형을 갖는 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)이 이웃하게 형성되어 있다. The first conductive semiconductor layer 51 exposed to the lower portions of the adjacent first trenches 55 may have a first conductivity type impurity region 57a and a second conductivity type impurity region 58a having different conductivity types. This is formed adjacent to.
이때, 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)은 고농도로 도핑되어 있는 것으로, 제1도전형 불순물영역(57a)은 붕산(B2O3) 계열의 불순물로 도핑되어 있고, 제2도전형 불순물영역(58a)은 인산(P2O5)계열의 불순물로 도핑되어 있다. In this case, the first conductive impurity region 57a and the second conductive impurity region 58a are heavily doped, and the first conductive impurity region 57a is doped with boric acid (B 2 O 3) -based impurities. The second conductive impurity region 58a is doped with an impurity of the phosphoric acid (P 2 O 5) series.
상기에서 인접한 제1트렌치(55)로 상기 제1, 제2도전형 불순물영역(57a, 58a)이 크로스 확산되는 것을 방지하기 위해 제1, 제2도전형 액적(57, 58)이 형성된 제1트렌치(55) 내에 SOG와 같은 캡핑(CAPPING) 물질이 더 도포될 수도 있다. 이와 같이 SOG와 같은 캡핑 물질을 더 도포하면, 옆 도핑부로 도핑되는 상황을 방지할 수 있다.The first and second conductive droplets 57 and 58 having first and second conductive droplets 57 and 58 formed thereon to prevent cross diffusion of the first and second conductive impurity regions 57a and 58a into the adjacent first trench 55. In the trench 55, a capping material such as SOG may be further applied. In this way, if a capping material such as SOG is further applied, it is possible to prevent the doping of the side doping portion.
그리고, 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)에 대응되는 각 제1트렌치(55)들 내부에는 제1트렌치(55)를 채우도록 각각 제1, 제2금속전극(59, 60)들이 형성되어 있다. 상기 제1, 제2금속전극(59, 60)들은 차후에 구동전지와 콘택을 위한 복수 콘택층 역할을 하는 것이다. The first and second metals may be filled in the first trenches 55 corresponding to the first conductive impurity region 57a and the second conductive impurity region 58a, respectively. Electrodes 59 and 60 are formed. The first and second metal electrodes 59 and 60 serve as a plurality of contact layers for contact with the driving battery.
그리고, 상기 구성을 갖는 태양전지는, 도 4에 도시한 바와 같이, 태양광이 입사되면, 포톤(Photon)에 의해 전자와 홀이 발생하여 제1도전형 불순물영역(57a)으로는 홀(+)이 이동하고, 제2도전형 불순물영역(58a)으로는 전자가(-) 이동한다. 그리고, 이동된 홀(+)과 전자(-)는 제1, 제2금속전극(59, 60)을 거쳐서 구동전지(61)로 전달된다. 이와 같은 흐름에 의해서 태양전지에 전기가 흐르게 되는 것이다. In the solar cell having the above-described configuration, when sunlight is incident, as shown in FIG. 4, electrons and holes are generated by photons, and holes (+) are formed in the first conductive impurity region 57a. ) Moves and electrons (-) move to the second conductive impurity region 58a. The moved holes (+) and electrons (-) are transferred to the driving battery 61 through the first and second metal electrodes 59 and 60. By this flow, electricity flows to the solar cell.
다음에, 상기 구조를 갖는 본 발명의 실시예에 따른 태양전지의 제조방법에 대하여 설명하기로 한다. Next, a method of manufacturing a solar cell according to an embodiment of the present invention having the above structure will be described.
본 발명의 실시예에 따른 태양전지의 제조방법은, 도 5a에 도시한 바와 같이, 기판 역할을 하는 제1도전형 반도체층(51)의 표면을 태양전지의 효율을 향상시키기 위하여 텍스쳐링(texturing) 처리한다. In the method of manufacturing a solar cell according to an embodiment of the present invention, as illustrated in FIG. 5A, the surface of the first conductive semiconductor layer 51 serving as a substrate is textured to improve the efficiency of the solar cell. Process.
텍스쳐링이란 태양전지의 기판 표면에 입사되는 빛의 반사에 의한 광학적 손실에 의해 그 특성이 저하되는 현상을 방지하지 위한 것으로서, 태양전지에서 사용되는 기판의 표면을 거칠게 만드는 것, 즉, 기판 표면에 요철 형상의 패턴을 형성하는 것을 말한다. 텍스쳐링으로 기판 표면이 거칠어지면 한번 반사된 빛이 재반사되어 입사된 빛의 반사율을 감소시킴으로써 광 포획량이 증가되어 광학적 손실이 저감되는 효과를 얻을 수 있다.Texturing is to prevent the phenomenon of deterioration due to the optical loss caused by the reflection of light incident on the substrate surface of the solar cell, and to roughen the surface of the substrate used in the solar cell, that is, the uneven surface of the substrate To form a pattern of shapes. If the surface of the substrate is roughened by texturing, the light reflected once is reflected back to decrease the reflectance of the incident light, thereby increasing the amount of light trapped, thereby reducing the optical loss.
다음에, 도 5b에 도시한 바와 같이, 텍스쳐링 처리된 제1도전형 반도체층(51)의 표면에 고농도의 제1도전형 불순물을 주입하여 제1도전형 고농도 반도체층(52)을 형성한다. Next, as shown in FIG. 5B, the first conductive high concentration semiconductor layer 52 is formed by injecting a high concentration of the first conductive type impurity into the surface of the textured first conductive semiconductor layer 51.
상기에는 P타입 태양전지를 구성하기 위해서 고농도의 제1도전형 불순물인 P+ 불순물을 주입하였는데, 만일, N타입 태양전지를 구성하려고 한다면, N형 고농도 불순물을 주입하여 형성할 수 있다. In order to form a P-type solar cell, a high concentration of P + impurity, which is a first conductivity type impurity, is implanted. If an N-type solar cell is to be formed, it may be formed by implanting an N-type high concentration impurity.
이후에, 도 5c에 도시한 바와 같이, 양면 열산화공정을 진행하여 텍스쳐링된 상면에 제1산화막(53)을 형성하고, 제1도전형 반도체층(51)의 배면에 제2산화막(54)을 형성한다. Subsequently, as shown in FIG. 5C, a first oxide film 53 is formed on the textured upper surface by performing a double-sided thermal oxidation process, and a second oxide film 54 is formed on the rear surface of the first conductive semiconductor layer 51. To form.
다음에, 도 5d에 도시한 바와 같이, 포토마스크(미도시)를 이용하여 제1도전형 반도체층(51) 배면의 제2산화막(54) 및 제1도전형 반도체층(51)을 순차적으로 식각해서 일정간격 이격된 복수개의 제1트렌치(55)들을 형성한다. Next, as shown in FIG. 5D, the second oxide film 54 and the first conductive semiconductor layer 51 on the back surface of the first conductive semiconductor layer 51 are sequentially formed using a photomask (not shown). Etching is performed to form a plurality of first trenches 55 spaced apart from each other.
이때, 제1트렌치(55)들은 이격된 복수개의 도트(dot) 형태로 구성할 수도 있고, 이격된 복수개의 라인(line) 형상으로 형성할 수도 있다. In this case, the first trenches 55 may be formed in the form of a plurality of spaced apart dots, or may be formed in the form of a plurality of spaced apart lines.
이후에, 도 5e에 도시한 바와 같이, 상기 구조물에 열산화공정을 진행하여 제1트렌치(55)의 표면에 제3산화막(56)을 형성한다. Thereafter, as illustrated in FIG. 5E, a thermal oxidation process is performed on the structure to form a third oxide film 56 on the surface of the first trench 55.
다음에, 도 5f에 도시한 바와 같이, 제1트렌치(55)가 상면으로 오도록 상기 구조물을 뒤집어서 배치시킨다. Next, as shown in FIG. 5F, the structure is turned upside down so that the first trench 55 is brought up.
이후에, 제1트렌치(55)의 표면에 형성된 제3산화막(56)의 일부를 제거할 수 있도록, 제1트렌치(55)에 잉크젯 방식의 장치를 이용하여 산화막 제거용액을 액적(액체로 된 물방울) 형태로 떨어뜨린다. 이와 같은 공정을 진행하면, 제1트렌치(55) 하면 및 하부측면의 제3산화막(56)이 제거되고, 제1트렌치(55) 하면 및 하부측면의 제1도전형 반도체층(51)이 드러나게 된다. Subsequently, an oxide film removing solution is dropped into the first trench 55 by using an inkjet device to remove a portion of the third oxide film 56 formed on the surface of the first trench 55. Drops in the form of water droplets). In this process, the third oxide film 56 on the lower surface and the lower side of the first trench 55 is removed, and the first conductive semiconductor layer 51 on the lower surface and the lower side of the first trench 55 is exposed. do.
이때, 산화막 제거용액으로는 불산(HF) 함유 용액을 사용할 수 있다. At this time, a hydrofluoric acid (HF) -containing solution may be used as the oxide film removal solution.
다음에, 도 5g에 도시한 바와 같이, 이격된 제1트렌치(55)의 노출된 제1도전형 반도체층(51)의 상부에 각각 제1도전형 액적(57)과 제2도전형 액적(58)을 떨어뜨린다. Next, as shown in FIG. 5G, the first conductive droplet 57 and the second conductive droplet 57 may be disposed on the exposed first conductive semiconductor layer 51 of the first trench 55 spaced apart from each other. 58) drop.
이때, 상기 제1트렌치(55)가 도트(dot) 형태로 형성되었을 때는 사방으로 인접한 제1트렌치(55)들간에는 서로 다른 도전형의 액적들을 떨어뜨린다. 그리고, 제1트렌치(55)가 라인(line) 형태로 형성되어 있을 때도 서로 인접한 제1트렌치(55)에는 서로 다른 도전형의 액적들을 떨어뜨린다.At this time, when the first trench 55 is formed in a dot shape, droplets of different conductivity types are dropped between the first trenches 55 that are adjacent in all directions. Also, even when the first trench 55 is formed in a line shape, droplets of different conductivity types are dropped in the adjacent first trenches 55.
이때, 제1도전형 액적(57)은 P형 액적으로 주로 붕산(B2O3)계열을 사용하고, 제2도전형 액적(58)은 N형 액적으로 주로 인산(P2O5)계열을 사용한다. In this case, the first conductive droplet 57 mainly uses boric acid (B 2 O 3) series as a P-type droplet, and the second conductive droplet 58 mainly uses phosphoric acid (P 2 O 5) series as an N-type droplet.
이후에, 도 5h에 도시한 바와 같이, 이격된 상기 제1트렌치(55)들에 떨어뜨린 제1도전형 액적(57)과 제2도전형 액적(58)들에 확산(Diffusion) 공정을 진행하여 제1트렌치(55)들에 접한 제1도전형 반도체층(51)에 이격된 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)을 형성한다. 이때, 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)은 고농도로 도핑되어 있다. Subsequently, as illustrated in FIG. 5H, a diffusion process is performed on the first conductive droplets 57 and the second conductive droplets 58 dropped on the spaced apart first trenches 55. Thus, the first conductive impurity region 57a and the second conductive impurity region 58a spaced apart from the first conductive semiconductor layer 51 in contact with the first trenches 55 are formed. At this time, the first conductive impurity region 57a and the second conductive impurity region 58a are heavily doped.
이때, 인접한 제1트렌치(55)로 크로스 확산되는 것을 방지하기 위해 제1, 제2도전형 액적(57, 58)이 형성된 제1트렌치(55) 내에 SOG와 같은 캡핑(CAPPING) 물질을 더 도포해 줄 수도 있다.In this case, a capping material such as SOG is further applied to the first trench 55 in which the first and second conductive droplets 57 and 58 are formed to prevent cross diffusion into the adjacent first trench 55. You can also
다음에, 도 5i에 도시한 바와 같이, 제1도전형 불순물영역(57a)과 제2도전형 불순물영역(58a)이 형성된 영역에 대응되는 제1트렌치(55)에 액화 금속물질 즉, 금속 액적을 떨어뜨린다. 이와 같은 공정을 진행하면, 이격된 제1트렌치(55) 내부를 채우도록 각각 제1, 제2금속전극(59, 60)이 형성된다.Next, as illustrated in FIG. 5I, a liquefied metal material, that is, a metal liquid, is formed in the first trench 55 corresponding to a region where the first conductive impurity region 57a and the second conductive impurity region 58a are formed. Drop the enemy. In this process, first and second metal electrodes 59 and 60 are formed to fill the spaced inside of the first trench 55, respectively.
상기 구성 및 제조방법을 갖는 본 발명의 태양전지는 제1도전형 반도체층(51)의 배면에 PN 접합을 형성할 수 있는 깊이를 갖도록 복수개의 이격된 제1트렌치(55)가 형성되어 있고, 이격된 제1트렌치(55) 하부에 각각 P형과 N형 정션을 형성하여 PN간의 영역 거리를 축소시키고, 제1트렌치(55)의 측벽을 제3산화막(56)으로 보호하여 재결합(recombination)으로 인해 광효율이 감소되는 것을 방지하여 광효율을 극대화할 수 있다. In the solar cell of the present invention having the above-described configuration and manufacturing method, a plurality of first trenches 55 spaced apart from each other are formed on the rear surface of the first conductive semiconductor layer 51 to have a depth capable of forming a PN junction. P-type and N-type junctions are formed below the first trench 55 spaced apart to reduce the area distance between the PNs, and the sidewalls of the first trench 55 are protected by the third oxide layer 56 to be recombined. Therefore, the light efficiency can be prevented from being reduced, thereby maximizing the light efficiency.
또한, 제1도전형 반도체층(51)의 표면에 텍스쳐링 처리를 하므로써, 종래의 EVA 없이도 반사방지 필름으로 대체하여 태양전지의 광효율을 증대시킬 수 있다. In addition, by texturing the surface of the first conductive semiconductor layer 51, it is possible to increase the light efficiency of the solar cell by replacing the anti-reflection film without conventional EVA.
그리고, 제1트렌치(55)를 도트(dot)형으로 형성하는 것도 가능하므로 광효율이 증가하며, 드라이 에치(dry etch)를 활용하여 제1트렌치(55)를 더 깊게 형성할 수도 있다. 이와 같이 제1트렌치를 더 깊게 형성하면, 옆 도핑물질과 PN 정션을 형성하기 위한 확률을 높이고 측면 확산을 적게해도 되므로 패턴을 조밀하게 형성할 수 있다. 또한, 빛이 투과되어 백면 정션까지 도달하는 거리를 줄여줌으로써, 재결합(recombination) 없이 광효율이 증대될 수 있도록 할 수 있다. 그리고, 각각의 메탈 콘택이 웨이퍼내의 전하 평균이동거리(Carrier life time 내의 이동거리) 내에 있도록 패턴의 위치와 트렌치의 깊이를 결정하며, 때문에 웨이퍼 두께의 1/2까지 식각할 수 있다.In addition, since the first trench 55 may be formed in a dot shape, light efficiency may be increased, and the first trench 55 may be formed deeper by using a dry etch. If the first trench is formed deeper as described above, the pattern may be densely formed because the probability of forming the side doping material and the PN junction may be increased and the side diffusion may be reduced. In addition, by reducing the distance that the light is transmitted to reach the back surface junction, it is possible to increase the light efficiency without recombination (recombination). Then, the position of the pattern and the depth of the trench are determined so that each metal contact is within the average charge movement distance in the wafer (carrier life time), so that the metal contact can be etched to 1/2 of the wafer thickness.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아니다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. 따라서, 본 발명의 범위는 설명된 예에 의해서가 아니라 청구범위에 의해서 정해져야 할 것이다.Although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Accordingly, the scope of the invention should be defined by the claims rather than by the examples described.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
51 : 제1도전형 반도체층 52 : 제1도전형 고농도 반도체층 51: first conductive semiconductor layer 52: first conductive semiconductor layer
53 : 제1산화막 54 : 제2산화막 53: first oxide film 54: second oxide film
55 : 제1트렌치 56 : 제3산화막 55: first trench 56: third oxide film
57 : 제1도전형 액적 58 : 제2도전형 액적 57: first conductive droplet 58: second conductive droplet
57a : 제1도전형 불순물영역 58a : 제2도전형 불순물영역 57a: first conductive impurity region 58a: second conductive impurity region
59 : 제1금속전극 60 : 제2금속전극 59: first metal electrode 60: second metal electrode

Claims (9)

  1. 표면이 텍스쳐링 처리된 제1도전형 반도체층과; A first conductive semiconductor layer whose surface is textured;
    상기 제1도전형 반도체층의 표면내에 형성된 제1도전형 고농도 반도체층과; A first conductive high concentration semiconductor layer formed in a surface of the first conductive semiconductor layer;
    상기 제1도전형 반도체층의 텍스쳐링된 상면과 배면에 각각 형성된 제1, 제2산화막과; First and second oxide films formed on textured top and bottom surfaces of the first conductive semiconductor layer, respectively;
    상기 제1도전형 반도체층의 배면에 이격 형성된 복수개의 제1트렌치들과; A plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer;
    상기 제1트렌치의 상측면에 형성된 제3산화막과; A third oxide film formed on the upper side of the first trench;
    인접한 상기 제1트렌치들 하부의 상기 제1도전형 반도체층에 서로 다른 도전형을 갖고 형성된 제1, 제2도전형 불순물영역과; First and second conductive impurity regions formed in the first conductive semiconductor layer under the adjacent first trenches with different conductivity types;
    상기 제1, 제2도전형 불순물영역에 대응되는 상기 각각 제1트렌치내에 형성된 제1, 제2금속전극으로 구성된 것을 특징으로 하는 태양전지. And a first and a second metal electrode formed in each of the first trenches corresponding to the first and second conductive impurity regions.
  2. 제1항에 있어서, The method of claim 1,
    상기 제1트렌치들은 일정간격을 갖고 이격된 복수개의 도트(dot) 형태나 라인(line) 형상으로 형성된 것을 특징으로 하는 태양전지. The first trench is a solar cell, characterized in that formed in a plurality of dots (dot) shape or a line shape spaced apart at a predetermined interval.
  3. 제1도전형 반도체층의 표면을 텍스쳐링 처리하는 단계; Texturing the surface of the first conductive semiconductor layer;
    상기 제1도전형 반도체층의 표면내에 제1도전형 고농도 반도체층을 형성하는 단계; Forming a first conductive high concentration semiconductor layer on a surface of the first conductive semiconductor layer;
    상기 제1도전형 반도체층의 상면과 배면에 각각 제1, 제2산화막을 형성하는 단계; Forming first and second oxide films on the top and bottom surfaces of the first conductive semiconductor layer, respectively;
    상기 제1도전형 반도체층의 배면에 이격된 복수개의 제1트렌치들을 형성하는 단계; Forming a plurality of first trenches spaced apart from a rear surface of the first conductive semiconductor layer;
    상기 제1트렌치의 표면에 제3산화막을 형성하는 단계; Forming a third oxide film on a surface of the first trench;
    상기 제1트렌치의 하면 및 하부측면이 드러나도록 상기 제3산화막을 제거하는 단계; Removing the third oxide layer so that the bottom and bottom sides of the first trench are exposed;
    인접한 상기 제1트렌치들 하부의 상기 제1도전형 반도체층에 서로 다른 도전형을 갖는 제1, 제2도전형 불순물영역을 형성하는 단계; Forming first and second conductive impurity regions having different conductivity types in the first conductive semiconductor layer under the adjacent first trenches;
    상기 제1, 제2도전형 불순물영역에 대응되는 상기 제1트렌치 내에 각각 제1, 제2금속전극을 형성하는 것을 특징으로 하는 태양전지의 제조방법. And forming first and second metal electrodes in the first trenches corresponding to the first and second conductive impurity regions, respectively.
  4. 제3항에 있어서, The method of claim 3,
    상기 제1트렌치들은 이격된 복수개의 도트(dot) 형태나 복수개의 라인(line) 형상으로 형성하는 것을 특징으로 하는 태양전지의 제조방법. The first trenches are formed in a plurality of dot (dot) shape or a plurality of line (line) shape manufacturing method of a solar cell, characterized in that.
  5. 제3항에 있어서, The method of claim 3,
    상기 제1트렌치 하면 및 하부측면의 상기 제3산화막을 제거하는 단계는, Removing the third oxide film on the lower surface and the lower side of the first trench,
    상기 제1트렌치에 잉크젯 방식의 장치를 이용하여 산화막 제거용액을 액적형태로 떨어뜨려서 진행하는 것을 특징으로 하는 태양전지의 제조방법. The method of manufacturing a solar cell, characterized in that to proceed by dropping the oxide film removal solution in the form of droplets using an inkjet device in the first trench.
  6. 제5항에 있어서, The method of claim 5,
    상기 산화막 제거용액으로는 불산(HF) 함유 용액을 사용하는 것을 특징으로 하는 태양전지의 제조방법. A method of manufacturing a solar cell, wherein a solution containing hydrofluoric acid (HF) is used as the oxide film removal solution.
  7. 제3항에 있어서, The method of claim 3,
    상기 제1, 제2도전형 불순물영역의 형성은, Formation of the first and second conductive impurity regions is
    이격된 상기 제1트렌치들의 노출된 상기 제1도전형 반도체층의 상부에 각각 제1, 제2도전형 액적을 떨어뜨린 후, 확산공정을 진행하여 형성하는 것을 특징으로 하는 태양전지의 제조방법. And dropping first and second conductive droplets on the exposed first conductive semiconductor layer, respectively, of the first trenches spaced apart from each other, followed by a diffusion process.
  8. 제7항에 있어서, The method of claim 7, wherein
    상기 제1도전형 액적은 고농도의 붕산(B2O3) 계열의 불순물을 사용하고, 상기 제2도전형 액적은 고농도의 인산(P2O5) 계열의 불순물을 사용하는 것을 특징으로 하는 태양전지의 제조방법. The first conductive droplet uses a high concentration of boric acid (B2O3) based impurities, and the second conductive droplet uses a high concentration of phosphoric acid (P2O5) based impurities.
  9. 제3항에 있어서, The method of claim 3,
    상기 제1, 제2금속전극은 상기 제1, 제2도전형 불순물영역에 대응되는 상기 제1트렌치 내에 금속 액적을 떨어뜨려서 형성하는 것을 특징으로 하는 태양전지의 제조방법. The first and second metal electrodes are formed by dropping metal droplets in the first trenches corresponding to the first and second conductive impurity regions.
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