WO2012068754A1 - 液晶显示器的像素阵列制造方法 - Google Patents

液晶显示器的像素阵列制造方法 Download PDF

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WO2012068754A1
WO2012068754A1 PCT/CN2010/079802 CN2010079802W WO2012068754A1 WO 2012068754 A1 WO2012068754 A1 WO 2012068754A1 CN 2010079802 W CN2010079802 W CN 2010079802W WO 2012068754 A1 WO2012068754 A1 WO 2012068754A1
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Prior art keywords
layer
photoresist layer
data line
region
etching
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French (fr)
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贺成明
李明羲
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a liquid crystal display manufacturing technology, and more particularly to a pixel array manufacturing method for a liquid crystal display.
  • TFT Thin film transistor liquid crystal display
  • LCD uses a thin film transistor (TFT) as a pixel switch, which is suitable for applications requiring high resolution, and therefore plays an important role.
  • each pixel has one TFT as a switch.
  • the gate of the TFT is connected to the scan line (Scan) Line), source (Source) connected to the data line (Data Line), and the drain is connected to the pixel electrode.
  • scan line scan line
  • Source Source
  • Data Line data line
  • drain is connected to the pixel electrode.
  • the TFT LCD manufacturing process generally consists of three phases: Array Process (Array Process), liquid crystal injection process (Cell process) and assembly process (Module) Process).
  • Array Process Array Process
  • Cell process liquid crystal injection process
  • Module Module Process
  • TFTs storage capacitors, lines, and the like are formed on a glass substrate.
  • FIGS. 1 to 3 show the steps of a pixel array manufacturing method of a thin film transistor liquid crystal display of the prior art.
  • Each of FIGS. 1 to 3 includes two portions (A) and (B), wherein part (A) shows a cross section of a TFT portion (also referred to as a switch region), and (B) a portion shows A section of the data line region is formed.
  • the pixel array manufacturing method of the thin film transistor liquid crystal display of the prior art mainly adopts a four-mask process.
  • a first metal layer is formed on a glass substrate 100 by a deposition process, and a development process is performed using a photomask.
  • the developing process is: after applying a photoresist (not shown) on the first metal layer, the photoresist is exposed by an exposure machine according to the first mask having a specific pattern, and then the developer is used. The exposed photoresist is washed away.
  • the first metal layer is then etched. In this step, a wet etching process is generally employed.
  • the etching process etches the first metal layer not covered by the photoresist by strong acid removal to form the gate metal layer 110 as shown.
  • a gate insulating layer 120 is formed, and a semiconductor layer 130 is formed on the gate insulating layer 120.
  • the semiconductor layer 130 is generally amorphous silicon (Amorphous) Si; a-Si) layer.
  • a second metal layer 140 is formed on the semiconductor layer 130 as a source/drain of the TFT, and thus this layer is also referred to as a source/drain metal layer.
  • this layer of photoresist 150 includes a photoresist layer 152 of a general thickness in the switching region (hereinafter referred to as a switching region photoresist layer), wherein light above the corresponding gate metal layer 110 is shown.
  • a recess is formed in the resist layer, here a position where the source-drain conductive channel 155 is predetermined to be formed, that is, the source-drain conductive via photoresist layer 154 at the bottom of the recess has a small thickness.
  • the photoresist forms a photoresist layer 156 of a desired pattern (hereinafter referred to as a data line region photoresist layer) in the data line region.
  • the second metal layer (ie, the source/drain metal layer) 140 is etched by the patterned photoresist 150 to be unpatterned. Portions of the second metal layer 140 covered by the photoresist 150 are removed to form a first portion 142 (ie, source/drain) and a second portion 146 (ie, data lines).
  • a wet etching process is generally employed. Since wet etching is an isotropic etching (Isotropic Etch), so there is an Undercut, which is the part of the metal layer that you want to keep, and the surrounding area will still be etched away, so the part of the metal layer left will be smaller than the covered photoresist layer. As shown in the figure.
  • the semiconductor layer 130 is etched in the switching region and the data line region.
  • dry etching is generally employed.
  • the layer of photoresist 150 is etched in the switching region for the purpose of removing the photoresist layer 154 to turn on the source and drain conductive vias 155 and etching the layer of photoresist 150 in the data line region. Dry etching is usually used here, and oxygen (O2) is generally used as an etching gas.
  • the thickness of the photoresist 150 is uniform in the switching region and the data line region.
  • the thickness h1 of the switch region photoresist layer 152 and the thickness h2 of the data line region photoresist layer 156 are 2.2 ⁇ m. That is, before the photoresist 150 is etched, the photoresist thickness ratio h1:h2 provided in the switching region and the data line region is 1:1. If the photoresist thickness h3 of the etching removal is 0.7 ⁇ m, the thickness h4 of the remaining switch region photoresist layer 152 and the thickness h5 of the data line region photoresist layer 156 are each 1.5 ⁇ m.
  • the semiconductor layer 136 finally left in the data line region has a large area, so that the aperture ratio (Aperture) Ratio) is low.
  • the aperture ratio is the effective area where each pixel can transmit light divided by the total area of the pixels. The higher the aperture ratio, the brighter the overall picture. Therefore, if the aperture ratio is low, the picture will appear dark.
  • a primary object of the present invention is to provide a method of fabricating a pixel array for a liquid crystal display, which can increase an aperture ratio.
  • the pixel array manufacturing method of the liquid crystal display includes: forming a first metal layer on a glass substrate and etching to form a first metal layer of a desired pattern; forming an insulating layer to cover the first metal layer and the glass substrate Forming a semiconductor layer on the insulating layer; forming a second metal layer on the semiconductor layer; forming a photoresist layer of a predetermined pattern on the second metal layer, the photoresist layer comprising a switch region photoresist layer And a data line region photoresist layer; etching the second metal layer to remove a portion of the second metal layer not covered by the switch region photoresist layer and the data line region photoresist layer; etching the semiconductor a layer; etching the switch region photoresist layer and the data line region photoresist layer; etching an edge portion of the semiconductor layer of the switching region and the data
  • the pixel array manufacturing method of the liquid crystal display includes: forming a first metal layer on a glass substrate and etching to form a first metal layer of a desired pattern; forming an insulating layer to cover the first metal layer and the glass substrate; Forming a semiconductor layer on the insulating layer; forming a second metal layer on the semiconductor layer; forming a photoresist layer of a predetermined pattern on the second metal layer, the photoresist layer comprising a switch region photoresist layer and a data line region photoresist layer; etching the second metal layer to remove a portion of the second metal layer not covered by the switch region photoresist layer and the data line region photoresist layer; etching the semiconductor layer Etching an edge portion of the semiconductor layer of the switching region and the data line region; etching the switching region photoresist layer and the data line region photoresist layer.
  • the area of the semiconductor layer of the switching region and the data line region is etched by the fluorine gas at the same time as or after the etching of the photoresist layer, the area of the semiconductor layer of the data line region is further reduced, thereby improving Opening ratio.
  • FIGS. 1 to 3 are schematic cross-sectional views showing steps in a method of fabricating a pixel array of a thin film transistor liquid crystal display of the prior art, in which part (A) of each figure shows a switching area, and part (B) shows a data line area.
  • FIGS. 4 to 6 are schematic cross-sectional views showing respective steps of a method of fabricating a pixel array of a thin film transistor liquid crystal display according to the present invention, wherein part (A) of each figure shows a switching area, and part (B) shows a data line area.
  • FIGS. 4 to 6 are schematic cross-sectional views showing respective steps of a method of fabricating a pixel array of a thin film transistor liquid crystal display according to the present invention, wherein part (A) of each of the figures shows a switching region, that is, a conductive channel connecting the source and the drain, (B) Part of the display data line area.
  • a first metal layer is first deposited on a glass substrate 400, and a development process is performed using a photomask.
  • the developing process is to apply a photoresist (not shown) on the first metal layer, expose the photoresist by an exposure machine according to the first mask having a specific pattern, and then expose the developer with a developer.
  • the photoresist is washed away.
  • the first metal layer is then etched. In this step, a wet etching process is generally employed.
  • the etching process etches the first metal layer not covered by the photoresist by strong acid removal to form a first metal layer of a desired pattern, that is, the gate metal layer 410 as shown in the drawing.
  • an insulating layer is formed by a deposition process to cover the gate metal layer 410 and the glass substrate 400 exposed by the switching region and the data line region, that is, the gate insulating layer 420 is formed in the figure, and then the gate insulating layer 420 is formed.
  • a semiconductor layer 430 is formed thereon.
  • This semiconductor layer 430 is generally amorphous silicon (Amorphous) Si; a-Si) layer.
  • a second metal layer 440 is formed on the semiconductor layer 430.
  • this layer of metal will serve as the source/drain of the TFT, this layer is also referred to as a source/drain metal layer.
  • a photoresist 450 is applied on the source/drain metal layer 440, and the photoresist 450 is formed into a desired pattern by a process of exposing and developing the photoresist 450 by using a photomask. As shown in FIG.
  • this layer of photoresist (also referred to as a photoresist layer) 450 includes a photoresist layer 452 of a general thickness in the switching region (hereinafter referred to as a switch region photoresist layer), wherein A recess is formed over the gate metal layer 410, here a location where the source-drain conductive channel 455 is predetermined, that is, the source-drain conductive via photoresist layer 454 at the bottom of the recess has a small thickness.
  • the photoresist forms a photoresist layer 456 of a desired pattern (hereinafter referred to as a data line region photoresist layer) in the data line region.
  • the thickness h2 of the data line region photoresist layer 456 is smaller than the thickness h1 of the switch region photoresist layer 452.
  • the thickness h1 of the switch region photoresist layer 452 is 2.2 ⁇ m
  • the thickness h2 of the data line region photoresist layer 456 may be 1.8 ⁇ m. Therefore, the photoresist thickness ratio h1:h2 of the switching area and the data line area is 11:9 instead of 1:1 as in the prior art.
  • the ratio of the photoresist thickness ratio h1:h2 of the switching region to the data line region is preferably 11:10 or more and 11:5 or less.
  • the second metal layer (ie, the source/drain metal layer) 440 is etched to form the second metal layer by using the patterned photoresist 450.
  • the portion 440 that is not covered by the photoresist 450 is removed to form a first portion 442 (ie, a source/drain portion) and a second portion 446 (ie, a data line).
  • a wet etching process is generally employed. As mentioned earlier, wet etching is an isotropic etching (Isotropic Etch), so the second metal layer 440 will produce an undercut, as shown in the figure.
  • the semiconductor layer 430 is etched in the switching region and the data line region.
  • dry etching is generally employed.
  • the photoresist 450 layer is etched in the switching region and the data line region in order to remove the photoresist layer 454 at the recess to open the source and drain conductive vias 455. Dry etching is usually employed here.
  • the switch region photoresist layer (452, 454) and the data line region photoresist layer 456 can be partially etched using oxygen or other suitable gas.
  • oxygen (O2) and fluorine gas are used as an etching gas, and the photoresist 450 and the semiconductor layer 430 are etched at the same time.
  • the fluorine gas is preferably, for example, sulfur hexafluoride (SF6) or tetrafluorocarbon. Carbon (CF4).
  • the area of the data line region semiconductor layer 436 is made small, so that the aperture ratio is improved.
  • the ratio of the ratio of oxygen to fluorine gas is preferably 4:3 or more and 4:1 or less, more preferably 2:1.
  • the second metal layer 442 and the portion of the semiconductor layer 432 at the recesses are further etched to form a drain source, and finally all of the switch regions are The photoresist layer 452 is stripped.
  • the photoresist layer 456 of the remaining data line region is a second metal layer 446 for protecting the underside thereof.
  • the portion divided by the broken line and partitioned by the shadow is the portion to be etched away.
  • the thickness h2 of the data line region photoresist layer 456 is only 1.8 ⁇ m
  • the photoresist thickness h3 which is etched away as in the prior art is 0.7 ⁇ m
  • the residual switch region photoresist layer 452 has a thickness h4. It is 1.5 ⁇ m, and the thickness h5 of the remaining data line region photoresist layer 456 will be only 1.1 ⁇ m.
  • the area of the data line region photoresist layer 456 is therefore smaller than that of the prior art, and the area of the semiconductor layer 436 is also small, so that the fluorine gas can contact the edge portion of the more semiconductor layer 436 and etch it away. .
  • the area of the data line region semiconductor layer 436 can be further reduced, and the aperture ratio can be further improved.

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Description

液晶显示器的像素阵列制造方法 技术领域
本发明是有关于一种液晶显示器制造技术，特别是有关于一种液晶显示器的像素阵列制造方法。
 背景技术
现今液晶显示器已成为显示技术的主流，广泛应用于各种电子产品，诸如移动电话、个人数字助理（PDA）、数码相机、计算机屏幕或笔记本计算机屏幕等等。其中薄膜晶体管液晶显示器（TFT LCD）使用薄膜晶体管（Thin film transistor；TFT）作为像素的开关，适用于需要高分辨率的应用，因此占有重要的地位。
在TFT LCD中，每个像素具有一个TFT作为开关。所述TFT的栅极（Gate）连接至扫描线（Scan line），源极（Source）连接至数据线（Data line），而漏极（Drain）连接至像素电极。当扫描线被驱动时，所述TFT被导通，对应的数据线送入视讯信号，将像素电极充电到适当的电压。然后所述TFT关断，直到下次写入信号。
TFT LCD的制造工艺流程一般包含三个阶段：阵列工艺（Array process）、液晶注入工艺（Cell process）以及组装工艺（Module process）。其中在Array工艺阶段中，是将TFT、储存电容以及线路等形成于玻璃基板上。
图1至图3显示习知技术之薄膜晶体管液晶显示器的像素阵列制造方法的步骤。图1至图3的各个图均包含两个部份（A）与（B），其中（A）部份显示形成TFT部份（亦可称为开关区）的截面，（B）部份显示形成数据线区的截面。
习知技术之薄膜晶体管液晶显示器的像素阵列制造方法主要采用四道光罩工艺。如图1所示，在习知技术之薄膜晶体管液晶显示器的像素阵列制造方法中，先在玻璃基板100上利用沈积工艺形成第一金属层，并一利用光罩进行显影制程。显影制程是在第一金属层上涂布光阻剂（未图示）后，依据具有特定图案的第一道光罩利用一曝光机对光阻剂进行曝光再用显影剂（developer）将已曝光的光阻剂洗除。之后对第一金属层进行蚀刻制程。在这个步骤中，一般是采用湿蚀刻工艺。蚀刻制程是将没有被光阻剂覆盖的第一金属层以强酸移除而加以蚀刻，形成如图中所示的栅极金属层110。接着，形成栅极绝缘层120，再于栅极绝缘层120上形成半导体层130。此半导体层130一般为非晶硅（Amorphous Si；a-Si）层。然后，在半导体层130上形成第二金属层140作为TFT的源极/漏极，因此这一层亦称为源漏极金属层。接着，在源漏极金属层140上涂布一层光阻剂150，利用一光罩，通过对光阻剂150进行曝光、显影等工艺使光阻剂150形成为所需的图案。如图1（A）所示，这层光阻剂150包含在开关区的一般厚度的光阻层152（其后称为开关区光阻层），其中在对应栅极金属层110上方的光阻层中形成一凹陷处，此处为预定形成源漏极导电沟道155的位置，也就是说，凹陷处底部的源漏极导电通道光阻层154具有较小的厚度。此外，如图1（B）所示，光阻剂在数据线区形成所需图案的光阻层156（其后称为数据线区光阻层）。
而后，如图2的（A）与（B）部份所示，利用图案化的光阻剂150，而对第二金属层（亦即源漏极金属层）140进行蚀刻以将未被图案化的光阻剂150覆盖的第二金属层140的部份移除，以形成第一部分142（亦即源/漏极）与第二部份146（亦即数据线）。在这个步骤中，一般是采用湿蚀刻工艺。由于湿蚀刻是一种等向性蚀刻（Isotropic etch），因此会产生底切现象（Undercut），也就是所欲保留的金属层部份，其周围多少仍会被蚀刻掉，因此留下的金属层部份会比覆盖的光阻层来得小，如图中所示。
接下来，如图3之（A）图与（B）图所示，在开关区与数据线区对半导体层130进行蚀刻。在此，一般采用干蚀刻。
然后，在开关区对光阻剂150这一层进行蚀刻，目的是去除光阻层154以开通源漏极导电通道155，并在数据线区对光阻剂150这一层进行蚀刻。在此通常采用干蚀刻，一般是利用氧气（O2）作为蚀刻气体。
在习知技术中，光阻剂150涂布的厚度在开关区与数据线区是一致的，例如开关区光阻层152的厚度h1与数据线区光阻层156的厚度h2为2.2μm，也就是说，在蚀刻光阻剂150之前，提供于开关区与数据线区的光阻厚度比例h1：h2为1：1。如果蚀刻去除的光阻剂厚度h3为0.7μm，则残留的开关区光阻层152的厚度h4以及数据线区光阻层156的厚度h5各还有1.5μm。
习知技术的方法所制造的TFT，如图3的（B）部份所示，数据线区最终留下的半导体层136具有较大的面积，使开口率（Aperture ratio）偏低。开口率是每个像素可透光的有效区域除以像素的总面积，开口率愈高，整体画面愈亮。因此，如果开口率低，则画面会显得较暗。
 技术问题
本发明的主要目的在于提供一种液晶显示器的像素阵列制造方法，其能提高开口率。
 技术解决方案
为达成本发明的前述目的，提供一种液晶显示器的像素阵列制造方法。所述液晶显示器的像素阵列制造方法包含：在玻璃基板上形成第一金属层并加以蚀刻，以形成所需图案的第一金属层；形成绝缘层以覆盖在所述第一金属层与玻璃基板；在所述绝缘层上形成半导体层；在所述半导体层上形成第二金属层；在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层；蚀刻所述第二金属层以移除未被所述开关区光阻层与数据线区光阻层覆盖的所述第二金属层的部份；蚀刻所述半导体层；蚀刻所述开关区光阻层与所述数据线区光阻层；利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份。
为达成本发明的前述目的，提供另一种液晶显示器的像素阵列制造方法。所述液晶显示器的像素阵列制造方法包含：在玻璃基板上形成第一金属层并加以蚀刻，以形成所需图案的第一金属层；形成绝缘层以覆盖所述第一金属层与玻璃基板；在所述绝缘层上形成半导体层；在所述半导体层上形成第二金属层；在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层；蚀刻所述第二金属层以移除未被所述开关区光阻层与数据线区光阻层覆盖的所述第二金属层的部份；蚀刻所述半导体层；蚀刻在所述开关区与所述数据线区的半导体层的边缘部份；蚀刻所述开关区光阻层与所述数据线区光阻层。
 有益效果
由于可以在蚀刻光阻层的同时或之后，利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份，进一步缩减的数据线区半导体层的面积，从而提高了开口率。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
图1至图3是显示习知技术之薄膜晶体管液晶显示器的像素阵列制造方法中的步骤的截面示意图，其中各图的（A）部份显示开关区，（B）部份显示数据线区。
图4至图6是显示根据本发明之薄膜晶体管液晶显示器的像素阵列制造方法各个步骤的截面示意图，其中各图的（A）部份显示开关区，（B）部份显示数据线区。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所显示与提及的长度、宽度、高度、厚度等尺寸仅为用以说明及理解本发明，而非用以限制本发明。
图4至图6是显示根据本发明之薄膜晶体管液晶显示器的像素阵列制造方法各个步骤的截面示意图，其中各图的（A）部份显示开关区，即连接源漏极的导电沟道处，（B）部份显示数据线区。
如图4所示，在根据本发明实施例之薄膜晶体管液晶显示器的像素阵列制造方法中，先在玻璃基板400上沈积第一金属层，并利用一光罩进行显影制程。显影制程是在第一金属层上涂布光阻剂（未图示）后，依据具有特定图案的第一道光罩利用一曝光机对光阻进行曝光再用显影剂（developer）将已曝光的光阻剂洗除。之后对第一金属层进行蚀刻制程。在这个步骤中，一般是采用湿蚀刻工艺。蚀刻制程是将没有被光阻剂覆盖的第一金属层以强酸移除加以蚀刻，以形成所需图案的第一金属层，亦即如图中所示的栅极金属层410。接着，利用沉积工艺形成绝缘层以覆盖栅极金属层410以及开关区与数据线区露出来的玻璃基板400，亦即形成图中所示的栅极绝缘层420，再于栅极绝缘层420上形成半导体层430。此半导体层430一般为非晶硅（Amorphous Si；a-Si）层。然后，在半导体层430上形成第二金属层440，由于这一层金属将作为TFT的源极/漏极，因此这一层亦称为源漏极金属层。接着，在源漏极金属层440上涂布一层光阻剂450，利用一光罩，通过对光阻剂450进行曝光、显影等工艺使光阻剂450形成为所需的图案。如图4（A）所示，这层光阻剂（亦可称光阻层）450包含在开关区的一般厚度的光阻层452（其后称为开关区光阻层），其中在对应栅极金属层410上方形成一凹陷处，此处为预定形成源漏极导电沟道455的位置，也就是说，凹陷处底部的源漏极导电通道光阻层454具有较小的厚度。此外，如图4（B）所示，光阻剂在数据线区形成所需图案的光阻层456（其后称为数据线区光阻层）。应注意的是，在本实施例中，数据线区光阻层456的厚度h2是小于开关区光阻层452的厚度h1。举例而言，开关区光阻层452的厚度h1为2.2μm，而数据线区光阻层456的厚度h2可为1.8μm。因此，开关区与数据线区的光阻厚度比例h1：h2为11：9，而非如先前技术中的1：1。一般而言，开关区与数据线区的光阻厚度比例h1：h2的范围优选为大于等于11：10且小于等于11：5。
而后，如图5的（A）与（B）部份所示，利用图案化的光阻剂450，对第二金属层（亦即源漏极金属层）440进行蚀刻以将第二金属层440未被光阻剂450覆盖的部份移除，以形成第一部分442（亦即源/漏极部份）与第二部份446（亦即数据线）。在这个步骤中，一般是采用湿蚀刻工艺。如前所述，由于湿蚀刻是一种等向性蚀刻（Isotropic etch），因此第二金属层440会产生底切现象（Undercut），如图中所示。
接下来，如图6之（A）图与（B）图所示，在开关区与数据线区对半导体层430进行蚀刻。在此，一般采用干蚀刻。
然后，在开关区与数据线区对光阻剂450这一层进行蚀刻，目的是去除凹陷处的光阻层454以开通源漏极导电通道455。在此通常采用干蚀刻。如前所述，可利用氧气或其它适当气体部份蚀刻所述开关区光阻层(452、454)与所述数据线区光阻层456。于本发明之实施例中，是利用氧气（O2）与氟素气体作为蚀刻气体，同时蚀刻光阻剂450以及半导体层430，氟素气体优选例如为六氟化硫（SF6）或是四氟化碳（CF4）。藉由利用氟素气体蚀刻数据线区半导体层436的边缘部份，使的数据线区半导体层436面积变小，使得开口率得以提高。氧气与氟素气体的比例范围优选为大于等于4：3且小于等于4：1，更优选为2：1。
在蚀刻了光阻层450和半导体层430的边缘部分之后，接下来还要再进一步蚀刻凹陷处的第二金属层442以及部分半导体层432，以形成漏源极，最后再将开关区的所有光阻层452剥除。所保留的数据线区的光阻层456是用于保护其下面的第二金属层446。
如图中所示，以虚线划分并以阴影区隔的部份为被蚀刻掉的部份。如图6所示，由于数据线区光阻层456的厚度h2只有1.8μm，当与先前技术同样被蚀刻掉的光阻剂厚度h3为0.7μm时，残留的开关区光阻层452厚度h4是1.5μm，而残留的数据线区光阻层456的厚度h5将只剩下1.1μm。数据线区光阻层456的面积因此会比先前技术中来得小，遮住半导体层436的面积亦较小，故氟素气体能接触到更多半导体层436的边缘部份而将之蚀刻掉。藉由如此，能进一步缩减的数据线区半导体层436的面积，使开口率更加提高。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (17)

  1. 一种液晶显示器的像素阵列制造方法，其特征在于：所述方法包含：
    在玻璃基板上形成第一金属层并加以蚀刻，以形成所需图案的第一金属层；
    形成绝缘层以覆盖所述第一金属层与玻璃基板；
    在所述绝缘层上形成半导体层；
    在所述半导体层上形成第二金属层；
    在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层，且所述数据线区光阻层的厚度小于所述开关区光阻层的厚度；
    蚀刻所述第二金属层；
    蚀刻所述半导体层；
    蚀刻所述开关区光阻层与所述数据线区光阻层；
    蚀刻在所述开关区与所述数据线区的半导体层的边缘部份。
  2. 根据权利要求1所述的方法，其特征在于，所述蚀刻开关区光阻层与所述数据线区光阻层包括：利用氧气蚀刻所述开关区光阻层与所述数据线区光阻层。
  3. 根据权利要求1所述的方法，其特征在于，所述蚀刻在所述开关区与所述数据线区的半导体层的边缘部份包括：利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份。
  4. 根据权利要求3所述的方法，其特征在于：所述氟素气体为SF6或CF4。
  5. 根据权利要求1所述的方法，其特征在于：所述蚀刻所述开关区光阻层与所述数据线区光阻层，以及所述蚀刻在所述开关区与所述数据线区的半导体层的边缘部份，包括：利用氧气蚀刻开关区光阻层与所述数据线区光阻层同时利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份。
  6. 根据权利要求5所述的方法，其特征在于：氧气与氟素气体的比例范围为大于等于4：3且小于等于4：1。
  7. 根据权利要求1所述的方法，其特征在于：所述开关区光阻层的厚度与数据线区光阻层的厚度的比例范围为大于等于11：10且小于等于11：5。
  8. 一种液晶显示器的像素阵列制造方法，其特征在于：所述方法包含：
    在玻璃基板上形成第一金属层并加以蚀刻，以形成所需图案的第一金属层；
    形成绝缘层以覆盖所述第一金属层与玻璃基板；
    在所述绝缘层上形成半导体层；
    在所述半导体层上形成第二金属层；
    在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层；
    蚀刻所述第二金属层以移除未被所述开关区光阻层与数据线区光阻层覆盖的所述第二金属层的部份；
    蚀刻所述半导体层；
    蚀刻所述开关区光阻层与所述数据线区光阻层；
    利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份。
  9. 根据权利要求8所述的方法，其特征在于，所述蚀刻开关区光阻层与所述数据线区光阻层包括：利用氧气蚀刻所述开关区光阻层与所述数据线区光阻层。
  10. 根据权利要求9所述的方法，其特征在于：所述利用氧气蚀刻开关区光阻层与所述数据线区光阻层，与所述利用氟素气体蚀刻在所述开关区与所述数据线区的半导体层的边缘部份同时进行。
  11. 根据权利要求10所述的方法，其特征在于：氧气与氟素气体的比例范围为大于等于4：3且小于等于4：1。
  12. 根据权利要求8所述的方法，其特征在于：所述氟素气体为SF6或CF4。
  13. 根据权利要求8所述的方法，其特征在于：所述在第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层，包括：
    在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层，且所述数据线区光阻层的厚度小于所述开关区光阻层的厚度。
  14. 根据权利要求13所述的方法，其特征在于：所述开关区光阻层的厚度与数据线区光阻层的厚度的比例范围为大于等于11：10且小于等于11：5。
  15. 一种液晶显示器的像素阵列制造方法，其特征在于：所述方法包含：
    在玻璃基板上形成第一金属层并加以蚀刻，以形成所需图案的第一金属层；
    形成绝缘层以覆盖所述第一金属层与玻璃基板；
    在所述绝缘层上形成半导体层；
    在所述半导体层上形成第二金属层；
    在所述第二金属层上形成预定图案的光阻层，所述光阻层包含开关区光阻层与数据线区光阻层；
    蚀刻所述第二金属层以移除未被所述开关区光阻层与数据线区光阻层覆盖的所述第二金属层的部份；
    蚀刻所述半导体层；
    蚀刻在所述开关区与所述数据线区的半导体层的边缘部份；
    蚀刻所述开关区光阻层与所述数据线区光阻层。
  16. 根据权利要求15所述的方法，其特征在于：所述开关区光阻层的厚度与数据线区光阻层的厚度的比例范围为大于等于11：10且小于等于11：5。
  17. 根据权利要求15所述的方法，其特征在于：所述蚀刻在所述开关区与所述数据线区的半导体层的边缘部份，以及蚀刻开关区光阻层与所述数据线区光阻层，包括：
    利用氧气与氟素气体同时对所述开关区光阻层与所述数据线区光阻层以及在所述开关区与所述数据线区的所述半导体层的边缘部份进行蚀刻。
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