WO2012068752A1 - 保护层及薄膜晶体管矩阵基板的制造方法 - Google Patents

保护层及薄膜晶体管矩阵基板的制造方法 Download PDF

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WO2012068752A1
WO2012068752A1 PCT/CN2010/079684 CN2010079684W WO2012068752A1 WO 2012068752 A1 WO2012068752 A1 WO 2012068752A1 CN 2010079684 W CN2010079684 W CN 2010079684W WO 2012068752 A1 WO2012068752 A1 WO 2012068752A1
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substrate
reaction chamber
vacuum reaction
protective layer
manufacturing
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French (fr)
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贺成明
刘凤举
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a protective layer and a method of manufacturing a thin film transistor matrix substrate.
  • Liquid crystal display (Liquid Crystal Display, LCD) has been widely used in a variety of electronic products, most of the liquid crystal display is a backlight type liquid crystal display, which is composed of a liquid crystal display panel and a backlight module (backlight Module).
  • a general liquid crystal display panel includes a color filter (CF) substrate and a thin film transistor (TFT). Matrix substrate. A plurality of color filters and a common electrode are disposed on the CF substrate.
  • the TFT matrix substrate is provided with a plurality of parallel scan lines, a plurality of parallel data lines, a plurality of thin film transistors and pixel electrodes, wherein the scan lines are perpendicular to the data lines, and two adjacent scan lines and two adjacent data
  • a pixel (Pixel) region can be defined between the lines.
  • a protective layer is required (passivation) Layer) on the TFT.
  • this protective layer is plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor) Deposition, PECVD) for deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • the TFT matrix substrate is transferred into a vacuum chamber of the PECVD apparatus to deposit the protective layer.
  • the temperature in the vacuum chamber is rapidly lowered due to the rapid drop in the air pressure, so that the water vapor easily condenses on the TFT matrix substrate. Therefore, after the protective layer is formed, moisture or water droplets easily remain between the protective layer and the substrate, which seriously affects the performance of the TFT.
  • a main object of the present invention is to provide a method for manufacturing a protective layer, a method for fabricating a thin film transistor matrix substrate, and a method for manufacturing a thin film transistor matrix substrate.
  • the main object of the present invention is to provide a method for manufacturing a protective layer, the method comprising the steps of: placing a substrate in a vacuum reaction chamber; supplying ammonia and nitrogen into the vacuum reaction chamber; applying a voltage to the vacuum Between the two electrodes in the reaction chamber to form a plasma and evaporate water vapor; and to form the protective layer on the substrate.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor matrix substrate, the manufacturing method comprising the steps of: forming a gate on a transparent substrate; forming a source electrode and a drain electrode on the gate, wherein the trench a channel formed between the source electrode and the drain electrode; placing the transparent substrate in a vacuum reaction chamber; supplying ammonia gas and nitrogen gas into the vacuum reaction chamber; applying a voltage to the vacuum reaction chamber Between the two electrodes to form a plasma and evaporate water vapor; forming a protective layer on the channel, the source electrode and the drain electrode; and forming a pixel electrode layer on the protective layer and electrically connecting On the drain electrode.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor matrix substrate, the manufacturing method comprising the steps of: forming a gate on a transparent substrate; forming a source electrode and a drain electrode on the gate, wherein the trench a channel formed between the source electrode and the drain electrode; placing the transparent substrate in a vacuum reaction chamber; supplying ammonia gas and nitrogen gas into the vacuum reaction chamber; applying a voltage to the vacuum reaction chamber Between the two electrodes to form a plasma and evaporate water vapor, and use the hydrogen ions dissociated by the ammonia gas to fill the dangling bonds of the amorphous silicon of the channel; forming a protective layer on the channel, On the source electrode and the drain electrode; and forming a pixel electrode layer on the protective layer and electrically connected to the drain electrode.
  • the substrate within the vacuum chamber is heated prior to providing the ammonia gas and the nitrogen gas.
  • the voltage is a radio frequency signal.
  • hydrogen gas is supplied to the vacuum reaction chamber and the voltage is applied between the electrodes to form a plasma before the ammonia gas and the nitrogen gas are supplied.
  • a reactive gas is supplied into the vacuum reaction chamber, and the voltage is applied between the electrodes to form a plasma.
  • hydrogen gas is simultaneously supplied into the vacuum reaction chamber.
  • the protective layer and the method for manufacturing the thin film transistor matrix substrate of the present invention can completely eliminate water vapor on the substrate to ensure the performance of the transistor and reduce the scrapping of the product. Furthermore, the NH3 plasma treatment of the present invention can be combined with or substituted for H2 plasma treatment to reduce process time and increase process throughput.
  • the protective layer and the method for manufacturing the thin film transistor matrix substrate of the present invention can completely eliminate water vapor on the substrate to ensure the performance of the transistor and reduce the scrapping of the product. Furthermore, the NH3 plasma treatment of the present invention can be combined with or substituted for H2 plasma treatment to reduce process time and increase process throughput.
  • FIG. 1 is a cross-sectional view showing a display panel and a backlight module in accordance with an embodiment of the present invention
  • FIG. 2 to FIG. 7 are schematic cross-sectional views showing a process of a thin film transistor matrix substrate of a display panel according to an embodiment of the present invention
  • FIG. 8 shows a method flow diagram of a method of fabricating a protective layer in accordance with an embodiment of the present invention
  • Figure 9 shows a schematic diagram of a PECVD apparatus in accordance with an embodiment of the present invention.
  • FIG. 1 shows a cross-sectional view of a display panel and a backlight module according to an embodiment of the invention.
  • the manufacturing method of the protective layer of the present embodiment can be applied to the manufacturing process of the liquid crystal display panel 100 to manufacture a protective layer of a transistor.
  • the display panel 100 can be disposed on the backlight module 200, thereby forming a liquid crystal display device.
  • the liquid crystal display panel 100 can include a first substrate 110, a second substrate 120, a liquid crystal layer 130, a first polarizer 140, and a second polarizer 150.
  • the substrate material of the first substrate 110 and the second substrate 120 may be a glass substrate or a flexible plastic substrate.
  • the first substrate 110 may be, for example, a thin film transistor (Thin Film Transistor (TFT) matrix substrate
  • the second substrate 120 may be, for example, a color filter (Color) Filter, CF) substrate.
  • TFT Thin Film Transistor
  • CF color filter
  • the color filter and the TFT matrix may also be disposed on the same substrate.
  • the liquid crystal layer 130 is formed between the first substrate 110 and the second substrate 120 .
  • the first polarizer 140 is a side on which the first substrate 110 is disposed, and is opposite to the liquid crystal layer 130 (ie, the light incident side of the first substrate 110), and the second polarizer 150 is a side on which the second substrate 120 is disposed, and is opposite.
  • the liquid crystal layer 130 ie, the light exiting side of the second substrate 120).
  • FIG. 2 to FIG. 7 are schematic cross-sectional views showing a process of a thin film transistor matrix of a display panel according to an embodiment of the invention.
  • the TFT matrix substrate such as the first substrate 110
  • a transparent substrate 111 such as a quartz or a glass substrate is provided.
  • the electrode layer 112, the gate insulating layer 113, the semiconductor layer 114, and the ohmic contact layer 115 are sequentially formed on the transparent substrate 111.
  • the material of the electrode layer 112 is, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, metal nitride or an alloy of any combination thereof, or a multilayer structure having a heat resistant metal film and a low resistivity film. For example, a two-layer structure of a molybdenum nitride film and an aluminum film.
  • the material of the gate insulating layer 113 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx), which is, for example, plasma enhanced chemical vapor deposition (Plasma) Enhanced Chemical Vapor Deposition, PECVD) way to deposit formation.
  • the material of the semiconductor layer 114 of the present embodiment is preferably polysilicon (Poly-Silicon).
  • the semiconductor layer 114 may be first deposited with an amorphous silicon (a-Si) layer, and then the amorphous silicon layer is rapidly thermally annealed (Rapid). Thermal annealing, The RTA) step is such that the amorphous silicon layer is recrystallized into a polysilicon layer.
  • the material of the ohmic contact layer 115 is, for example, formed of N+ amorphous silicon (a-Si) heavily doped with an N-type impurity (for example, phosphorus) or a silicide thereof, or for example, by chemical vapor deposition (In-situ) ) deposition formation.
  • a-Si N+ amorphous silicon
  • an N-type impurity for example, phosphorus
  • silicide for example, by chemical vapor deposition (In-situ) ) deposition formation.
  • the electrode layer 112, the gate insulating layer 113, the semiconductor layer 114, and the ohmic contact layer 115 are patterned to form a patterned electrode layer 112a, a patterned gate insulating layer 113a, and a patterned semiconductor layer 114a. And patterning the ohmic contact layer 115a, and exposing the partially patterned electrode layer 112a to form a gate of the thin film transistor on the transparent substrate 111, wherein the patterned semiconductor layer 114a can serve as a semiconductor island structure of the thin film transistor.
  • an insulating layer 116 is formed on the gate (patterned electrode layer 112a) and the partially patterned ohmic contact layer 115a, respectively, wherein the insulating layer 116 is formed on the opposite sides of the patterned ohmic contact layer 115a. The other side exposes another portion of the patterned ohmic contact layer 115a.
  • the source electrode 117a and the drain electrode 117b are formed on the gate by a photolithography process, and the partially patterned semiconductor layer 114a is exposed. (Semiconductor island) to form a channel C in which a channel C is formed between the source electrode 117a and the drain electrode 117b.
  • a protective layer 118 is formed on the channel C, the source electrode 117a, and the drain electrode 117b, wherein the protective layer 118 has at least one via hole 118a to expose a portion of the drain electrode 117b.
  • FIG. 8 is a flow chart showing a method of manufacturing a protective layer according to an embodiment of the present invention
  • FIG. 9 is a schematic view showing a PECVD apparatus according to an embodiment of the present invention.
  • the protective layer 118 may be formed by a plasma enhanced chemical vapor deposition (PECVD) apparatus 101.
  • PECVD plasma enhanced chemical vapor deposition
  • the substrate 110 i.e., the transparent substrate 111 to be formed with the protective layer 118 is placed in the vacuum reaction chamber 102 of the PECVD apparatus 101 (step 301), wherein the substrate 110 is Located between the two electrodes 103 in the vacuum reaction chamber 102. Vacuuming may then be performed within the vacuum chamber 102 to create a vacuum environment within the vacuum chamber 102.
  • the substrate 110 in the vacuum chamber 102 can be heated to eliminate moisture on the surface of the substrate 110.
  • ammonia gas (NH3) and nitrogen gas (N2) are supplied into the vacuum reaction chamber 102 (step 302), and voltage is applied to the two electrodes in the vacuum reaction chamber 102.
  • the water vapor on the substrate 110 is evaporated by the high temperature generated during the reaction (step 303), such as a radio frequency signal (RF) Signal).
  • RF radio frequency signal
  • ammonia gas and nitrogen gas can be introduced into the vacuum reaction chamber 102 to form a plasma to generate a high temperature, thereby evaporating water vapor on the substrate 110.
  • hydrogen (H2) may be supplied into the vacuum reaction chamber 102, and a voltage is applied to the two electrodes 103 in the vacuum reaction chamber 102. Between to form a plasma. At this time, hydrogen ions (H+) can be formed by plasma, which can fill the a-Si dangling bond of the channel C (dangling) Bond) to improve channel defects and reduce leakage current.
  • a reaction gas such as SiH4
  • a voltage is applied to the vacuum reaction chamber 102.
  • a plasma is formed between the electrodes 103 to generate a chemical reaction for deposition, and a protective layer 118 may be formed on the substrate 110 (step 304).
  • the water vapor on the substrate 110 can be completely evaporated by the high temperature generated by the plasma to prevent the water vapor from being covered by the protective layer 118, thereby ensuring the TFT assembly of the substrate 110.
  • a light-transmissive conductive layer (for example, ITO, IZO, AZO, GZO, TCO, or ZnO) may be formed on the protective layer 118, and then the light-transmitting conductive layer is patterned by a photolithography process.
  • the pixel electrode layer 119 Since the pixel electrode layer 119 covers the connection hole 118a, the connection hole 118a of the protective layer 118 can be electrically connected to the drain electrode 117b, so that the thin film transistor matrix substrate 110 of the present embodiment is formed.
  • H2 when NH3 and N2 are supplied into the vacuum reaction chamber 102, H2 may be simultaneously supplied into the vacuum reaction chamber 102, and a voltage is applied to the vacuum reaction chamber 102. Between the two electrodes 103 to form a plasma. At this time, the plasma formed by NH3 and H2 can completely eliminate the water vapor on the substrate 110, and the H+ dissociated by NH3 and H2 can fill the a-Si dangling bond of the channel to reduce the leakage current. Therefore, NH3 plasma treatment and H2 plasma treatment can be performed simultaneously to reduce the processing time of the protective layer 118 and increase the throughput (production) Capacity).
  • H2 may not need to be provided into the vacuum reaction chamber 102.
  • the a+Si dangling bond of the channel can be filled with H+ dissociated by NH3 to reduce leakage current. Therefore, in the present embodiment, the NH3 plasma treatment can simultaneously remove water vapor on the substrate 110 and fill the a-Si dangling bonds of the channel to reduce leakage current.
  • the protective layer of the present invention and the method of manufacturing the thin film transistor matrix substrate can completely eliminate the water vapor on the substrate to ensure the performance of the transistor and reduce the scrapping of the product.
  • the NH3 plasma treatment of the present invention can be combined with or substituted for H2 plasma treatment to reduce process time and increase process throughput.

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  • Liquid Crystal (AREA)

Description

保护层及薄膜晶体管矩阵基板的制造方法 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种保护层及薄膜晶体管矩阵基板的制造方法。
 背景技术
液晶显示器(Liquid Crystal Display，LCD)已被广泛应用于各种电子产品中，液晶显示器大部分为背光型液晶显示器，其是由液晶显示面板及背光模块(backlight module)所组成。一般的液晶显示面板包含彩色滤光片(Color Filter，CF)基板及薄膜晶体管(Thin Film Transistor，TFT) 矩阵基板。CF基板上设有多个彩色滤光片和共同电极。TFT矩阵基板上设有多条彼此平行的扫描线、多条彼此平行的数据线、多个薄膜晶体管及像素电极，其中扫描线是垂直于数据线，且两相邻扫描线和两相邻数据线之间可界定像素(Pixel)区域。
在TFT矩阵基板的制程中，需制造保护层(passivation layer)于TFT上。通常，此保护层是通过等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)来进行沉积。此时， TFT矩阵基板是被传送入PECVD设备的真空腔室来沉积此保护层。
然而，当PECVD设备的真空腔室内进行抽真空时，由于气压急速下降，因而真空腔室内的温度亦急速下降，使得水汽容易凝结于TFT矩阵基板上。因此，在形成保护层后，水汽或水滴容易残留于保护层与基板之间，而严重地影响TFT的性能。
故，有必要提供一种保护层及薄膜晶体管矩阵基板的制造方法，以解决现有技术所存在的问题。
 技术问题
本发明的主要目的在于提供一种保护层的制造方法,提供一种薄膜晶体管矩阵基板的制造方法以及提供一种薄膜晶体管矩阵基板的制造方法。
 技术解决方案
本发明的主要目的在于提供一种保护层的制造方法，所述制造方法包括如下步骤：放置基板于真空反应腔室内；提供氨气与氮气至所述真空反应腔室内；施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽；以及形成所述保护层于所述基板上。
本发明的另一目的在于提供一种薄膜晶体管矩阵基板的制造方法，所述制造方法包括如下步骤：形成栅极于透明基材上；形成源电极及漏电极于所述栅极上，其中沟道是形成于所述源电极和所述漏电极之间；放置所述透明基材于真空反应腔室内；提供氨气与氮气至所述真空反应腔室内；施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽；形成保护层于所述沟道、所述源电极及所述漏电极上；以及形成像素电极层于所述保护层上，并电性连接于所述漏电极。
本发明的又一目的在于提供一种薄膜晶体管矩阵基板的制造方法，所述制造方法包括如下步骤：形成栅极于透明基材上；形成源电极及漏电极于所述栅极上，其中沟道是形成于所述源电极和所述漏电极之间；放置所述透明基材于真空反应腔室内；提供氨气与氮气至所述真空反应腔室内；施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽，且利用所述氨气所解离的氢离子来填补所述沟道的非晶硅的悬空键；形成保护层于所述沟道、所述源电极及所述漏电极上；以及形成像素电极层于所述保护层上，并电性连接于所述漏电极。
在本发明的一实施例中，在提供所述氨气与所述氮气之前，加热所述真空腔室内的所述基板。
在本发明的一实施例中，所述电压为射频信号。
在本发明的一实施例中，在提供所述氨气与所述氮气之前，提供氢气至所述真空反应腔室内，并施加所述电压于所述电极之间，以形成等离子。
在本发明的一实施例中，当形成所述保护层于所述基板上时，提供反应气体至所述真空反应腔室内，并施加所述电压于所述电极之间来形成等离子。
在本发明的一实施例中，当提供所述氨气与所述氮气时，同时提供氢气至所述真空反应腔室内。
本发明的保护层及薄膜晶体管矩阵基板的制造方法可完全地消除基板上的水汽，以确保晶体管的性能，减少产品的报废。再者，本发明的NH3等离子处理可结合或取代H2等离子处理，以减少制程时间，并可增加制程产能。
 有益效果
本发明的保护层及薄膜晶体管矩阵基板的制造方法可完全地消除基板上的水汽，以确保晶体管的性能，减少产品的报废。再者，本发明的NH3等离子处理可结合或取代H2等离子处理，以减少制程时间，并可增加制程产能。
 附图说明
图1显示依照本发明的一实施例的显示面板与背光模块的剖面示意图；
图2至图7，其显示依照本发明的实施例的显示面板的薄膜晶体管矩阵基板的制程剖面示意图；
图8显示依照本发明的实施例的保护层的制造方法的方法流程图；以及
图9显示依照本发明的实施例的PECVD设备的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，其显示依照本发明的一实施例的显示面板与背光模块的剖面示意图。本实施例的保护层的制造方法可应用于液晶显示面板100的制造过程中，以制造晶体管的保护层。当应用本实施例的液晶显示面板100来制造显示装置时，可设置显示面板100于背光模块200上，因而形成液晶显示装置。此液晶显示面板100可包括第一基板110、第二基板120、液晶层130、第一偏光片140及第二偏光片150。第一基板110和第二基板120的基板材料可为玻璃基板或可挠性塑料基板，在本实施例中，第一基板110可例如为薄膜晶体管(Thin Film Transistor，TFT)矩阵基板，而第二基板120可例如为彩色滤光片(Color Filter，CF)基板。值得注意的是，在一些实施例中，彩色滤光片和TFT矩阵亦可配置在同一基板上。
如图1所示，液晶层130是形成于第一基板110与第二基板120之间。第一偏光片140是设置第一基板110的一侧，并相对于液晶层130(即第一基板110的入光侧)，第二偏光片150是设置第二基板120的一侧，并相对于液晶层130(即第二基板120的出光侧)。
请参照图2至图7，其显示依照本发明的实施例的显示面板的薄膜晶体管矩阵的制程剖面示意图。当制造本实施例之TFT矩阵基板(如第一基板110)时，首先，如图2所示，提供透明基材111，此透明基材111例如为石英或玻璃基材。接着，依序形成电极层112、栅极绝缘层113、半导体层114及欧姆接触层115于透明基材111上。电极层112的材料例如为Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构，例如氮化钼薄膜和铝薄膜的双层结构。栅极绝缘层113的材料例如为氮化硅(SiNx)或氧化硅(SiOx)，其例如是以等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition, PECVD)方式来沉积形成。本实施例的半导体层114的材料优选为多晶硅(Poly-Silicon)。在本实施例中，半导体层114可先沉积一非晶硅(a-Si)层，接着，对此非晶硅层进行快速热退火(Rapid thermal annealing, RTA)步骤，藉以使此非晶硅层再结晶成一多晶硅层。欧姆接触层115的材料例如是由重掺杂有N型杂质(例如磷)的N+非晶硅(a-Si)或其硅化物所形成，或者例如是以化学气相沉积方式临场(In-situ)沉积形成。
接着，如图3所示，图案化电极层112、栅极绝缘层113、半导体层114及欧姆接触层115，以形成图案化电极层112a、图案化栅极绝缘层113a、图案化半导体层114a及图案化欧姆接触层115a，且暴露出部分图案化电极层112a，以形成薄膜晶体管的栅极于透明基材111上，其中图案化半导体层114a可作为薄膜晶体管的半导体岛结构。
接着，如图4所示，分别形成绝缘层116于栅极(图案化电极层112a)及部分图案化欧姆接触层115a上，其中，绝缘层116是形成于图案化欧姆接触层115a的相对两侧，而暴露出另一部分的图案化欧姆接触层115a。接着，如图5所示，通过光刻工艺来形成源电极117a及漏电极117b于栅极上，并暴露部分图案化半导体层114a (半导体岛)来形成一沟道C，其中沟道C是形成于源电极117a和漏电极117b之间。
接着，如图6所示，形成保护层118于沟道C、源电极117a及漏电极117b上，其中保护层118具有至少一接孔118a，以暴露出部分漏电极117b。
请参照图8及图9，图8显示依照本发明的实施例的保护层的制造方法的方法流程图，图9显示依照本发明的实施例的PECVD设备的示意图。当形成保护层118时，例如，保护层118可通过等离子体增强化学气相沉积(PECVD)设备101来形成。在形成源电极117a及漏电极117b后，需形成保护层118的基板110(亦即透明基材111)是被放置于PECVD设备101的真空反应腔室102内(步骤301)，其中基板110是位于真空反应腔室102内的二个电极103之间。接着，可在真空腔室102内进行抽真空，以形成真空环境于真空腔室102内。且可加热真空腔室102内的基板110，以消除基板110表面的水汽。
接着，如图8及图9所示，氨气(NH3)与氮气(N2)是被提供至真空反应腔室102内(步骤302)，并施加电压于真空反应腔室102内的二个电极103之间，以形成等离子，用反应过程中产生的高温来蒸发基板110上的水汽(步骤303)，此电压例如为射频信号(RF signal)。此时，氨气与氮气可通入真空反应腔室102内，以形成等离子并来产生高温，进而可蒸发基板110上的水汽。再者，此时，由于未在基板110表面上形成固体物质，因而基板110上的水汽可完全地被消除，避免水汽被薄膜覆盖住。被蒸发的水汽(H2O)和氨气(NH3)可反应成NH3•H2O，另外有部分被电离，生成NH4+，这些NH3•H2O、NH4+可被抽出真空反应腔室102的外部。
如图8及图9所示，在通入氨气与氮气来形成等离子之前，可提供氢气(H2)至真空反应腔室102内，并施加电压于真空反应腔室102内的二个电极103之间，以形成等离子。此时，通过等离子，可形成氢离子(H+)，其可填补沟道C的a-Si悬空键(dangling bond)，以改善沟道缺陷，并可降低漏电流(leakage current)。
如图8及图9所示，接着，在通入氨气与氮气来形成等离子之后，提供反应气体(如SiH4)至真空反应腔室102内，并施加电压于真空反应腔室102内的二个电极103之间来形成等离子，以产生化学反应来进行沉积，而可形成保护层118于基板110上(步骤304)。
因此，在沉积保护层118于基板110上之前，基板110上的水汽可通过等离子所产生的高温来完全地被蒸发消除，以避免水汽被保护层118覆盖住，因而可确保基板110的TFT组件的效能，减少产品的报废。
接着，如图7所示，可先形成一透光导电层(例如ITO、IZO、AZO、GZO、TCO或ZnO)于保护层118上，接着通过光刻工艺来图案化此透光导电层，以形成像素电极层119。由于像素电极层119是覆盖于接孔118a上，因而可利用保护层118的接孔118a来电性连接于漏电极117b，故形成本实施例的薄膜晶体管矩阵基板110。
如图9所示，在一实施例中，当提供NH3与N2至真空反应腔室102内时，亦可同时提供H2至真空反应腔室102内，并施加电压于真空反应腔室102内的二个电极103之间，以形成等离子。此时，NH3与H2所形成的等离子可完全地消除基板110上的水汽，且NH3与H2所解离的H+可填补沟道的a-Si悬空键，以降低漏电流。因此，NH3等离子处理与H2等离子处理可同时进行，以减少保护层118的制程时间，并可增加产能(production capacity)。
如图7所示，在又一实施例中，H2亦可不需被提供至真空反应腔室102内。此时，可利用NH3所解离的H+来填补沟道的a-Si悬空键，以降低漏电流。因此，在本实施例中，NH3等离子处理可同时消除基板110上的水汽，并可填补沟道的a-Si悬空键，以降低漏电流。
由上述可知，本发明的保护层及薄膜晶体管矩阵基板的制造方法可完全地消除基板上的水汽，以确保晶体管的性能，减少产品的报废。再者，本发明的NH3等离子处理可结合或取代H2等离子处理，以减少制程时间，并可增加制程产能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (13)

  1. 一种薄膜晶体管矩阵基板的制造方法，其特征在于：所述制造方法包括如下步骤：
    形成栅极于透明基材上；
    形成源电极及漏电极于所述栅极上，其中沟道是形成于所述源电极和所述漏电极之间；
    放置所述透明基材于真空反应腔室内；
    提供氨气与氮气至所述真空反应腔室内；
    施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽，且利用所述氨气所解离的氢离子来填补所述沟道的非晶硅的悬空键；
    形成保护层于所述沟道、所述源电极及所述漏电极上；以及
    形成像素电极层于所述保护层上，并电性连接于所述漏电极。
  2. 一种保护层的制造方法，其特征在于：所述制造方法包括如下步骤：
    放置基板于真空反应腔室内；
    提供氨气与氮气至所述真空反应腔室内；
    施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽；以及
    形成所述保护层于所述基板上。
  3. 根据权利要求2所述的方法，其特征在于：在提供所述氨气与所述氮气之前，加热所述真空腔室内的所述基板。
  4. 根据权利要求2所述的方法，其特征在于：所述电压为射频信号。
  5. 根据权利要求2所述的方法，其特征在于：在提供所述氨气与所述氮气之前，提供氢气至所述真空反应腔室内，并施加所述电压于所述电极之间，以形成等离子。
  6. 根据权利要求2所述的方法，其特征在于：当形成所述保护层于所述基板上时，提供反应气体至所述真空反应腔室内，并施加所述电压于所述电极之间来形成等离子。
  7. 根据权利要求2所述的方法，其特征在于：当提供所述氨气与所述氮气时，同时提供氢气至所述真空反应腔室内。
  8. 一种薄膜晶体管矩阵基板的制造方法，其特征在于：所述制造方法包括如下步骤：
    形成栅极于透明基材上；
    形成源电极及漏电极于所述栅极上，其中沟道是形成于所述源电极和所述漏电极之间；
    放置所述透明基材于真空反应腔室内；
    提供氨气与氮气至所述真空反应腔室内；
    施加电压于所述真空反应腔室内的二个电极之间，以形成等离子并蒸发水汽；
    形成保护层于所述沟道、所述源电极及所述漏电极上；以及
    形成像素电极层于所述保护层上，并电性连接于所述漏电极。
  9. 根据权利要求8所述的方法，其特征在于：在提供所述氨气与所述氮气之前，加热所述真空腔室内的所述基板。
  10. 根据权利要求8所述的方法，其特征在于：所述电压为射频信号。
  11. 根据权利要求8所述的方法，其特征在于：在提供所述氨气与所述氮气之前，提供氢气至所述真空反应腔室内，并施加所述电压于所述电极之间，以形成等离子。
  12. 根据权利要求8所述的方法，其特征在于：当形成所述保护层于所述基板上时，提供反应气体至所述真空反应腔室内，并施加所述电压于所述电极之间来形成等离子。
  13. 根据权利要求8所述的方法，其特征在于：当提供所述氨气与所述氮气时，同时提供氢气至所述真空反应腔室内。
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