WO2012063347A1 - Dispositif commutateur et procédé pour tester le dispositif commutateur - Google Patents

Dispositif commutateur et procédé pour tester le dispositif commutateur Download PDF

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Publication number
WO2012063347A1
WO2012063347A1 PCT/JP2010/070128 JP2010070128W WO2012063347A1 WO 2012063347 A1 WO2012063347 A1 WO 2012063347A1 JP 2010070128 W JP2010070128 W JP 2010070128W WO 2012063347 A1 WO2012063347 A1 WO 2012063347A1
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WIPO (PCT)
Prior art keywords
frame
address
switch device
port
processor
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PCT/JP2010/070128
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English (en)
Japanese (ja)
Inventor
裕哉 河▲崎▼
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富士通株式会社
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Priority to PCT/JP2010/070128 priority Critical patent/WO2012063347A1/fr
Publication of WO2012063347A1 publication Critical patent/WO2012063347A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/555—Error detection

Definitions

  • the present invention relates to a switch device and a test method for the switch device.
  • Boundary scan tests based on JTAG IEEE Standard 1149.1
  • tests performed by connecting a counter test machine to a port are known as test methods for switch devices.
  • the boundary scan test by JTAG can perform an electrical connection test between boundary scan devices using a standard interface, but has a disadvantage that an internal test of the boundary scan device cannot be performed.
  • the test using the counter test machine can compensate for the disadvantages of the boundary scan test, but it requires multiple counter test machines with interfaces according to the communication speed and transmission medium, and the cost required for testing the switching device. Has the disadvantage of being expensive. Therefore, by connecting the port that outputs the test signal and the port that inputs the test signal, and comparing the output signal and the input signal, it is possible to connect the boundary scan devices without using the opposing test machine. Test methods have been proposed for performing tests and internal testing of boundary scan devices.
  • an object of the present invention is to provide a technique capable of performing an electrical connection test between boundary scan devices and an internal test of the boundary scan device with a single switch device. To do.
  • the switch device has an address conversion unit and a switching unit.
  • the address conversion unit converts at least the destination address of the frame into the predetermined address.
  • the switching unit refers to a table storing a record in which the destination address and the output port are associated with each other at least for the frame in which the destination address is converted, and outputs the frame from the output port associated with the frame destination address.
  • the switch device sets the address conversion unit and the table so that the test path that returns to the processor through all the ports is defined in response to an instruction from the outside, and sets the base point of the test path.
  • a frame with the destination port as the destination address is output to the switching unit.
  • the switch device analyzes the frame returned to the processor to determine whether there is a problem in the connection between the boundary scan devices or in the boundary scan device.
  • FIG. 1 shows an example of a switch device according to the present embodiment.
  • the switch device 100 is, for example, a network device operating in the data link layer, specifically, a layer 2 switch device having 16 ports (ports 00h to 0Fh).
  • the switch device 100 stores a MAC (Media Access Control) table 110 in a RAM (Random Access Memory) or the like.
  • the MAC table 110 is a table for managing network devices connected to each port, and holds a record in which a destination address, an output port, a type, and a valid flag are associated as shown in FIG.
  • the destination address stores a MAC address that identifies the network device that is the transmission destination of the frame.
  • the output port stores the identifier of the port to which the network device specified by the destination address is connected.
  • the type can be static with the destination address and output port set whether or not they exist, or it can be dynamic only while it is recognized that the destination address and output port exist. Stores if there is any.
  • the valid flag stores information for distinguishing whether the destination address and the output port are valid, for example, “1” if valid and “0” if invalid.
  • the frame includes a preamble (including SFD [Start [Frame Delimiter] in the case of IEEE802.3), destination address, source address, type, user data, and FCS (Frame Check Sequence). including.
  • a preamble including SFD [Start [Frame Delimiter] in the case of IEEE802.3), destination address, source address, type, user data, and FCS (Frame Check Sequence).
  • the preamble an 8-byte value in which “1” and “0” for announcing the start of a frame are alternately arranged is stored.
  • the destination address stores a 6-byte MAC address that identifies the network device that is the transmission destination of the frame.
  • the transmission source address stores a 6-byte MAC address that identifies the network device that is the transmission source of the frame.
  • 2-byte information for identifying a protocol located in an upper layer of a network access layer such as IP (Internet Protocol) is stored.
  • the user data stores a data body of 46 to 1500 bytes (or more
  • the switch device 100 has a connector 120 for connecting the network cable 200 and a PHY (Physical Layer) function 130 for each port.
  • the PHY function 130 converts an internal electrical signal into a signal corresponding to a transmission path and converts it in the opposite direction in an interface such as Ethernet (registered trademark).
  • the network cable 200 when testing the switch device 100, has, for example, a folded path that connects the output port and the input port of each connector 120 to each other, or a path that connects each connector 120 to each other. It only has to be.
  • the network cable 200 may be a cable connected to a network such as a LAN (Local Area Network).
  • the switch device 100 further includes a switching unit 140, an address conversion unit 150, and a CPU (Central Processing Unit) 160 as a processor.
  • the switching unit 140 refers to the MAC table 110 and transmits the frame from the port associated with the destination address of the frame. At this time, if the port is not associated with the destination address of the frame, the switching unit 140 floods the frame from all ports except the frame source address.
  • the address conversion unit 150 rewrites at least a destination address set in advance among the destination address and the source address of the frame that has passed through the PHY function 130.
  • the CPU 160 controls the switching unit 140 and the address conversion unit 150 and manages the MAC table 110. In the switch device 100, the CPU 160 is recognized as the port 10h.
  • the address translation unit 150 incorporates a destination translation register 150A and a source translation register 150B that can operate at a small capacity and at a high speed, as shown in FIG. 4, in order to rewrite the destination address and the source address of the frame.
  • Arbitrary address conversion data is set by the CPU 160 in the destination conversion register 150A and the transmission source conversion register 150B. Then, when data is set in the destination conversion register 150A, the address conversion unit 150 rewrites the data by overwriting the data at the destination address of the frame, and when data is set in the transmission source conversion register 150B, Overwrite and rewrite data in the source address.
  • a console 300 for performing a test start instruction or the like is detachably connected to the CPU 160 of the switch device 100.
  • a general-purpose computer such as a PC (Personal Computer) can be used.
  • test data returns to the CUP 160 via the path of port 00h ⁇ port 01h ⁇ ... ⁇ port 0Fh. Form a test path.
  • the switch device 100 is tested by transmitting test data with the destination address set to the port 00h from the CPU 160 to the switching unit 140 and analyzing the test data returned around the test path.
  • FIG. 5 shows a first test program executed by the CPU 160 of the switch device 100 when the console 300 is instructed to start a test.
  • step 1 the CPU 160 follows the first predetermined rule, as shown in FIG. 6, for each port including the CPU 160, the destination address and the output port. Are registered in the MAC table 110. At this time, the CPU 160 stores “static” and “1” (valid) in the type and valid flag of the MAC table 110, respectively.
  • the first predetermined rule is determined, for example, by selecting one rule from a plurality of rules stored in the console 300 when an operator or the like gives an instruction to start a test on the console 300 (hereinafter, referred to as “first rule”). The same).
  • the first predetermined rule may be stored in a non-volatile memory such as a flash memory of the switch device 300 (the same applies hereinafter).
  • step 2 the CPU 160 sets address conversion data in the destination conversion register 150A of the address conversion unit 150 of the ports 00h to 0Fh according to the second predetermined rule.
  • the second predetermined rule as shown in FIG. 7, a rule is applied such that the destination address of the frame received at port [n] is converted to port [n + 1].
  • step 3 the CPU 160 transmits a test data frame with the destination address as the MAC address “00: 00: 00: 00: 00: 00: 00” of the port 00h to the switching unit 140.
  • step 4 the CPU 160 determines whether or not a test data frame has been received. If the CPU 160 determines that a frame has been received, the process proceeds to step 5 (Yes), whereas if it determines that no frame has been received, the process proceeds to step 6 (No).
  • step 5 the CPU 160 confirms, for example, whether there is an FCS error in the received frame, and whether the user data of the frame transmitted from the CPU 160 is the same as the user data of the received frame. It is determined whether or not is abnormal. That is, the CPU 160 analyzes the received frame to determine whether there is a problem in the boundary scan device. If the CPU 160 determines that the received frame is abnormal, the process proceeds to step 7 (Yes), whereas if it is determined that the received frame is not abnormal, the process ends (No).
  • step 6 the CPU 160 has a problem with the connection between the boundary scan devices through whether or not the first predetermined time has passed since the test data frame was transmitted (that is, whether or not a timeout has occurred). It is determined whether or not there is. If the CPU 160 determines that a timeout has occurred, the process proceeds to step 7 (Yes), while if it determines that a timeout has not occurred, the process returns to step 4 (No).
  • step 7 the CPU 160 notifies the console 300 that there is an abnormality in the switch device 100.
  • the CPU 160 may turn on a failure lamp or the like of the switch device 100 instead of notifying the console 300 of the abnormality (the same applies hereinafter).
  • the destination address is set to “00: 00: 00: 00” from the CPU 160 to the switching unit 140.
  • a test data frame of 00:00 ”(port 00h) is transmitted.
  • the MAC table 110 illustrated in FIG. 6 is referred to, and the frame is output from the output port 00h associated with the destination address “00: 00: 00: 00: 00: 00”.
  • the frame output from the port 00h is returned by the network cable 200 and returns to the port 00h.
  • the address conversion unit 150 When the port 00h receives the frame, the address conversion unit 150 rewrites the destination address of the frame to “00: 00: 00: 00: 00: 01” (port 01h) (see FIG. 7). Is delivered to the switching unit 140. In the switching unit 140, the MAC table 110 shown in FIG. 6 is referred again, and a frame is output from the output port 01h associated with the destination address “00: 00: 00: 00: 01: 01”. The frame output from the port 01h is returned by the network cable 200 and returned to the port 01h. By sequentially repeating such processing, the frame returns to the CPU 160 via the test path of port 00h ⁇ port 01h ⁇ ... ⁇ port 0Fh.
  • the frame sent from the CPU 160 is returned to the CPU 160 through the test path in which the respective ports are connected in sequence while being processed by each boundary scan device of the switch device 100.
  • the connection test between the boundary scan devices and the internal test of the boundary scan device can be performed by the switch device 100 alone without connecting a conventional counter test machine.
  • the switch device 100 is tested through various paths by distributing test data frames to the test path while sequentially changing the settings of the MAC table 110 and the address conversion unit 150. For this reason, it becomes possible to check the communication of all the switching routes, and the test accuracy of the switch device 100 can be improved.
  • a plurality of first predetermined rules and second predetermined rules may be designated on the console 300, and tests based on the respective rules may be sequentially executed.
  • FIG. 9 shows a second test program executed by the CPU 160 of the switch device 100 when the console 300 is instructed to start a test.
  • step 11 the CPU 160 clears the MAC table 110, that is, resets the MAC table 110 to a state in which nothing is set.
  • step 12 the CPU 160 sets address conversion data in the destination conversion register 150A and the transmission source conversion register 150B of the address conversion unit 150 of the ports 00h to 0Fh according to the third predetermined rule.
  • the third predetermined rule as shown in FIG. 10, the destination address of the frame received at port [n] is port [n + 1], and the source address of the frame received at port [n] is port [n].
  • the rules that are converted to] apply.
  • step 13 the CPU 160 sets the destination address as one of the ports, for example, the MAC address “00: 00: 00: 00: 00: 00” of the port 00h, and sets the source address as the MAC address of the CPU 160.
  • the test data frame having the address “00: 00: 00: 00: 00: 10” is transmitted to the switching unit 140.
  • step 14 the CPU 160 determines whether or not the test data frame of the number of ports (specifically, 16) has been received. If the CPU 160 determines that the frame of the number of ports has been received, the process proceeds to step 15 (Yes), whereas if it determines that the frame of the number of ports has not been received, the process proceeds to step 16 (No). ).
  • step 15 the CPU 160 transmits a frame of test data with the destination address as the MAC address “00: 00: 00: 00: 00: 00: 00” of the port 00h to the switching unit 140.
  • step 16 the CPU 160 determines whether the first predetermined time has elapsed since the test data frame was transmitted in step 13 (that is, whether or not a timeout has occurred) between the boundary scan devices. Determine if there is a connection problem. If the CPU 160 determines that a timeout has occurred, the process proceeds to step 20 (Yes), while if it determines that a timeout has not occurred, the process returns to step 14 (No).
  • step 17 the CPU 160 determines whether or not a test data frame has been received. If the CPU 160 determines that the frame has been received, the process proceeds to step 18 (Yes), whereas if it determines that the frame has not been received, the process proceeds to step 19 (No).
  • step 18 the CPU 160 determines whether or not the received frame is abnormal. If the CPU 160 determines that the received frame is abnormal, the process proceeds to step 20 (Yes), whereas if it is determined that the received frame is not abnormal, the process ends (No).
  • step 19 CPU 160 determines whether or not a first predetermined time has elapsed since sending the test data frame in step 15 (that is, whether or not a timeout has occurred). If the CPU 160 determines that a timeout has occurred, the process proceeds to step 20 (Yes), whereas if it determines that a timeout has not occurred, the process returns to step 17 (No).
  • step 20 the CPU 160 notifies the console 300 that there is an abnormality in the switch device 100.
  • the destination address is set to “00: 00: 00: 00: 00: 00: 00” from the CPU 160 to the switching unit 140.
  • a frame of test data is transmitted with “(port 00h) and source address“ 00: 00: 00: 00: 10 ”(CPU).
  • the output port associated with the destination address “00: 00: 00: 00: 00: 00: 00” is not set, so the transmission source Frames are output from all other ports 00h to 0Fh except the port specified by the address.
  • the frames output from the ports 00h to 0Fh are folded back by the network cable 200 and returned to the port that output the frame.
  • the address conversion unit 150 rewrites the destination address and the source address of the frame according to the address conversion rule shown in FIG. 10, and the frame is delivered to the switching unit 140.
  • the MAC table 110 is learned as shown in FIG. 12 by the MAC address learning function originally provided in the switch device 100.
  • the frame delivered from the address conversion unit 150 of each port 00h to 0Fh to the switching unit 140 finally returns to the CPU 160 via the same path as the first test method.
  • a frame of test data with a destination address “00: 00: 00: 00: 00: 00: 00” (port 00h) is transmitted from the CPU 160 to the switching unit 140. Then, the frame returns to the CPU 160 through the test path of port 00h ⁇ port 01h ⁇ ... ⁇ port 0Fh by the same processing as in the first test method.
  • the MAC table 110 is automatically cleared. It can be determined whether or not.
  • the switch device 100 is tested through various paths by distributing the test data frame to the test path while sequentially changing the setting of the address conversion unit 150. For this reason, it becomes possible to check the communication of all the switching routes, and the test accuracy of the switch device 100 can be improved.
  • a plurality of third predetermined rules may be designated on the console 300, and tests based on the respective rules may be sequentially executed.
  • FIGS. 13 and 14 show a third test program executed by the CPU 160 of the switch device 100 when the console 300 is instructed to start a test.
  • the present invention can also be applied to the second test method.
  • step 21 according to the first predetermined rule, the CPU 160 registers a record in which the destination address and the output port are associated with each other including the CPU 160 in the MAC table 110 as shown in FIG.
  • the CPU 160 sets data for address conversion in the destination conversion register 150A of the address conversion unit 150 of ports 00h to 0Fh according to the fourth predetermined rule.
  • a rule is applied so that the destination address is converted to port 00h.
  • the fourth predetermined rule forms an infinite loop test path in which a frame received at port 0Fh is output to port 00h.
  • step 23 as shown in FIG. 8, the CPU 160 transmits a frame of test data with the destination address as the MAC address “00: 00: 00: 00: 00: 00” of the port 00h to the switching unit 140.
  • step 24 the CPU 160 determines whether or not a frame of the maximum bandwidth is distributed to the switch device 100 by referring to a buffer overflow display mounted on the switch device 100, for example. If the CPU 160 determines that a buffer overflow has occurred, the process proceeds to step 25 (Yes), whereas if it determines that a buffer overflow has not occurred, the process proceeds to step 26 (No). At this time, the CPU 160 also counts the number N of frames transmitted until the buffer overflow occurs.
  • step 25 the CPU 160 waits for a third predetermined time in order to secure a time during which the state where the frame of the maximum bandwidth is distributed is maintained to some extent.
  • step 26 the CPU 160 determines whether or not there is a problem in the connection between the boundary scan devices through whether or not a timeout has occurred. If the CPU 160 determines that a timeout has occurred, the process proceeds to step 31 (Yes), while if it determines that a timeout has not occurred, the process returns to step 23 (No).
  • step 27 the CPU 160 sets “00: 00: 00: 00: 00: 10” indicating the MAC address of the CPU 160 in the destination conversion register 150A of the address conversion unit 150 of the port 0Fh. In this way, the frame received at the port 0Fh is returned to the CPU 160 because the address conversion unit 150 rewrites the destination address to the MAC address of the CPU 160.
  • step 28 the CPU 160 determines whether or not N frames, that is, all frames distributed in the maximum bandwidth have been received. If the CPU 160 determines that N frames have been received, the process proceeds to step 29 (Yes), whereas if it determines that N frames have not been received, the process proceeds to step 30 (No). ).
  • step 29 the CPU 160 determines whether or not the received frame is abnormal. If the CPU 160 determines that the received frame is abnormal, the process proceeds to step 31 (Yes), whereas if it is determined that the received frame is not abnormal, the process ends (No).
  • step 30 the CPU 160 determines whether or not there is a problem in the connection between the boundary scan devices through whether or not a timeout has occurred. If the CPU 160 determines that a timeout has occurred, the process proceeds to step 31 (Yes), whereas if it determines that a timeout has not occurred, the CPU 160 returns the process to step 28 (No). Since the connection test between the boundary scan devices has already been performed in step 26, the process in step 30 may be omitted.
  • step 31 the CPU 160 notifies the console 300 that there is an abnormality in the switch device 100.
  • the destination address of the address conversion unit 150 of the port 0Fh is set to the MAC address “00: 00: 00: 00: 00: 00” of the port 00h, so that the frame test path is infinite. A loop will be formed. Then, until the buffer overflow occurs, as shown in FIG. 16, the test with the maximum bandwidth, that is, the test with the maximum load can be performed by distributing N frames on the test path. In addition, after executing the test in the maximum bandwidth for the third predetermined time, the destination address of the address conversion unit 150 of the port 0Fh is changed to the MAC address “00: 00: 00: 00: 00: 10” of the CPU 160. The frame received at port 0Fh returns to the CPU 160. Therefore, as in the first and second test methods, an internal test of the scan device can be performed by analyzing the frame received by the CPU 160.
  • the MAC test is performed so that each port 00h to 0Fh is a random test path that always passes through once.
  • the table 110 and the address conversion unit 150 may be set.
  • the network cable 200 may have a path in which, for example, an input port and an output port are appropriately connected.
  • the switch device 100 is not limited to the 16 ports 00h to 0Fh, and may include other numbers of ports.
  • test start instruction may be issued not only from the console 300 but also by activating a test mode mounted on the switch device 100.
  • the first to fourth predetermined rules may be stored in advance in the nonvolatile memory of the switch device 100.
  • Switch apparatus 110 MAC table 120 Connector 130 PHY function 140 Switching part 150 Address conversion part 150A Destination conversion register 150B Transmission source conversion register 160 CPU 200 Network cable 300 Console

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Abstract

La présente invention se rapporte à un dispositif commutateur qui, en réponse à une instruction reçue de l'extérieur, active un module de conversion d'adresse qui convertit l'adresse de destination pour une trame en une adresse arbitraire, et qui définit une table contenant des enregistrements associant des adresses de destination à des ports de sortie, de sorte à créer ainsi un chemin de test qui passe par l'ensemble des ports et retourne au processeur (CPU). Ensuite, le dispositif commutateur délivre en sortie, à l'intention d'un module de commutation, une trame pour laquelle le port qui sert de point de base au chemin de test correspond à l'adresse de destination. Puis, le dispositif commutateur analyse la trame qui retourne au processeur et détermine la présence d'un problème éventuel.
PCT/JP2010/070128 2010-11-11 2010-11-11 Dispositif commutateur et procédé pour tester le dispositif commutateur WO2012063347A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174848A (ja) * 1998-12-07 2000-06-23 Nec Corp 通信制御装置
JP2002152317A (ja) * 2000-11-10 2002-05-24 Fujitsu Ltd 試験装置
JP2010118823A (ja) * 2008-11-12 2010-05-27 Nec Access Technica Ltd イーサネットポート検査システム、イーサネットポート検査方法及び通信装置検査プログラム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174848A (ja) * 1998-12-07 2000-06-23 Nec Corp 通信制御装置
JP2002152317A (ja) * 2000-11-10 2002-05-24 Fujitsu Ltd 試験装置
JP2010118823A (ja) * 2008-11-12 2010-05-27 Nec Access Technica Ltd イーサネットポート検査システム、イーサネットポート検査方法及び通信装置検査プログラム

Non-Patent Citations (1)

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Title
CISCO SYSTEMS, INC.: "ATM/Layer 3 Switch Router Troubleshooting Guide 12.1(12C)E, ATM/Layer 3 Switch Router Troubleshooting Guide, 12.1(12C)E, Cisco Systems, Inc.", CISCO SYSTEMS, INC., 31 December 2008 (2008-12-31), pages 39, Retrieved from the Internet <URL:http://www.cisco.com/japanese/warp/public/3/jp/service/manualj/sw/cat85/al3srtg/196901.pdf> *

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