WO2012053127A1 - Dispositif d'imagerie à semi-conducteurs, procédé d'entraînement de celui-ci, et dispositif d'imagerie - Google Patents

Dispositif d'imagerie à semi-conducteurs, procédé d'entraînement de celui-ci, et dispositif d'imagerie Download PDF

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WO2012053127A1
WO2012053127A1 PCT/JP2011/002034 JP2011002034W WO2012053127A1 WO 2012053127 A1 WO2012053127 A1 WO 2012053127A1 JP 2011002034 W JP2011002034 W JP 2011002034W WO 2012053127 A1 WO2012053127 A1 WO 2012053127A1
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Prior art keywords
potential
imaging device
solid
state imaging
transfer
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PCT/JP2011/002034
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English (en)
Japanese (ja)
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網川裕之
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device using the solid-state imaging device as an imaging device.
  • FIG. 21 is a diagram illustrating a configuration of a solid-state imaging device according to the related art.
  • the solid-state imaging device according to the prior art includes a pixel array unit 11, a vertical selection circuit 12, a power supply circuit 13, a noise canceller circuit (CDS) 14, a horizontal selection circuit 15, a horizontal selection transistor 16, and a horizontal signal line. 17 and a timing generator (TG) 18.
  • the pixel array unit 11 has a plurality of unit pixels 20 arranged in a matrix.
  • FIG. 22 shows a circuit configuration of the unit pixel 20 shown in FIG.
  • the unit pixel 20 includes a photodiode 21, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, a row selection transistor 25, and a floating diffusion unit 26.
  • FIG. 23 is a waveform diagram showing the relationship between drive pulses in a solid-state imaging device according to the prior art.
  • FIG. 23 shows a reset pulse RST for driving the reset transistor and a transfer pulse TR for driving the transfer transistor.
  • the transfer transistor is driven by applying a ternary potential (specifically ⁇ 2V / ⁇ 1V / 3V) to the gate electrode of the transfer transistor.
  • a ternary potential specifically ⁇ 2V / ⁇ 1V / 3V
  • the transfer transistor is driven by a negative intermediate potential simultaneously with or before the fall of the reset pulse RST, so that the P well under the transfer transistor and the N of the floating diffusion (FD) portion are It has been reported that the electric field applied to the boundary with the + layer is relaxed, thereby suppressing the leakage current caused by GIDL (Gate Induced Leakage).
  • the pixel portion has been configured using a circuit in which a floating diffusion (FD) portion is shared by a plurality of transfer transistors.
  • FD floating diffusion
  • a ternary drive pulse is input to the gate electrode of the transfer transistor.
  • GIDL occurs when the potential applied to the gate electrode of another transfer transistor sharing the same FD portion is fixed to the lowest potential among the three values.
  • charge (leakage current) flows into the FD portion, and the charge and the signal charge transferred from the photodiode are mixed in the FD portion and become noise.
  • the reset transistor also has a problem that the channel length is shortened and off-leakage is increased as the device is miniaturized. In order to cope with this problem, a negative voltage is applied to the gate electrode at the time of OFF. At this time, since the reset transistor shares the FD portion as well as the transfer transistor, a leak current caused by GIDL is generated and becomes noise.
  • the potential of the transfer pulse input to the gate electrode of the transfer transistor that transfers the signal charge of the photodiode is an intermediate potential (specifically, -1 V) of the three values.
  • the potential barrier below the transfer transistor is lowered and off-leakage is increased. For this reason, the signal charge of the photodiode leaks to the FD portion before the transfer transistor is turned on, resulting in a decrease in the signal charge.
  • the present invention has been made in view of the above problems, and it is possible to suppress the influence of a decrease in signal charge of a photodiode by more effectively reducing GIDL for a fine pixel cell.
  • An object is to provide a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device.
  • a first solid-state imaging device includes a photoelectric conversion element, a plurality of transfer transistors that transfer a signal charge photoelectrically converted by the photoelectric conversion element to a floating diffusion,
  • a solid-state imaging device having a pixel array unit in which unit pixels including a reset transistor for resetting a floating diffusion are arranged in a matrix, and a first potential, a first potential with respect to a gate electrode of each transfer transistor
  • Drive means for applying a potential of at least three values of a second potential lower than one potential and a third potential lower than the first potential and higher than the second potential;
  • the driving means turns on each of the transfer transistors by applying the first potential, and causes the signal charge to float.
  • Transfer to the diffusion turn off each transfer transistor by applying the second potential, accumulate and hold the signal charge in the photoelectric conversion element, and transfer one of the plurality of transfer transistors
  • the third potential is applied to the gate electrode of the transistor, the third potential is applied to the gate electrode of another transfer transistor connected to the floating diffusion.
  • a second solid-state imaging device includes a photoelectric conversion element and at least one or more of transferring a signal charge photoelectrically converted by the photoelectric conversion element to a floating diffusion.
  • a solid-state imaging device having a pixel array unit in which unit pixels including a transfer transistor and a reset transistor for resetting the floating diffusion are arranged in a matrix, and the first pixel is arranged with respect to the gate electrode of the transfer transistor.
  • Drive means for applying at least three potentials: a potential, a second potential lower than the first potential, and a third potential lower than the first potential and higher than the second potential. Further, the driving means turns on the transfer transistor by applying the first potential to thereby advance the signal charge.
  • the signal charge provided to each vertical signal line corresponding to each column of the pixel array unit and read out to each vertical signal line is amplified.
  • Gain setting of column amplifier section or analog / digital conversion gain in the analog / digital conversion circuit And in conjunction with the down setting may further have a means for varying the magnitude of said third potential.
  • a driving method of a first solid-state imaging device includes a photoelectric conversion element and a plurality of transfer transistors that transfer a signal charge photoelectrically converted by the photoelectric conversion element to a floating diffusion.
  • a solid-state imaging device having a pixel array unit in which unit pixels including a reset transistor for resetting the floating diffusion are arranged in a matrix, and a first electrode is connected to the gate electrode of each transfer transistor. Applying a potential of at least three values of one potential, a second potential lower than the first potential, and a third potential lower than the first potential and higher than the second potential; By applying the first potential, each transfer transistor is turned on and the signal charge is transferred to the floating diffusion.
  • Each of the transfer transistors is turned off by applying the second potential to accumulate and hold the signal charge in the photoelectric conversion element, and the gate electrode of one of the transfer transistors is applied to the gate electrode of the transfer transistor.
  • the third potential is applied, the third potential is applied to the gate electrode of another transfer transistor connected to the floating diffusion.
  • a driving method of a second solid-state imaging device includes a photoelectric conversion element and at least one for transferring a signal charge photoelectrically converted by the photoelectric conversion element to a floating diffusion.
  • a driving method of a solid-state imaging device having a pixel array unit in which unit pixels including one or more transfer transistors and a reset transistor for resetting the floating diffusion are arranged in a matrix, the gate electrode of the transfer transistor being On the other hand, the first potential, the second potential that is lower than the first potential, and the third potential that is lower than the first potential and higher than the second potential. And the transfer transistor is turned on by applying the first potential, and the signal charge is changed to the floating device.
  • Transfer to fusion turn off the transfer transistor by applying the second potential, accumulate and hold the signal charge in the photoelectric conversion element, and the third potential with respect to the gate electrode of the transfer transistor Is applied, the third potential or a potential higher than the third potential is applied to the gate electrode of the reset transistor.
  • a first imaging device includes a solid-state imaging device that images a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and the solid-state imaging device.
  • the solid-state imaging device includes a photoelectric conversion element and a plurality of signals that transfer the signal charges photoelectrically converted by the photoelectric conversion element to a floating diffusion.
  • a pixel array unit in which unit pixels including a transfer transistor and a reset transistor for resetting the floating diffusion are arranged in a matrix; One potential, a second potential lower than the first potential, and a second potential lower than the first potential and the second potential Driving means for applying at least a ternary potential of a higher third potential, wherein the driving means turns on each of the transfer transistors by applying the first potential to transfer the signal charge to the floating diffusion. And by applying the second potential, each transfer transistor is turned off to accumulate and hold the signal charge in the photoelectric conversion element, and one transfer transistor of the plurality of transfer transistors When the third potential is applied to the gate electrode, the third potential is applied to the gate electrode of another transfer transistor connected to the floating diffusion.
  • a second imaging device includes a solid-state imaging device that images a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and the solid-state imaging device.
  • An image pickup apparatus including a signal processing unit that processes an output signal from the image pickup apparatus, wherein the solid-state image pickup device transfers a photoelectric conversion element and a signal charge photoelectrically converted by the photoelectric conversion element to a floating diffusion.
  • the solid-state imaging device has a pixel array unit in which unit pixels including at least one transfer transistor and a reset transistor that resets the floating diffusion are arranged in a matrix, and the solid-state imaging device has a gate electrode of the transfer transistor.
  • Driving means for applying at least a ternary potential of a third potential higher than the second potential, wherein the driving means turns on the transfer transistor by applying the first potential to The charge is transferred to the floating diffusion, the transfer transistor is turned off by applying the second potential, the signal charge is accumulated and held in the photoelectric conversion element, and the gate electrode of the transfer transistor is When the third potential is applied, the third potential or a potential higher than the third potential is applied to the gate electrode of the reset transistor.
  • the present invention it is possible to suppress the adverse effect on the pixel signal by effectively suppressing the leakage current caused by GIDL in the FD section.
  • the above-described effect is more noticeable.
  • FIG. FIG. 4 is a potential diagram corresponding to the cross-sectional view shown in FIG.
  • FIG. 5 is a diagram illustrating an example of the vertical buffer circuit for the transfer pulse TR in the vertical buffer circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 6 is a diagram illustrating another example of the vertical buffer circuit for the transfer pulse TR in the vertical buffer circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 7 is a diagram illustrating an example of drive timing for explaining an operation when the vertical buffer circuit illustrated in FIG. 5 or 6 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 8 is a diagram illustrating another example of drive timing for explaining the operation when the vertical buffer circuit shown in FIG. 5 or 6 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 9 is a diagram illustrating another example of the drive timing for explaining the operation when the vertical buffer circuit shown in FIG. 5 or FIG. 6 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 10 is a diagram illustrating another example of drive timing for explaining the operation when the vertical buffer circuit shown in FIG. 5 or 6 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 11 is a diagram illustrating another example of the vertical buffer circuit for the transfer pulse TR in the vertical buffer circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 12 is a diagram illustrating an example of drive timing for explaining the operation when the vertical buffer circuit shown in FIG. 11 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 10 is a diagram illustrating another example of drive timing for explaining the operation when the vertical buffer circuit shown in FIG. 5 or 6 is used in the solid-state imaging device according to the first embodiment.
  • FIG. 11 is a diagram illustrating another example of the vertical buffer circuit for the transfer pulse TR in the vertical
  • FIG. 18A is a cross-sectional view illustrating an example of a cross-sectional structure of the transfer transistor, the photodiode portion, and the reset transistor in the unit pixel of the solid-state imaging device according to the second embodiment
  • FIG. 18 is a potential diagram corresponding to the cross-sectional view illustrated in FIG.
  • FIG. 19A is a diagram illustrating a design example of an AD gain value, an AD input range, and an intermediate voltage (third potential) of a transfer pulse (TR) in the solid-state imaging device according to the second embodiment.
  • FIG. 19 (b) shows a design of the gain value of the column amplifier circuit (CLAMP), the CLAMP input range, and the intermediate voltage (third potential) of the transfer pulse (TR) in the solid-state imaging device according to the modification of the second embodiment. It is a figure which shows an example.
  • FIG. 20 is a block diagram illustrating a configuration of an imaging apparatus according to the third embodiment.
  • FIG. 21 is a diagram illustrating a configuration of a solid-state imaging device according to the related art.
  • FIG. 22 is a diagram illustrating a circuit configuration of a unit pixel in the solid-state imaging device according to the related art.
  • FIG. 23 is a waveform diagram showing the relationship between drive pulses in a solid-state imaging device according to the prior art.
  • FIG. 1 is a configuration diagram of a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 31 includes a pixel array in which a large number of unit pixels 33 each including a photodiode that performs photoelectric conversion and MOS (metal-oxide-semiconductor-) switch elements are arranged in a matrix.
  • MOS metal-oxide-semiconductor-
  • the vertical buffer circuit 34 that drives pixel array unit 32, vertical scanning circuit 37, noise canceller (CDS) circuit 41 that receives pixel signals in one column and has a difference means, and pixel signals from CDS circuit 41
  • CDS noise canceller
  • ADC analog / digital conversion circuit
  • DM digital memory
  • horizontal scanning circuit 45 for sequentially selecting held pixel signals
  • TG timing generation circuit
  • the TG 38 is configured to receive data from outside and generate drive pulses corresponding to a plurality of drive modes.
  • the vertical buffer circuit 34 includes a reset pulse buffer circuit 35 and a transfer pulse buffer circuit 36.
  • a vertical signal line 39 is provided for each column with respect to the matrix arrangement of the unit pixels 33, and drive control lines (for example, a reset control line 50, a transfer control line 51, and the like) are provided for each row. 52).
  • a constant current source 40 is connected to the vertical signal line 39 in each column.
  • the vertical scanning circuit 37 is composed of a shift register or an address decoder and generates a row selection pulse as appropriate.
  • a shutter shift register signal ESR corresponding to the electronic shutter and a shift register signal SR corresponding to the readout row are output from the vertical scanning circuit 37, and each shift register signal is received by the vertical buffer circuit 34.
  • the reset pulse buffer circuit 34 generates a reset pulse RST
  • the transfer pulse buffer circuit 36 generates a drive pulse such as the transfer pulse TR.
  • each unit pixel 33 of the pixel array unit 32 is scanned in the vertical direction (up and down direction) for each of the electronic shutter row and the readout row, and the unit pixel 33 of the row is scanned with respect to the electronic shutter row.
  • An electronic shutter operation for performing signal discharge is performed, and a readout operation for performing signal readout of the unit pixel 33 in the row is performed on the readout row.
  • the vertical scanning circuit 37 can select a plurality of readout rows simultaneously. In this case, the vertical scanning circuit 37 receives signals from the selected unit pixels in the plurality of rows. Includes a configuration for reading simultaneously.
  • the vertical scanning circuit 37 can also select a plurality of electronic shutter rows at the same time. In that case, the vertical scanning circuit 37 includes a configuration in which signals are simultaneously discharged from the selected unit pixels of the plurality of rows.
  • the CDS circuit 41 is connected to each column of unit pixels 33 arranged in a matrix in the pixel array unit 32, for example.
  • the CDS circuit 41 performs a CDS (correlated double sampling) process on the signal output from the unit pixel 33 in the row selected by the vertical scanning circuit 37 through the vertical signal line 39, so that the unit pixel 33 Signal processing for removing generated reset noise and pixel-specific fixed pattern noise caused by transistor threshold variation is performed, and the pixel signal after signal processing is temporarily held.
  • CDS correlated double sampling
  • the analog-to-digital conversion circuit (ADC) 42 has an AGC (Auto Gain Control) function and an analog-to-digital conversion function.
  • the ADC 42 converts a pixel signal, which is an analog signal held by the CDS circuit 41, into a digital signal. Is done.
  • FIG. 2A is a circuit diagram showing an example of the circuit configuration of the unit pixel 33.
  • the unit pixel 33 according to this circuit example includes elements that perform photoelectric conversion, such as photodiodes 60 and 61, transfer transistors 62 and 63, a reset transistor 64, and an amplification transistor 65. ing.
  • the transistors 62 to 65 for example, an N-channel MOS transistor may be used.
  • the transfer transistor 62 is connected between the cathode electrode of the photodiode 60 and the floating diffusion (FD) portion 66.
  • the transfer transistor 63 is connected between the cathode electrode of the photodiode 61 and the FD portion 66. That is, in this embodiment, for example, a circuit configuration in which two transfer transistors are connected to the same FD unit is used.
  • the transfer control line 52 is connected to the gate electrode of the transfer transistor 62, and the transfer control line 51 is connected to the gate electrode of the transfer transistor 63.
  • the transfer pulse TR (2n) When the transfer pulse TR (2n) is applied from the transfer control line 52 to the gate electrode of the transfer transistor 62, the transfer transistor 62 is turned on, and the signal charge (specifically, photoelectrically converted by the photodiode 60 and accumulated in the photodiode 60) In other words, electrons are transferred to the FD unit 66.
  • the transfer pulse TR (2n ⁇ 1) is applied from the transfer control line 51 to the gate electrode of the transfer transistor 63, the transfer transistor 63 is turned on, and the signal charge photoelectrically converted by the photodiode 61 and accumulated in the photodiode 61 is turned on. Is transferred to the FD unit 66.
  • the reset control line 50 is connected to the gate electrode, the pulse power supply Vddcell of the pixel is connected to the drain electrode, and the FD section 66 is connected to the source electrode.
  • the reset transistor 64 is The pixel is turned on, the potential of the pulse power supply Vddcell of the pixel is set to the power supply potential Vdd, and the potential of the FD portion 66 is reset to the power supply potential Vdd.
  • the gate electrode is connected to the FD section 66
  • the drain electrode is connected to the pixel pulse power supply Vddcell
  • the source electrode is connected to the vertical signal line 39.
  • the amplification transistor 65 outputs the potential of the FD unit 66 after being reset by the reset transistor 64 to the vertical signal line 39 as a reset level, and further, the FD unit 66 after the signal charge is transferred by the transfer transistors 62 and 63. Is output to the vertical signal line 39 as a signal level.
  • the vertical signal line 39 is connected to the source electrode of the selection transistor 67, and the pixel signal amplified by the amplification transistor 65 is output to the vertical signal line 39 through the selection transistor 67.
  • the wiring corresponding to the selection control line 53 is not shown in FIG. 1, a selection pulse is supplied from the vertical buffer circuit 34 through the selection control line 53 as in the case of the reset control line 50 and the like.
  • the unit pixel 33 has a configuration including two photodiodes and transfer transistors.
  • the unit pixel 33 is not limited to this, and includes a configuration including one photodiode and transfer transistor, or a photodiode and transfer transistor. It is also possible to use a structure including four transistors.
  • FIG. 3A is a cross-sectional view showing an example of a cross-sectional structure of a plurality of transfer transistors and photodiode portions in a unit pixel
  • FIG. 3B is a potential corresponding to the cross-sectional view shown in FIG. FIG.
  • the photodiode 60 of this embodiment is formed by a PN junction between a P well 70 and an N type diffusion layer 71 formed in the P well 70.
  • a high-concentration P-type diffusion layer 72 is formed on the surface portion of the N-type diffusion layer 71.
  • the PN junction corresponding to the photodiode 61 is formed by the P well 70 and the N type diffusion layer 73.
  • a high-concentration P-type diffusion layer 74 is formed on the surface portion of the N-type diffusion layer 73.
  • the transfer transistor 62 uses the N-type diffusion layer 75 that becomes the FD portion 66 as a drain region.
  • a gate electrode 76 is formed through an insulating film (not shown) to form a channel.
  • a gate electrode 77 is formed on the region between the N-type diffusion layer 75 and the N-type diffusion layer 73 of the photodiode 61 via an insulating film (not shown) to form a channel. Yes.
  • the concentration of the N-type diffusion layer 75 is set high in order to make contact. Further, a negative voltage is applied to the gate electrodes of the transfer transistors 62 and 63 when they are turned off. As a result, the regions 78 and 79 where the gate electrodes 76 and 77 overlap with the N-type diffusion layer 75 therebelow are depleted and the electric field becomes stronger. As a result, high electric field effects such as avalanche multiplication and interband tunneling are obtained. Increases significantly and the leakage current due to GIDL increases.
  • a negative intermediate potential is applied to the gate electrode 76 of the transfer transistor 62 that reads the signal charge from the photodiode 60, and the p-well 70 and the N-type diffusion layer of the FD portion are located below the gate electrode 76 of the transfer transistor 62. Even if the electric field applied to the region 78 that is the boundary with the transistor 75 is relaxed, the region 79 that is the boundary between the P well 70 and the N-type diffusion layer 75 in the FD portion is provided below the gate electrode 77 of the other transfer transistor 63. As a result, the leakage current caused by GIDL cannot be suppressed. This leakage current increases remarkably as the number of transfer transistors sharing the FD portion increases with device miniaturization.
  • FIG. 4A is a cross-sectional view illustrating an example of a cross-sectional structure of the transfer transistor, the photodiode portion, and the reset transistor in the unit pixel
  • FIG. 4B corresponds to the cross-sectional view illustrated in FIG. It is a potential diagram.
  • the reset transistor 64 includes an N-type diffusion layer 68 connected to the pixel pulse power supply Vddcell as a drain electrode using the N-type diffusion layer 75 as an FD portion as a source electrode.
  • a gate electrode 80 is formed on the region between the drain electrode and the source electrode in the reset transistor 64 via an insulating film (not shown) in order to form a channel.
  • the N-type diffusion layer 75 has a high concentration in order to make contact. Also in the reset transistor 64, a negative voltage is applied to the gate electrode 80 when the device is turned off in order to cope with the problem that the channel length is shortened and off-leakage is increased as the device is miniaturized. For this reason, as in the transfer transistor, the region 69 where the gate electrode 80 and the N-type diffusion layer 75 located therebelow overlap is depleted and the electric field becomes stronger, resulting in an increase in leakage current due to GIDL. To do.
  • a pulse signal that takes, for example, a ternary reset pulse RST among the drive pulses output from the vertical buffer circuit 34 for driving the unit pixel 33, that is, among the reset pulse RST and the transfer pulse TR.
  • a pulse signal that takes, for example, a ternary reset pulse RST As described above, a configuration in which the reset pulse RST is set to a potential equal to or higher than the intermediate potential when the transfer pulse TR is at the intermediate potential is used.
  • Vt of the reset transistor 64 may be adjusted so that the “L” level of the reset pulse signal becomes a potential equal to or higher than the intermediate potential as a binary pulse signal.
  • FIG. 5 shows an example of the vertical buffer circuit 36 for the transfer pulse TR in the vertical buffer circuit 34 of the present embodiment.
  • the transfer pulse vertical buffer circuit 36 is a circuit for supplying the transfer pulse TR to the unit pixel 33 of the pixel array section 33, and includes means for supplying the ternary or binarized transfer pulse TR. .
  • the transfer pulse vertical buffer circuit 36 includes a multiplexer unit 82 including an AND circuit, a NAND circuit, a 2-input OR circuit, and a selector circuit, and an output stage buffer circuit 81.
  • the transfer pulse vertical buffer circuit 36 is applied with three types of potentials [1] to [3]. That is, the positive potential [1] is a potential (for example, 3V) required for completely reading out signal charges from the photodiode, and the negative potential [2] suppresses dark current and white spot scratches. Therefore, the potential [3] may be an intermediate potential (for example, -1 V) between the negative potential [2] and about 0 V.
  • the potential [3] when the potential [3] is 0 V, the potential [3] can be easily supplied by grounding, which is advantageous in that a circuit such as a step-down circuit is not required.
  • the GND potential fluctuates due to current fluctuation or the like, the potential fluctuation is combined with the signal component due to coupling between the gate electrode of the transfer transistor and the FD portion, resulting in noise. .
  • the wiring for supplying the potential [3] to the substrate wiring (having the substrate potential) of the pixel array unit 32 where current does not flow constantly, and supplying the GND potential, the potential variation is prevented. You may suppress the influence of the image pick-up image quality which originates.
  • the transfer pulse vertical buffer circuit 36 receives, as input signals, a read shift register pulse SR [n] and a shutter shift register pulse ESR output from the vertical scanning circuit 37 as a read row. [n], a transfer timing pulse TRi output from the timing generation circuit 38, a transfer timing pulse ETRi during shuttering, and a potential switching pulse PUL are input.
  • a high level is output to the read shift register pulse SR [n].
  • the shutter shift register pulse ESR [n] is output. A high level is output.
  • the output side of the transfer buffer vertical buffer circuit 36 is connected to a transfer control line 52 connected to the gate electrode of the transfer transistor 62 and a transfer control line 51 connected to the gate electrode of the transfer transistor 63.
  • a transfer pulse TR [n] having a ternary potential is output to each transfer control line.
  • the output stage buffer circuit 81 is composed of, for example, a P-channel transistor and an N-channel translator, and the fluctuation of the substrate potential in each transistor is suppressed by the potential [1] or the potential [2].
  • the potential variation of the P well is suppressed by the potential [2]
  • the potential variation of the N well is suppressed by the potential [1].
  • the potential [1] and the potential [2] are used as the power supply potential of the AND circuit that controls the gate of each transistor. As a result, a high driving force can be obtained without increasing the channel width W of the transistor, so that the chip area can be reduced.
  • FIG. 6 shows another example of the vertical buffer circuit 36 for the transfer pulse TR of this embodiment.
  • the vertical buffer circuit shown in FIG. 6 has a multiplexer unit 83 instead of the multiplexer unit 82 of the circuit shown in FIG.
  • two types of voltages [1] and [2] are applied to the vertical buffer circuit shown in FIG.
  • a diode is connected between the wiring supplying the potential [2] and the selector circuit, and a potential gradient between the potential [2] and the GND potential is generated by generating a potential gradient at the diode connection portion. Is generated.
  • a circuit such as a step-down circuit for supplying the potential [3] becomes unnecessary, and the chip area can be reduced.
  • the aforementioned diode may be provided in a circuit block outside the vertical buffer circuit shown in FIG. 6 to generate a potential gradient.
  • FIG. 7 shows an example of drive timing for explaining the operation of the solid-state imaging device 31 using the vertical buffer circuit shown in FIG. 5 or 6 in the present embodiment.
  • the transfer pulse TR [2n] for the read row and the transfer pulse TR [2n-1] for the non-read row are at the “L” level (that is, the potential [2] (for example, ⁇ 2V) to an intermediate potential (that is, potential [3] (for example, -1V)).
  • the reset pulse RST [n] becomes an “L” level that is equal to or higher than the intermediate potential (that is, the potential [3] (eg, ⁇ 1V)), and the reset transistor 64 Turn off.
  • the potential of the FD unit 66 is output to the vertical signal line 39 as a reset level, and is clamped by the clamp pulse CDS (CL) in the CDS circuit 41 from time t4 to time t5.
  • the transfer pulse TR [2n] in the readout row becomes “H” level (that is, potential [1] (for example, 3V)), and signal charges are transferred from the photodiode 60 to the FD portion 66 via the transfer transistor 62. Is transferred.
  • the transfer pulse TR [2n] in the readout row becomes an intermediate potential (that is, potential [3] (for example, ⁇ 1V)), the transfer transistor is turned off, and the signal charge is transferred.
  • the potential of 66 is transmitted to the vertical signal line 39 through the amplification transistor 65.
  • the sample hold pulse CDS (SH) becomes “H” level in the CDS circuit 41 and the potential of the vertical signal line 39 is held.
  • the CDS circuit 41 uses the difference between the signal level held by the clamp pulse CDS (CL) and the signal level held by the sample hold pulse CDS (SH) as a pixel signal, and the analog / digital conversion circuit at the next stage. (ADC) 42 for output.
  • the potential of the transfer pulse TR [2n] in the read row and the potential of the transfer pulse TR [2n-1] in the non-read row are changed from the intermediate potential to the “L” level (that is, the potential [2] (for example, ⁇ 2V)), then, at time t11, the pixel pulse power supply Vddcell is set to “L” level (eg, 0 V), and then at time t12, the reset pulse RST [n] is set to “H” level to reset transistor Turn on 64.
  • the pixel pulse power supply Vddcell is set to “L” level (eg, 0 V)
  • the reset pulse RST [n] is set to “H” level to reset transistor Turn on 64.
  • the “L” level of the pixel pulse power supply Vddcell is written to the FD unit 66, and the amplification transistor 65 is turned off, so that the unit pixel 33 is in a non-selected state.
  • the reset pulse RST [n] is set to the “L” level, and the reset transistor 64 is turned off.
  • the pixel pulse power supply Vddcell is set to the “H” level (for example, 3 V), thereby completing the setting of the non-selected state of the unit pixel 33.
  • the electric potential of the FD portion 66 is a low electric potential (for example, 0 V)
  • the electric field is relaxed, so that no leakage current due to GIDL is generated.
  • the merit of driving the transfer pulse TR [2n] to be an intermediate potential (that is, the potential [3] (for example, ⁇ 1V)) before the reset pulse RST [n] rises is as follows. That is, there is a parasitic capacitance between the gates of the transfer transistors 62 and 63 and the FD unit 66.
  • the transfer pulses TR [2n] and TR [2n-1] fluctuate, the capacitance coupling causes the FD unit 66 to change. Potential fluctuation is transmitted.
  • FIG. 8 shows another example of the drive timing for explaining the operation of the solid-state imaging device 31 using the vertical buffer circuit shown in FIG. 5 or FIG. 6 in the present embodiment.
  • the description will be given focusing on differences from the drive timing shown in FIG.
  • the transfer pulse As will be described later, by setting the transfer pulse to an intermediate potential, the potential barrier below the gate electrode of the transfer transistor is lowered, and as a result, off-leak from the photodiode 60 to the FD portion 66 increases. As a result, part of the signal charge is transferred from the photodiode 60 to the FD unit 66 during the period from when the intermediate potential is applied to the transfer transistor to when the CDS circuit 41 performs clamping, and the transferred state In this case, clamping is performed with the potential of the FD portion 66 at the reset level, so that the signal charge is reduced. On the other hand, when driving as shown in FIG. 8 is performed, the period from when the intermediate potential is applied to the transfer transistor to when clamping is performed by the CDS circuit 41 is shortened, and the decrease in signal charge can be suppressed.
  • FIG. 9 shows another example of drive timing for explaining the operation of the solid-state imaging device 31 using the vertical buffer circuit shown in FIG. 5 or 6 in the present embodiment.
  • the description will be given focusing on differences from the drive timing shown in FIG.
  • each of the three potentials of the reset pulse RST [n] is set to be the same as that of the transfer pulse TR [2n], but the present invention is not limited to this.
  • the intermediate potential of the reset pulse RST [n] is set to a potential equal to or higher than the intermediate potential of the transfer pulse TR [2n].
  • FIG. 10 shows another example of the drive timing for explaining the operation of the solid-state imaging device 31 using the vertical buffer circuit shown in FIG. 5 or 6 in this embodiment.
  • the 2n ⁇ 1 line is a read line.
  • the signal potential of the potential switching pulse PUL becomes “H” level, and the potential of the selector output node NODE1 (see FIG. 5 or FIG. 6) changes from the potential [2] (for example, ⁇ 2 V) to the potential [3] ( For example, shift to ⁇ 1V).
  • the potential of the transfer pulse TR [2n-1] of the 2n-1 row and the potential of the transfer pulse TR [2n] of the 2n row are intermediate from the “L” level (that is, the potential [2] (eg, ⁇ 2 V)). It shifts to a potential (that is, potential [3] (for example, -1 V)).
  • the transfer timing pulse TRi becomes “H” level (that is, potential [1] (for example, 3 V)) at time t2
  • the transfer pulse TR [2n ⁇ 1] of the 2n ⁇ 1 row as the read row is “
  • the transfer transistor 63 is turned on and the signal charge is transferred from the photodiode 61 to the FD unit 66.
  • the transfer pulse TR [2n-1] becomes potential [3] (for example, -1V)
  • the signal potential of the potential switching pulse PUL becomes "L" level
  • the selector The potential of the output node NODE1 is shifted from the potential [3] (for example, ⁇ 1V) to the potential [2] (for example ⁇ 2V).
  • the potential of the transfer pulse TR [2n-1] and the potential of the transfer pulse TR [2n] are shifted from the potential [3] (for example, -1V) to the potential [2] (for example, -2V).
  • the operation at the time of reading of the 2nth row is different from the operation at the time of reading of the 2n-1th row only in that the transfer pulse TR [2n-1] and the transfer pulse TR [2n] are interchanged. Since the other pulses are the same as the operation at the time of reading in the 2n-1th row, the description is omitted.
  • both the shift register pulses SR [2n ⁇ 1] and SR [2n] are at “L” level, and the transfer pulses TR [2n ⁇ 1] and TR [2n] are both at “L” level ( That is, it remains fixed at the potential [2] (for example, ⁇ 2 V).
  • the shutter shift register pulse ESR [2n-1] is at the “H” level.
  • the shutter transfer timing pulse ETRi becomes “H” level
  • the transfer pulse TR [2n ⁇ 1] becomes “H” level (that is, potential [1] (for example, 3V)).
  • 63 is turned on, and signal charges are discharged from the photodiode 61 to the FD section 66.
  • the transfer pulse TR [2n-1] becomes the “L” level (that is, the potential [2] (eg, ⁇ 2 V)), the transfer transistor 63 is turned off, and the signal charge discharging of the photodiode 61 is completed. To do.
  • FIG. 11 shows another example of the vertical buffer circuit 36 for the transfer pulse TR of the present embodiment.
  • the vertical buffer circuit shown in FIG. 11 has a multiplexer unit 84 instead of the multiplexer unit 82 of the circuit shown in FIG.
  • the vertical buffer circuit shown in FIG. 11 has a configuration in which a read shift register pulse SR and a shutter shift register pulse ESR are input to a multi-input OR. As a result, a ternary pulse is output as the transfer pulse TR [2n] or the like to the row selected as the shutter row.
  • FIG. 12 shows an example of drive timing for explaining the operation of the solid-state imaging device using the vertical buffer circuit shown in FIG. 11 in the present embodiment.
  • the timing from time t1 to time t14, which is the reading operation of the 2n-th row, is the same as the timing shown in FIG.
  • the shutter row shift register pulse ESR [2n] becomes “H” level, and the row is selected. Subsequently, at time t16, the transfer pulse TR [2n] and the transfer pulse TR [2n-1] are changed from the “L” level (that is, the potential [2] (for example, ⁇ 2 V)) to the intermediate potential (that is, the potential [3] ( For example, shift to -1V)).
  • the reset pulse RST [n] becomes “H” level, and the FD unit 66 is reset to the potential of the pulse power supply Vddcell of the pixel.
  • the reset pulse RST [n] becomes “L” level, and the potential at the time of resetting the FD unit 66 is determined.
  • the transfer pulse TR [2n] in the 2n-th row becomes the “H” level (that is, the potential [1] (for example, 3V)), and the signal is transferred from the photodiode 60 to the FD unit 66 via the transfer transistor 62. Charge is transferred.
  • the potential of the FD unit 66 varies due to the coupling pulse generated by the variation of the transfer pulse TR [2n] and the parasitic capacitance between the gate electrode of the transfer transistor 62 and the FD unit 66.
  • the potential of the transfer pulse TR [2n] is shifted from the potential [3] that is the intermediate potential to the potential [1] that is the “H” level.
  • the potential fluctuation amount of the FD unit 66 is the same at the time of reading and at the time of the shutter operation. How signal charges are transferred from the photodiode 60 to the FD unit 66 is determined by the potential of the gate electrode of the transfer transistor 62 and the potential of the FD unit 66. For example, when the transfer transistor 62 is turned on, if the potential of the FD portion 66 becomes lower than the channel potential below the gate electrode of the transfer transistor 62, a part of the signal charge remains in the channel portion. When the transistor 62 is turned off, a phenomenon that the signal charge remaining in the channel portion returns to the photodiode 60 occurs.
  • the transfer pulse TR [2n] in the 2n-th row becomes the level of the potential [3] (for example, ⁇ 1V), and then, at time t21, the transfer pulse TR [2n] in the 2n-th row becomes the potential.
  • the level is [2] (for example, -2V).
  • the pixel pulse power supply Vddcell is set to “L” level (for example, 0 V), and subsequently, at time t23, the reset pulse RST [n] is set to “H” level to turn on the reset transistor 64. .
  • the “L” level of the pixel pulse power supply Vddcell is written to the FD unit 66, and the amplifying transistor 65 is turned off so that the unit pixel 33 is not selected.
  • the reset pulse RST [n] is set to the “L” level to turn off the reset transistor 64.
  • the pixel pulse power supply Vddcell is set to the “H” level (for example, 3 V). Setting of the non-selected state of the unit pixel 33 is completed.
  • the electronic shutter shift register pulse ESR [2n ⁇ 1] is at the “H” level during the shutter operation of the 2n ⁇ 1th row.
  • the transfer pulses TR [2n ⁇ 1] and TR [2n] are changed from the potential [2] (for example ⁇ 2V) to the potential [3] (for example ⁇ 1V). ).
  • the transfer pulse TR [2n ⁇ 1] in the 2n ⁇ 1th row is set to “H” level (that is, the potential [1] (eg, 3V). ))
  • the transfer transistor 63 is turned on, and the signal charge is transferred from the photodiode 61 to the FD portion 66.
  • the transfer pulse TR [2n-1] is shifted to the potential [3] (for example, -1V), the transfer transistor 63 is turned off, and the discharge of the signal charge from the photodiode 61 is completed.
  • the transfer pulses TR [2n ⁇ 1] and TR [2n] are changed from the potential [3] (for example, ⁇ 1 V) to the potential [2] (for example ⁇ ). 2V) and fixed at the same potential as that in the non-selected row.
  • FIG. 14 is a configuration diagram of a solid-state imaging device according to the second embodiment.
  • the solid-state imaging device 91 shown in FIG. 14 the same components as those in the solid-state imaging device 31 of the first embodiment shown in FIG. Differences from the solid-state imaging device 31 shown in FIG. 1 will be mainly described.
  • a solid imaging device 91 of the present embodiment shown in FIG. 14 is different from the solid imaging device 31 shown in FIG. 1 in that a column amplifier circuit (CLAMP) 92 is connected to each vertical signal line 39.
  • the pixel signal transmitted through the vertical signal line 39 is amplified by a column amplifier circuit (CLAMP) 92.
  • the gain of the column amplifier circuit (CLAMP) 92 is controlled by a control pulse supplied from the timing generation circuit (TG) 38.
  • the output of the column amplifier circuit (CLAMP) 92 is input to the CDS circuit 41 and subjected to CDS processing. Subsequent pixel signal processing is equivalent to that of the solid-state imaging device 31 shown in FIG.
  • the BIAS circuit 93 is a vertical buffer circuit as a circuit for supplying a potential [3]. 34 is connected.
  • the BIAS circuit 93 is supplied with control pulses SW1 and SW2 from a timing generation circuit (TG) 38, and the potential output from the BIAS circuit 93 is controlled by the control pulses SW1 and SW2.
  • FIG. 15 shows an example of a BIAS circuit that generates the potential [3] in the present embodiment.
  • the circuit shown in FIG. 15 is configured as a charge pump step-down circuit. Specifically, it is determined whether or not the potential [3] generated by the pump circuit unit 130 has reached a desired potential. , R1 to R3 for dividing the output potential [3] output from the charge pump step-down circuit 132 into potentials that can be compared with the comparator 127, and R1 to R3 A resistance voltage dividing circuit 126 that controls the ratio of R3 with control pulses SW1 and SW2 and an AND logic circuit 129 are provided.
  • the value of the potential [3] can be changed by controlling the resistance voltage dividing ratio.
  • the AND logic circuit 129 receives a CLK1_IN signal that is a drive clock signal supplied from the clock generation circuit 128 and a CLKEN signal that is a drive clock stop control signal supplied from the comparator 127.
  • the CLK1 signal for controlling the operation or stop of the unit 130 is output.
  • the pump circuit unit 130 When the pump unit 130 operates, the pump circuit unit 130 outputs the potential [3].
  • the charge generated by the charge pump step-down circuit 132 is distributed by the smoothing capacitive element 131, thereby stabilizing the potential [3].
  • FIG. 16 shows an example of the drive timing of the BIAS circuit for generating the potential [3] in the present embodiment.
  • potential [3] is the output potential of BIAS circuit 93
  • CLK1_IN is a drive clock signal generated by CLK generation circuit 128,
  • CLKEN is an output of comparator 127
  • CLK1 is This is the output of the AND logic circuit 129.
  • CLKEN is an enable signal for the pump circuit unit 130 and is input to the AND logic circuit 129 and serves as a drive clock stop control signal for stopping CLK1_IN supplied from the CLK generation circuit 128.
  • CLKEN is at “L” level
  • the drive pulse CLK1 input to the pump circuit unit 130 is stopped, and when CLKEN is at “H” level, the drive pulse CLK1 is resumed. Yes.
  • the potential [3] periodically rises at times t1, t2, t5, and t6.
  • the potential [3] exceeds the determination voltage Vref and the CLKEN signal output from the comparator 127 of the charge pump step-down circuit 132 becomes the “H” level, the CLK1 input to the pump circuit unit 130
  • the signal becomes a clock pulse in synchronization with CLK1_IN, and the pump circuit unit 130 is operated. That is, when CLK1 as a clock pulse is input to the pump circuit unit 130, the charge pump step-down circuit 132 performs a step-down operation.
  • FIG. 17 shows an example of the vertical buffer circuit 36 for the transfer pulse TR of the present embodiment as a modification of the voltage control method of the potential [3].
  • the vertical buffer circuit shown in FIG. 17 has a multiplexer unit 85 instead of the multiplexer unit 82 of the circuit shown in FIG.
  • two types of voltages [1] and [2] are applied to the vertical buffer circuit shown in FIG.
  • a plurality of (for example, two) diodes are connected in series between the wiring for supplying the potential [2] and the selector circuit, and MOS transistors are connected to both ends of each diode.
  • Mode signals SW3 and SW4 are supplied from the timing generation circuit 38 to the gate portion of the MOS transistor.
  • a potential gradient between the potential [2] and the GND potential is generated by generating a potential gradient at the diode connection portion.
  • the number of potential gradient stages can be changed, whereby a plurality of voltages can be input to the selector.
  • the potential [3] can be controlled by the mode signals SW3 and SW4, and a potential corresponding to the mode signal can be supplied.
  • the aforementioned diode may be provided in a circuit block outside the vertical buffer circuit shown in FIG. 17 to generate a potential gradient.
  • FIG. 18A is a cross-sectional view showing an example of a cross-sectional structure of the transfer transistor, the photodiode portion, and the reset transistor in the unit pixel of this embodiment
  • FIG. 18B is a cross-sectional view shown in FIG. It is a potential diagram corresponding to the figure. Note that the cross-sectional view of FIG. 18A is the same as FIG.
  • the solid-state imaging device 91 of this embodiment shown in FIG. 14 is provided in each vertical signal line 39 corresponding to each column of the pixel array unit 32 and each vertical signal line. 39, a column amplifier circuit (CLAMP) 92 that amplifies the signal charge read to 39, a CDS circuit 41 that performs noise cancellation on the output signal of the column amplifier circuit (CLAMP) 92, and a pixel signal from the CDS circuit 41
  • An ADC circuit 42 that performs analog-to-digital conversion, a digital memory (DM) 43 that holds digital signals, and an input unit that supplies a plurality of drive mode signals to a timing generation circuit (TG) 38 that generates drive signals.
  • a digital camera can set a shooting sensitivity.
  • a low-sensitivity shooting mode corresponding to ISO sensitivity 100 of film sensitivity and a high-sensitivity shooting mode corresponding to ISO 400 of film sensitivity can be set.
  • the solid-state imaging device 91 of the present embodiment is configured to set the gain of the column amplifier circuit (CLAMP) 92 based on the drive signal output from the TG 38 according to a plurality of drive mode signals corresponding to the plurality of imaging modes.
  • CLAMP column amplifier circuit
  • FIG. 19A shows a design example of the shooting voltage (ISO), AD gain value, AD input range, and intermediate voltage (potential [3]) of the transfer pulse (TR) in the present embodiment.
  • the ADC circuit 42 arranged for each column includes an AGC, and the BIAS circuit 93 includes a control unit that switches the potential [3].
  • the control pulse from the TG 38 that has received the drive mode signal from the outside of the chip is transmitted to the ADC circuit 42 and the BIAS circuit 93, whereby the gain value and the potential [3] are set.
  • the higher the ISO sensitivity of the film sensitivity that is, the higher the gain value
  • the AD gain is 0 dB as a default setting
  • This setting is a shooting condition at high illuminance corresponding to, for example, ISO sensitivity 100 (low sensitivity shooting mode) of film sensitivity, and the signal charge photoelectrically converted by the photodiode 60 is compared with the leakage current of the FD unit 66. This is equivalent to having a sufficient amount of charge.
  • the leakage current of the FD unit 66 is allowed while the off-leakage of the transfer transistor 62 is suppressed.
  • reduction of the signal charge of the photodiode 60 is prevented.
  • the AD input range is half of the default setting, and the saturation output level of the photodiode 60 is a level that cannot be converted from analog to digital.
  • This setting is, for example, a shooting condition at medium illuminance corresponding to ISO sensitivity 200 (medium sensitivity shooting mode) of film sensitivity, and the signal charge photoelectrically converted by the photodiode 60 is determined by the potential barrier below the transfer transistor. Only an amount is accumulated. For this reason, the signal charges accumulated in the photodiode 60 are converted from analog to digital, and the potential [3], which is an intermediate voltage, is set to, for example, -1 V which is 1 V higher than the potential [2].
  • the electric field applied to is suppressed, thereby suppressing the leakage current of the FD portion caused by GIDL.
  • the AD gain is 12 dB
  • the AD input range is a quarter of the default setting
  • the saturation output level of the photodiode 60 is a level at which analog-digital conversion cannot be performed.
  • This setting is a shooting condition at low illuminance corresponding to, for example, ISO sensitivity 400 (high sensitivity shooting mode) of film sensitivity
  • the amount of signal charge photoelectrically converted by the photodiode 60 is the above-described medium illuminance or high It is in a state that is less than at the time of illumination. Therefore, the AD gain is increased, the signal component is amplified, and analog-digital conversion is performed.
  • the signal charge amount of the photodiode 60 is smaller than that at the time of high illuminance or medium illuminance, the influence of the leakage current of the FD portion 66 appears to be relatively large. Therefore, by setting the potential [3], which is an intermediate voltage, to 0 V, for example, the leakage current of the FD unit 66 is suppressed, and the influence of noise on the image quality is suppressed even when a high gain is applied.
  • the solid-state imaging device 91 may not have the column amplifier circuit (CLAMP) 92 and each vertical signal line 39 may be connected to the CDS circuit 41.
  • CLAMP column amplifier circuit
  • the solid-state imaging device 91 is interlocked with the analog / digital conversion gain setting in the ADC circuit 42 based on the drive signal output from the TG 38 according to the plurality of drive mode signals corresponding to the plurality of imaging modes.
  • means for changing the potential [3] which is an intermediate potential of the transfer pulse of the transfer transistor for transferring the signal charge.
  • the target of gain setting is not limited to the AD gain, and for example, the gain of the column amplifier circuit (CLAMP) 92 may be controlled.
  • FIG. 19B shows a shooting mode (ISO), a gain value of the column amplifier circuit (CLAMP) 92, a CLAMP input range, and an intermediate voltage (potential [3]) of the transfer pulse (TR) in the modification of the present embodiment. A design example is shown. In the example shown in FIG. 19B, the value of the intermediate voltage (potential [3]) decreases as the ISO sensitivity of the film sensitivity increases (that is, the gain value of the column amplifier circuit (CLAMP) 92 increases). Is set to
  • the supply of the intermediate voltage (potential [3]) of the transfer pulse is not limited to the supply by the BIAS circuit 93 that generates the potential [3].
  • the vertical buffer shown in FIG. An intermediate voltage (potential [3]) may be supplied by control in the circuit.
  • solid-state imaging means for changing the intermediate voltage (potential [3]) of the transfer pulse to a predetermined value set for each imaging condition according to a plurality of imaging conditions set in advance. You may provide in the apparatus 91. FIG.
  • the transfer transistor when a transfer transistor is performing a read operation, the transfer transistor is driven using a ternary potential, while the transfer transistor performs a read operation. If not, the transfer transistor may be driven using a binary potential.
  • the solid-state imaging device of the first or second embodiment (including each modification example) is incorporated in, for example, a video camera capable of shooting a moving image or a digital still camera for shooting a still image. This is applied to a photographing apparatus such as a camera.
  • FIG. 20 is a block diagram showing a configuration of the photographing apparatus of the present embodiment.
  • the imaging device 140 includes a solid-state imaging device 141, an imaging optical system 142 that guides incident light from a subject to the solid-state imaging device 141, and a signal processing unit that processes an output signal from the solid-state imaging device 141. 143, a drive circuit 144 that drives the solid-state imaging device 141, and a system control unit 145 that controls the drive circuit 144.
  • the solid-state imaging device of the first or second embodiment (including the respective modifications) described above is used as the solid-state imaging device 141.
  • the drive circuit 144 receives a control signal corresponding to the drive mode from the system control unit 145, and supplies the drive mode signal to the solid-state imaging device 141.
  • the timing generation circuit (TG 38 in FIG. 1 or FIG. 14) generates a drive pulse corresponding to the drive mode signal to each block in the solid-state imaging device 141. Supply.
  • the signal processing unit 143 receives the image signal output from the solid-state imaging device 141 and performs various signal processing on the image signal.
  • the solid-state imaging apparatus according to the first or second embodiment (including each modification) described above is used. Therefore, in the solid-state imaging device, the influence of the leak current caused by GIDL on the pixel signal can be suppressed according to a plurality of drive modes, and thus the image quality of the captured image can be further improved.
  • the present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device using the solid-state imaging device as an imaging device.

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Abstract

Selon l'invention, des transistors de transfert sont mis en marche par application d'un premier potentiel, et une charge de signal est transférée vers une diffusion flottante. Les transistors de transfert sont mis à l'arrêt par application d'un second potentiel plus faible que le premier potentiel, et la charge de signal est accumulée et conservée dans un élément de conversion photoélectrique. Lorsqu'un troisième potentiel plus faible que le premier potentiel et plus élevé que le second potentiel, est appliqué à une électrode de grille d'un transistor de transfert, ce troisième potentiel est appliqué à l'électrode de grille d'un autre transistor connecté à la diffusion flottante.
PCT/JP2011/002034 2010-10-19 2011-04-06 Dispositif d'imagerie à semi-conducteurs, procédé d'entraînement de celui-ci, et dispositif d'imagerie WO2012053127A1 (fr)

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WO2018139187A1 (fr) * 2017-01-24 2018-08-02 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'images à semi-conducteurs, son procédé de commande et dispositif électronique
CN110445960A (zh) * 2018-05-02 2019-11-12 索尼半导体解决方案公司 固体摄像元件和摄像装置
CN110445960B (zh) * 2018-05-02 2023-08-18 索尼半导体解决方案公司 固体摄像元件和摄像装置
WO2020194615A1 (fr) * 2019-03-27 2020-10-01 パナソニックＩｐマネジメント株式会社 Dispositif d'imagerie à semi-conducteurs, dispositif de mesure de distance, et procédé de mesure de distance
JPWO2020194615A1 (fr) * 2019-03-27 2020-10-01
JP7203364B2 (ja) 2019-03-27 2023-01-13 パナソニックＩｐマネジメント株式会社 固体撮像装置、距離測定装置および距離測定方法

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