WO2012039073A1 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

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Publication number
WO2012039073A1
WO2012039073A1 PCT/JP2011/000348 JP2011000348W WO2012039073A1 WO 2012039073 A1 WO2012039073 A1 WO 2012039073A1 JP 2011000348 W JP2011000348 W JP 2011000348W WO 2012039073 A1 WO2012039073 A1 WO 2012039073A1
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WO
WIPO (PCT)
Prior art keywords
wiring
layer
semiconductor
substrate
rewiring
Prior art date
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PCT/JP2011/000348
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French (fr)
Japanese (ja)
Inventor
秀夫 中野
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パナソニック株式会社
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Publication of WO2012039073A1 publication Critical patent/WO2012039073A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device for switching a connection path between a plurality of input / output terminals using a semiconductor switch for a high frequency circuit of a portable terminal and a method for manufacturing the semiconductor device.
  • terminals that support 4 bands or 8 bands in the dual mode of GSM (Global System for Mobile Communication) standard or WCDMA (Wideband Code Division Multiple Access) standard have been developed.
  • Information communication technology such as WLAN (Wireless LAN), BT (Bluetooth), GPS (Global Positioning System), and DTV (Digital Television), and antenna diversity for improving communication quality and communication speed MIMO (Multiple Input Multiple Multiple Output) compatible terminals equipped with technology have also been developed.
  • MIMO Multiple Input Multiple Multiple Output
  • the current portable terminal is configured to select a destination circuit of the received signal using a semiconductor switch in order to allocate to the high frequency circuit corresponding to the received signal when the received signal is received by the antenna, and the antenna
  • a semiconductor device configured to transmit the transmission signal from a predetermined high-frequency circuit to the antenna via a semiconductor switch is mounted.
  • the current multi-mode multi-band portable terminal is equipped with a semiconductor device configured to switch a path between one to three antennas and a high-frequency circuit for 10 bands with a semiconductor switch. Yes.
  • a method of reducing the facing area of the intersecting wires by narrowing the wires or a method of increasing the distance between the intersecting wires is being studied.
  • a semiconductor device having a semiconductor switch In the former method of reducing the facing area of intersecting wirings, a semiconductor device having a semiconductor switch generally requires insertion loss of 1 dB or less, but is inserted as the wiring becomes thinner. Since there is a problem of increasing the loss, it is considered that the latter method of increasing the distance between the intersecting wires and reducing the capacitance between the wires is more effective.
  • one of the intersecting wires is formed on the surface of a mounting substrate on which a circuit pattern of a matrix switch composed of a plurality of SPDT (Single-Pole-Dual-Throw) switches is patterned. Further, it is disclosed that the other wiring is formed on the back surface of the mounting substrate and that a grounding surface is formed in a portion where each wiring is opposed to sandwich the mounting substrate to form a microstrip line structure.
  • SPDT Single-Pole-Dual-Throw
  • the number of input / output terminals of a high-frequency circuit for portable terminals and the number of semiconductor switches required to switch their connection paths tend to increase in the future.
  • patterning can be performed so as not to generate a location where the wiring connecting the input / output terminals and the semiconductor switch intersects. Such patterning is difficult.
  • the area of the mounting substrate must be increased, which increases the size and cost of the semiconductor device.
  • the present invention has been made in order to solve the above-described conventional problems, and even if a location where wirings electrically connecting the input / output terminal and the semiconductor switch cross each other occurs, the terminal
  • An object of the present invention is to provide a semiconductor device capable of reducing the size and cost while improving the isolation characteristics between the two.
  • a semiconductor device is alternately formed on a semiconductor substrate, a semiconductor switch circuit formed on the semiconductor substrate, and the semiconductor substrate on which the semiconductor switch circuit is formed.
  • a mold resin layer formed so as to cover the uppermost rewiring interlayer insulating film so that a plurality of input terminals and a plurality of output terminals connected to the rewiring layer are exposed, and the semiconductor switch Circuit
  • An arbitrary input terminal among the plurality of input terminals can be connected to an arbitrary output terminal among the plurality of output terminals via the wiring layer or the
  • a wiring connecting between the input terminal and a certain terminal of the plurality of output terminals and the semiconductor switch circuit, the other terminal of the plurality of input terminals and the plurality of output terminals, and the semiconductor switch circuit Between the wirings connected to each other when viewed from the thickness direction of the semiconductor substrate, one of the intersecting wirings is constituted by the wiring layer, and the other wiring is the rewiring layer It is made up of.
  • one wiring may be configured by the wiring layer, and the other wiring may be configured by the rewiring layer.
  • a wiring connecting between the output terminal and the semiconductor switch circuit and a wiring connecting the other output terminal and the semiconductor switch circuit are formed from the thickness direction of the semiconductor substrate.
  • one of the interconnects may be the interconnect layer, and the other interconnect may be the redistribution layer.
  • a wiring connecting between the certain input terminal and the semiconductor switch circuit and a wiring connecting between the certain output terminal and the semiconductor switch circuit are seen from the thickness direction of the semiconductor substrate.
  • one of the intersecting wirings may be configured by the wiring layer, and the other wiring may be configured by the rewiring layer.
  • the separation distance between the wiring layer in the semiconductor chip and the rewiring layer in the wafer CSP process is much longer than the wiring interlayer distance formed in the semiconductor chip having the multilayer wiring structure. For this reason, it is possible to suppress the capacitance between the wirings, and it is possible to suppress the deterioration of isolation due to the leakage of signals between the terminals via the wiring capacitance.
  • a pad for connecting the wiring layer formed in the semiconductor chip and the rewiring layer for the wafer CSP process is formed.
  • the pad diameter may be smaller than the bonding pad to which the bonding wire is connected, and the pad can be formed on an element formed on the semiconductor substrate. For this reason, even if it is necessary to form a large number of pads due to an increase in the number of input / output terminals, there is no need to increase the area of the semiconductor substrate. For this reason, the cost and size of the semiconductor device can be suppressed.
  • the semiconductor device capable of suppressing the size and cost while improving the isolation characteristics between the terminals even when the wirings that electrically connect the input / output terminals and the semiconductor switch occur. Can be provided.
  • a plurality of the rewiring layers may be formed, and the other wiring may be the uppermost rewiring layer of the plurality of rewiring layers.
  • the separation distance between the intersecting wiring layer and the rewiring layer can be further increased.
  • the capacitance between the wirings can be further reduced, and the deterioration of isolation can be more reliably suppressed.
  • the semiconductor substrate may be an SOI (Silicon On Insulator) substrate.
  • the semiconductor substrate may be an SOS (Silicon On Sapphire) substrate.
  • the sapphire substrate resistance of the sapphire substrate that is the foundation of the SOS substrate is very large, signals are not easily leaked to each capacitor of other MOS transistors through the sapphire substrate resistance, and formed on the sapphire substrate.
  • the isolation characteristics of the MOS transistors constituting the semiconductor switch circuit thus made are improved.
  • a substrate contact is usually formed in the outer peripheral region of the element, and the substrate contact is connected to a ground or a power source in order to increase the capacitance and isolation between transistor elements. Measures have been implemented to provide a dedicated pad.
  • another method of manufacturing a semiconductor device includes a plurality of input terminals, a plurality of output terminals, and an arbitrary input terminal of the plurality of input terminals.
  • a semiconductor switch circuit configured to be connected to an arbitrary output terminal, and a step of forming the semiconductor switch circuit on the semiconductor substrate; and the semiconductor switch circuit is formed.
  • one wiring is comprised by the said wiring layer
  • the other wiring is comprised by the said rewiring layer.
  • the size and cost can be suppressed while improving the isolation characteristics between the terminals even when the wiring that electrically connects the input / output terminals and the semiconductor switch occurs.
  • a possible semiconductor device can be provided.
  • the size and cost can be suppressed while improving the isolation characteristics between the terminals even when the wirings that electrically connect the input / output terminals and the semiconductor switch cross each other.
  • a semiconductor device and a method for manufacturing the same can be provided.
  • FIG. 1 is a circuit configuration diagram of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along line C-C ′ of the semiconductor device shown in FIG.
  • FIG. 3 is a circuit configuration diagram of the semiconductor switch according to the first embodiment of the present invention.
  • FIG. 4 is a circuit configuration diagram of the semiconductor switch according to the first embodiment of the present invention.
  • FIG. 5 is a circuit configuration diagram of a modification of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a circuit configuration diagram of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view taken along the section line D-D ′ of the semiconductor device shown in FIG. 6.
  • FIG. 8 is a circuit configuration diagram of a modification of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is a circuit configuration diagram of a semiconductor device according to the third embodiment of the present invention.
  • FIG. 10 is a cross-sectional view taken along line E-E ′ of the semiconductor device shown in FIG. 9.
  • FIG. 11 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the semiconductor device shown in FIG. 11 taken along section line A-A ′.
  • FIG. 13 is a circuit configuration diagram of a semiconductor device exemplified as another comparative example of the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view taken along line B-B ′ of the semiconductor device shown in FIG.
  • FIG. 15 is a circuit configuration diagram of the semiconductor SPDT switch shown in FIG.
  • FIG. 16 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the second embodiment of the present invention.
  • FIG. 17 is a diagram showing the structure of the MOS transistor constituting the semiconductor switch shown in FIG.
  • FIG. 18 is a diagram showing the structure of a MOS transistor constituting the semiconductor switch according to the second embodiment of the present invention.
  • FIG. 1 is a circuit configuration diagram of a semiconductor device according to the first embodiment of the present invention.
  • 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the section line CC ′.
  • the semiconductor device shown in FIG. 1 includes a first input terminal 31, a second input terminal 32, a first output terminal 41, a second output terminal 42, a third output terminal 43, a fourth output terminal 44, And a semiconductor switch circuit 20 including eight semiconductor switches 21 to 28 corresponding to eight patterns of input / output paths.
  • the semiconductor switch circuit 20 is configured to selectively connect any one of the first and second input terminals 31 and 32 to any one of the first to fourth output terminals 41 to 44. It is configured.
  • the semiconductor device shown in FIG. 1 is a semiconductor package manufactured by a wafer level CSP (ChipCSize Package) process.
  • a first rewiring layer 251 is formed on the surface of the chip 1.
  • the chip 1 includes a semiconductor substrate 10, first to third interlayer insulating films 11 to 13, a protective film 14, and a pad 60.
  • the wafer level CSP process is a manufacturing method in which packaging is performed in a semiconductor wafer state before dicing into individual semiconductor chips in a semiconductor device manufacturing process.
  • the wafer level CSP process it is possible to form all the structures necessary for conventional packaging all over the semiconductor wafer, including the formation of external terminals by solder bumps. By dicing the semiconductor wafer, a packaged semiconductor device can be obtained.
  • the semiconductor substrate 10 is configured by an SOI (Silicon On Insulator) substrate configured by inserting a SiO 2 layer between a silicon substrate and a surface silicon layer.
  • SOI Silicon On Insulator
  • the SOI substrate can suppress the parasitic capacitance of a transistor formed there, and is effective in improving operation speed and reducing power consumption.
  • the first input terminal 31 is connected to the semiconductor switch 21 via the first rewiring layer 251, the first rewiring layer pad 261, the second wiring layer 52, the first via 54, and the first wiring layer 51. , 23, 25, 27.
  • the semiconductor switches 21, 23, 25, and 27 include the first wiring layer 51, the first via 54, the second wiring layer 52, the first rewiring layer pad 261, and the first rewiring layer 251.
  • the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 are connected.
  • the second input terminal 32 is connected to the semiconductor switch 22 via the first rewiring layer 251, the first rewiring layer pad 261, the second wiring layer 52, the first via 54, and the first wiring layer 51. , 24, 26, 28.
  • the semiconductor switches 22, 24, 26, and 28 include the first wiring layer 51, the first via 54, the second wiring layer 52, the first rewiring layer pad 261, and the first rewiring layer 251.
  • the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 are connected.
  • the semiconductor switches 21 to 28 are formed on the semiconductor substrate 10 so as to be covered with the first interlayer insulating film 11 and are connected to the first wiring layer 51 through contacts.
  • the semiconductor switches 21 to 28 are configured, for example, as shown in FIG. 3 or FIG.
  • n is a natural number
  • MOS transistors M1 to Mn are connected in series at each drain terminal and source terminal to form a current path.
  • the gate terminals of the MOS transistors M1 to Mn are connected to the control voltage terminal via a resistor, and the control voltage Vb + is applied to the control voltage terminal.
  • MOS transistors Mn + 1 to Mn + k are connected in series at each drain terminal and source terminal to form a current path, and the MOS transistor
  • Each gate terminal of Mn + 1 to Mn + k is connected to a control voltage terminal through a resistor, and a control voltage Vb ⁇ is applied to the control terminal.
  • the control voltage Vb + and the control voltage Vb ⁇ are generally given two values corresponding to logic signals HIGH and LOW, and are set to logic values opposite to each other.
  • Vb + is 3V
  • Vb ⁇ is 0V
  • Vb + is 3V
  • Vb + is 3V
  • Vb ⁇ is ⁇ 3V
  • a control voltage in which the polarity of the voltage is inverted is given such that ⁇ is 3V.
  • This control voltage is set to an appropriate voltage depending on the characteristics of the threshold voltage depending on the manufacturing process of the MOS transistor.
  • the input port 2 and the output port 3 are electrically connected (ON), and control is performed.
  • an arbitrary negative voltage to the voltage Vb + and an arbitrary positive voltage to the control voltage Vb ⁇ the input port 2 and the output port 3 are disconnected (OFF) and the input port 2 is connected to the ground.
  • the semiconductor switches 21 to 28 By configuring the semiconductor switches 21 to 28 in this way, the paths for connecting the first input terminal 31 and the second input terminal 32 to different output terminals among the first to fourth output terminals 41 to 44 are selected. it can. For example, when the semiconductor switches 22 and 23 are turned on (conductive) and the other semiconductor switches 21 and 24 to 28 are turned off (cut off), the first input terminal 31 and the second output terminal 42 are connected. In addition, the second input terminal 32 and the first output terminal 41 are connected.
  • the first rewiring layer 251 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 23, and the first wiring layer is used for the wiring connecting the second input terminal 32 and the semiconductor switch 22. 51 is used.
  • the first rewiring layer 251 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 25, and the first wiring layer is used for the wiring connecting the second input terminal 32 and the semiconductor switch 24. 51 is used.
  • the first wiring layer 51 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 27, and the first rewiring layer 251 is used for the wiring connecting the second input terminal 32 and the semiconductor switch 26. Is used.
  • the semiconductor device shown in FIG. 1 includes wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20, and wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20. Are crossed when viewed from the thickness direction of the semiconductor substrate 10, the first rewiring layer 251 is used for one wiring, and the first wiring layer 51 is used for the other wiring. .
  • the semiconductor device shown in FIG. 1 has wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20, and from the second input terminal 32 toward the semiconductor switch circuit 20.
  • the first wiring layer 51 and the first rewiring layer 251 are formed to face each other in a cross-sectional view at a location where the extended wiring intersects with the thickness direction of the semiconductor substrate 10.
  • the semiconductor device shown in FIG. 1 includes a semiconductor substrate 10 having an element region in which a circuit pattern of the semiconductor switch circuit 20 is formed, and a first interlayer insulating film 11 formed so as to cover the semiconductor substrate 10.
  • a second via 55 filling the via hole; a pad 60 formed on the second via 55; a protective film 14 formed so as to cover the pad 60 and having an opening exposing the surface of the pad 60; It has.
  • the interlayer insulating films (11, 12, 13) and the wiring layers (51, 52) are alternately formed on the semiconductor substrate 10.
  • the second wiring layer 52 penetrates through the second interlayer insulating film 12 to the first wiring layer 51, and the second wiring layer 52 and the first wiring layer 51 are connected to each other.
  • a first via 54 is formed to fill the formed via hole.
  • the first wiring layer 51 is connected to the input port 2 and the output port 3 of each of the semiconductor switches 21 to 28 formed in the element region on the semiconductor substrate 10.
  • the semiconductor device shown in FIG. 1 includes a protective film 14 and a first rewiring interlayer insulating film 111 formed so as to cover the pad 60 exposed in the opening formed in the protective film 14 and a first rewiring interlayer.
  • a rewiring layer via 254 that fills the via hole formed so as to penetrate the insulating film 111 and reach the pad 60, a first rewiring layer pad 261 formed on the rewiring layer via 254, and a first rewiring layer
  • a second rewiring interlayer insulating film 112 formed so as to cover and a mold resin layer 110 formed so as to seal the entire semiconductor device are provided.
  • the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112.
  • the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112, and vias penetrating the second redistribution interlayer insulating film 112 are formed.
  • a pad exposed to an opening formed in the mold resin layer 110 and a solder bump formed on the pad are formed.
  • the rewiring interlayer insulating films (111, 112) and the rewiring layer (251) are alternately formed on the protective film 14 and the pad 60 of the semiconductor chip.
  • the thickness is about 1 ( ⁇ m) in the direction from the first wiring layer 51 to the first rewiring layer 251.
  • a semiconductor substrate 10 is formed by forming a SiO 2 layer and a surface silicon layer in this order on a silicon substrate by CVD (Chemical Vapor Deposition) or the like. Thereby, an SOI substrate is formed.
  • CVD Chemical Vapor Deposition
  • the semiconductor switch circuit 20 is formed in the element region of the semiconductor substrate 10 by film deposition by sputtering, CVD, etc., and patterning of the film by photolithography and etching.
  • an interlayer insulating film (11, 12, 13) and a wiring layer (51) are formed on the semiconductor substrate 10 on which the semiconductor switch circuit 20 is formed by film deposition by CVD, sputtering, etc., and patterning of the film by photolithography and etching. , 52) are alternately formed.
  • the first via 54 that connects the second wiring layer 52 and the first wiring layer 51 is formed.
  • a pad 60 is formed on the third interlayer insulating film 13 in the uppermost layer by sputtering or the like so as to be connected to the second wiring layer 52.
  • the second via 55 that connects the pad 60 and the second wiring layer 52 is formed.
  • the protective film 14 is formed so as to cover the third interlayer insulating film 13 in the uppermost layer so that the pad 60 is exposed to the outside by CVD or the like.
  • the rewiring interlayer insulating films (111, 112) and the first rewiring layer 251 are alternately formed on the protective film 14 by film deposition by CVD, sputtering, etc. and film patterning by photolithography and etching.
  • the first redistribution layer pad 261 is formed on the first redistribution interlayer insulating film 111 and the first redistribution layer pad 261 and the pad 60 on the protective film 14 are connected to each other.
  • a first redistribution layer via 254 is formed.
  • first and second input terminals 31 and 32 and first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112 by film deposition by sputtering and film patterning by photolithography and etching.
  • a pad to be formed is formed.
  • a via that connects this pad and the first redistribution layer 251 is formed.
  • the uppermost second redistribution interlayer insulating film 112 is so exposed that the pads constituting the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are exposed by CVD or the like.
  • a mold resin layer 110 is formed so as to cover the surface.
  • a semiconductor device group of the wafer level CSP process is formed on the SOI substrate.
  • solder bumps are formed on the pads constituting the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 exposed from the mold resin layer 110, and then the individual semiconductor devices are diced.
  • a packaged semiconductor device can be obtained.
  • a connection between one of the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 is made by photolithography, etching, or the like.
  • one of the intersecting wirings is the first wiring.
  • the wiring layer 51 is used, and the first rewiring layer 251 is used for the other wiring.
  • FIG. 11 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the semiconductor device shown in FIG. 11 taken along section line AA ′.
  • the semiconductor device shown in FIG. 11 is provided with a two-input four-output type semiconductor switch circuit 20 including semiconductor switches 21 to 28, and between the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20. There is no crossing between the wirings to be connected when viewed from the thickness direction of the semiconductor substrate 10, but there are wirings extending from the first input terminal 31 toward the semiconductor switch circuit 20 and from the second input terminal 32 to the semiconductor.
  • one wiring is a wiring formed on the semiconductor substrate 10 and the other wiring is a bonding wire.
  • the semiconductor device shown in FIG. 11 includes, on a semiconductor substrate 10, first and second input terminals 31, 32, first to fourth output terminals 41 to 44, and eight semiconductor switches 21 to 28.
  • the semiconductor switch circuit 20 and six bonding pads 61 to 66 are provided.
  • the first input terminal 31 is connected to any one of the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 by controlling the semiconductor switch circuit 20. It is comprised so that.
  • the second input terminal 32 is any one of the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 by controlling the semiconductor switch circuit 20. Are connected to each other.
  • the first input terminal 31 and the semiconductor switches 21 and 23 are connected by the first wiring layer 51 via the bonding pad 61 and the bonding pad 63 or 64.
  • the bonding pad 63 and the bonding pad 64 are connected via a bonding wire 72.
  • the first wiring layer 51 connected to the second input terminal 32 intersects with the bonding wire 72 connecting the bonding pads 63 and 64 as viewed from the thickness direction of the semiconductor substrate 10.
  • the semiconductor device shown in FIG. 11 is formed on the semiconductor substrate 10, the first interlayer insulating film 11 formed so as to cover the semiconductor substrate 10, and the first interlayer insulating film 11.
  • the first wiring layer 51 formed, the second interlayer insulating film 12 formed so as to cover the first wiring layer 51, and the first wiring layer 51 are formed so as to penetrate the second interlayer insulating film 12.
  • the second via 55 that fills the via hole formed so as to penetrate the film 13 and reach the second wiring layer 52, the bonding pads 63 to 66 formed on the second via 55, and the bonding pads 63 to 66 are covered.
  • the bonding pads 63 and 64 exposed from the protective film 14 are connected to each other via bonding wires 72, and the bonding pads 65 and 66 exposed from the protective film 14 are connected to each other via bonding wires 73.
  • one of the intersecting wirings is composed of the first wiring layer 51 and the other wiring is composed of the bonding wires 71 to 73, so that they intersect. Since the separation distance between the wirings can be made longer, the capacitance between the wirings can be reduced and the isolation characteristics can be improved.
  • FIG. 13 is a circuit configuration diagram of a semiconductor device exemplified as another comparative example of the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of the semiconductor device shown in FIG. 13 taken along section line BB ′.
  • the semiconductor device shown in FIG. 13 includes a two-input four-output type semiconductor SPDT switch circuit 120 including semiconductor SPDT (single pole dual pole) switches 121 to 124 on a mounting board 100 such as a module board or a printed wiring board. Yes.
  • MOS transistors M1 to Mn are connected in series at each drain terminal and source terminal to form a current path, and each gate terminal of the MOS transistors M1 to Mn is a control voltage to which a control voltage Vb + is applied via a resistor. Connected to the terminal.
  • k is a natural number
  • MOS transistors Mn + 1 to Mn + k are connected in series at each drain terminal and source terminal.
  • each gate terminal of the MOS transistors Mn + 1 to Mn + k is connected via a resistor to a control voltage terminal to which the control voltage Vb ⁇ is applied.
  • appropriate control voltages Vb + and Vb ⁇ are applied to the control voltage terminal for controlling the MOS transistors M1 to Mn and the control voltage terminal for controlling the MOS transistors Mn + 1 to Mn + k, respectively.
  • a path for connecting the terminal 31 and the second input terminal 32 to different output terminals among the first to fourth output terminals 41 to 44 can be selected.
  • wiring that connects the first input terminal 31 and the semiconductor SPDT switch group 120 and wiring that connects the second input terminal 32 and the semiconductor SPDT switch group 120 are mounted. Intersections occur when viewed from the thickness direction of the substrate 100. A portion surrounded by a broken-line ellipse shown in FIGS. 13 and 14 represents the intersecting portion.
  • one wiring is a first substrate wiring layer 151 formed on the semiconductor substrate 10
  • the other wiring is a second substrate wiring layer 152 formed on the semiconductor substrate 10. That is, the first substrate wiring layer 151 and the second substrate wiring layer 152 intersect when viewed from the thickness direction of the mounting substrate 100.
  • the first substrate wiring layer 151 is formed on one plane of the mounting substrate 100 and the second plane of the mounting substrate 100 is second as shown in FIG.
  • a substrate wiring layer 152 is formed.
  • a substrate via 154 that fills a via hole penetrating the mounting substrate 100 is formed at a location where the first substrate wiring layer 151 and the second substrate wiring layer 152 are connected.
  • a mold resin layer 110 for sealing the mounting substrate 100 is formed so as to cover the first substrate wiring layer 151 and the second substrate wiring layer 152 formed on both planes of the mounting substrate 100.
  • the separation distance between the first substrate wiring layer 151 and the second substrate wiring layer 152 that intersect with each other is a distance corresponding to the thickness (wiring layer) of the mounting substrate 100.
  • the distance between wiring layers formed on the semiconductor substrate 10 is about 1 ( ⁇ m), whereas the thickness of the mounting substrate 100 is about 0.1 to 0.2 (mm). The interspace capacity is reduced, and the isolation characteristics can be improved.
  • the wiring interlayer distance between the first wiring layer 51 and the second wiring layer 52 formed on the normal semiconductor substrate 10 is about 1 ( ⁇ m)
  • the separation distance between the one wiring layer 51 and the first rewiring layer 251 is about 10 ( ⁇ m), which is about 10 times the distance between the wiring layers on the semiconductor substrate 10.
  • the second wiring layer 52 formed on the semiconductor substrate 10 and the first redistribution layer of the wafer CSP process are formed as in Comparative Example 1.
  • a pad 60 for connecting to H.251 is formed.
  • the pad 60 has a diameter of about 30 ( ⁇ m) and can be connected to the first rewiring layer via 254, and the pad 60 can be formed on an element formed on the semiconductor substrate 10. For this reason, even if it is necessary to form a large number of pads 60, there is no need to increase the area of the semiconductor substrate 10, so that the size and cost of the semiconductor device can be suppressed.
  • FIG. 5 is a circuit configuration diagram of a modification of the semiconductor device according to the first embodiment of the present invention.
  • the difference from the above embodiment is that the wirings connecting the first input terminal 31 and the second input terminal 32 and the semiconductor switch circuit 20 do not intersect each other when viewed from the thickness direction of the semiconductor substrate 10.
  • the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the semiconductor substrate 10.
  • a portion surrounded by a broken-line ellipse shown in FIG. 5 represents this intersecting portion.
  • the first wiring layer 51 which is part of the wiring that connects the first output terminal 41 and the semiconductor switch 25, is a wiring that connects the second output terminal 42 and the semiconductor switch 22.
  • the first redistribution layer 251 which is a part, the first redistribution layer 251 which is a part of the wiring connecting the third output terminal 43 and the semiconductor switch 23, the fourth output terminal 44 and the semiconductor switch 24 And the first rewiring layer 251 that is a part of the wiring connecting the two.
  • the first wiring layer 51 which is a part of the wiring that connects the second output terminal 42 and the semiconductor switch 26, is a part of the wiring that connects the third output terminal 43 and the semiconductor switch 23.
  • the first redistribution layer 251 intersects with the first redistribution layer 251 which is a part of the wiring connecting the fourth output terminal 44 and the semiconductor switch 24.
  • the first wiring layer 51 which is a part of wiring that connects the third output terminal 43 and the semiconductor switch 27, is a part of wiring that connects the fourth output terminal 44 and the semiconductor switch 24. 1 crosses the rewiring layer 251.
  • the first wiring is connected to the first wiring.
  • the rewiring layer 251 may be used, and the first wiring layer 51 may be used for the other wiring. Also with this structure, the same effect as in the first embodiment can be obtained.
  • FIG. 6 is a circuit configuration diagram of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of the semiconductor device shown in FIG.
  • a difference from the first embodiment is that an SOS (Silicon On Sapphire) substrate in which a silicon-based semiconductor layer is formed on an insulating sapphire substrate 336 is used instead of the semiconductor substrate 10. .
  • SOS Silicon On Sapphire
  • the semiconductor switches 21 to 28 are configured as shown in FIG. 3 or FIG.
  • a wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20 and a wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20 are sapphire. The same applies to the point where the first rewiring layer 251 is used for one wiring and the first wiring layer 51 is used for the other wiring at a location intersecting when viewed from the thickness direction of the substrate 336.
  • the semiconductor device shown in FIG. 6 includes a sapphire substrate 336, a barrier SiO 2 334 formed so as to cover the sapphire substrate 336, and a surface silicon layer 313 formed on the barrier SiO 2 334.
  • a semiconductor substrate is used.
  • the first interlayer insulating film 11 formed so as to cover the surface silicon layer 313 on the sapphire substrate 336, the first wiring layer 51 formed on the first interlayer insulating film 11, and the first wiring layer 51
  • Second interlayer insulating film 12 formed to cover, second wiring layer 52 formed on second interlayer insulating film 12, and third interlayer insulating film 13 formed to cover second wiring layer 52
  • a second via 55 that fills the via hole formed so as to penetrate the third interlayer insulating film 13 and reach the second wiring layer 52, a pad 60 formed on the second via 55, and the pad 60.
  • a protective film 14 formed with an opening that exposes the surface of the pad 60. Although not shown in FIG. 7, it penetrates through the second interlayer insulating film 12 to the first wiring layer 51 and connects the second wiring layer 52 and the first wiring layer 51.
  • a first via 54 that fills the formed via hole is formed.
  • the semiconductor device shown in FIG. 6 penetrates the first redistribution interlayer insulating film 111 formed so as to cover the protective film 14 and the pad 60 exposed from the protective film 14, and the first redistribution interlayer insulating film 111.
  • the rewiring layer via 254 filling the via hole formed to reach the pad 60, the first rewiring layer pad 261 formed on the rewiring layer via 254, and the first rewiring interlayer insulating film 111
  • the first redistribution layer 251 formed to connect the adjacent first redistribution layer pads 261, and the first redistribution layer pad 261 and the first redistribution layer 251 are formed to be covered.
  • a second redistribution interlayer insulating film 112 and a mold resin layer 110 formed so as to seal the entire semiconductor device.
  • the thickness is about 1 ( ⁇ m) in the direction from the first wiring layer 51 to the first rewiring layer 251.
  • a barrier SiO 2 334 is formed so as to cover the sapphire substrate 336
  • a field oxide film 335 is formed on the barrier SiO 2 334
  • the surface silicon layer 313 and the well region of the field oxide film 335 are formed.
  • N-type diffusion regions 311 are formed on both sides thereof.
  • a source terminal 302 and a drain terminal 303 are taken out from each N-type diffusion region 311.
  • a gate oxide film 301 is formed on the surface silicon layer 313, and the gate terminal 300 is taken out from the gate electrode formed on the gate oxide film 301.
  • a gate-substrate capacitance Cgb is generated between the surface silicon layer 313 and the sapphire substrate 336 and between the two N-type diffusion regions 311 and the sapphire substrate 336.
  • a capacitance Cdsub is generated between the surface silicon layer 313 and the sapphire substrate 336 and between the two N-type diffusion regions 311 and the sapphire substrate 336.
  • a difference from the first embodiment is that an SOS substrate is used as a semiconductor substrate. After a barrier SiO 2 334 is formed on a sapphire substrate 336 by CVD or the like, this barrier SiO 2 is first formed. A surface silicon layer 313 is formed on 334. The subsequent processes are the same as those in the first embodiment.
  • FIG. 16 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the second embodiment of the present invention.
  • the semiconductor device shown in FIG. 16 is formed by removing the gate oxide film on the outer periphery of the semiconductor switches 21, 23, 25, and 27 connected to the first input terminal 31 in addition to the circuit configuration shown in FIG.
  • Semiconductor switches 22, 24 connected to the substrate contacts 271, P-type substrate terminals 281 connected to the substrate contacts 271, and connected to the ground outside the package, and the second input terminal 32.
  • 26, 28, and a substrate contact 272 formed by removing the gate oxide film on the outer periphery, and a P-type substrate terminal connected to each substrate contact 272 and connecting each substrate contact 272 to the ground outside the package 282.
  • FIG. 17 is a diagram showing the structure of the MOS transistors constituting the semiconductor switches 21 to 28 shown in FIG.
  • a field oxide film 335 is formed in a predetermined region on the semiconductor substrate 10, and an N-type diffusion region 311 is formed in the well region of the field oxide film 335.
  • a source terminal 302 and a drain terminal 303 are taken out from each N-type diffusion region 311.
  • a gate oxide film 301 is formed on the region between the N-type diffusion regions 311, and the gate terminal 300 is taken out from the gate electrode formed on the gate oxide film 301.
  • a gate-substrate capacitance Cgb between the gate oxide film 301 and the semiconductor substrate 10 and between the two N-type diffusion regions 311 and the semiconductor substrate 10, a gate-substrate capacitance Cgb, a source-substrate capacitance Csb, and a drain-substrate interval, respectively.
  • a capacitance Cdb is generated. Since these capacitors Cgb, Csb, and Cdb are connected to the capacitors Cgb, Csb, and Cdb of other MOS transistors (not shown) through the P-type substrate resistor 315, the isolation between the MOS transistors Mj is deteriorated.
  • the substrate contacts 271 and 272 are provided on the semiconductor substrate 10, and the substrate contacts 271 and 272 are connected to the ground or the like.
  • P-type substrate terminals 281 and 282 for reducing the impedance of the P-type substrate resistor 315 are provided.
  • substrate contacts 271 and 272 are provided on the outer periphery of the semiconductor switches 21 to 28, and these are connected to an external ground.
  • P-type substrate terminals 281 and 282 are provided for lowering the impedance of the substrate.
  • CSP since the number of terminals that can be mounted depends on the chip size, it is important to reduce the number of external terminals as much as possible. Therefore, when the P-type substrate terminals 281 and 282 are provided, extra terminals that do not transmit and receive signals are provided, which increases the size and cost of the semiconductor device.
  • the sapphire substrate resistance 333 of the sapphire substrate 336 shown in FIG. 18 is as large as 1 ⁇ 10 12 ( ⁇ cm), each MOS transistor is connected via the sapphire substrate resistance 333. Input signals are not easily leaked toward the capacitors Cgb, Csb, and Cdb, and the isolation between the MOS transistors Mj formed on the sapphire substrate 336 is very high. Therefore, unlike the comparative example 3, it is not necessary to provide the substrate contacts 271 and 272 and the P-type substrate terminals 281 and 282. As described above, the use of the sapphire substrate 336 can reduce the size and cost of the semiconductor device.
  • FIG. 8 is a circuit configuration diagram of a modification of the semiconductor device according to the second embodiment of the present invention.
  • the difference from the above embodiment is that the wirings connecting the first input terminal 31 and the second input terminal 32 and the semiconductor switch circuit 20 do not intersect with each other, but the first to fourth output terminals 41. That is, the wirings connecting between .about.44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the sapphire substrate 336.
  • FIG. A portion surrounded by a broken-line ellipse shown in FIG. 8 represents this intersecting portion.
  • the first wiring layer 51 which is part of the wiring that connects the first output terminal 41 and the semiconductor switch 25, is a wiring that connects the second output terminal 42 and the semiconductor switch 22.
  • the first redistribution layer 251 which is a part, the first redistribution layer 251 which is a part of the wiring connecting the third output terminal 43 and the semiconductor switch 23, the fourth output terminal 44 and the semiconductor switch 24 And the first rewiring layer 251 that is a part of the wiring connecting the two.
  • the first wiring layer 51 which is a part of the wiring that connects the second output terminal 42 and the semiconductor switch 26, is a part of the wiring that connects the third output terminal 43 and the semiconductor switch 23.
  • the first redistribution layer 251 intersects with the first redistribution layer 251 which is a part of the wiring connecting the fourth output terminal 44 and the semiconductor switch 24.
  • the first wiring layer 51 which is a part of wiring that connects the third output terminal 43 and the semiconductor switch 27, is a part of wiring that connects the fourth output terminal 44 and the semiconductor switch 24. 1 crosses the rewiring layer 251.
  • the first wiring is connected to one wiring.
  • the rewiring layer 251 may be used, and the first wiring layer 51 may be used for the other wiring.
  • a wiring for connecting between an input terminal of the first and second input terminals 31 and 32 and the semiconductor switch circuit 20, and an output terminal of the first to fourth output terminals 41 to 44 and the semiconductor switch circuit The first redistribution layer 251 is used for one of the intersecting wirings and the other wiring is connected to the wiring connecting the wirings 20 to each other when viewed from the thickness direction of the sapphire substrate 336.
  • the first wiring layer 51 may be used.
  • FIG. 9 is a circuit configuration diagram of a semiconductor device according to the third embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of the semiconductor device shown in FIG. 9 taken along section line EE ′.
  • the difference from the first embodiment of the present invention is that an SOS in which a silicon-based semiconductor layer is formed on an insulating sapphire substrate 336 instead of the semiconductor substrate 10 is the same as the second embodiment.
  • the (Silicon On Sapphire) substrate is used.
  • the redistribution layer formed by the wafer level CSP process has a two-layer structure.
  • the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 do not intersect with each other, but the first input terminal 31 and the second input terminal
  • a portion surrounded by a broken-line ellipse shown in FIGS. 9 and 10 represents the intersecting portion.
  • the second rewiring layer 252 that is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 23 is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 22. Crosses the first wiring layer 51.
  • the second rewiring layer 252 that is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 25 is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 24. Crosses the first wiring layer 51.
  • the first wiring layer 51 which is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 27, is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 26. 2 intersects with the rewiring layer 252.
  • the wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20 and the wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20 are formed from the thickness direction of the sapphire substrate 336.
  • the second rewiring layer 252 is used for one wiring
  • the first wiring layer 51 is used for the other wiring.
  • the semiconductor device includes a sapphire substrate 336, a barrier SiO 2 334 formed so as to cover the sapphire substrate 336, and a surface silicon layer 313 formed on the barrier SiO 2 334.
  • substrate provided with these is used.
  • the first interlayer insulating film 11 formed so as to cover the surface silicon layer 313 on the sapphire substrate 336, the first wiring layer 51 formed on the first interlayer insulating film 11, and the first wiring layer 51
  • Second interlayer insulating film 12 formed to cover, second wiring layer 52 formed on second interlayer insulating film 12, and third interlayer insulating film 13 formed to cover second wiring layer 52
  • a protective film 14 formed so as to cover the third interlayer insulating film 13.
  • the semiconductor device includes a first redistribution interlayer insulating film 111 formed so as to cover the protective film 14, and a first redistribution interlayer insulating film 111 formed on the first redistribution interlayer insulating film 111.
  • the wiring layer pad 261, the second rewiring layer insulating film 112 formed so as to cover the first rewiring layer insulating film 111 and the first rewiring layer pad 261, and the second rewiring layer insulating film 112 are penetrated.
  • a second redistribution layer via 255 filling the via hole formed to reach the first redistribution layer pad 261, a second redistribution layer pad 262 formed on the second redistribution layer via 255, A second redistribution layer 252 formed on the redistribution interlayer insulating film 112 and connected to the adjacent second redistribution layer pad 262, the second redistribution layer pad 262, and the second redistribution layer Third redistribution formed to cover layer 252 An interlayer insulating film 113, and a mold resin layer 110 formed so as to hermetically seal the entire semiconductor device.
  • the thickness is about 1 ( ⁇ m) in the direction from the first wiring layer 51 to the second rewiring layer 252.
  • the second interlayer insulating film 12 and the third interlayer insulating film 13, the protective film 14 having a thickness of about 3 ( ⁇ m), the first rewiring interlayer insulating film 111 having a thickness of about 5 ( ⁇ m), and the first Two rewiring interlayer insulating films 112 are formed in this order.
  • the rewiring layer formed by the wafer level CSP process has a two-layer structure, and the second rewiring layer is formed on the second rewiring interlayer insulating film 112.
  • the third redistribution layer insulating film 112 is covered on the second redistribution interlayer insulating film 112 so as to cover the second redistribution layer pad 262 and the second redistribution layer 252 by CVD or the like.
  • a rewiring interlayer insulating film 113 is formed, and a mold resin layer 110 is formed on the third rewiring interlayer insulating film 113.
  • the separation distance between the first wiring layer 51 and the second rewiring layer 252 is about 15 ( ⁇ m), and the first wiring layer 51 and the first rewiring layer 251 in the case of the second embodiment. It is about 5 ( ⁇ m) longer than the separation distance. For this reason, the inter-wiring capacity can be made smaller than in the second embodiment, and the deterioration of isolation due to the leakage of signals to each other through the inter-wiring capacity can be more reliably suppressed.
  • Wirings connecting one output terminal of the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 and wiring connecting another output terminal and the semiconductor switch circuit 20 are sapphire substrates.
  • the second rewiring layer 252 may be used for one of the intersecting wirings
  • the first wiring layer 51 may be used for the other wiring.
  • the second redistribution layer 252 is used for one of the intersecting wirings and the first wiring for the other wiring at a location where the wirings connecting the two intersect with each other as viewed from the thickness direction of the sapphire substrate 336.
  • the wiring layer 51 may be used.
  • the SOS substrate may be configured by forming the surface silicon layer 313 directly on the sapphire substrate 336 without providing the barrier SiO 2 334.
  • the present invention is useful for a semiconductor device in which a connection path between a plurality of input / output terminals is switched by a semiconductor switch for a high-frequency circuit of a portable terminal.

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Abstract

A semiconductor switching circuit (20) is configured so as to have an arbitrary input terminal from among a plurality of input terminals (31, 32) connected to an arbitrary output terminal from among a plurality of output terminals (41-44), via a wiring layer (51) or a rewiring layer (251). At a place where a wiring connecting a terminal from among the plurality of input terminals (31, 32) and the plurality of output terminals (41-44), and the semiconductor switching circuit (20), and a wiring connecting another terminal from among the plurality of terminals and the semiconductor switching circuit (20) intersect with each other, one wiring of the intersecting wirings is made to be the wiring layer (51), and the other wiring of the intersecting wirings is made to be the rewiring layer (251).

Description

半導体装置及び半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は、半導体装置及び半導体装置の製造方法に関し、特に携帯端末の高周波回路向けとして複数の入出力端子間の接続経路を半導体スイッチにより切り替える半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device for switching a connection path between a plurality of input / output terminals using a semiconductor switch for a high frequency circuit of a portable terminal and a method for manufacturing the semiconductor device.
　近年、無線通信機器の分野では、小型化、低コスト化、及び高機能化の要求に加えて、グローバルな地域での使用を前提として、複数の通信方式に対応し、かつ多くの周波数帯域で通信可能なマルチモード・マルチバンド端末に対応した半導体装置が求められている。 In recent years, in the field of wireless communication equipment, in addition to demands for miniaturization, cost reduction, and high functionality, it is compatible with multiple communication systems and used in many frequency bands on the assumption that it will be used in global regions. There is a need for a semiconductor device compatible with a communicable multimode / multiband terminal.
　例えば、携帯端末では、ＧＳＭ（Global System for Mobile Communication）規格やＷＣＤＭＡ（Wideband Code Division Multiple Access）規格のデュアルモードで４バンド（band）又は８バンド（band）に対応した端末が開発されている。また、ＷＬＡＮ（Wireless LAN）、ＢＴ（Bluetooth）、ＧＰＳ（Global Positioning System）、及びＤＴＶ（Digital Television）等の情報通信技術や、通信品質及び通信速度の向上を目的としたアンテナのダイバーシティ（diversity）技術を備えたＭＩＭＯ（Multiple Input Multiple Output）対応端末等も開発されている。これらの端末では、アンテナで送受信される信号の種類や周波数の組み合わせが増加しており、それに伴って通信方式や周波数バンドに対応した高周波信号の処理経路が複雑化している。このため、これらの端末に搭載される高周波回路を高集積化して小型化することが困難な状況となっている。 For example, as mobile terminals, terminals that support 4 bands or 8 bands in the dual mode of GSM (Global System for Mobile Communication) standard or WCDMA (Wideband Code Division Multiple Access) standard have been developed. Information communication technology such as WLAN (Wireless LAN), BT (Bluetooth), GPS (Global Positioning System), and DTV (Digital Television), and antenna diversity for improving communication quality and communication speed MIMO (Multiple Input Multiple Multiple Output) compatible terminals equipped with technology have also been developed. In these terminals, the types of signals transmitted and received by antennas and combinations of frequencies are increasing, and the processing paths of high-frequency signals corresponding to the communication method and frequency band are complicated accordingly. For this reason, it is difficult to downsize the high-frequency circuits mounted on these terminals by high integration.
　現行の携帯端末は、アンテナで受信信号を受信した場合に該受信信号に対応する高周波回路へ割り振るために該受信信号の送り先回路を半導体スイッチを用いて選択するように構成されており、かつアンテナから送信信号を送信する場合には所定の高周波回路から半導体スイッチを経由して該アンテナへと該送信信号を送信するように構成された半導体装置が搭載されている。特に、現行のマルチモード・マルチバンド携帯端末は、1～3本のアンテナと１０バンド（band）分の高周波回路との間の経路を半導体スイッチで切り替えるように構成された半導体装置が搭載されている。 The current portable terminal is configured to select a destination circuit of the received signal using a semiconductor switch in order to allocate to the high frequency circuit corresponding to the received signal when the received signal is received by the antenna, and the antenna When a transmission signal is transmitted from a semiconductor device, a semiconductor device configured to transmit the transmission signal from a predetermined high-frequency circuit to the antenna via a semiconductor switch is mounted. In particular, the current multi-mode multi-band portable terminal is equipped with a semiconductor device configured to switch a path between one to three antennas and a high-frequency circuit for 10 bands with a semiconductor switch. Yes.
　このように複数の入力端子と複数の出力端子との間の接続経路を半導体スイッチを介して切り替える半導体装置では、ある一つの入力端子と半導体スイッチとの間を接続する配線と、もう一つの入力端子と半導体スイッチとの間を接続する配線とが交差している箇所が必ず発生する。このように配線が交差している箇所には、配線間容量が存在し、該配線間容量を介して配線間の信号が相互に漏洩することになるため、入力端子間のアイソレーションが劣化する。 Thus, in a semiconductor device that switches connection paths between a plurality of input terminals and a plurality of output terminals via a semiconductor switch, wiring that connects between one input terminal and the semiconductor switch, and another input A location where the wiring connecting the terminal and the semiconductor switch intersects always occurs. In this way, there is an inter-wiring capacitance at the intersection of the wirings, and signals between the wirings leak to each other through the inter-wiring capacitance, so that the isolation between the input terminals deteriorates. .
　配線間容量を抑制するために、配線を細めて交差する配線の対向面積を小さくする手法、若しくは交差する配線間の距離を長くする手法が検討されている。交差する配線の対向面積を小さくする前者の手法の場合、半導体スイッチを備える半導体装置では一般的に１ｄＢ以下の挿入損失が求められているにも関らず、配線を細くすることに伴って挿入損失を増大させるという問題があるので、交差する配線間の距離を長くして配線間容量を小さくする後者の手法の方が有効と考えられる。 In order to suppress the inter-wiring capacitance, a method of reducing the facing area of the intersecting wires by narrowing the wires or a method of increasing the distance between the intersecting wires is being studied. In the former method of reducing the facing area of intersecting wirings, a semiconductor device having a semiconductor switch generally requires insertion loss of 1 dB or less, but is inserted as the wiring becomes thinner. Since there is a problem of increasing the loss, it is considered that the latter method of increasing the distance between the intersecting wires and reducing the capacitance between the wires is more effective.
　例えば、特許文献１には、交差する配線のうち、一方の配線が、複数のＳＰＤＴ（Single Pole Dual Throw）スイッチで構成されたマトリックススイッチの回路パターンがパターニングされている実装基板の表面に形成され、他方の配線が該実装基板の裏面に形成されることと、各配線が該実装基板を挟んで対向する部分に接地面を形成してマイクロストリップライン構造にすることが開示されている。 For example, in Patent Document 1, one of the intersecting wires is formed on the surface of a mounting substrate on which a circuit pattern of a matrix switch composed of a plurality of SPDT (Single-Pole-Dual-Throw) switches is patterned. Further, it is disclosed that the other wiring is formed on the back surface of the mounting substrate and that a grounding surface is formed in a portion where each wiring is opposed to sandwich the mounting substrate to form a microstrip line structure.
特開２００３－２１８７２４号公報JP 2003-218724 A
　ところで、携帯端末向けの高周波回路の入出力端子の数及びそれらの接続経路を切り替えるのに要する半導体スイッチの数は将来的に増加する傾向にある。この場合、特許文献１のように配線の形態が単純であれば、入出力端子と半導体スイッチとの間を接続する配線同士が交差する箇所が生じないようにパターニングすることができるが、一般にはそのようにパターニングすることは困難である。また、一般的には配線同士が交差する箇所が生じないようにパターニングするためには、実装基板の面積を大きくせざるを得ず、半導体装置のサイズ及びコストの増大を招くことになる。 By the way, the number of input / output terminals of a high-frequency circuit for portable terminals and the number of semiconductor switches required to switch their connection paths tend to increase in the future. In this case, if the form of the wiring is simple as in Patent Document 1, patterning can be performed so as not to generate a location where the wiring connecting the input / output terminals and the semiconductor switch intersects. Such patterning is difficult. In general, in order to perform patterning so that there is no place where the wirings intersect each other, the area of the mounting substrate must be increased, which increases the size and cost of the semiconductor device.
　本発明は、上記のような従来の課題を解決するためになされたものであり、入出力端子と半導体スイッチとの間を電気的に接続する配線同士が交差する箇所が発生しても、端子間のアイソレーション特性を向上させつつサイズ及びコストを抑制可能な半導体装置を提供することを目的とする。 The present invention has been made in order to solve the above-described conventional problems, and even if a location where wirings electrically connecting the input / output terminal and the semiconductor switch cross each other occurs, the terminal An object of the present invention is to provide a semiconductor device capable of reducing the size and cost while improving the isolation characteristics between the two.
　上記目的を達成するために、本発明に係る半導体装置は、半導体基板と、前記半導体基板上に形成された半導体スイッチ回路と、前記半導体スイッチ回路が形成された前記半導体基板の上に交互に形成された層間絶縁膜及び配線層と、最上位層にある前記層間絶縁膜上に前記配線層と接続されるように形成されたパッドと、前記パッドが露出するように、前記最上位層にある層間絶縁膜を覆うように形成された保護膜と、前記保護膜上に前記パッドと再配線層とが接続されるように交互に形成された再配線層間絶縁膜及び前記再配線層と、前記再配線層と接続された複数の入力端子及び複数の出力端子が露出するように、最上位にある前記再配線層間絶縁膜を覆うように形成されたモールド樹脂層と、を備え、前記半導体スイッチ回路は、前記複数の入力端子のうち任意の入力端子を、前記配線層又は前記再配線層を介して、前記複数の出力端子のうち任意の出力端子と接続することが可能なように構成され、前記複数の入力端子及び前記複数の出力端子のうちのある端子と前記半導体スイッチ回路との間を接続する配線と、前記複数の入力端子及び前記複数の出力端子のうちの他の端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、ものである。 In order to achieve the above object, a semiconductor device according to the present invention is alternately formed on a semiconductor substrate, a semiconductor switch circuit formed on the semiconductor substrate, and the semiconductor substrate on which the semiconductor switch circuit is formed. An interlayer insulating film and a wiring layer, a pad formed on the interlayer insulating film in the uppermost layer so as to be connected to the wiring layer, and the uppermost layer so that the pad is exposed; A protective film formed to cover the interlayer insulating film, and a rewiring interlayer insulating film and the rewiring layer that are alternately formed on the protective film so that the pad and the rewiring layer are connected; and A mold resin layer formed so as to cover the uppermost rewiring interlayer insulating film so that a plurality of input terminals and a plurality of output terminals connected to the rewiring layer are exposed, and the semiconductor switch Circuit An arbitrary input terminal among the plurality of input terminals can be connected to an arbitrary output terminal among the plurality of output terminals via the wiring layer or the rewiring layer. A wiring connecting between the input terminal and a certain terminal of the plurality of output terminals and the semiconductor switch circuit, the other terminal of the plurality of input terminals and the plurality of output terminals, and the semiconductor switch circuit Between the wirings connected to each other when viewed from the thickness direction of the semiconductor substrate, one of the intersecting wirings is constituted by the wiring layer, and the other wiring is the rewiring layer It is made up of.
　上記の半導体装置において、ある前記入力端子と前記半導体スイッチ回路との間を接続する配線と、他の前記入力端子と前記半導体スイッチ回路との間を接続する配線とが交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、としてもよい。 In the above semiconductor device, at a location where a wiring connecting between the certain input terminal and the semiconductor switch circuit and a wiring connecting between the other input terminal and the semiconductor switch circuit intersect, Of the intersecting wirings, one wiring may be configured by the wiring layer, and the other wiring may be configured by the rewiring layer.
　上記の半導体装置において、ある前記出力端子と前記半導体スイッチ回路との間を接続する配線と、他の前記出力端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線を前記配線層とし、他方の配線を前記再配線層とする、としてもよい。 In the semiconductor device, a wiring connecting between the output terminal and the semiconductor switch circuit and a wiring connecting the other output terminal and the semiconductor switch circuit are formed from the thickness direction of the semiconductor substrate. Of the interconnects that intersect when viewed, one of the interconnects may be the interconnect layer, and the other interconnect may be the redistribution layer.
　上記の半導体装置において、ある前記入力端子と前記半導体スイッチ回路との間を接続する配線と、ある前記出力端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、としてもよい。 In the semiconductor device, a wiring connecting between the certain input terminal and the semiconductor switch circuit and a wiring connecting between the certain output terminal and the semiconductor switch circuit are seen from the thickness direction of the semiconductor substrate. In the intersecting part, one of the intersecting wirings may be configured by the wiring layer, and the other wiring may be configured by the rewiring layer.
　この構成によれば、多層配線構造の半導体チップ内に形成される配線層間距離と比べて、半導体チップ内の配線層とウェハＣＳＰプロセスの再配線層との間の離隔距離は非常に長い。このため、配線間容量を抑制することができ、端子間で該配線間容量を介して信号が互いに漏洩することに伴うアイソレーションの劣化を抑制できる。 According to this configuration, the separation distance between the wiring layer in the semiconductor chip and the rewiring layer in the wafer CSP process is much longer than the wiring interlayer distance formed in the semiconductor chip having the multilayer wiring structure. For this reason, it is possible to suppress the capacitance between the wirings, and it is possible to suppress the deterioration of isolation due to the leakage of signals between the terminals via the wiring capacitance.
　また、半導体基板上にウェハＣＳＰプロセスの再配線層を形成する場合に、半導体チップ内に形成される配線層とウェハＣＳＰプロセスの再配線層とを接続するためのパッドが形成されている。しかし、パッドの直径はボンディングワイヤが接続されるボンディングパッドよりも小さくて済み、かつパッドは半導体基板上に形成された素子上に形成可能である。このため、入出力端子数の増加によって多数のパッドが形成される必要が生じても、半導体基板の面積を増大させる必要性は無い。このため、半導体装置のコスト及びサイズを抑制できる。 In addition, when a rewiring layer for the wafer CSP process is formed on the semiconductor substrate, a pad for connecting the wiring layer formed in the semiconductor chip and the rewiring layer for the wafer CSP process is formed. However, the pad diameter may be smaller than the bonding pad to which the bonding wire is connected, and the pad can be formed on an element formed on the semiconductor substrate. For this reason, even if it is necessary to form a large number of pads due to an increase in the number of input / output terminals, there is no need to increase the area of the semiconductor substrate. For this reason, the cost and size of the semiconductor device can be suppressed.
　以上より、入出力端子と半導体スイッチとの間を電気的に接続する配線同士が交差する箇所が発生しても、端子間のアイソレーション特性を向上させつつ、サイズ及びコストを抑制可能な半導体装置を提供することができる。 As described above, the semiconductor device capable of suppressing the size and cost while improving the isolation characteristics between the terminals even when the wirings that electrically connect the input / output terminals and the semiconductor switch occur. Can be provided.
　上記の半導体装置において、複数の前記再配線層が形成されており、前記他方の配線が前記複数の再配線層のうちの最上位層の再配線層である、としてもよい。 In the semiconductor device described above, a plurality of the rewiring layers may be formed, and the other wiring may be the uppermost rewiring layer of the plurality of rewiring layers.
　この構成によれば、交差する配線層及び再配線層の離隔距離を更に長くすることができ、この結果、配線間容量がさらに減少し、アイソレーションの劣化をより確実に抑制できる。 According to this configuration, the separation distance between the intersecting wiring layer and the rewiring layer can be further increased. As a result, the capacitance between the wirings can be further reduced, and the deterioration of isolation can be more reliably suppressed.
　上記の半導体装置において、前記半導体基板はＳＯＩ（Silicon On Insulator）基板である、としてもよい。 In the above semiconductor device, the semiconductor substrate may be an SOI (Silicon On Insulator) substrate.
　この構成によれば、一般的にＳＯＩ基板に形成されるＭＯＳトランジスタの寄生容量は小さいという特徴があるので、ＳＯＩ基板に形成された半導体スイッチ回路を構成するＭＯＳトランジスタ間のアイソレーション特性を向上させることができる。 According to this configuration, since the parasitic capacitance of the MOS transistor formed on the SOI substrate is generally small, the isolation characteristics between the MOS transistors constituting the semiconductor switch circuit formed on the SOI substrate are improved. be able to.
　上記の半導体装置において、前記半導体基板はＳＯＳ（Silicon On Sapphire）基板である、としてもよい。 In the above semiconductor device, the semiconductor substrate may be an SOS (Silicon On Sapphire) substrate.
　この構成によれば、ＳＯＳ基板の土台となるサファイア基板のサファイア基板抵抗は非常に大きいため、サファイア基板抵抗を介して他のＭＯＳトランジスタの各容量に向けて信号が漏洩されにくく、サファイア基板に形成された半導体スイッチ回路を構成するＭＯＳトランジスタのアイソレーション特性が高くなる。なお、シリコン基板を用いた半導体装置においては、通常、容量やトランジスタ素子間のアイソレーションを高くするため、素子の外周領域に基板コンタクトを形成し、かつ該基板コンタクトをグランドや電源などに接続するための専用パッドを設ける対策が実施されている。従って、ＳＯＳ基板上の半導体スイッチでは、上記の基板コンタクトと、それらを接続する専用パッドとを形成することが不要となることから、ＳＯＳ基板を含むＳＯＩ基板を採用したことに伴い、アイソレーション特性を向上させつつ、半導体装置のサイズ及びコストを低減できる。　 According to this configuration, since the sapphire substrate resistance of the sapphire substrate that is the foundation of the SOS substrate is very large, signals are not easily leaked to each capacitor of other MOS transistors through the sapphire substrate resistance, and formed on the sapphire substrate. The isolation characteristics of the MOS transistors constituting the semiconductor switch circuit thus made are improved. In a semiconductor device using a silicon substrate, a substrate contact is usually formed in the outer peripheral region of the element, and the substrate contact is connected to a ground or a power source in order to increase the capacitance and isolation between transistor elements. Measures have been implemented to provide a dedicated pad. Therefore, in the semiconductor switch on the SOS substrate, it is not necessary to form the above-described substrate contact and the dedicated pad for connecting them, so that the isolation characteristic is accompanied by the adoption of the SOI substrate including the SOS substrate. Thus, the size and cost of the semiconductor device can be reduced. *
　上記目的を達成するために、その他の本発明に係る半導体装置の製造方法は、複数の入力端子及び複数の出力端子と、前記複数の入力端子のうち任意の入力端子を前記複数の出力端子のうち任意の出力端子と接続されるように構成された半導体スイッチ回路と、を備える半導体装置の製造方法において、前記半導体基板上に前記半導体スイッチ回路を形成するステップと、前記半導体スイッチ回路が形成された前記半導体基板の上に層間絶縁膜及び配線層を交互に形成するステップと、最上位層にある前記層間絶縁膜上に前記配線層と接続されるようにパッドを形成するステップと、前記パッドが露出するように、前記最上位層にある層間絶縁膜を覆うように保護膜を形成するステップと、前記保護膜上に前記パッドと再配線層とが接続されるように再配線層間絶縁膜及び前記再配線層を交互に形成するステップと、前記再配線層と接続された複数の入力端子及び複数の出力端子が露出するように、最上位にある前記再配線層間絶縁膜を覆うようにモールド樹脂層を形成するステップと、を備え、前記複数の入力端子及び前記複数の出力端子のうちのある端子と前記半導体スイッチ回路との間を接続する配線と、前記複数の入力端子及び前記複数の出力端子のうちの他の端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、ものである。 In order to achieve the above object, another method of manufacturing a semiconductor device according to the present invention includes a plurality of input terminals, a plurality of output terminals, and an arbitrary input terminal of the plurality of input terminals. A semiconductor switch circuit configured to be connected to an arbitrary output terminal, and a step of forming the semiconductor switch circuit on the semiconductor substrate; and the semiconductor switch circuit is formed. Alternately forming an interlayer insulating film and a wiring layer on the semiconductor substrate, forming a pad on the interlayer insulating film in the uppermost layer so as to be connected to the wiring layer, and the pad Forming a protective film so as to cover the interlayer insulating film in the uppermost layer, and connecting the pad and the rewiring layer on the protective film. The step of alternately forming the rewiring interlayer insulation film and the rewiring layer so that the plurality of input terminals and the plurality of output terminals connected to the rewiring layer are exposed. Forming a mold resin layer so as to cover the wiring interlayer insulating film, and wiring for connecting between the semiconductor switch circuit and a terminal of the plurality of input terminals and the plurality of output terminals, Wiring that intersects at a point where wiring connecting between the plurality of input terminals and other terminals of the plurality of output terminals and the semiconductor switch circuit intersects when viewed from the thickness direction of the semiconductor substrate. Among these, one wiring is comprised by the said wiring layer, and the other wiring is comprised by the said rewiring layer.
　この製造方法によれば、入出力端子と半導体スイッチとの間を電気的に接続する配線同士が交差する箇所が発生しても、端子間のアイソレーション特性を向上させつつ、サイズ及びコストを抑制可能な半導体装置を提供することができる。 According to this manufacturing method, the size and cost can be suppressed while improving the isolation characteristics between the terminals even when the wiring that electrically connects the input / output terminals and the semiconductor switch occurs. A possible semiconductor device can be provided.
　本発明によれば、入出力端子と半導体スイッチとの間を電気的に接続する配線同士が交差する箇所が発生しても、端子間のアイソレーション特性を向上させつつ、サイズ及びコストを抑制可能な半導体装置及びその製造方法を提供することができる。 According to the present invention, the size and cost can be suppressed while improving the isolation characteristics between the terminals even when the wirings that electrically connect the input / output terminals and the semiconductor switch cross each other. A semiconductor device and a method for manufacturing the same can be provided.
図１は本発明の第１の実施の形態に係る半導体装置の回路構成図である。FIG. 1 is a circuit configuration diagram of a semiconductor device according to the first embodiment of the present invention. 図２は図１に示した半導体装置の切断線Ｃ－Ｃ’における’断面図である。FIG. 2 is a cross-sectional view taken along line C-C ′ of the semiconductor device shown in FIG. 図３は本発明の第１の実施の形態における半導体スイッチの回路構成図である。FIG. 3 is a circuit configuration diagram of the semiconductor switch according to the first embodiment of the present invention. 図４は本発明の第１の実施の形態における半導体スイッチの回路構成図である。FIG. 4 is a circuit configuration diagram of the semiconductor switch according to the first embodiment of the present invention. 図５は本発明の第１の実施の形態に係る半導体装置の変形例の回路構成図である。FIG. 5 is a circuit configuration diagram of a modification of the semiconductor device according to the first embodiment of the present invention. 図６は本発明の第２の実施の形態に係る半導体装置の回路構成図である。FIG. 6 is a circuit configuration diagram of a semiconductor device according to the second embodiment of the present invention. 図７は図６に示した半導体装置の切断線Ｄ－Ｄ’における断面図である。FIG. 7 is a cross-sectional view taken along the section line D-D ′ of the semiconductor device shown in FIG. 6. 図８は本発明の第２実施の形態に係る半導体装置の変形例の回路構成図である。FIG. 8 is a circuit configuration diagram of a modification of the semiconductor device according to the second embodiment of the present invention. 図９は本発明の第３の実施の形態に係る半導体装置の回路構成図である。FIG. 9 is a circuit configuration diagram of a semiconductor device according to the third embodiment of the present invention. 図１０は図９に示した半導体装置の切断線Ｅ－Ｅ’における’断面図である。FIG. 10 is a cross-sectional view taken along line E-E ′ of the semiconductor device shown in FIG. 9. 図１１は本発明の第１の実施の形態の比較例として例示する半導体装置の回路構成図である。FIG. 11 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the first embodiment of the present invention. 図１２は図１１に示す半導体装置の切断線Ａ－Ａ’における断面図である。FIG. 12 is a cross-sectional view of the semiconductor device shown in FIG. 11 taken along section line A-A ′. 図１３は本発明の第１の実施の形態のその他の比較例として例示する半導体装置の回路構成図である。FIG. 13 is a circuit configuration diagram of a semiconductor device exemplified as another comparative example of the first embodiment of the present invention. 図１４は図１３に示す半導体装置の切断線Ｂ－Ｂ’における断面図である。FIG. 14 is a cross-sectional view taken along line B-B ′ of the semiconductor device shown in FIG. 図１５は図１３に示す半導体ＳＰＤＴスイッチの回路構成図である。FIG. 15 is a circuit configuration diagram of the semiconductor SPDT switch shown in FIG. 図１６は本発明の第２の実施の形態の比較例として例示する半導体装置の回路構成図である。FIG. 16 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the second embodiment of the present invention. 図１７は図１６に示す半導体スイッチを構成するＭＯＳトランジスタの構造を示した図である。FIG. 17 is a diagram showing the structure of the MOS transistor constituting the semiconductor switch shown in FIG. 図１８は本発明の第２の実施の形態における半導体スイッチを構成するＭＯＳトランジスタの構造を示した図である。FIG. 18 is a diagram showing the structure of a MOS transistor constituting the semiconductor switch according to the second embodiment of the present invention.
　以下、本発明の好ましい実施の形態を、図面を参照しながら説明する。なお、以下では全ての図を通じて同一又は相当する要素には同一の参照符号を付して、その重複する説明を省略する。
（第１の実施の形態）
　[半導体装置の構造]
　図１は、本発明の第１の実施の形態に係る半導体装置の回路構成図である。図２は、図１に示す半導体装置の切断線Ｃ－Ｃ’における断面図である。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.
(First embodiment)
[Structure of semiconductor device]
FIG. 1 is a circuit configuration diagram of a semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the section line CC ′.
　図１に示す半導体装置は、第１入力端子３１と、第２入力端子３２と、第１出力端子４１と、第２出力端子４２と、第３出力端子４３と、第４出力端子４４と、８パターンの入出力経路に応じた８つの半導体スイッチ２１～２８から成る半導体スイッチ回路２０と、を備えている。半導体スイッチ回路２０は、第１及び第２入力端子３１，３２のうち任意の端子を、択一的に第１乃至第４出力端子４１～４４のうち任意の端子と電気的に接続させるように構成されている。 The semiconductor device shown in FIG. 1 includes a first input terminal 31, a second input terminal 32, a first output terminal 41, a second output terminal 42, a third output terminal 43, a fourth output terminal 44, And a semiconductor switch circuit 20 including eight semiconductor switches 21 to 28 corresponding to eight patterns of input / output paths. The semiconductor switch circuit 20 is configured to selectively connect any one of the first and second input terminals 31 and 32 to any one of the first to fourth output terminals 41 to 44. It is configured.
　また、図１に示す半導体装置は、ウェハレベルＣＳＰ（Chip Size Package）プロセスによって製造された半導体パッケージであり、チップ１内の半導体基板１０上には半導体内の第１配線層５１の他に、当該チップ１の表面上に第１再配線層２５１が形成されている。チップ１は、半導体基板１０、第１乃至第３層間絶縁膜１１～１３、保護膜１４、及びパッド６０を含む。 The semiconductor device shown in FIG. 1 is a semiconductor package manufactured by a wafer level CSP (ChipCSize Package) process. In addition to the first wiring layer 51 in the semiconductor, on the semiconductor substrate 10 in the chip 1, A first rewiring layer 251 is formed on the surface of the chip 1. The chip 1 includes a semiconductor substrate 10, first to third interlayer insulating films 11 to 13, a protective film 14, and a pad 60.
　なお、ウェハレベルＣＳＰプロセスとは、半導体装置の製造工程において個々の半導体チップに切断（ダイシング）する前に半導体ウェハの状態のままでパッケージングまでを行う製法のことである。ウェハレベルＣＳＰプロセスでは、はんだバンプによる外部端子の形成を含めて、半導体ウェハ全面に従来のパッケージングに必要なすべての構造を一括して形成することが可能になり、はんだバンプを全面に形成した半導体ウェハをダイシングすることにより、パッケージング済みの半導体装置を得ることが可能になる。 The wafer level CSP process is a manufacturing method in which packaging is performed in a semiconductor wafer state before dicing into individual semiconductor chips in a semiconductor device manufacturing process. In the wafer level CSP process, it is possible to form all the structures necessary for conventional packaging all over the semiconductor wafer, including the formation of external terminals by solder bumps. By dicing the semiconductor wafer, a packaged semiconductor device can be obtained.
　また、半導体基板１０は、シリコン基板と表面シリコン層との間にＳｉＯ２層を介挿させて構成されたＳＯＩ（Silicon On Insulator）基板で構成されている。ＳＯＩ基板は、そこに形成されるトランジスタの寄生容量を抑えることができ、動作速度の向上と消費電力の削減に効果がある。 Further, the semiconductor substrate 10 is configured by an SOI (Silicon On Insulator) substrate configured by inserting a SiO 2 layer between a silicon substrate and a surface silicon layer. The SOI substrate can suppress the parasitic capacitance of a transistor formed there, and is effective in improving operation speed and reducing power consumption.
　第１入力端子３１は、第１再配線層２５１と、第１再配線層パッド２６１と、第２配線層５２と、第１ビア５４と、第１配線層５１とを介して、半導体スイッチ２１，２３，２５，２７に接続されている。また、半導体スイッチ２１，２３，２５，２７は、第１配線層５１と、第１ビア５４と、第２配線層５２と、第１再配線層パッド２６１と、第１再配線層２５１とを介して、第１出力端子４１、第２出力端子４２、第３出力端子４３、第４出力端子４４と接続されている。 The first input terminal 31 is connected to the semiconductor switch 21 via the first rewiring layer 251, the first rewiring layer pad 261, the second wiring layer 52, the first via 54, and the first wiring layer 51. , 23, 25, 27. In addition, the semiconductor switches 21, 23, 25, and 27 include the first wiring layer 51, the first via 54, the second wiring layer 52, the first rewiring layer pad 261, and the first rewiring layer 251. The first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 are connected.
　第２入力端子３２は、第１再配線層２５１と、第１再配線層パッド２６１と、第２配線層５２と、第１ビア５４と、第１配線層５１とを介して、半導体スイッチ２２，２４，２６，２８に接続されている。また、半導体スイッチ２２，２４，２６，２８は、第１配線層５１と、第１ビア５４と、第２配線層５２と、第１再配線層パッド２６１と、第１再配線層２５１とを介して、第１出力端子４１、第２出力端子４２、第３出力端子４３、第４出力端子４４と接続されている。 The second input terminal 32 is connected to the semiconductor switch 22 via the first rewiring layer 251, the first rewiring layer pad 261, the second wiring layer 52, the first via 54, and the first wiring layer 51. , 24, 26, 28. The semiconductor switches 22, 24, 26, and 28 include the first wiring layer 51, the first via 54, the second wiring layer 52, the first rewiring layer pad 261, and the first rewiring layer 251. The first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 are connected.
　半導体スイッチ２１～２８は、図２に示されていないが、半導体基板１０上に第１層間絶縁膜１１に覆われて形成され、コンタクトを介して第１配線層５１に接続されている。半導体スイッチ２１～２８は、例えば、図３又は図４に示されるように構成されている。図３に示す構成では、入力ポート２と出力ポート３との間において、ｎ（ｎは自然数）個のＭＯＳトランジスタＭ１～Ｍｎが各ドレイン端子及びソース端子において直列に接続されて電流経路が形成され、かつＭＯＳトランジスタＭ１～Ｍｎの各ゲート端子が抵抗を介して制御電圧端子接続され、この制御電圧端子に制御電圧Ｖｂ＋が印加されるように構成されている。また、入力ポート２とグランド（grand）との間に、ｋ（ｋは自然数）個のＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋが各ドレイン端子及びソース端子において直列に接続されて電流経路が形成され、かつＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋの各ゲート端子が抵抗を介して制御電圧端子と接続され、この制御端子に制御電圧Ｖｂ－が印加されるように構成されている。制御電圧Ｖｂ＋と制御電圧Ｖｂ－とは、一般に論理信号のＨＩＧＨとＬＯＷに相当する2値が与えられ、互いに逆の論理値に設定されるものである。例えばＶｂ＋が３Ｖ、Ｖｂ－が０Ｖ、その逆はＶｂ＋が０Ｖ、Ｖｂ－が３Ｖのような制御電圧となる場合や、Ｖｂ＋が３Ｖ、Ｖｂ－が－３Ｖ、その逆はＶｂ＋が－３Ｖ、Ｖｂ－が３Ｖのように、電圧の極性が反転する制御電圧を与える場合がある。この制御電圧はＭＯＳトランジスタの製造プロセスに依存する閾値電圧の特性によって適切な電圧に定められる。図３の構成においては、制御電圧Ｖｂ＋に任意の正の電圧及び制御電圧Ｖｂ－に任意の負の電圧を与えることで、入力ポート２と出力ポート３との間が導通し(ON)、制御電圧Ｖｂ＋に任意の負の電圧及び制御電圧Ｖｂ－に任意の正の電圧を与えることで、入力ポート２と出力ポート３との間が遮断される(OFF)とともに入力ポート２がグランドに接続される。 Although not shown in FIG. 2, the semiconductor switches 21 to 28 are formed on the semiconductor substrate 10 so as to be covered with the first interlayer insulating film 11 and are connected to the first wiring layer 51 through contacts. The semiconductor switches 21 to 28 are configured, for example, as shown in FIG. 3 or FIG. In the configuration shown in FIG. 3, between the input port 2 and the output port 3, n (n is a natural number) MOS transistors M1 to Mn are connected in series at each drain terminal and source terminal to form a current path. The gate terminals of the MOS transistors M1 to Mn are connected to the control voltage terminal via a resistor, and the control voltage Vb + is applied to the control voltage terminal. Also, between the input port 2 and the ground, k (k is a natural number) MOS transistors Mn + 1 to Mn + k are connected in series at each drain terminal and source terminal to form a current path, and the MOS transistor Each gate terminal of Mn + 1 to Mn + k is connected to a control voltage terminal through a resistor, and a control voltage Vb− is applied to the control terminal. The control voltage Vb + and the control voltage Vb− are generally given two values corresponding to logic signals HIGH and LOW, and are set to logic values opposite to each other. For example, when Vb + is 3V, Vb− is 0V, and vice versa, the control voltage is such that Vb + is 0V and Vb− is 3V, or Vb + is 3V, Vb− is −3V, and vice versa. There is a case where a control voltage in which the polarity of the voltage is inverted is given such that − is 3V. This control voltage is set to an appropriate voltage depending on the characteristics of the threshold voltage depending on the manufacturing process of the MOS transistor. In the configuration of FIG. 3, by applying an arbitrary positive voltage to the control voltage Vb + and an arbitrary negative voltage to the control voltage Vb−, the input port 2 and the output port 3 are electrically connected (ON), and control is performed. By applying an arbitrary negative voltage to the voltage Vb + and an arbitrary positive voltage to the control voltage Vb−, the input port 2 and the output port 3 are disconnected (OFF) and the input port 2 is connected to the ground. The
　図４に示す構成では、図３に示す構成において、入力ポート２とグランドとの間にＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋが直列接続される構成が省略されている。図４の構成においては、制御電圧Ｖｂ＋の極性を制御することで、入力ポート２と出力ポート３との間が導通し(ON)、又は、入力ポート２と出力ポート３との間が遮断される(OFF)。 In the configuration shown in FIG. 4, the configuration in which MOS transistors Mn + 1 to Mn + k are connected in series between the input port 2 and the ground in the configuration shown in FIG. 3 is omitted. In the configuration of FIG. 4, by controlling the polarity of the control voltage Vb +, the input port 2 and the output port 3 are made conductive (ON), or the input port 2 and the output port 3 are blocked. (OFF).
　半導体スイッチ２１～２８がこのように構成されることで、第１入力端子３１及び第２入力端子３２を、第１乃至第４出力端子４１～４４のうちそれぞれ異なる出力端子に接続する経路を選択できる。例えば、半導体スイッチ２２，２３がＯＮ（導通）した状態で、その他の半導体スイッチ２１、２４～２８がＯＦＦ（遮断）した状態の場合、第１入力端子３１と第２出力端子４２とが接続され、かつ第２入力端子３２と第１出力端子４１とが接続された状態となる。 By configuring the semiconductor switches 21 to 28 in this way, the paths for connecting the first input terminal 31 and the second input terminal 32 to different output terminals among the first to fourth output terminals 41 to 44 are selected. it can. For example, when the semiconductor switches 22 and 23 are turned on (conductive) and the other semiconductor switches 21 and 24 to 28 are turned off (cut off), the first input terminal 31 and the second output terminal 42 are connected. In addition, the second input terminal 32 and the first output terminal 41 are connected.
　図１に示す半導体装置の構成において、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士は交差していないが、第１入力端子３１及び第２入力端子３２と半導体スイッチ回路２０との間を接続する配線同士が半導体基板１０の厚み方向から見て交差している箇所が存在する。図１、図２に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。 In the configuration of the semiconductor device shown in FIG. 1, the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 do not intersect with each other, but the first input terminal 31 and the second input terminal There are places where wirings connecting between the semiconductor switch circuit 20 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the semiconductor substrate 10. A portion surrounded by a broken-line ellipse shown in FIGS. 1 and 2 represents the intersecting portion.
　第１入力端子３１と半導体スイッチ２３との間を接続する配線と、第２入力端子３２と半導体スイッチ２２との間を接続する配線とが半導体基板１０の厚み方向から見て交差している箇所では、第１入力端子３１と半導体スイッチ２３との間を接続する配線に第１再配線層２５１が使用され、第２入力端子３２と半導体スイッチ２２との間を接続する配線に第１配線層５１が使用されている。 A location where the wiring connecting the first input terminal 31 and the semiconductor switch 23 and the wiring connecting the second input terminal 32 and the semiconductor switch 22 intersect when viewed from the thickness direction of the semiconductor substrate 10. Then, the first rewiring layer 251 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 23, and the first wiring layer is used for the wiring connecting the second input terminal 32 and the semiconductor switch 22. 51 is used.
　第１入力端子３１と半導体スイッチ２５との間を接続する配線と、第２入力端子３２と半導体スイッチ２４との間を接続する配線とが半導体基板１０の厚み方向から見て交差している箇所では、第１入力端子３１と半導体スイッチ２５との間を接続する配線に第１再配線層２５１が使用され、第２入力端子３２と半導体スイッチ２４との間を接続する配線に第１配線層５１が使用されている。 A location where wiring connecting between the first input terminal 31 and the semiconductor switch 25 and wiring connecting between the second input terminal 32 and the semiconductor switch 24 intersect when viewed from the thickness direction of the semiconductor substrate 10. Then, the first rewiring layer 251 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 25, and the first wiring layer is used for the wiring connecting the second input terminal 32 and the semiconductor switch 24. 51 is used.
　第１入力端子３１と半導体スイッチ２７との間を接続する配線と第２入力端子３２と半導体スイッチ２６との間を接続する配線とが半導体基板１０の厚み方向から見て交差している箇所では、第１入力端子３１と半導体スイッチ２７との間を接続する配線に第１配線層５１が使用され、第２入力端子３２と半導体スイッチ２６との間を接続する配線に第１再配線層２５１が使用されている。 At a location where the wiring connecting the first input terminal 31 and the semiconductor switch 27 and the wiring connecting the second input terminal 32 and the semiconductor switch 26 intersect when viewed from the thickness direction of the semiconductor substrate 10. The first wiring layer 51 is used for the wiring connecting the first input terminal 31 and the semiconductor switch 27, and the first rewiring layer 251 is used for the wiring connecting the second input terminal 32 and the semiconductor switch 26. Is used.
　このように、図１に示す半導体装置は、第１入力端子３１から半導体スイッチ回路２０に向けて延設される配線と第２入力端子３２から半導体スイッチ回路２０に向けて延設される配線とが半導体基板１０の厚み方向から見て交差している箇所では、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されるように構成されている。 As described above, the semiconductor device shown in FIG. 1 includes wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20, and wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20. Are crossed when viewed from the thickness direction of the semiconductor substrate 10, the first rewiring layer 251 is used for one wiring, and the first wiring layer 51 is used for the other wiring. .
　また、図１に示す半導体装置は、図２に示されるように、第１入力端子３１から半導体スイッチ回路２０に向けて延設される配線と、第２入力端子３２から半導体スイッチ回路２０に向けて延設される配線とが半導体基板１０の厚み方向から見て交差している箇所では、第１配線層５１と第１再配線層２５１とが断面視において対向して形成されている。 Further, as shown in FIG. 2, the semiconductor device shown in FIG. 1 has wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20, and from the second input terminal 32 toward the semiconductor switch circuit 20. The first wiring layer 51 and the first rewiring layer 251 are formed to face each other in a cross-sectional view at a location where the extended wiring intersects with the thickness direction of the semiconductor substrate 10.
　詳述すると、図１に示す半導体装置は、半導体スイッチ回路２０の回路パターンが形成された素子領域を備えている半導体基板１０と、半導体基板１０を覆うように形成された第１層間絶縁膜１１と、第１層間絶縁膜１１上に形成された第１配線層５１と、第１配線層５１を覆うように形成された第２層間絶縁膜１２と、第２層間絶縁膜１２上に形成された第２配線層５２と、第２配線層５２を覆うように形成された第３層間絶縁膜１３と、第３層間絶縁膜１３を貫通して第２配線層５２に至るように形成されたビアホールを埋める第２ビア５５と、第２ビア５５上に形成されたパッド６０と、パッド６０を覆うように形成され、かつパッド６０の表面を露出させる開口部が形成された保護膜１４と、を備えている。このように、半導体基板１０上には層間絶縁膜（１１，１２，１３）と配線層（５１，５２）とが交互に形成されている。 More specifically, the semiconductor device shown in FIG. 1 includes a semiconductor substrate 10 having an element region in which a circuit pattern of the semiconductor switch circuit 20 is formed, and a first interlayer insulating film 11 formed so as to cover the semiconductor substrate 10. A first wiring layer 51 formed on the first interlayer insulating film 11, a second interlayer insulating film 12 formed so as to cover the first wiring layer 51, and a second interlayer insulating film 12. The second wiring layer 52, the third interlayer insulating film 13 formed so as to cover the second wiring layer 52, and the second wiring layer 52 formed so as to penetrate the third interlayer insulating film 13. A second via 55 filling the via hole; a pad 60 formed on the second via 55; a protective film 14 formed so as to cover the pad 60 and having an opening exposing the surface of the pad 60; It has. Thus, the interlayer insulating films (11, 12, 13) and the wiring layers (51, 52) are alternately formed on the semiconductor substrate 10.
　なお、図２には示されていないが、第２層間絶縁膜１２を貫通して第１配線層５１に至り、かつ第２配線層５２と第１配線層５１との間を連結させるように形成されたビアホールを埋める第１ビア５４が形成されている。また、第１配線層５１は、半導体基板１０上の素子領域に形成された半導体スイッチ２１～２８のそれぞれの入力ポート２及び出力ポート３と接続されている。 Although not shown in FIG. 2, the second wiring layer 52 penetrates through the second interlayer insulating film 12 to the first wiring layer 51, and the second wiring layer 52 and the first wiring layer 51 are connected to each other. A first via 54 is formed to fill the formed via hole. The first wiring layer 51 is connected to the input port 2 and the output port 3 of each of the semiconductor switches 21 to 28 formed in the element region on the semiconductor substrate 10.
　さらに、図１に示す半導体装置は、保護膜１４及び保護膜１４に形成された開口部に露出したパッド６０を覆うように形成された第１再配線層間絶縁膜１１１と、第１再配線層間絶縁膜１１１を貫通してパッド６０に至るように形成されたビアホールを埋める再配線層ビア２５４と、再配線層ビア２５４上に形成された第１再配線層パッド２６１と、第１再配線層間絶縁膜１１１上に、かつ隣り合う第１再配線層パッド２６１との間を連結するように形成された第１再配線層２５１と、第１再配線層パッド２６１及び第１再配線層２５１を覆うように形成された第２再配線層間絶縁膜１１２と、半導体装置全体を封止するように形成されたモールド樹脂層１１０と、を備えている。また、図示されないが、第２再配線層間絶縁膜１１２上に、第１及び第２入力端子３１，３２と第１乃至第４出力端子４１～４４とが形成されている。第１及び第２入力端子３１，３２と第１乃至第４出力端子４１～４４は、第２再配線層間絶縁膜１１２上に形成され、当該第２再配線層間絶縁膜１１２を貫通するビアを介して第１再配線層２５１と接続され、かつモールド樹脂層１１０に形成された開口部に露出したパッドと、このパッド上に形成されたはんだバンプとで構成されている。このように、半導体チップの保護膜１４及びパッド６０の上には再配線層間絶縁膜（１１１，１１２）と再配線層（２５１）とが交互に形成されている。 Further, the semiconductor device shown in FIG. 1 includes a protective film 14 and a first rewiring interlayer insulating film 111 formed so as to cover the pad 60 exposed in the opening formed in the protective film 14 and a first rewiring interlayer. A rewiring layer via 254 that fills the via hole formed so as to penetrate the insulating film 111 and reach the pad 60, a first rewiring layer pad 261 formed on the rewiring layer via 254, and a first rewiring layer A first redistribution layer 251 formed on the insulating film 111 so as to connect between adjacent first redistribution layer pads 261, a first redistribution layer pad 261, and a first redistribution layer 251. A second rewiring interlayer insulating film 112 formed so as to cover and a mold resin layer 110 formed so as to seal the entire semiconductor device are provided. Although not shown, the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112. The first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112, and vias penetrating the second redistribution interlayer insulating film 112 are formed. And a pad exposed to an opening formed in the mold resin layer 110 and a solder bump formed on the pad. Thus, the rewiring interlayer insulating films (111, 112) and the rewiring layer (251) are alternately formed on the protective film 14 and the pad 60 of the semiconductor chip.
　第１配線層５１と第１再配線層２５１とが断面視において対向して形成される箇所では、第１配線層５１から第１再配線層２５１に向う方向で、約1（μm）の厚さの第２層間絶縁膜１２及び第３層間絶縁膜１３と、約3（μm）の厚さの保護膜１４と、約5（μm）の厚さの第１再配線層間絶縁膜１１１とがこの順に形成されている。 At a location where the first wiring layer 51 and the first rewiring layer 251 are formed to face each other in a cross-sectional view, the thickness is about 1 (μm) in the direction from the first wiring layer 51 to the first rewiring layer 251. A second interlayer insulating film 12 and a third interlayer insulating film 13, a protective film 14 having a thickness of about 3 (μm), and a first redistribution interlayer insulating film 111 having a thickness of about 5 (μm). They are formed in this order.
　[半導体装置の製造方法]
　以下では、図１、図２に示したウェハレベルＣＳＰプロセスによる半導体装置の製造方法を説明する。 [Method for Manufacturing Semiconductor Device]
Below, the manufacturing method of the semiconductor device by the wafer level CSP process shown in FIG. 1, FIG. 2 is demonstrated.
　まず、ＣＶＤ（Chemical Vapor Deposition）等によりシリコン基板上にＳｉＯ２層と表面シリコン層とをこの順に形成させて半導体基板１０を形成する。これにより、ＳＯＩ基板が形成される。 First, a semiconductor substrate 10 is formed by forming a SiO 2 layer and a surface silicon layer in this order on a silicon substrate by CVD (Chemical Vapor Deposition) or the like. Thereby, an SOI substrate is formed.
　次に、スパッタリング、ＣＶＤ等による膜堆積とフォトリソグラフィ及びエッチングによる膜のパターニング等により半導体基板１０の素子領域に半導体スイッチ回路２０が形成される。 Next, the semiconductor switch circuit 20 is formed in the element region of the semiconductor substrate 10 by film deposition by sputtering, CVD, etc., and patterning of the film by photolithography and etching.
　次に、ＣＶＤ、スパッタリング等による膜堆積とフォトリソグラフィ及びエッチングによる膜のパターニング等により、半導体スイッチ回路２０が形成された半導体基板１０上に層間絶縁膜（１１，１２，１３）及び配線層（５１，５２）が交互に形成される。なお、この過程では、第２配線層５２と第１配線層５１との間を接続する第１ビア５４が形成される。 Next, an interlayer insulating film (11, 12, 13) and a wiring layer (51) are formed on the semiconductor substrate 10 on which the semiconductor switch circuit 20 is formed by film deposition by CVD, sputtering, etc., and patterning of the film by photolithography and etching. , 52) are alternately formed. In this process, the first via 54 that connects the second wiring layer 52 and the first wiring layer 51 is formed.
　次に、スパッタリング等により最上位層にある第３層間絶縁膜１３上に第２配線層５２と接続されるようにパッド６０が形成される。なお、この過程では、パッド６０と第２配線層５２との間を接続する第２ビア５５が形成される。 Next, a pad 60 is formed on the third interlayer insulating film 13 in the uppermost layer by sputtering or the like so as to be connected to the second wiring layer 52. In this process, the second via 55 that connects the pad 60 and the second wiring layer 52 is formed.
　次に、ＣＶＤ等によりパッド６０が外部に露出されるように、最上位層にある第３層間絶縁膜１３を覆うように保護膜１４が形成される。 Next, the protective film 14 is formed so as to cover the third interlayer insulating film 13 in the uppermost layer so that the pad 60 is exposed to the outside by CVD or the like.
　次に、ＣＶＤ、スパッタリング等による膜堆積とフォトリソグラフィ及びエッチングによる膜のパターニング等により保護膜１４上に再配線層間絶縁膜（１１１，１１２）及び第１再配線層２５１が交互に形成される。なお、この過程で、第１再配線層間絶縁膜１１１上に第１再配線層パッド２６１が形成されるとともに、この第１再配線層パッド２６１と保護膜１４上のパッド６０との間を接続する第１再配線層ビア２５４が形成される。 Next, the rewiring interlayer insulating films (111, 112) and the first rewiring layer 251 are alternately formed on the protective film 14 by film deposition by CVD, sputtering, etc. and film patterning by photolithography and etching. In this process, the first redistribution layer pad 261 is formed on the first redistribution interlayer insulating film 111 and the first redistribution layer pad 261 and the pad 60 on the protective film 14 are connected to each other. A first redistribution layer via 254 is formed.
　次に、スパッタリングによる膜堆積とフォトリソグラフィ及びエッチングによる膜のパターニングにより第２再配線層間絶縁膜１１２上に第１及び第２入力端子３１，３２並びに第１乃至第４出力端子４１～４４を構成するパッドが形成される。なお、この過程で、このパッドと第１再配線層２５１とを接続するビアが形成される。 Next, first and second input terminals 31 and 32 and first to fourth output terminals 41 to 44 are formed on the second redistribution interlayer insulating film 112 by film deposition by sputtering and film patterning by photolithography and etching. A pad to be formed is formed. In this process, a via that connects this pad and the first redistribution layer 251 is formed.
　次に、ＣＶＤ等により第１及び第２入力端子３１，３２並びに第１乃至第４出力端子４１～４４を構成するパッドが露出されるように、最上位にある第２再配線層間絶縁膜１１２を覆うようにモールド樹脂層１１０が形成される。これにより、ＳＯＩ基板上にウェハレベルＣＳＰプロセスの半導体装置群が形成される。その後、モールド樹脂層１１０から露出された、第１及び第２入力端子３１，３２及び第１乃至第４出力端子４１～４４を構成するパッドにはんだバンプを形成した後、個々の半導体装置をダイシングによって切り出すことで、パッケージング済みの半導体装置が得られる。 Next, the uppermost second redistribution interlayer insulating film 112 is so exposed that the pads constituting the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 are exposed by CVD or the like. A mold resin layer 110 is formed so as to cover the surface. Thereby, a semiconductor device group of the wafer level CSP process is formed on the SOI substrate. Thereafter, solder bumps are formed on the pads constituting the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 exposed from the mold resin layer 110, and then the individual semiconductor devices are diced. Thus, a packaged semiconductor device can be obtained.
　なお、上記のステップにおいて、フォトリソグラフィ及びエッチング等によって、第１及び第２入力端子３１，３２及び第１乃至第４出力端子４１～４４のうち、ある端子と半導体スイッチ回路２０との間を接続する配線と、その他のある端子と半導体スイッチ回路２０との間を接続する配線とが半導体基板１０の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線に第１配線層５１が使用され、他方の配線に第１再配線層２５１が使用されるようにする。 In the above steps, a connection between one of the first and second input terminals 31 and 32 and the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 is made by photolithography, etching, or the like. In a place where a wiring to be connected and a wiring for connecting the other terminal and the semiconductor switch circuit 20 cross each other when viewed from the thickness direction of the semiconductor substrate 10, one of the intersecting wirings is the first wiring. The wiring layer 51 is used, and the first rewiring layer 251 is used for the other wiring.
　 [比較例１]
　図１１は本発明の第１の実施の形態の比較例として例示する半導体装置の回路構成図である。図１２は、図１１に示す半導体装置の切断線Ａ－Ａ’における断面図である。
図１１に示す半導体装置は、半導体スイッチ２１～２８から成る2入力4出力タイプの半導体スイッチ回路２０が設けられており、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線間では半導体基板１０の厚み方向から見て交差している箇所が無いが、第１入力端子３１から半導体スイッチ回路２０に向けて延設される配線と、第２入力端子３２から半導体スイッチ回路２０に向けて延設される配線とが半導体基板１０の厚み方向から見て交差している箇所が発生している。図１１、図１２に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。この交差している配線のうち、一方の配線を半導体基板１０上に形成される配線としており、他方の配線をボンディングワイヤによる配線としている。 [Comparative Example 1]
FIG. 11 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the first embodiment of the present invention. FIG. 12 is a cross-sectional view of the semiconductor device shown in FIG. 11 taken along section line AA ′.
The semiconductor device shown in FIG. 11 is provided with a two-input four-output type semiconductor switch circuit 20 including semiconductor switches 21 to 28, and between the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20. There is no crossing between the wirings to be connected when viewed from the thickness direction of the semiconductor substrate 10, but there are wirings extending from the first input terminal 31 toward the semiconductor switch circuit 20 and from the second input terminal 32 to the semiconductor. A portion where the wiring extending toward the switch circuit 20 intersects when viewed from the thickness direction of the semiconductor substrate 10 occurs. A portion surrounded by a broken-line ellipse shown in FIGS. 11 and 12 represents the intersecting portion. Among the intersecting wirings, one wiring is a wiring formed on the semiconductor substrate 10 and the other wiring is a bonding wire.
　詳述すると、図１１に示す半導体装置は、半導体基板１０上に、第１及び第２入力端子３１，３２と、第１乃至第４出力端子４１～４４と、８つの半導体スイッチ２１～２８から成る半導体スイッチ回路２０と、６つのボンディングパッド６１～６６と、を備えている。第１入力端子３１は、半導体スイッチ回路２０が制御されることで、第１出力端子４１、第２出力端子４２、第３出力端子４３、又は第４出力端子４４のうちいずれか１つと接続されるように構成されている。同様に、第２入力端子３２は、半導体スイッチ回路２０が制御されることで、第１出力端子４１、第２出力端子４２、第３出力端子４３、又は第４出力端子４４のうちいずれか１つと接続されるように構成されている。第１入力端子３１と半導体スイッチ２１，２３との間は、ボンディングパッド６１及びボンディングパッド６３又は６４を経由して第１配線層５１で接続されている。また、ボンディングパッド６３とボンディングパッド６４との間は、ボンディングワイヤ７２を介して接続されている。第２入力端子３２に接続された第１配線層５１は、ボンディングパッド６３，６４の間を接続するボンディングワイヤ７２と半導体基板１０の厚み方向から見て交差している。 More specifically, the semiconductor device shown in FIG. 11 includes, on a semiconductor substrate 10, first and second input terminals 31, 32, first to fourth output terminals 41 to 44, and eight semiconductor switches 21 to 28. The semiconductor switch circuit 20 and six bonding pads 61 to 66 are provided. The first input terminal 31 is connected to any one of the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 by controlling the semiconductor switch circuit 20. It is comprised so that. Similarly, the second input terminal 32 is any one of the first output terminal 41, the second output terminal 42, the third output terminal 43, and the fourth output terminal 44 by controlling the semiconductor switch circuit 20. Are connected to each other. The first input terminal 31 and the semiconductor switches 21 and 23 are connected by the first wiring layer 51 via the bonding pad 61 and the bonding pad 63 or 64. The bonding pad 63 and the bonding pad 64 are connected via a bonding wire 72. The first wiring layer 51 connected to the second input terminal 32 intersects with the bonding wire 72 connecting the bonding pads 63 and 64 as viewed from the thickness direction of the semiconductor substrate 10.
　また、図１１に示す半導体装置は、図１２に示されるように、半導体基板１０と、半導体基板１０を覆うように形成された第１層間絶縁膜１１と、第１層間絶縁膜１１上に形成された第１配線層５１と、第１配線層５１を覆うように形成された第２層間絶縁膜１２と、第２層間絶縁膜１２を貫通して第１配線層５１に至るように形成されたビアホールを埋める第１ビア５４と、第１ビア５４上に形成された第２配線層５２と、第２配線層５２を覆うように形成された第３層間絶縁膜１３と、第３層間絶縁膜１３を貫通して第２配線層５２に至るように形成されたビアホールを埋める第２ビア５５と、第２ビア５５上に形成されたボンディングパッド６３～６６と、ボンディングパッド６３～６６を覆うように形成され、かつボンディングパッド６３～６６の表面を露出させる開口部が形成された保護膜１４と、を備えている。なお、保護膜１４から露出されたボンディングパッド６３，６４は互いにボンディングワイヤ７２を介して接続されており、同様に保護膜１４から露出されたボンディングパッド６５，６６は互いにボンディングワイヤ７３を介して接続されている。 Further, as shown in FIG. 12, the semiconductor device shown in FIG. 11 is formed on the semiconductor substrate 10, the first interlayer insulating film 11 formed so as to cover the semiconductor substrate 10, and the first interlayer insulating film 11. The first wiring layer 51 formed, the second interlayer insulating film 12 formed so as to cover the first wiring layer 51, and the first wiring layer 51 are formed so as to penetrate the second interlayer insulating film 12. A first via 54 filling the via hole, a second wiring layer 52 formed on the first via 54, a third interlayer insulating film 13 formed so as to cover the second wiring layer 52, and a third interlayer insulation The second via 55 that fills the via hole formed so as to penetrate the film 13 and reach the second wiring layer 52, the bonding pads 63 to 66 formed on the second via 55, and the bonding pads 63 to 66 are covered. Formed with a bonding pad A protective film 14 an opening for exposing the surface of the de 63-66 are formed, and a. The bonding pads 63 and 64 exposed from the protective film 14 are connected to each other via bonding wires 72, and the bonding pads 65 and 66 exposed from the protective film 14 are connected to each other via bonding wires 73. Has been.
　上記の半導体装置の構造を採用することによっても、交差する配線のうち、一方の配線が第１配線層５１で構成され、他方の配線がボンディングワイヤ７１～７３で構成されているので、交差する配線間の離隔距離を長めにとることが可能となるため、配線間容量が小さくなり、アイソレーション特性を向上することができる。 Also by adopting the structure of the semiconductor device described above, one of the intersecting wirings is composed of the first wiring layer 51 and the other wiring is composed of the bonding wires 71 to 73, so that they intersect. Since the separation distance between the wirings can be made longer, the capacitance between the wirings can be reduced and the isolation characteristics can be improved.
　 [比較例２]
　図１３は本発明の第１の実施の形態のその他の比較例として例示する半導体装置の回路構成図である。図１４は、図１３に示す半導体装置の切断線Ｂ－Ｂ’における断面図である。 [Comparative Example 2]
FIG. 13 is a circuit configuration diagram of a semiconductor device exemplified as another comparative example of the first embodiment of the present invention. FIG. 14 is a cross-sectional view of the semiconductor device shown in FIG. 13 taken along section line BB ′.
　図１３に示す半導体装置は、モジュール基板やプリント配線板等の実装基板１００上に、半導体ＳＰＤＴ（single pole dual throw）スイッチ１２１～１２４から成る２入力４出力タイプの半導体ＳＰＤＴスイッチ回路１２０を備えている。 The semiconductor device shown in FIG. 13 includes a two-input four-output type semiconductor SPDT switch circuit 120 including semiconductor SPDT (single pole dual pole) switches 121 to 124 on a mounting board 100 such as a module board or a printed wiring board. Yes.
　半導体ＳＰＤＴスイッチ１２１～１２４は、図１５に示されるように、第１入力端子３３と出力端子４５との間及び第２入力端子３４及び出力端子４５との間において、ｎ（ｎは自然数）個のＭＯＳトランジスタＭ１～Ｍｎが各ドレイン端子及びソース端子において直列に接続されて電流経路が形成され、かつＭＯＳトランジスタＭ１～Ｍｎの各ゲート端子が抵抗を介して、制御電圧Ｖｂ＋が印加される制御電圧端子と接続されている。また、第１入力端子３３とグランドとの間及び第２入力端子３４とグランドとの間において、ｋ（ｋは自然数）個のＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋが各ドレイン端子及びソース端子において直列に接続されて電流経路が形成され、かつＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋの各ゲート端子が抵抗を介して、制御電圧Ｖｂ－が印加される制御電圧端子と接続されている。この構成により、ＭＯＳトランジスタＭ１～Ｍｎを制御する制御電圧端子と、ＭＯＳトランジスタＭｎ＋１～Ｍｎ＋ｋを制御する制御電圧端子と、にそれぞれ適切な制御電圧Ｖｂ＋，Ｖｂ－が印加されることで、第１入力端子３１及び第２入力端子３２を、第１乃至第４出力端子４１～４４のうちそれぞれ異なる出力端子に接続する経路を選択できる。 As shown in FIG. 15, there are n semiconductor SPDT switches 121 to 124 between the first input terminal 33 and the output terminal 45 and between the second input terminal 34 and the output terminal 45 (n is a natural number). MOS transistors M1 to Mn are connected in series at each drain terminal and source terminal to form a current path, and each gate terminal of the MOS transistors M1 to Mn is a control voltage to which a control voltage Vb + is applied via a resistor. Connected to the terminal. In addition, between the first input terminal 33 and the ground and between the second input terminal 34 and the ground, k (k is a natural number) MOS transistors Mn + 1 to Mn + k are connected in series at each drain terminal and source terminal. Thus, a current path is formed, and each gate terminal of the MOS transistors Mn + 1 to Mn + k is connected via a resistor to a control voltage terminal to which the control voltage Vb− is applied. With this configuration, appropriate control voltages Vb + and Vb− are applied to the control voltage terminal for controlling the MOS transistors M1 to Mn and the control voltage terminal for controlling the MOS transistors Mn + 1 to Mn + k, respectively. A path for connecting the terminal 31 and the second input terminal 32 to different output terminals among the first to fourth output terminals 41 to 44 can be selected.
　図１３に示す半導体装置では、第１入力端子３１と半導体ＳＰＤＴスイッチ群１２０との間を接続する配線と、第２入力端子３２と半導体ＳＰＤＴスイッチ群１２０との間を接続する配線と、が実装基板１００の厚み方向から見て交差している箇所が発生している。図１３、図１４に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。この交差する配線のうち、一方の配線を半導体基板１０上に形成される第１基板配線層１５１としており、他方の配線を半導体基板１０上に形成される第２基板配線層１５２としている。つまり、第１基板配線層１５１と第２基板配線層１５２とが実装基板１００の厚み方向から見て交差している。 In the semiconductor device shown in FIG. 13, wiring that connects the first input terminal 31 and the semiconductor SPDT switch group 120 and wiring that connects the second input terminal 32 and the semiconductor SPDT switch group 120 are mounted. Intersections occur when viewed from the thickness direction of the substrate 100. A portion surrounded by a broken-line ellipse shown in FIGS. 13 and 14 represents the intersecting portion. Among the intersecting wirings, one wiring is a first substrate wiring layer 151 formed on the semiconductor substrate 10, and the other wiring is a second substrate wiring layer 152 formed on the semiconductor substrate 10. That is, the first substrate wiring layer 151 and the second substrate wiring layer 152 intersect when viewed from the thickness direction of the mounting substrate 100.
　また、図１３に示す半導体装置は、図１４に示されるように、実装基板１００の一方の平面上には第１基板配線層１５１が形成され、実装基板１００の他方の平面上には第２基板配線層１５２が形成されている。なお、第１基板配線層１５１と第２基板配線層１５２とを接続する箇所では、実装基板１００を貫通するビアホールを埋める基板ビア１５４が形成されている。そして、実装基板１００の双方の平面に形成された第１基板配線層１５１及び第２基板配線層１５２を覆うように実装基板１００を封止させるモールド樹脂層１１０が形成されている。 In the semiconductor device shown in FIG. 13, the first substrate wiring layer 151 is formed on one plane of the mounting substrate 100 and the second plane of the mounting substrate 100 is second as shown in FIG. A substrate wiring layer 152 is formed. A substrate via 154 that fills a via hole penetrating the mounting substrate 100 is formed at a location where the first substrate wiring layer 151 and the second substrate wiring layer 152 are connected. A mold resin layer 110 for sealing the mounting substrate 100 is formed so as to cover the first substrate wiring layer 151 and the second substrate wiring layer 152 formed on both planes of the mounting substrate 100.
　ここで、互いに交差する第１基板配線層１５１と第２基板配線層１５２との間の離隔距離は、実装基板１００の厚み（配線層間）相当の距離となっている。一般的に、半導体基板１０上に形成される配線層間距離は１（μｍ）程度であるのに対して、実装基板１００の厚みは０．１～０．２（ｍｍ）程度もあるので、配線間容量が小さくなり、アイソレーション特性を向上することができる。 Here, the separation distance between the first substrate wiring layer 151 and the second substrate wiring layer 152 that intersect with each other is a distance corresponding to the thickness (wiring layer) of the mounting substrate 100. Generally, the distance between wiring layers formed on the semiconductor substrate 10 is about 1 (μm), whereas the thickness of the mounting substrate 100 is about 0.1 to 0.2 (mm). The interspace capacity is reduced, and the isolation characteristics can be improved.
 [効果]
　比較例１の場合、半導体基板１０上にボンディングワイヤ７１～７３を接続するためには、半導体基板１０上に直径５０（μｍ）から１００（μｍ）程度の大きさのボンディングパッド６１～６６が形成される必要がある。現行の携帯端末では、マルチモード、マルチバンド、アンテナダイバーシティ、及びMIMO等への対応に伴って、アンテナ本数、アンテナからの高周波回路への接続経路、入出力端子数、及び半導体スイッチの個数の増加が予測されている。このため、配線同士が交差している箇所が増加した場合には、半導体基板１０上に形成されるべきボンディングパッドの個数が増え、ひいては半導体基板１０の面積が増大することになる。 [effect]
In the case of the comparative example 1, in order to connect the bonding wires 71 to 73 on the semiconductor substrate 10, bonding pads 61 to 66 having a diameter of about 50 (μm) to 100 (μm) are formed on the semiconductor substrate 10. Need to be done. In the current portable terminal, the number of antennas, the connection path from the antenna to the high-frequency circuit, the number of input / output terminals, and the number of semiconductor switches are increased with the support for multimode, multiband, antenna diversity, MIMO, etc. Is predicted. For this reason, when the number of locations where wirings intersect each other increases, the number of bonding pads to be formed on the semiconductor substrate 10 increases, and as a result, the area of the semiconductor substrate 10 increases.
　比較例２の場合、実装基板１００上で比較的面積の大きい半導体ＳＰＤＴスイッチを除いた領域で入出力端子間の配線を引き回す必要がある。このため、半導体ＳＰＤＴスイッチ回路よりも大きい面積の実装基板１００が用いられる必要があり、実装基板１００上に部品を搭載して構成されるモジュールのサイズが大きくなる。 In the case of the comparative example 2, it is necessary to route the wiring between the input / output terminals in a region on the mounting substrate 100 excluding the semiconductor SPDT switch having a relatively large area. For this reason, it is necessary to use the mounting substrate 100 having an area larger than that of the semiconductor SPDT switch circuit, and the size of the module configured by mounting components on the mounting substrate 100 increases.
　一方、第１の実施の形態の場合、通常の半導体基板１０上に形成される第１配線層５１と第２配線層５２との配線層間距離は約1（μm）であるのに対し、第１配線層５１と第１再配線層２５１との間の離隔距離は約１０（μm）であり、半導体基板１０上の配線層間距離の約１０倍である。このため、配線間容量は約１０分の１以下にすることができ、配線間容量を介して複数の入力端子間で信号が互いに漏洩することに伴うアイソレーションの劣化を抑制することができる。 On the other hand, in the case of the first embodiment, the wiring interlayer distance between the first wiring layer 51 and the second wiring layer 52 formed on the normal semiconductor substrate 10 is about 1 (μm), whereas The separation distance between the one wiring layer 51 and the first rewiring layer 251 is about 10 (μm), which is about 10 times the distance between the wiring layers on the semiconductor substrate 10. For this reason, the inter-wiring capacity can be reduced to about 1/10 or less, and the degradation of isolation due to the leakage of signals between the plurality of input terminals via the inter-wiring capacity can be suppressed.
　また、半導体基板１０上にウェハＣＳＰプロセスの再配線層を形成する場合に、比較例１と同様に、半導体基板１０上に形成される第２配線層５２とウェハＣＳＰプロセスの第１再配線層２５１とを接続するためのパッド６０が形成されている。しかし、パッド６０の直径は３０（μm）程度で第１再配線層ビア２５４と接続可能であり、かつパッド６０は半導体基板１０上に形成された素子上に形成可能である。このため、多数のパッド６０が形成される必要が生じても、半導体基板１０の面積を増大させる必要性は無いため、半導体装置のサイズ及びコストを抑制できる。 Further, when the redistribution layer of the wafer CSP process is formed on the semiconductor substrate 10, the second wiring layer 52 formed on the semiconductor substrate 10 and the first redistribution layer of the wafer CSP process are formed as in Comparative Example 1. A pad 60 for connecting to H.251 is formed. However, the pad 60 has a diameter of about 30 (μm) and can be connected to the first rewiring layer via 254, and the pad 60 can be formed on an element formed on the semiconductor substrate 10. For this reason, even if it is necessary to form a large number of pads 60, there is no need to increase the area of the semiconductor substrate 10, so that the size and cost of the semiconductor device can be suppressed.
 　[変形例]
　図５は本発明の第１の実施の形態に係る半導体装置の変形例の回路構成図である。 [Modification]
FIG. 5 is a circuit configuration diagram of a modification of the semiconductor device according to the first embodiment of the present invention.
　上記の実施の形態と相違する点は、第１入力端子３１及び第２入力端子３２と半導体スイッチ回路２０との間を接続する配線同士は半導体基板１０の厚み方向から見て交差していないが、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士が半導体基板１０の厚み方向から見て交差している点である。図５に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。 The difference from the above embodiment is that the wirings connecting the first input terminal 31 and the second input terminal 32 and the semiconductor switch circuit 20 do not intersect each other when viewed from the thickness direction of the semiconductor substrate 10. In other words, the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the semiconductor substrate 10. A portion surrounded by a broken-line ellipse shown in FIG. 5 represents this intersecting portion.
　具体的には、第１出力端子４１と半導体スイッチ２５との間を接続する配線の一部である第１配線層５１は、第２出力端子４２と半導体スイッチ２２との間を接続する配線の一部である第１再配線層２５１と、第３出力端子４３と半導体スイッチ２３との間を接続する配線の一部である第１再配線層２５１と、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１とそれぞれ交差している。 Specifically, the first wiring layer 51, which is part of the wiring that connects the first output terminal 41 and the semiconductor switch 25, is a wiring that connects the second output terminal 42 and the semiconductor switch 22. The first redistribution layer 251 which is a part, the first redistribution layer 251 which is a part of the wiring connecting the third output terminal 43 and the semiconductor switch 23, the fourth output terminal 44 and the semiconductor switch 24 And the first rewiring layer 251 that is a part of the wiring connecting the two.
　第２出力端子４２と半導体スイッチ２６との間を接続する配線の一部である第１配線層５１は、第３出力端子４３と半導体スイッチ２３との間を接続する配線の一部である第１再配線層２５１と、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１とそれぞれ交差している。 The first wiring layer 51, which is a part of the wiring that connects the second output terminal 42 and the semiconductor switch 26, is a part of the wiring that connects the third output terminal 43 and the semiconductor switch 23. The first redistribution layer 251 intersects with the first redistribution layer 251 which is a part of the wiring connecting the fourth output terminal 44 and the semiconductor switch 24.
　第３出力端子４３と半導体スイッチ２７との間を接続する配線の一部である第１配線層５１は、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１と交差している。 The first wiring layer 51, which is a part of wiring that connects the third output terminal 43 and the semiconductor switch 27, is a part of wiring that connects the fourth output terminal 44 and the semiconductor switch 24. 1 crosses the rewiring layer 251.
　このように、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士が半導体基板１０の厚み方向から見て交差している箇所において、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されていてもよい。この構造によっても、上記の第１の実施の形態と同様の効果が得られる。 As described above, at the place where the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the semiconductor substrate 10, the first wiring is connected to the first wiring. The rewiring layer 251 may be used, and the first wiring layer 51 may be used for the other wiring. Also with this structure, the same effect as in the first embodiment can be obtained.
　また、第１及び第２入力端子３１，３２のうちある入力端子と半導体スイッチ回路２０との間を接続する配線と、第１乃至第４出力端子４１～４４のうちある出力端子と半導体スイッチ回路２０との間を接続する配線とが半導体基板１０の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されてもよい。
（第２の実施の形態）
　[半導体装置の構造]
　図６は、本発明の第２の実施の形態に係る半導体装置の回路構成図である。図７は、図６に示す半導体装置の切断線Ｄ－Ｄ’における断面図である。 Also, a wiring for connecting between an input terminal of the first and second input terminals 31 and 32 and the semiconductor switch circuit 20, and an output terminal of the first to fourth output terminals 41 to 44 and the semiconductor switch circuit The first redistribution layer 251 is used for one of the intersecting wirings, and the other wiring is connected to a wiring that connects to the wiring 20 when viewed from the thickness direction of the semiconductor substrate 10. The first wiring layer 51 may be used.
(Second Embodiment)
[Structure of semiconductor device]
FIG. 6 is a circuit configuration diagram of a semiconductor device according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view of the semiconductor device shown in FIG.
　第１の実施の形態と相違する点は、半導体基板１０の代わりに、絶縁性のサファイア基板３３６上にシリコン系半導体層が形成されたＳＯＳ（Silicon On Sapphire）基板が使用されている点である。 A difference from the first embodiment is that an SOS (Silicon On Sapphire) substrate in which a silicon-based semiconductor layer is formed on an insulating sapphire substrate 336 is used instead of the semiconductor substrate 10. .
　なお、第１の実施の形態と同様に、半導体スイッチ２１～２８は、図３又は図４に示されるように構成されている。 In addition, as in the first embodiment, the semiconductor switches 21 to 28 are configured as shown in FIG. 3 or FIG.
　また、図７に示されるように、第１入力端子３１から半導体スイッチ回路２０に向けて延設される配線と第２入力端子３２から半導体スイッチ回路２０に向けて延設される配線とがサファイア基板３３６の厚み方向から見て交差している箇所において、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されている点も同様である。 Further, as shown in FIG. 7, a wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20 and a wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20 are sapphire. The same applies to the point where the first rewiring layer 251 is used for one wiring and the first wiring layer 51 is used for the other wiring at a location intersecting when viewed from the thickness direction of the substrate 336.
　詳述すると、図６に示す半導体装置は、サファイア基板３３６と、サファイア基板３３６を覆うように形成されたバリアＳｉＯ２３３４と、バリアＳｉＯ２３３４上に形成された表面シリコン層３１３と、を備えた半導体基板を使用している。 Specifically, the semiconductor device shown in FIG. 6 includes a sapphire substrate 336, a barrier SiO 2 334 formed so as to cover the sapphire substrate 336, and a surface silicon layer 313 formed on the barrier SiO 2 334. A semiconductor substrate is used.
　また、サファイア基板３３６上の表面シリコン層３１３を覆うように形成された第１層間絶縁膜１１と、第１層間絶縁膜１１上に形成された第１配線層５１と、第１配線層５１を覆うように形成された第２層間絶縁膜１２と、第２層間絶縁膜１２上に形成された第２配線層５２と、第２配線層５２を覆うように形成された第３層間絶縁膜１３と、第３層間絶縁膜１３を貫通して第２配線層５２に至るように形成されたビアホールを埋める第２ビア５５と、第２ビア５５上に形成されたパッド６０と、パッド６０を覆うように形成され、かつパッド６０の表面を露出させる開口部が形成された保護膜１４と、を備えている。なお、図７には示されていないが、第２層間絶縁膜１２を貫通して第１配線層５１に至り、かつ第２配線層５２と第１配線層５１との間を連結させるように形成されたビアホールを埋める第１ビア５４が形成されている。 The first interlayer insulating film 11 formed so as to cover the surface silicon layer 313 on the sapphire substrate 336, the first wiring layer 51 formed on the first interlayer insulating film 11, and the first wiring layer 51 Second interlayer insulating film 12 formed to cover, second wiring layer 52 formed on second interlayer insulating film 12, and third interlayer insulating film 13 formed to cover second wiring layer 52 A second via 55 that fills the via hole formed so as to penetrate the third interlayer insulating film 13 and reach the second wiring layer 52, a pad 60 formed on the second via 55, and the pad 60. And a protective film 14 formed with an opening that exposes the surface of the pad 60. Although not shown in FIG. 7, it penetrates through the second interlayer insulating film 12 to the first wiring layer 51 and connects the second wiring layer 52 and the first wiring layer 51. A first via 54 that fills the formed via hole is formed.
　さらに、図６に示す半導体装置は、保護膜１４及び保護膜１４から露出されたパッド６０を覆うように形成された第１再配線層間絶縁膜１１１と、第１再配線層間絶縁膜１１１を貫通してパッド６０に至るように形成されたビアホールを埋める再配線層ビア２５４と、再配線層ビア２５４上に形成された第１再配線層パッド２６１と、第１再配線層間絶縁膜１１１上に、かつ隣り合う第１再配線層パッド２６１との間を連結するように形成された第１再配線層２５１と、第１再配線層パッド２６１及び第１再配線層２５１を覆うように形成された第２再配線層間絶縁膜１１２と、半導体装置全体を封止させるように形成されたモールド樹脂層１１０と、を備えている。 Furthermore, the semiconductor device shown in FIG. 6 penetrates the first redistribution interlayer insulating film 111 formed so as to cover the protective film 14 and the pad 60 exposed from the protective film 14, and the first redistribution interlayer insulating film 111. The rewiring layer via 254 filling the via hole formed to reach the pad 60, the first rewiring layer pad 261 formed on the rewiring layer via 254, and the first rewiring interlayer insulating film 111 In addition, the first redistribution layer 251 formed to connect the adjacent first redistribution layer pads 261, and the first redistribution layer pad 261 and the first redistribution layer 251 are formed to be covered. A second redistribution interlayer insulating film 112 and a mold resin layer 110 formed so as to seal the entire semiconductor device.
　第１配線層５１と第１再配線層２５１とが断面視において対向して形成される箇所では、第１配線層５１から第１再配線層２５１に向う方向で、約1（μm）の厚さの第２層間絶縁膜１２及び第３層間絶縁膜１３と、約3（μm）の厚さの保護膜１４と、約5（μm）の厚さの第１再配線層間絶縁膜１１１とがこの順に形成されている。 At a location where the first wiring layer 51 and the first rewiring layer 251 are formed to face each other in a cross-sectional view, the thickness is about 1 (μm) in the direction from the first wiring layer 51 to the first rewiring layer 251. A second interlayer insulating film 12 and a third interlayer insulating film 13, a protective film 14 having a thickness of about 3 (μm), and a first redistribution interlayer insulating film 111 having a thickness of about 5 (μm). They are formed in this order.
　図１８は、半導体スイッチ２１～２８を構成するＭＯＳトランジスタＭｊ（ｊ＝１～ｎ＋ｋ）の構造を示した図である。図１８に示されるように、サファイア基板３３６を覆うようにバリアＳｉＯ２３３４が形成され、バリアＳｉＯ２３３４上にフィールド酸化膜３３５が形成され、フィールド酸化膜３３５のウェル領域において表面シリコン層３１３及びその両側にＮ型拡散領域３１１が形成される。各Ｎ型拡散領域３１１からソース端子３０２、ドレイン端子３０３が取り出されている。また、表面シリコン層３１３上にはゲート酸化膜３０１が形成され、このゲート酸化膜３０１の上に形成されたゲート電極からゲート端子３００が取り出されている。なお、表面シリコン層３１３とサファイア基板３３６との間及び２つのＮ型拡散領域３１１とサファイア基板３３６との間には、それぞれゲート－基板間容量Ｃｇｂ、ソース－基板間容量Ｃｓｓｕｂ、ドレイン－基板間容量Ｃｄｓｕｂが生じている。 FIG. 18 is a diagram showing the structure of MOS transistors Mj (j = 1 to n + k) constituting the semiconductor switches 21 to 28. In FIG. As shown in FIG. 18, a barrier SiO 2 334 is formed so as to cover the sapphire substrate 336, a field oxide film 335 is formed on the barrier SiO 2 334, and the surface silicon layer 313 and the well region of the field oxide film 335 are formed. N-type diffusion regions 311 are formed on both sides thereof. A source terminal 302 and a drain terminal 303 are taken out from each N-type diffusion region 311. A gate oxide film 301 is formed on the surface silicon layer 313, and the gate terminal 300 is taken out from the gate electrode formed on the gate oxide film 301. Note that, between the surface silicon layer 313 and the sapphire substrate 336 and between the two N-type diffusion regions 311 and the sapphire substrate 336, a gate-substrate capacitance Cgb, a source-substrate capacitance Cssub, and a drain-substrate interval, respectively. A capacitance Cdsub is generated.
　[半導体装置の製造方法]
　第１の実施の形態と相違する点は、半導体基板としてＳＯＳ基板が使用されている点であり、まずＣＶＤ等によりサファイア基板３３６の上にバリアＳｉＯ２３３４が形成された後、このバリアＳｉＯ２３３４上に表面シリコン層３１３が形成される。この後のプロセスは、第１の実施の形態と同様である。 [Method for Manufacturing Semiconductor Device]
A difference from the first embodiment is that an SOS substrate is used as a semiconductor substrate. After a barrier SiO 2 334 is formed on a sapphire substrate 336 by CVD or the like, this barrier SiO 2 is first formed. A surface silicon layer 313 is formed on 334. The subsequent processes are the same as those in the first embodiment.
　[比較例３]
　図１６は本発明の第２の実施の形態の比較例として例示する半導体装置の回路構成図である。 [Comparative Example 3]
FIG. 16 is a circuit configuration diagram of a semiconductor device exemplified as a comparative example of the second embodiment of the present invention.
　図１６に示す半導体装置は、図１に示した回路構成に加えて、第１入力端子３１と接続された半導体スイッチ２１，２３，２５，２７外周部のゲート酸化膜を除去して形成された基板コンタクト２７１と、各基板コンタクト２７１と接続され、かつ各基板コンタクト２７１をパッケージ外のグランドへと接続するためのＰ型基板端子２８１と、第２入力端子３２と接続された半導体スイッチ２２，２４，２６，２８外周部のゲート酸化膜を除去して形成された基板コンタクト２７２と、各基板コンタクト２７２と接続され、かつ各基板コンタクト２７２をパッケージ外のグランドへと接続するためのＰ型基板端子２８２と、を備えている。 The semiconductor device shown in FIG. 16 is formed by removing the gate oxide film on the outer periphery of the semiconductor switches 21, 23, 25, and 27 connected to the first input terminal 31 in addition to the circuit configuration shown in FIG. Semiconductor switches 22, 24 connected to the substrate contacts 271, P-type substrate terminals 281 connected to the substrate contacts 271, and connected to the ground outside the package, and the second input terminal 32. , 26, 28, and a substrate contact 272 formed by removing the gate oxide film on the outer periphery, and a P-type substrate terminal connected to each substrate contact 272 and connecting each substrate contact 272 to the ground outside the package 282.
　図１６に示される半導体スイッチ２１～２８は、図３、図４に示されるように、ＭＯＳトランジスタＭｊ（ｊ＝１～ｎ＋ｋ）によって構成される。 16 are constituted by MOS transistors Mj (j = 1 to n + k) as shown in FIGS. 3 and 4.
　図１７は、図１６に示される半導体スイッチ２１～２８を構成するＭＯＳトランジスタの構造を示した図である。図１７に示されるように、半導体基板１０上の所定領域にフィールド酸化膜３３５が形成され、フィールド酸化膜３３５のウェル領域においてＮ型拡散領域３１１が形成されている。各Ｎ型拡散領域３１１からソース端子３０２、ドレイン端子３０３が取り出されている。また、各Ｎ型拡散領域３１１の間の領域の上にはゲート酸化膜３０１が形成され、このゲート酸化膜３０１の上に形成されたゲート電極からゲート端子３００が取り出されている。 FIG. 17 is a diagram showing the structure of the MOS transistors constituting the semiconductor switches 21 to 28 shown in FIG. As shown in FIG. 17, a field oxide film 335 is formed in a predetermined region on the semiconductor substrate 10, and an N-type diffusion region 311 is formed in the well region of the field oxide film 335. A source terminal 302 and a drain terminal 303 are taken out from each N-type diffusion region 311. A gate oxide film 301 is formed on the region between the N-type diffusion regions 311, and the gate terminal 300 is taken out from the gate electrode formed on the gate oxide film 301.
　なお、ゲート酸化膜３０１と半導体基板１０との間及び２つのＮ型拡散領域３１１と半導体基板１０との間には、それぞれゲート－基板間容量Ｃｇｂ、ソース－基板間容量Ｃｓｂ、ドレイン－基板間容量Ｃｄｂが生じている。これらの容量Ｃｇｂ、Ｃｓｂ、Ｃｄｂは、Ｐ型基板抵抗３１５を介して、不図示の他のＭＯＳトランジスタの容量Ｃｇｂ、Ｃｓｂ、Ｃｄｂと接続されるので、ＭＯＳトランジスタＭｊ間のアイソレーションが悪くなる。 Note that, between the gate oxide film 301 and the semiconductor substrate 10 and between the two N-type diffusion regions 311 and the semiconductor substrate 10, a gate-substrate capacitance Cgb, a source-substrate capacitance Csb, and a drain-substrate interval, respectively. A capacitance Cdb is generated. Since these capacitors Cgb, Csb, and Cdb are connected to the capacitors Cgb, Csb, and Cdb of other MOS transistors (not shown) through the P-type substrate resistor 315, the isolation between the MOS transistors Mj is deteriorated.
　このため、図１６に示されるように、ＭＯＳトランジスタＭｊ間のアイソレーションを改善するために、半導体基板１０上に基板コンタクト２７１，２７２が設けられ、かつ基板コンタクト２７１，２７２をグランドなどに接続してＰ型基板抵抗３１５のインピーダンスを低くするためのＰ型基板端子２８１，２８２が設けられている。 Therefore, as shown in FIG. 16, in order to improve the isolation between the MOS transistors Mj, the substrate contacts 271 and 272 are provided on the semiconductor substrate 10, and the substrate contacts 271 and 272 are connected to the ground or the like. P-type substrate terminals 281 and 282 for reducing the impedance of the P-type substrate resistor 315 are provided.
　[効果]
　比較例３の場合、半導体スイッチを構成するＭＯＳトランジスタ間のアイソレーション特性を向上させるために、半導体スイッチ２１～２８外周部に基板コンタクト２７１，２７２が設けられ、かつそれらを外部のグランドに接続して基板のインピーダンスを下げるためのＰ型基板端子２８１，２８２が設けられている。なお、ＣＳＰの場合、搭載可能な端子数はチップサイズに依存するので、外部端子数を極力少なくすることが重要である。従って、Ｐ型基板端子２８１，２８２が設けられると、信号の授受をしない端子が余分に設けられることになるため、半導体装置のサイズ及びコストの増大を招くことになる。 [effect]
In the case of the comparative example 3, in order to improve the isolation characteristics between the MOS transistors constituting the semiconductor switch, substrate contacts 271 and 272 are provided on the outer periphery of the semiconductor switches 21 to 28, and these are connected to an external ground. P-type substrate terminals 281 and 282 are provided for lowering the impedance of the substrate. In the case of CSP, since the number of terminals that can be mounted depends on the chip size, it is important to reduce the number of external terminals as much as possible. Therefore, when the P-type substrate terminals 281 and 282 are provided, extra terminals that do not transmit and receive signals are provided, which increases the size and cost of the semiconductor device.
　一方、第２の実施の形態の場合、図１８に示されるサファイア基板３３６のサファイア基板抵抗３３３は、１ｘ１０１２（Ωcm）と非常に大きいため、サファイア基板抵抗３３３を介して他のＭＯＳトランジスタの各容量Ｃｇｂ，Ｃｓｂ，Ｃｄｂに向けて入力信号が漏洩されにくく、サファイア基板３３６に形成されたＭＯＳトランジスタＭｊ間のアイソレーションが非常に高い。このため、比較例３のように、基板コンタクト２７１，２７２、及びＰ型基板端子２８１，２８２が設けられる必要がない。このように、サファイア基板３３６が使用されることで、半導体装置のサイズ及びコストを低減できる。 On the other hand, in the case of the second embodiment, since the sapphire substrate resistance 333 of the sapphire substrate 336 shown in FIG. 18 is as large as 1 × 10 12 (Ωcm), each MOS transistor is connected via the sapphire substrate resistance 333. Input signals are not easily leaked toward the capacitors Cgb, Csb, and Cdb, and the isolation between the MOS transistors Mj formed on the sapphire substrate 336 is very high. Therefore, unlike the comparative example 3, it is not necessary to provide the substrate contacts 271 and 272 and the P-type substrate terminals 281 and 282. As described above, the use of the sapphire substrate 336 can reduce the size and cost of the semiconductor device.
　さらに、上記の第２の実施の形態に係る半導体装置の構造が採用されると、上記の第１の実施の形態の効果と同様の効果が得られる。 Furthermore, when the structure of the semiconductor device according to the second embodiment is employed, the same effect as that of the first embodiment can be obtained.
　[変形例]
　図８は本発明の第２の実施の形態に係る半導体装置の変形例の回路構成図である。 [Modification]
FIG. 8 is a circuit configuration diagram of a modification of the semiconductor device according to the second embodiment of the present invention.
　上記の実施の形態と相違する点は、第１入力端子３１及び第２入力端子３２と半導体スイッチ回路２０との間を接続する配線同士は交差していないが、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士がサファイア基板３３６の厚み方向から見て交差している点である。図８に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。 The difference from the above embodiment is that the wirings connecting the first input terminal 31 and the second input terminal 32 and the semiconductor switch circuit 20 do not intersect with each other, but the first to fourth output terminals 41. That is, the wirings connecting between .about.44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the sapphire substrate 336. FIG. A portion surrounded by a broken-line ellipse shown in FIG. 8 represents this intersecting portion.
　具体的には、第１出力端子４１と半導体スイッチ２５との間を接続する配線の一部である第１配線層５１は、第２出力端子４２と半導体スイッチ２２との間を接続する配線の一部である第１再配線層２５１と、第３出力端子４３と半導体スイッチ２３との間を接続する配線の一部である第１再配線層２５１と、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１とそれぞれ交差している。 Specifically, the first wiring layer 51, which is part of the wiring that connects the first output terminal 41 and the semiconductor switch 25, is a wiring that connects the second output terminal 42 and the semiconductor switch 22. The first redistribution layer 251 which is a part, the first redistribution layer 251 which is a part of the wiring connecting the third output terminal 43 and the semiconductor switch 23, the fourth output terminal 44 and the semiconductor switch 24 And the first rewiring layer 251 that is a part of the wiring connecting the two.
　第２出力端子４２と半導体スイッチ２６との間を接続する配線の一部である第１配線層５１は、第３出力端子４３と半導体スイッチ２３との間を接続する配線の一部である第１再配線層２５１と、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１とそれぞれ交差している。 The first wiring layer 51, which is a part of the wiring that connects the second output terminal 42 and the semiconductor switch 26, is a part of the wiring that connects the third output terminal 43 and the semiconductor switch 23. The first redistribution layer 251 intersects with the first redistribution layer 251 which is a part of the wiring connecting the fourth output terminal 44 and the semiconductor switch 24.
　第３出力端子４３と半導体スイッチ２７との間を接続する配線の一部である第１配線層５１は、第４出力端子４４と半導体スイッチ２４との間を接続する配線の一部である第１再配線層２５１と交差している。 The first wiring layer 51, which is a part of wiring that connects the third output terminal 43 and the semiconductor switch 27, is a part of wiring that connects the fourth output terminal 44 and the semiconductor switch 24. 1 crosses the rewiring layer 251.
　このように、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士がサファイア基板３３６の厚み方向から見て交差している箇所において、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されていてもよい。 As described above, at the place where the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the sapphire substrate 336, the first wiring is connected to one wiring. The rewiring layer 251 may be used, and the first wiring layer 51 may be used for the other wiring.
　また、第１及び第２入力端子３１，３２のうちある入力端子と半導体スイッチ回路２０との間を接続する配線と、第１乃至第４出力端子４１～４４のうちある出力端子と半導体スイッチ回路２０との間を接続する配線とがサファイア基板３３６の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線に第１再配線層２５１が使用され、他方の配線に第１配線層５１が使用されてもよい。 Also, a wiring for connecting between an input terminal of the first and second input terminals 31 and 32 and the semiconductor switch circuit 20, and an output terminal of the first to fourth output terminals 41 to 44 and the semiconductor switch circuit The first redistribution layer 251 is used for one of the intersecting wirings and the other wiring is connected to the wiring connecting the wirings 20 to each other when viewed from the thickness direction of the sapphire substrate 336. The first wiring layer 51 may be used.
　また、ＳＯＳ基板は、バリアＳｉＯ２３３４を設けずに、サファイア基板３３６上に直接的に表面シリコン層３１３を形成して構成してもよい。
（第３の実施の形態）
　[半導体装置の構造]
　図９は、本発明の第３の実施の形態に係る半導体装置の回路構成図である。図１０は、図９に示す半導体装置の切断線Ｅ－Ｅ’における断面図である。
本発明の第１の実施の形態と相違する点は、上記の第２の実施の形態と同様に、半導体基板１０の代わりに絶縁性のサファイア基板３３６上にシリコン系半導体層が形成されたＳＯＳ（Silicon On Sapphire）基板が用いられている点である。さらに、本発明の第３の実施の形態に係る半導体装置では、上記の第２の実施の形態と異なり、ウェハレベルＣＳＰプロセスによって形成された再配線層が２層構造となっている。 Further, the SOS substrate may be configured by forming the surface silicon layer 313 directly on the sapphire substrate 336 without providing the barrier SiO 2 334.
(Third embodiment)
[Structure of semiconductor device]
FIG. 9 is a circuit configuration diagram of a semiconductor device according to the third embodiment of the present invention. FIG. 10 is a cross-sectional view of the semiconductor device shown in FIG. 9 taken along section line EE ′.
The difference from the first embodiment of the present invention is that an SOS in which a silicon-based semiconductor layer is formed on an insulating sapphire substrate 336 instead of the semiconductor substrate 10 is the same as the second embodiment. The (Silicon On Sapphire) substrate is used. Furthermore, in the semiconductor device according to the third embodiment of the present invention, unlike the second embodiment, the redistribution layer formed by the wafer level CSP process has a two-layer structure.
　図９に示す半導体装置の構成では、第１乃至第４出力端子４１～４４と半導体スイッチ回路２０との間を接続する配線同士は交差していないが、第１入力端子３１及び第２入力端子３２と半導体スイッチ回路２０との間を接続する配線同士がサファイア基板３３６の厚み方向から見て交差している箇所が存在する。図９、図１０に示される破線の楕円で囲まれた箇所が、この交差している箇所を表している。
第１入力端子３１と半導体スイッチ２３との間を接続する配線の一部である第２再配線層２５２は、第２入力端子３２と半導体スイッチ２２との間を接続する配線の一部である第１配線層５１と交差している。 In the configuration of the semiconductor device shown in FIG. 9, the wirings connecting the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 do not intersect with each other, but the first input terminal 31 and the second input terminal There are places where wirings connecting between the semiconductor switch circuit 20 and the semiconductor switch circuit 20 intersect each other when viewed from the thickness direction of the sapphire substrate 336. A portion surrounded by a broken-line ellipse shown in FIGS. 9 and 10 represents the intersecting portion.
The second rewiring layer 252 that is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 23 is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 22. Crosses the first wiring layer 51.
　第１入力端子３１と半導体スイッチ２５との間を接続する配線の一部である第２再配線層２５２は、第２入力端子３２と半導体スイッチ２４との間を接続する配線の一部である第１配線層５１と交差している。 The second rewiring layer 252 that is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 25 is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 24. Crosses the first wiring layer 51.
　第１入力端子３１と半導体スイッチ２７との間を接続する配線の一部である第１配線層５１は、第２入力端子３２と半導体スイッチ２６との間を接続する配線の一部である第２再配線層２５２と交差している。 The first wiring layer 51, which is a part of the wiring that connects the first input terminal 31 and the semiconductor switch 27, is a part of the wiring that connects the second input terminal 32 and the semiconductor switch 26. 2 intersects with the rewiring layer 252.
　このように、第１入力端子３１から半導体スイッチ回路２０に向けて延設される配線と第２入力端子３２から半導体スイッチ回路２０に向けて延設される配線とがサファイア基板３３６の厚み方向から見て交差している箇所において、一方の配線に第２再配線層２５２が使用され、他方の配線に第１配線層５１が使用されている。 Thus, the wiring extending from the first input terminal 31 toward the semiconductor switch circuit 20 and the wiring extending from the second input terminal 32 toward the semiconductor switch circuit 20 are formed from the thickness direction of the sapphire substrate 336. In a crossing position, the second rewiring layer 252 is used for one wiring, and the first wiring layer 51 is used for the other wiring.
　詳述すると、第３の実施の形態に係る半導体装置は、サファイア基板３３６と、サファイア基板３３６を覆うように形成されたバリアＳｉＯ２３３４と、バリアＳｉＯ２３３４上に形成された表面シリコン層３１３と、を備えたＳＯＳ（Silicon On Sapphire）基板を使用している。 Specifically, the semiconductor device according to the third embodiment includes a sapphire substrate 336, a barrier SiO 2 334 formed so as to cover the sapphire substrate 336, and a surface silicon layer 313 formed on the barrier SiO 2 334. The SOS (Silicon On Sapphire) board | substrate provided with these is used.
　また、サファイア基板３３６上の表面シリコン層３１３を覆うように形成された第１層間絶縁膜１１と、第１層間絶縁膜１１上に形成された第１配線層５１と、第１配線層５１を覆うように形成された第２層間絶縁膜１２と、第２層間絶縁膜１２上に形成された第２配線層５２と、第２配線層５２を覆うように形成された第３層間絶縁膜１３と、第３層間絶縁膜１３を覆うように形成された保護膜１４と、を備えている。 The first interlayer insulating film 11 formed so as to cover the surface silicon layer 313 on the sapphire substrate 336, the first wiring layer 51 formed on the first interlayer insulating film 11, and the first wiring layer 51 Second interlayer insulating film 12 formed to cover, second wiring layer 52 formed on second interlayer insulating film 12, and third interlayer insulating film 13 formed to cover second wiring layer 52 And a protective film 14 formed so as to cover the third interlayer insulating film 13.
　さらに、第３の実施の形態に係る半導体装置は、保護膜１４を覆うように形成された第１再配線層間絶縁膜１１１と、第１再配線層間絶縁膜１１１上に形成された第１再配線層パッド２６１と、第１再配線層絶縁膜１１１及び第１再配線層パッド２６１を覆うように形成された第２再配線層絶縁膜１１２と、第２再配線層絶縁膜１１２を貫通して第１再配線層パッド２６１に至るように形成されたビアホールを埋める第２再配線層ビア２５５と、第２再配線層ビア２５５上に形成された第２再配線層パッド２６２と、第２再配線層間絶縁膜１１２上に、かつ隣り合う第２再配線層パッド２６２との間を連結させるように形成された第２再配線層２５２と、第２再配線層パッド２６２及び第２再配線層２５２を覆うように形成された第３再配線層間絶縁膜１１３と、半導体装置全体を封止させるように形成されたモールド樹脂層１１０と、を備えている。 Furthermore, the semiconductor device according to the third embodiment includes a first redistribution interlayer insulating film 111 formed so as to cover the protective film 14, and a first redistribution interlayer insulating film 111 formed on the first redistribution interlayer insulating film 111. The wiring layer pad 261, the second rewiring layer insulating film 112 formed so as to cover the first rewiring layer insulating film 111 and the first rewiring layer pad 261, and the second rewiring layer insulating film 112 are penetrated. A second redistribution layer via 255 filling the via hole formed to reach the first redistribution layer pad 261, a second redistribution layer pad 262 formed on the second redistribution layer via 255, A second redistribution layer 252 formed on the redistribution interlayer insulating film 112 and connected to the adjacent second redistribution layer pad 262, the second redistribution layer pad 262, and the second redistribution layer Third redistribution formed to cover layer 252 An interlayer insulating film 113, and a mold resin layer 110 formed so as to hermetically seal the entire semiconductor device.
　第１配線層５１と第２再配線層２５２とが断面視において対向して形成される箇所では、第１配線層５１から第２再配線層２５２に向う方向で、約1（μm）の厚さの第２層間絶縁膜１２及び第３層間絶縁膜１３と、約3（μm）の厚さの保護膜１４と、約5（μm）の厚さの第１再配線層間絶縁膜１１１及び第２再配線層間絶縁膜１１２とがこの順に形成されている。　
[半導体装置の製造方法]
　第２の実施の形態と相違する点は、ウェハレベルＣＳＰプロセスによって形成された再配線層が２層構造となっている点であり、第２再配線層間絶縁膜１１２上に第２再配線層パッド２６２及び第２再配線層２５２が形成された後では、ＣＶＤ等により第２再配線層パッド２６２及び第２再配線層２５２を覆うように第２再配線層間絶縁膜１１２の上に第３再配線層間絶縁膜１１３が形成され、さらに第３再配線層間絶縁膜１１３の上にモールド樹脂層１１０が形成される。 At a location where the first wiring layer 51 and the second rewiring layer 252 are formed to face each other in a cross-sectional view, the thickness is about 1 (μm) in the direction from the first wiring layer 51 to the second rewiring layer 252. The second interlayer insulating film 12 and the third interlayer insulating film 13, the protective film 14 having a thickness of about 3 (μm), the first rewiring interlayer insulating film 111 having a thickness of about 5 (μm), and the first Two rewiring interlayer insulating films 112 are formed in this order.
[Method for Manufacturing Semiconductor Device]
The difference from the second embodiment is that the rewiring layer formed by the wafer level CSP process has a two-layer structure, and the second rewiring layer is formed on the second rewiring interlayer insulating film 112. After the pad 262 and the second redistribution layer 252 are formed, the third redistribution layer insulating film 112 is covered on the second redistribution interlayer insulating film 112 so as to cover the second redistribution layer pad 262 and the second redistribution layer 252 by CVD or the like. A rewiring interlayer insulating film 113 is formed, and a mold resin layer 110 is formed on the third rewiring interlayer insulating film 113.
　 [効果]
　第１配線層５１と第２再配線層２５２との間の離隔距離は約１５（μm）の距離があり、第２の実施の形態の場合の第１配線層５１と第１再配線層２５１との離隔距離と比べて５（μm）程度長くなっている。このため、第２の実施の形態よりも、配線間容量を小さくすることができ、配線間容量を介して信号が相互に漏洩することに伴うアイソレーションの劣化をより確実に抑制できる。 [effect]
The separation distance between the first wiring layer 51 and the second rewiring layer 252 is about 15 (μm), and the first wiring layer 51 and the first rewiring layer 251 in the case of the second embodiment. It is about 5 (μm) longer than the separation distance. For this reason, the inter-wiring capacity can be made smaller than in the second embodiment, and the deterioration of isolation due to the leakage of signals to each other through the inter-wiring capacity can be more reliably suppressed.
　また、上記の第３の実施の形態に係る半導体装置の構造が採用されることで、上記の第２の実施の形態の効果と同様の効果が得られる。 Further, by adopting the structure of the semiconductor device according to the third embodiment, the same effects as those of the second embodiment can be obtained.
　[変形例]
　第１乃至第４出力端子４１～４４のうちある出力端子と半導体スイッチ回路２０との間を接続する配線と、その他のある出力端子と半導体スイッチ回路２０との間を接続する配線とがサファイア基板３３６の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線に第２再配線層２５２が使用され、他方の配線に第１配線層５１が使用されていてもよい。 [Modification]
Wirings connecting one output terminal of the first to fourth output terminals 41 to 44 and the semiconductor switch circuit 20 and wiring connecting another output terminal and the semiconductor switch circuit 20 are sapphire substrates. Of the intersecting wirings, the second rewiring layer 252 may be used for one of the intersecting wirings, and the first wiring layer 51 may be used for the other wiring. .
　第１及び第２入力端子３１，３２のうちある入力端子と半導体スイッチ回路２０との間を接続する配線と、第１乃至第４出力端子４１～４４のうちある出力端子と半導体スイッチ回路２０との間を接続する配線とがサファイア基板３３６の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線に第２再配線層２５２が使用され、他方の配線に第１配線層５１が使用されていてもよい。 A wiring that connects between an input terminal of the first and second input terminals 31 and 32 and the semiconductor switch circuit 20, an output terminal of the first to fourth output terminals 41 to 44, and the semiconductor switch circuit 20; The second redistribution layer 252 is used for one of the intersecting wirings and the first wiring for the other wiring at a location where the wirings connecting the two intersect with each other as viewed from the thickness direction of the sapphire substrate 336. The wiring layer 51 may be used.
　また、ＳＯＳ基板は、バリアＳｉＯ２３３４を設けずに、サファイア基板３３６上に直接的に表面シリコン層３１３を形成して構成してもよい。 Further, the SOS substrate may be configured by forming the surface silicon layer 313 directly on the sapphire substrate 336 without providing the barrier SiO 2 334.
　上記説明から、当業者にとっては、本発明の多くの改良や他の実施形態が明らかである。従って、上記説明は、例示としてのみ解釈されるべきであり、本発明を実行する最良の態様を当業者に教示する目的で提供されたものである。本発明の精神を逸脱することなく、その構造及び／又は機能の詳細を実質的に変更できる。 From the above description, many modifications and other embodiments of the present invention are apparent to persons skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.
　本発明は、携帯端末の高周波回路向けとして複数の入出力端子間の接続経路を半導体スイッチにより切り替える半導体装置にとって有用である。 The present invention is useful for a semiconductor device in which a connection path between a plurality of input / output terminals is switched by a semiconductor switch for a high-frequency circuit of a portable terminal.
１０　半導体基板
１１　第１層間絶縁膜
１２　第２層間絶縁膜
１３　第３層間絶縁膜
１４　保護膜
２０　半導体スイッチ回路
２１～２８　半導体スイッチ
３１　第１入力端子
３２　第２入力端子
４１　第１出力端子
４２　第２出力端子
４３　第３出力端子
４４　第４出力端子
５１　第１配線層
５２　第２配線層
５４　第１ビア
５５　第２ビア
６０　パッド
１１０　モールド樹脂層
１１１　第１再配線層間絶縁膜
１１２　第２再配線層間絶縁膜
１１３　第３再配線層間絶縁膜
２５１　第１再配線層
２５２　第２再配線層
２５４　第１再配線層ビア
２６１　第１再配線層パッド
２６２　第２再配線層パッド
３３６　サファイア基板
３３４　バリアＳｉＯ２層
３１３　シリコン層 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 1st interlayer insulation film 12 2nd interlayer insulation film 13 3rd interlayer insulation film 14 Protective film 20 Semiconductor switch circuit 21-28 Semiconductor switch 31 1st input terminal 32 2nd input terminal 41 1st output terminal 42 1st 2 output terminal 43 3rd output terminal 44 4th output terminal 51 1st wiring layer 52 2nd wiring layer 54 1st via | veer 55 2nd via | veer 60 pad 110 Mold resin layer 111 1st rewiring interlayer insulation film 112 2nd rewiring Interlayer insulating film 113 Third rewiring interlayer insulating film 251 First rewiring layer 252 Second rewiring layer 254 First rewiring layer via 261 First rewiring layer pad 262 Second rewiring layer pad 336 Sapphire substrate 334 Barrier SiO 2- layer 313 silicon layer

Claims (8)

  1. 　半導体基板と、
    　前記半導体基板上に形成された半導体スイッチ回路と、
    　前記半導体スイッチ回路が形成された前記半導体基板の上に交互に形成された層間絶縁膜及び配線層と、
    　最上位層にある前記層間絶縁膜上に前記配線層と接続されるように形成されたパッドと、
    　前記パッドが露出するように、前記最上位層にある層間絶縁膜を覆うように形成された保護膜と、
    　前記保護膜上に前記パッドと再配線層とが接続されるように交互に形成された再配線層間絶縁膜及び前記再配線層と、
    　前記再配線層と接続された複数の入力端子及び複数の出力端子が露出するように、最上位にある前記再配線層間絶縁膜を覆うように形成されたモールド樹脂層と、
    　を備え、
    　前記半導体スイッチ回路は、前記複数の入力端子のうち任意の入力端子を、前記配線層又は前記再配線層を介して、前記複数の出力端子のうち任意の出力端子と接続することが可能なように構成され、
    　前記複数の入力端子及び前記複数の出力端子のうちのある端子と前記半導体スイッチ回路との間を接続する配線と、前記複数の入力端子及び前記複数の出力端子のうちの他の端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、半導体装置。     A semiconductor substrate;
    A semiconductor switch circuit formed on the semiconductor substrate;
    Interlayer insulating films and wiring layers alternately formed on the semiconductor substrate on which the semiconductor switch circuit is formed;
    A pad formed on the interlayer insulating film in the uppermost layer so as to be connected to the wiring layer;
    A protective film formed to cover the interlayer insulating film in the uppermost layer so that the pad is exposed;
    Rewiring interlayer insulating films and the rewiring layer alternately formed so that the pad and the rewiring layer are connected on the protective film,
    A mold resin layer formed so as to cover the uppermost rewiring interlayer insulating film so that a plurality of input terminals and a plurality of output terminals connected to the rewiring layer are exposed;
    With
    The semiconductor switch circuit can connect an arbitrary input terminal of the plurality of input terminals to an arbitrary output terminal of the plurality of output terminals via the wiring layer or the rewiring layer. Composed of
    Wiring connecting between a terminal of the plurality of input terminals and the plurality of output terminals and the semiconductor switch circuit, another terminal of the plurality of input terminals and the plurality of output terminals, and the semiconductor At a location where wiring connecting with the switch circuit intersects when viewed from the thickness direction of the semiconductor substrate, one of the intersecting wirings is constituted by the wiring layer, and the other wiring is A semiconductor device composed of a wiring layer.
  2. 　ある前記入力端子と前記半導体スイッチ回路との間を接続する配線と、他の前記入力端子と前記半導体スイッチ回路との間を接続する配線とが交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、請求項１に記載の半導体装置。 Among the wiring that intersects, at the point where the wiring that connects between the input terminal and the semiconductor switch circuit and the wiring that connects between the other input terminal and the semiconductor switch circuit intersect, The semiconductor device according to claim 1, wherein one wiring is constituted by the wiring layer and the other wiring is constituted by the rewiring layer.
  3. 　ある前記出力端子と前記半導体スイッチ回路との間を接続する配線と、他の前記出力端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線を前記配線層とし、他方の配線を前記再配線層とする、請求項１に記載の半導体装置。 A wiring connecting between the certain output terminal and the semiconductor switch circuit and a wiring connecting between the other output terminal and the semiconductor switch circuit intersect each other when viewed from the thickness direction of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein one of the intersecting wirings is the wiring layer and the other wiring is the rewiring layer.
  4. 　ある前記入力端子と前記半導体スイッチ回路との間を接続する配線と、ある前記出力端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、請求項１に記載の半導体装置。 A location where a wiring connecting between the certain input terminal and the semiconductor switch circuit and a wiring connecting between the certain output terminal and the semiconductor switch circuit intersect when viewed from the thickness direction of the semiconductor substrate 2. The semiconductor device according to claim 1, wherein one of the intersecting wirings is configured by the wiring layer, and the other wiring is configured by the rewiring layer.
  5. 　複数の前記再配線層が形成されており、前記他方の配線が前記複数の再配線層のうちの最上位層の再配線層である、請求項１乃至４のいずれか１項に記載の半導体装置。 5. The semiconductor according to claim 1, wherein a plurality of the rewiring layers are formed, and the other wiring is an uppermost rewiring layer of the plurality of rewiring layers. apparatus.
  6. 　前記半導体基板はＳＯＩ基板である、請求項1乃至５のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI substrate.
  7. 　前記半導体基板はＳＯＳ基板である、請求項1乃至５のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOS substrate.
  8. 　複数の入力端子及び複数の出力端子と、前記複数の入力端子のうち任意の入力端子を前記複数の出力端子のうち任意の出力端子と接続されるように構成された半導体スイッチ回路と、を備える半導体装置の製造方法において、
    　前記半導体基板上に前記半導体スイッチ回路を形成するステップと、
    　前記半導体スイッチ回路が形成された前記半導体基板の上に層間絶縁膜及び配線層を交互に形成するステップと
    　最上位層にある前記層間絶縁膜上に前記配線層と接続されるようにパッドを形成するステップと、
    　前記パッドが露出するように、前記最上位層にある層間絶縁膜を覆うように保護膜を形成するステップと、
    　前記保護膜上に前記パッドと再配線層とが接続されるように再配線層間絶縁膜及び前記再配線層を交互に形成するステップと、
    　前記再配線層と接続された複数の入力端子及び複数の出力端子が露出するように、最上位にある前記再配線層間絶縁膜を覆うようにモールド樹脂層を形成するステップと、
    　を備え、
    　前記複数の入力端子及び前記複数の出力端子のうちのある端子と前記半導体スイッチ回路との間を接続する配線と、前記複数の入力端子及び前記複数の出力端子のうちの他の端子と前記半導体スイッチ回路との間を接続する配線とが前記半導体基板の厚み方向から見て交差している箇所において、交差する配線のうち、一方の配線が前記配線層で構成され、他方の配線が前記再配線層で構成されている、
    　半導体装置の製造方法。     A plurality of input terminals, a plurality of output terminals, and a semiconductor switch circuit configured to connect any input terminal of the plurality of input terminals to any output terminal of the plurality of output terminals. In a method for manufacturing a semiconductor device,
    Forming the semiconductor switch circuit on the semiconductor substrate;
    A step of alternately forming an interlayer insulating film and a wiring layer on the semiconductor substrate on which the semiconductor switch circuit is formed and a pad to be connected to the wiring layer on the interlayer insulating film in the uppermost layer And steps to
    Forming a protective film so as to cover the interlayer insulating film in the uppermost layer so that the pad is exposed;
    Alternately forming a rewiring interlayer insulating film and the rewiring layer so that the pad and the rewiring layer are connected on the protective film;
    Forming a mold resin layer so as to cover the uppermost rewiring interlayer insulating film so that a plurality of input terminals and a plurality of output terminals connected to the rewiring layer are exposed;
    With
    Wiring connecting between a terminal of the plurality of input terminals and the plurality of output terminals and the semiconductor switch circuit, another terminal of the plurality of input terminals and the plurality of output terminals, and the semiconductor At a location where wiring connecting with the switch circuit intersects when viewed from the thickness direction of the semiconductor substrate, one of the intersecting wirings is constituted by the wiring layer, and the other wiring is Consists of wiring layers,
    A method for manufacturing a semiconductor device.
PCT/JP2011/000348 2010-09-21 2011-01-24 Semiconductor device and method of manufacturing semiconductor device WO2012039073A1 (en)

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JP7136563B2 (en) * 2018-02-05 2022-09-13 矢崎総業株式会社 POWER SEMICONDUCTOR DEVICE AND VEHICLE POWER SUPPLY SYSTEM INCLUDING THE POWER SEMICONDUCTOR DEVICE
JP7330146B2 (en) * 2020-08-07 2023-08-21 株式会社東芝 switch circuit

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