JP6717404B2 - Field-effect transistor and wireless communication device - Google Patents

Description

The present disclosure relates to a field effect transistor (FET) suitable for a switch element of a high frequency device and a wireless communication device including the field effect transistor.

A radio frequency switch (RF-SW) for turning on/off a radio frequency (RF) is used in a front end of a mobile communication terminal such as a mobile phone. An important characteristic of such a high frequency switch is a reduction in the loss of high frequencies passing through. For that purpose, it is important to reduce the resistance of the FET in the ON state (ON resistance) or the capacitance of the FET in the OFF state (OFF capacitance), that is, reduce the product of the ON resistance and the OFF capacitance (Ron*Coff). ..

The off-capacitance includes a component (internal component) generated in the diffusion layer and the substrate, and a component (external component) generated in the gate electrode, the contact plug and the wiring thereabove. For example, in the field of fine MOSFETs, it has been proposed to reduce the external component by reducing the parasitic capacitance between the gate electrode and the contact plug by forming a space around the gate electrode (see, for example, Patent Document 1). ..

JP 2002-359369 A

However, with the configuration of Patent Document 1, it is difficult to sufficiently reduce the parasitic capacitance between the gate electrode and the wiring on the contact plug or the capacitance (inter-wiring capacitance) generated between the wirings on the contact plug. There was still room for improvement.

An object of the present disclosure is to provide a field effect transistor capable of reducing an external component of off capacitance and a wireless communication device including the field effect transistor.

The first field effect transistor according to the present disclosure includes the following components (A) to (F).
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with the gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region A plurality of contact plugs including a plug and including a first conductive material (D) A plurality of first metal layers each stacked on the plurality of contact plugs and including a second conductive material different from the first conductive material ( E) One or more insulating film (F) semiconductor layers provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and in at least the region below the lower surface of the first metal in the stacking direction. A low dielectric constant region provided in a region between a plurality of contact plugs in the in-plane direction of the device and at least between a lower face of the first metal and an upper face of the gate electrode in the stacking direction. Includes a first portion and a second portion. The first portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction, and the first contact plug and the second contact are provided. It occupies a region between the side surface of the plug and the side surface of the gate electrode. The second portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction. The low dielectric constant region is constituted by a void provided inside the second portion of the insulating film of one or more layers.
The insulating film of one or more layers has a third insulating film located outside the side portion of the void and a fourth insulating film provided at least between the side portion of the void and the third insulating film.

In the field effect transistor of the present disclosure, in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer, in the stacking direction, at least between the lower surfaces of the plurality of first metals and the upper surface of the gate electrode, the low dielectric constant region Is provided. In addition, the plurality of contact plugs include a first conductive material, and the plurality of first metals include a second conductive material different from the first conductive material. The one or more insulating films include a first portion and a second portion. The first portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction, and the first contact plug and the second contact are provided. It occupies a region between the side surface of the plug and the side surface of the gate electrode. The second portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction. The low dielectric constant region is constituted by a void provided inside the second portion of the insulating film of one or more layers. The insulating film of one or more layers has a third insulating film located outside the side portion of the void and a fourth insulating film provided at least between the side portion of the void and the third insulating film. Therefore, the parasitic capacitance between the gate electrode and the contact plug or the parasitic capacitance between the gate electrode and the first metal is reduced, and the external component of the off capacitance is reduced.

A wireless communication device according to the present disclosure includes a high-frequency switch having a field-effect transistor and a high-frequency integrated circuit connected to the high-frequency switch, and the field-effect transistor has the following components (A) to (F). Is.
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with the gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region A plurality of contact plugs including a plug and including a first conductive material (D) A plurality of first metal layers each stacked on the plurality of contact plugs and including a second conductive material different from the first conductive material ( E) One or more insulating film (F) semiconductor layers provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and in at least the region below the lower surface of the first metal in the stacking direction. A low dielectric constant region provided in a region between a plurality of contact plugs in the in-plane direction of the device and at least between a lower face of the first metal and an upper face of the gate electrode in the stacking direction. Includes a first portion and a second portion. The first portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction, and the first contact plug and the second contact are provided. It occupies a region between the side surface of the plug and the side surface of the gate electrode. The second portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction. The low dielectric constant region is constituted by a void provided inside the second portion of the insulating film of one or more layers.
The insulating film of one or more layers has a third insulating film located outside the side portion of the void and a fourth insulating film provided at least between the side portion of the void and the third insulating film.

According to the field effect transistor of the present disclosure or the wireless communication device of the present disclosure, in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer, at least the lower surface of the first metal and the gate electrode in the stacking direction. A low dielectric constant region is provided between the upper surface and the upper surface. In addition, the plurality of contact plugs include a first conductive material, and the plurality of first metals include a second conductive material different from the first conductive material. The one or more insulating films include a first portion and a second portion. The first portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction, and the first contact plug and the second contact are provided. It occupies a region between the side surface of the plug and the side surface of the gate electrode. The second portion is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction. The low dielectric constant region is constituted by a void provided inside the second portion of the insulating film of one or more layers. The insulating film of one or more layers has a third insulating film located outside the side portion of the void and a fourth insulating film provided at least between the side portion of the void and the third insulating film. Therefore, it is possible to reduce the external component of the off capacitance.

Note that the effects described here are not necessarily limited, and may be any effects described in the present disclosure.

It is a figure showing an example of a high frequency switch which has a field effect transistor concerning a 1st embodiment of this indication. It is a figure showing the SPST switch which is a basic composition of the high frequency switch shown in FIG. FIG. 3 is an equivalent circuit diagram of the SPST switch shown in FIG. 2. FIG. 4 is an equivalent circuit diagram when the SPST switch shown in FIG. 3 is on. FIG. 4 is an equivalent circuit diagram when the SPST switch shown in FIG. 3 is off. FIG. 2 is a plan view showing the overall configuration of the field effect transistor according to the first embodiment of the present disclosure. It is sectional drawing in the VII-VII line of FIG. It is a figure which decomposes|disassembles and represents the off capacitance of a general field effect transistor for every component. FIG. 9 is a cross-sectional view showing Modification Example 1 of the low dielectric constant region shown in FIG. 7. FIG. 9 is a cross-sectional view showing a modified example 2 of the low dielectric constant region shown in FIG. 7. 6 is a cross-sectional view illustrating a configuration of a field effect transistor according to Reference Example 1. FIG. Simulation for examining the relationship between the width of the low dielectric constant region and the external component of the capacitance in the present embodiment shown in FIG. 7, the modification 2 shown in FIG. 10, and the reference example 1 shown in FIG. It is a figure showing a result. FIG. 8 is a cross-sectional view showing a positional relationship between the field effect transistor and the low dielectric constant region shown in FIG. 7 and a multilayer wiring portion. FIG. 8 is a plan view showing a positional relationship between the field effect transistor and the low dielectric constant region shown in FIG. 7, and a gate contact. It is sectional drawing in the XV-XV line of FIG. It is sectional drawing in the XVIA-XVIB line of FIG. It is sectional drawing in the XVIIB-XVIIC line of FIG. It is sectional drawing in the XVIIIC-XVIIID line of FIG. 9A to 9C are cross-sectional views showing a method of manufacturing the field effect transistor shown in FIG. It is sectional drawing showing the process of following FIG. It is sectional drawing showing the process of following FIG. FIG. 22 is a cross-sectional view showing a process following on from FIG. 21. FIG. 23 is a cross-sectional view showing a process following on the process shown in FIG. 22. It is sectional drawing showing the process of following FIG. FIG. 25 is a cross-sectional view showing a process following on the process shown in FIG. 24. It is sectional drawing showing the process of following FIG. FIG. 27 is a sectional view illustrating a process following the process in FIG. 26. FIG. 28 is a cross-sectional view showing a process following on the process shown in FIG. 27. FIG. 29 is a cross-sectional view showing a process following on the process shown in FIG. 28. FIG. 30 is a cross-sectional view showing a process following on the process shown in FIG. 29. It is sectional drawing showing the process of following FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a field effect transistor according to a second embodiment of the present disclosure. It is sectional drawing showing the structure of the field effect transistor which concerns on 3rd Embodiment of this indication. It is sectional drawing showing the structure of the field effect transistor which concerns on 4th Embodiment of this indication. It is a top view showing the composition of the field effect transistor concerning a 5th embodiment of this indication. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI of FIG. 35. FIG. 36 is a cross-sectional view taken along line XXXVII-XXXVII of FIG. 35. FIG. 36 is a plan view showing the method of manufacturing the field effect transistor shown in FIG. 35 in the order of steps. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 38. FIG. 39 is a plan view illustrating a process following the process in FIG. 38. FIG. 41 is a cross-sectional view taken along the line XXXXI-XXXXI of FIG. 40. FIG. 41 is a cross-sectional view taken along the line XXXXXXII-XXXXII in FIG. 40. It is a top view showing the composition of the field effect transistor concerning a 6th embodiment of this indication. It is a block diagram showing an example of a wireless communication device.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (high-frequency switch, field effect transistor; first region below the lower surface of the first metal in the stacking direction, a second region between the lower surface and the upper surface of the first metal, Example of providing a low dielectric constant region in the third region above the upper surface of the metal)
2. Second Embodiment (Field Effect Transistor; Example of stacking second metal on first metal and extending low-dielectric constant region between second metals)
3. Third Embodiment (Field Effect Transistor; Example of Providing Low Dielectric Constant Region with Width Greater Than Part of First Insulating Film and Second Insulating Film Covering Surface of Gate Electrode)
4. Fourth Embodiment (Field Effect Transistor; Example of Filling First and Second Regions of Low Dielectric Constant Region with Fifth Insulating Film and Forming Third Region as Void)
5. Fifth Embodiment (Field Effect Transistor; Example of Providing Low Dielectric Constant Region in Direction Crossing Gate Electrode)
6. Sixth Embodiment (Field Effect Transistor; Example of Providing Low Dielectric Constant Region in Finger Part of Gate Electrode and at least Part of Connecting Part)
7. Application example (wireless communication device)

(First embodiment)
FIG. 1 shows a configuration of a high frequency switch having a field effect transistor according to a first embodiment of the present disclosure. The high frequency switch 1 is used for a front end of a portable information terminal such as a mobile phone, and depending on the number of input/output ports, SPST (Single Pole Single Throw), SPDT (Single Pole Single Throw) shown in FIG. Single Pole Double Throw), SP3T... SPNT (N is a real number) are used properly. FIG. 1 shows an example of the SP10T switch. The SP10T switch has, for example, one pole connected to the antenna ANT and ten contacts. The high frequency switch 1 can have various configurations, but any configuration of the high frequency switch 1 is a combination of the basic circuit configurations of the SPST switch shown in FIG.

FIG. 3 shows an equivalent circuit of the SPST switch 1A shown in FIG. The SPST switch 1A has, for example, a first port Port1 connected to the antenna ANT, a second port Port2, a first switching element FET1, and a second switching element FET2. The first switching element FET1 is connected between the first port Port1 and the ground. The second switching element FET2 is connected between the first port Port1 and the second port Port2.

In this SPST switch 1A, on/off control is performed by applying control voltages Vc1 and Vc2 to the gates of the first switching element FET1 and the second switching element FET2 via resistors. At the time of turning on, as shown in FIG. 4, the second switching element FET2 becomes conductive and the first switching element FET1 becomes non-conductive. When turned off, as shown in FIG. 5, the first switching element FET1 is in a conducting state and the second switching element FET2 is in a non-conducting state.

The on-resistance and off-capacitance of the first switching element FET1 and the second switching element FET2 are calculated by using values Ron [Ωmm], Coff [fF/mm], and gate widths Wg1 and Wg2 [mm] of the FET per unit length. , Ron/Wg1, Ron/Wg2, Coff*Wg1, and Coff*Wg2, respectively. The ON resistance is inversely proportional to the gate widths Wg1 and Wg2, and the OFF capacitance is proportional to the gate widths Wg1 and Wg2.

Another feature of on-resistance and off-capacitance is that loss due to on-resistance does not depend on frequency, but off-capacitance loss increases with higher frequency. If the gate width Wg is increased in order to reduce the loss, high frequency loss due to the input capacitance will occur. Therefore, in order to reduce the loss by using the largest possible gate width Wg, it is important to reduce both Ron and Coff per unit length, that is, Ron*Coff (product) as small as possible.

FIG. 6 is a plan view showing the overall configuration of the field effect transistor according to the first embodiment of the present disclosure. The field-effect transistor 10 is a field-effect transistor for high-frequency devices that constitutes the first switching element FET1 or the second switching element FET2 in the SPST switch 1A shown in FIG. 3, and includes a gate electrode 20, a source electrode 30S, and a drain. It has an electrode 30D.

The gate electrode 20 has a multi-finger structure having a plurality of finger portions 21 extending in the same direction (for example, the Y direction) and a connecting portion (gate leading wiring) 22 that connects the plurality of finger portions 21. .. The gate width Wg of the field effect transistor 10 used for the high frequency switch 1 is considerably larger than that of a field effect transistor used for logic or the like in order to reduce loss, and is in the unit of several hundreds of um to several mm. The length (finger length) L21 of the finger portion 21 is, for example, several tens of um. The connecting portion 22 is connected to a gate contact (not shown in FIG. 6, see FIG. 14). In FIG. 6, the gate electrode 20 is shown with diagonal lines.

In the following description and drawings, the longitudinal direction of the finger portions 21 of the gate electrode 20 is the Y direction, the longitudinal direction of the connecting portion 22 is the X direction, and the direction orthogonal to both is the Z direction.

Similar to the gate electrode 20, the source electrode 30S has a finger portion 31S extending in the same direction (for example, the Y direction) and a connecting portion (source leading wiring) 32S that connects the plurality of finger portions 31S. The connecting portion 32S is connected to a source contact (not shown).

Similar to the gate electrode 20, the drain electrode 30D has a finger portion 31D extending in the same direction (for example, the Y direction) and a connecting portion (drain routing wiring) 32D that connects the plurality of finger portions 31D. The connecting portion 32D is connected to a drain contact (not shown).

The finger portions 31S of the source electrode 30S and the finger portions 31D of the drain electrode 30D are alternately arranged in the gap between the finger portions 21 of the gate electrode 20. The finger portion 21 of the gate electrode 20, the finger portion 31S of the source electrode 30S, and the finger portion 31D of the drain electrode 30D are arranged inside the active area (active area) AA. The connection portion 22 of the gate electrode 20, the connection portion 32S of the source electrode 30S, and the connection portion 32D of the drain electrode 30D are separated from each other by an element isolation region AB outside the active region AA (not shown in FIG. 6, see FIG. 14). It is located in.

FIG. 7 shows a cross-sectional structure taken along the line VII-VII of FIG. 6, and shows one finger portion 21 of the gate electrode 20, one finger portion 31S of the source electrode 30S arranged on both sides thereof, and the drain electrode. It shows one finger portion 31D of 30D. The field effect transistor 10 has the above-described gate electrode 20, the semiconductor layer 50, the contact plugs 60S and 60D, the first metal M1, and the low dielectric constant region 70.

The gate electrode 20 is provided on the semiconductor layer 50 with the gate oxide film 23 interposed therebetween. The gate electrode 20 has a thickness of, for example, 150 nm to 200 nm and is made of polysilicon. The gate oxide film 23 has a thickness of, for example, about 5 nm to 10 nm and is made of silicon oxide (SiO ₂ ).

The semiconductor layer 50 is made of, for example, silicon (Si). The semiconductor layer 50 has a source region 50S and a drain region 50D made of n-type (n+) silicon with the gate electrode 20 in between. Low resistance regions 51S and 51D made of high-concentration n-type (n++) silicon or silicide are provided on the surfaces of the source region 50S and the drain region 50D for connection with the contact plugs 60S and 60D. Extension regions 52S and 52D made of low-concentration n-type (n−) silicon are provided between the source region 50S and the gate electrode 20 and between the drain region 50D and the gate electrode 20.

The semiconductor layer 50 is provided, for example, on the support substrate 53 with the buried oxide film 54 in between. That is, the support substrate 53, the buried oxide film 54, and the semiconductor layer 50 form an SOI (Silicon on Insulator) substrate 55. The support substrate 53 is composed of, for example, a high resistance silicon substrate. The buried oxide film 54 is made of, for example, SiO ₂ .

The contact plugs 60S and 60D are connected to the low resistance regions 51S and 51D of the source region 50S. The contact plugs 60S and 60D have, for example, a laminated structure (not shown) of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. The titanium layer is a film that reduces the contact resistance with the lower layer of the contact plugs 60S and 60D. The titanium nitride layer is a barrier metal that suppresses the diffusion of the tungsten layer provided inside it into silicon.

The first metal M1 includes, for example, a source electrode 30S stacked on the contact plug 60S and a drain electrode 30D stacked on the contact plug 60D. The first metal M1 has a thickness of, for example, 500 nm to 1000 nm, and is made of aluminum (Al).

The low dielectric constant region 70 is provided in a region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50, that is, in a region between the source electrode 30S and the drain electrode 30D (above the finger portions 21 of the gate electrode 20). Has been. The low dielectric constant region 70 is provided in at least the first region A1 below the lower surface of the first metal M1 in the stacking direction Z. As a result, in this field effect transistor 10, it is possible to reduce the external component of the off capacitance.

That is, as shown in FIG. 8, the off capacitance includes a component (intrinsic component) Cin generated in the diffusion layer, the substrate, etc., the gate electrode 20, the contact plugs 60S and 60D, and the first metal M1 thereon. There is a component (extrinsic component) Cex that occurs in such as.

The internal component Cin includes, for example, the following. Capacitances Cssub and Cdsub generated between the source region 50S or the drain region 50D and the support substrate 53. Capacitances Csg and Cdg generated between the source region 50S or the drain region 50D and the gate electrode 20. A capacitance Cds generated between the source region 50S and the drain region 50D. Capacitances Csb and Cdb generated between the source region 50S or the drain region 50D and the lower portion (body) of the semiconductor layer 50.

The external component Cex includes, for example, the following. The capacitance between the gate electrode 20 and the contact plugs 60S and 60D or the capacitance CgM between the gate electrode 20 and the first metal M1. A capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1.

It is to be noted that FIG. 8 is a diagram in which the off-capacitance of a general field effect transistor is disassembled for each component. 8, constituent elements corresponding to the field effect transistor 10 of the present embodiment shown in FIG. 7 are denoted by the same reference numerals.

In order to reduce the off capacity, it is particularly effective to reduce the external component Cex. In this embodiment, the external component Cex is reduced by providing the low dielectric constant region 70 in the regions described above in the XY in-plane direction and the stacking direction Z. This makes it possible to reduce the product of the on-resistance and the off-capacitance (Ron*Coff) and reduce the loss of the high frequency switch 1.

Specifically, as shown in FIG. 7, the low dielectric constant region 70 includes the first region A1 described above and the second region A2 between the lower surface and the upper surface of the first metal M1 in the stacking direction Z. , And is preferably provided in the third region A3 above the upper surface of the first metal M1. As a result, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D, the capacitance CgM between the gate electrode 20 and the first metal M1, or the capacitance generated between the first metals M1 (inter-wiring capacitance). The CMM1 and the like are suppressed, and the external component Cex of the off capacitance is reduced.

(Modification 1)
Alternatively, the low dielectric constant region 70 may be provided in the first region A1 and the second region A2 in the stacking direction Z as shown in FIG. Also in this case, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D, the capacitance CgM between the gate electrode 20 and the first metal M1, or the capacitance generated between the first metals M1. (Inter-wiring capacitance) CMM1 and the like are suppressed, and the external component Cex of the off capacitance is reduced.

(Modification 2)
Further, the low dielectric constant region 70 may be provided in the first region A1 in the stacking direction Z as shown in FIG. Also in this case, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D or the capacitance CgM between the gate electrode 20 and the first metal M1 is suppressed, and the external component Cex of the off capacitance is reduced.

(Reference example 1)
FIG. 11 illustrates a cross-sectional configuration of the field effect transistor 10R according to the first reference example. The reference example 1 has the same configuration as the field effect transistor 10 of the present embodiment shown in FIG. 7 except that the low dielectric constant region 70 is provided in the second region A2 in the stacking direction Z. doing.

(simulation result)
FIG. 12 shows the width of the low dielectric constant region 70 of the external component Cex of the capacitance in the present embodiment shown in FIG. 7, the modification 1 shown in FIG. 9, and the reference example 1 shown in FIG. It is a figure showing the simulation result which investigated the dependence with respect to W70.

As can be seen from FIG. 12, the external component Cex of the capacitance tends to decrease as the width W70 of the low dielectric constant region 70 increases. Further, in the modified example 1 in which the low dielectric constant region 70 is provided in the first region A1 and the second region A2 in the stacking direction Z, compared to the reference example 1 in which the low dielectric constant region 70 is provided only in the second region A2 in the stacking direction Z. As a result, the external component Cex of the capacitance is reduced. Further, in the present embodiment in which the low dielectric constant region 70 is provided in the first region A1, the second region A2, and the third region A3 in the stacking direction Z, it depends on the extension length of the low dielectric constant region 70 in the stacking direction Z. However, it can be seen that the effect of reducing the external component Cex having a capacity equal to or greater than that of the first modification can be obtained.

Further, the field effect transistor 10 shown in FIG. 7 has at least one insulating film 80 on the semiconductor layer 50 and an opening provided from the upper surface of the at least one insulating film 80 toward the upper surface of the gate electrode 20. (Recessed portion) P. The low dielectric constant region 70 is preferably provided in this opening P. As a result, the width WP of the opening P can be widened. Therefore, when a gap is formed near the gate electrode 20 by wet etching, the problem that the etching solution is hard to enter the narrow gap is solved. This makes it possible to improve the etching uniformity in the wafer surface of the SOI substrate 55 and the uniformity of the characteristics of the field effect transistor 10. The width WP of the opening P is preferably 100 nm to 1000 nm, for example, because the opening P is provided between the source electrode 30S and the drain electrode 30D.

At least one insulating film 80 preferably includes a plurality of insulating films having different etching rates. In the manufacturing process described later, it is possible to control the etching stop position of the opening P with high accuracy by utilizing the difference in etching rate of the plurality of insulating films. Therefore, the dose loss of the Si surface that occurs when the surface of the gate electrode 20 is scraped or the side surface of the gate electrode 20 is scraped and the etching reaches the Si surface, the variation in the gate length due to the side etching of the gate oxide film 23, and the It is possible to suppress an increase in the variation of the threshold voltage caused by that, stably manufacture the field effect transistor 10, and improve the reliability of the field effect transistor 10.

Specifically, at least one layer of insulating film 80 preferably includes, for example, a first insulating film 81, a second insulating film 82, and a third insulating film 83. The first insulating film 81 covers the surface (upper surface and side surfaces) of the gate electrode 20 and the upper surface of the semiconductor layer 50. The second insulating film 82 covers the surface of the first insulating film 81. The third insulating film 83 is provided between the surface of the second insulating film 82 and the lower surface of the first metal M1. The second insulating film 82 is preferably made of a material having an etching rate different from those of the first insulating film 81 and the third insulating film 83. For example, the first insulating film 81 and the third insulating film 83 are preferably made of a silicon oxide (SiO ₂ ) film, and the second insulating film 82 is preferably made of a silicon nitride (SiN) film. This allows the second insulating film 82 to function as an etching stopper layer. It is preferable that the opening P penetrates at least the third insulating film 83 and reaches the upper surface of the second insulating film 82.

In addition, at least one layer of insulating film 80 preferably further includes a fourth insulating film 84. The fourth insulating film 84 covers the upper surface of the third insulating film 83 and the surface (upper surface and side surface) of the first metal M1. It is preferable that the opening P penetrates the fourth insulating film 84 and the third insulating film 83 from the upper surface of the fourth insulating film 84 and reaches the upper surface of the second insulating film 82. The fourth insulating film 84 is preferably made of, for example, a silicon oxide (SiO ₂ ) film.

Further, at least one layer of the insulating film 80 preferably further includes a fifth insulating film 85 on the fourth insulating film 84. It is preferable that a void AG (Air Gap) is provided as the low dielectric constant region 70 in at least a part of the opening P. The structure of the low dielectric constant region 70 or the air gap AG is particularly limited as long as it has a lower dielectric constant than the silicon oxide (SiO ₂ , dielectric constant 3.9) film forming the third insulating film 83 and the fourth insulating film 84. Alternatively, for example, air (dielectric constant 1.0) may be present in the void AG, or a vacuum may be applied. The upper portion of the gap AG is preferably closed by the fifth insulating film 85. As a result, the gap AG is hermetically sealed by the fifth insulating film 85. The fifth insulating film 85 may cover the side surface and the bottom surface of the opening P. The fifth insulating film 85 is made of, for example, a silicon oxide (SiO ₂ ) film. If necessary, a sixth insulating film 86 made of, for example, silicon oxide (SiO ₂ ) may be provided on the upper layer of the fifth insulating film 85.

The low dielectric constant region 70 is preferably provided with a width W70 that is equal to or less than the width W82 of the portion of the first insulating film 81 and the second insulating film 82 that covers the surface of the gate electrode 20, for example.

FIG. 13 shows a positional relationship in the stacking direction Z between the field effect transistor 10 and the low dielectric constant region 70 shown in FIG. 7 and the multilayer wiring part 90. The field effect transistor 10 and the low dielectric constant area 70 are provided in the element area AA1 of the active area AA. The multilayer wiring portion 90 is provided in the wiring area AA2 outside the element area AA1 in the active area AA. The element area AA1 and the wiring area AA2 are separated by an element separation layer 100 by an STI (Shallow Trench Isolation) method.

The multilayer wiring section 90 has, for example, a first wiring layer 91 and a second wiring layer 92. The first wiring layer 91 is, for example, the same layer as the source electrode 30S and the drain electrode 30D, that is, the first metal M1. The second wiring layer 92 is, for example, the second metal M2 that is an upper layer than the first metal M1. The first wiring layer 91 and the second wiring layer 92 are connected by a contact plug 93, for example.

The low dielectric constant region 70 is not provided between the first wiring layers 91 of the multilayer wiring portion 90 or between the second wiring layers 92. That is, the low dielectric constant region 70 is provided inside the field effect transistor 10 in the element region AA1 in the active region AA.

FIG. 14 shows the positional relationship in the XY plane direction between the field effect transistor 10 and the low dielectric constant region 70 shown in FIG. 7, and the gate contact GC. The field effect transistor 10 and the low dielectric constant area 70 are provided in the active area AA. The gate contact GC is provided in the element isolation region AB outside the active region AA. Instead of the semiconductor layer 50, the element isolation region AB is provided with an element isolation layer 100 by the STI method over the entire surface.

The finger portion 21 of the gate electrode 20, the finger portion 31S of the source electrode 30S, and the finger portion 31D of the drain electrode 30D are provided in the active area AA. The finger portion 21 of the gate electrode 20 extends in one direction (for example, the Y direction). The finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D extend on both sides of the finger portion 21 of the gate electrode 20 in parallel to the finger portion 21 of the gate electrode 20. The contact plugs 60S and 60D are provided below the finger portions 31S of the source electrode 30S and the finger portions 31D of the drain electrode 30D, and extend parallel to the finger portions 21 of the gate electrode 20. The low dielectric constant region 70 is provided on the finger portion 21 of the gate electrode 20 and extends parallel to the finger portion 21 of the gate electrode 20. In other words, the low dielectric constant region 70 is provided at a position overlapping the finger portion 21 of the gate electrode 20 in the XY in-plane direction.

In the element isolation region AB, the connecting portion 22 of the gate electrode 20, the connecting portion 32S of the source electrode 30S, and the connecting portion 32D of the drain electrode 30D are provided. The connecting portion 22 of the gate electrode 20 is connected to the gate contact GC. The connecting portion 32S of the source electrode 30S is connected to a source contact (not shown). The connecting portion 32D of the drain electrode 30D is connected to a drain contact (not shown).

FIG. 15 shows a cross-sectional structure of the gate contact GC shown in FIG. The gate contact GC has a connecting portion 22 of the gate electrode 20, a gate contact plug 24, and a gate contact layer 25 in this order on the element isolation layer 100 by the STI method. The gate contact plug 24 is provided in the same layer as the contact plugs 60S and 60D. The gate contact layer 25 is provided in the same layer as the source electrode 30S and the drain electrode 30D, that is, the first metal M1.

FIG. 16 shows a cross-sectional structure taken along line XVIA-XVIB of FIG. FIG. 17 shows a cross-sectional structure taken along line XVIIB-XVIIC in FIG. FIG. 18 shows a cross-sectional structure taken along line XVIIIC-XVIIID in FIG.

As shown in FIGS. 14 to 18, the low dielectric constant region 70 is preferably provided so as to avoid the gate contact GC. This is because it is difficult to provide the gate contact plug 24 on the connecting portion 22 when the low dielectric constant region 70 is provided on the connecting portion 22 of the gate contact GC.

Further, like the gate electrode 20 in the field effect transistor 10, the gate contact GC is preferably covered with at least one insulating film 80, that is, the first insulating film 81 to the sixth insulating film 86. Since the gate contact GC is covered with at least one insulating film 80, the reliability of the gate contact GC is maintained.

The field effect transistor 10 can be manufactured, for example, as follows.

19 to 31 show a method of manufacturing the field effect transistor 10 in the order of steps. First, as shown in FIG. 19, an SOI substrate 55 having a buried oxide film 54 and a semiconductor layer 50 on a support substrate 53 is prepared, and the semiconductor layer 50 of the SOI substrate 55 is provided with an element isolation layer by, for example, the STI method. 100 is formed to divide the element area AA1 in the active area AA.

Next, a silicon oxide film is formed as an in-place film (not shown) by, for example, a thermal oxidation method, well implantation and channel implantation are performed on the active area AA, and then the in-place film is removed. Subsequently, as shown in FIG. 20, a gate oxide film 23 made of, for example, silicon oxide is formed with a thickness of, for example, about 5 nm to 10 nm by a thermal oxidation method. After that, a gate electrode material film (not shown) made of polysilicon is formed with a thickness of, for example, 150 nm to 200 nm by, for example, a CVD (Chemical Vapor Deposition) method. By processing the gate electrode material film by, for example, photolithography and etching, as shown in FIG. 20, the gate electrode 20 is formed on the upper surface side of the semiconductor layer 50 with the gate oxide film 23 interposed therebetween. ..

After forming the gate electrode 20, as shown in FIG. 21, the implantation of the arsenic (As) or phosphorus (P) IMPL is performed by using the gate electrode 20 and an offset spacer (not shown) as a mask. Extension regions 52S and 52D are formed on both sides. Further, a sidewall (not shown) is formed on the side surface of the gate electrode 20, and arsenic (As) or phosphorus (P) is implanted. As a result, the source region 50S and the drain region 50D are formed in the semiconductor layer 50 with the gate electrode 20 interposed therebetween. After that, the sidewall is removed.

After forming the source region 50S and the drain region 50D, as shown in FIG. 22, a first insulating film 81 made of, for example, silicon oxide is formed on the surface of the gate electrode 20 and the upper surface of the semiconductor layer 50 by, for example, the CVD method. It is formed with a thickness of several tens nm, for example, 10 nm to 30 nm.

After forming the first insulating film 81, as shown in FIG. 23, a material having an etching rate different from that of the first insulating film 81, for example, silicon nitride is formed on the surface of the first insulating film 81 by, for example, a CVD method. The second insulating film 82 is formed with a thickness of several nm to several tens nm, for example, 5 nm to 30 nm.

After forming the second insulating film 82, as shown in FIG. 24, a third insulating film 83 made of silicon oxide is formed on the second insulating film 82 by CVD, for example, to a thickness of 500 nm to 1000 nm. To do.

After forming the third insulating film 83, as shown in FIG. 25, part of the third insulating film 83, the second insulating film 82, and the first insulating film 81 is removed by photolithography and etching, and the source region 50S is formed. And a contact hole H1 is formed in the drain region 50D. The contact hole H1 is provided in parallel with the finger portion 21 of the gate electrode 20, as shown in the plan view of FIG.

After forming the contact hole H1, as shown in FIG. 26, low resistance regions 51S and 51D are formed by implantation IMPL of high concentration arsenic (As) or phosphorus (P).

After forming the low resistance regions 51S and 51D, as shown in FIG. 27, contact plugs 60S and 60D having a laminated structure of a titanium layer, a titanium nitride layer and a tungsten layer are formed in the contact hole H1. The contact plugs 60S and 60D are provided on the source region 50S and the drain region 50D. Further, the contact plugs 60S and 60D are provided in parallel with the finger portions 21 of the gate electrode 20, as shown in the plan view of FIG.

After forming the contact plugs 60S and 60D, as shown in FIG. 28, the source electrode 30S and the drain electrode 30D made of aluminum (Al) are formed as the first metal M1 on the contact plugs 60S and 60D. The finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D are provided in parallel with the finger portion 21 of the gate electrode 20 as shown in the plan view of FIG.

After forming the source electrode 30S and the drain electrode 30D, as shown in FIG. 29, a fourth insulating film 84 made of silicon oxide is formed on the upper surface of the third insulating film 83 and the surface of the first metal M1 by, for example, the CVD method. To form.

After forming the fourth insulating film 84, as shown in FIG. 30, the opening P is formed by photolithography and dry etching. The opening P is formed in a region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50, specifically, in a region between the source electrode 30S and the drain electrode 30D (above the finger portion 21 of the gate electrode 20). Form. The width WP of the opening P is, for example, 100 nm to 1000 nm. At this time, the second insulating film 82 functions as an etching stopper, and the etching of the opening P proceeds through the fourth insulating film 84 and the third insulating film 83 made of silicon oxide, and the etching is performed on the upper surface of the second insulating film 82. Stop.

After forming the opening P, as shown in FIG. 31, a fifth insulating film 85 made of silicon oxide is formed on the fourth insulating film 84 by, for example, the CVD method. The fifth insulating film 85 is deposited on the opening P while overhanging. Therefore, before the fifth insulating film 85 is filled in the opening P, the upper portion of the opening P is closed by the fifth insulating film 85, and the airtightly sealed space AG is formed in the opening P. The side surface and the bottom surface of the opening P may be covered with the fifth insulating film 85. The void AG has a lower dielectric constant than the third insulating film 83, the fourth insulating film 84, and the fifth insulating film 85 (silicon oxide, dielectric constant 3.9), and has a function as the low dielectric constant region 70. Air (dielectric constant 1.0) may be present in the void AG or may be vacuum, and is not particularly limited. The air gap AG, that is, the low dielectric constant region 70, is formed from the first region A1 below the lower surface of the first metal M1, the second region A2 between the lower surface and the upper surface of the first metal M1, and the upper surface of the first metal. Is continuously and integrally provided over the upper third region A3.

After that, as shown in FIG. 7, a sixth insulating film 86 is formed on the fifth insulating film 85, if necessary. Although not shown, the second metal M2 and the third metal M3 are formed on the fifth insulating film 85 by sequentially forming the insulating film and the metal layer similarly to the first metal M1. Good. With the above, the field effect transistor 10 shown in FIG. 7 is completed.

In the field-effect transistor 10, in the region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50, the first region A1 below the lower surface of the first metal M1 in the stacking direction Z, and the first metal M1. The low dielectric constant region 70 is provided in the second region A2 between the lower surface and the upper surface of M1 and the third region A3 above the upper surface of the first metal M1. Therefore, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D, the capacitance CgM between the gate electrode 20 and the first metal M1, or the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1. And the like, and the external component Cex of the off capacitance is reduced.

As described above, in the present embodiment, the low dielectric constant is provided in the region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50 and in the first region A1 at least below the lower surface of the first metal M1 in the stacking direction Z. A rate area 70 is provided. Therefore, it is possible to reduce the external component Cex of the off capacitance, reduce the product of the on resistance and the off capacitance (RonCoff), and promote reduction of loss, which is an important characteristic of the high-frequency switch 1. Become.

Further, the low dielectric constant region 70 is provided in the stacking direction Z over the first region A1, the second region A2, and the third region A3 described above. Therefore, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D, the capacitance CgM between the gate electrode 20 and the first metal M1, the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1 and the like, It is possible to suppress the external component Cex of the off capacitance and further reduce it.

Further, at least one insulating film 80 including a plurality of insulating films having different etching rates is provided on the semiconductor layer 50. Therefore, it is possible to control the etching stop position of the opening P with high accuracy by utilizing the difference in the etching rates of the plurality of insulating films. Therefore, the dose loss of the Si surface that occurs when the surface of the gate electrode 20 is scraped or the side surface of the gate electrode 20 is scraped and the etching reaches the Si surface, the variation in the gate length due to the side etching of the gate oxide film 23, and the It is possible to suppress an increase in the variation of the threshold voltage caused by that, stably manufacture the field effect transistor 10, and improve the reliability of the field effect transistor 10.

In addition, an opening P is provided from the upper surface of at least one layer of insulating film 80 toward the upper surface of the gate electrode 20, and the low dielectric constant region 70 is provided in this opening P. Therefore, the width WP of the opening P can be widened. Therefore, when a gap is formed near the gate electrode 20 by wet etching, the problem that the etching solution is hard to enter the narrow gap is solved. This makes it possible to improve the etching uniformity in the wafer surface of the SOI substrate 55 and the uniformity of the characteristics of the field effect transistor 10.

(Second embodiment)
In addition, in the said 1st Embodiment, the case where only the 1st metal M1 was laminated|stacked on contact plug 60S, 60D was demonstrated. However, the present disclosure is also applicable to the case where the second metal M2 is laminated on the first metal M1 as in the field effect transistor 10A shown in FIG. Further, in this case, the low dielectric constant region 70 is provided so as to extend also between the second metals M2 to reduce the capacitance (inter-wiring capacitance) CMM2 between the second metals M2 and reduce the off capacitance. It is possible to further suppress the external component Cex.

The second metal M2 is provided between the fourth insulating film 84 and the fifth insulating film 85. The first metal M1 and the second metal M2 are connected by a contact plug 94. Further, at least one layer of insulating film 80 further includes a seventh insulating film 87 that covers the upper surface of the fourth insulating film 84 and the surface of the second metal M2. The opening P penetrates the seventh insulating film 87, the fourth insulating film 84, and the third insulating film 83 from the upper surface of the seventh insulating film 87, and reaches the upper surface of the second insulating film 82. In the opening P, a void AG similar to that of the first embodiment is provided as the low dielectric constant region 70.

In the stacking direction Z, the gap AG is formed from a first region A1 below the lower surface of the first metal M1, a second region A2 between the lower surface and the upper surface of the first metal M1, and an upper surface of the first metal M1. Is also provided in the upper third region A3. In the third region A3, the void AG is provided between the first metal M1 and the second metal M2. Therefore, in the present embodiment, as in the first embodiment, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D or the capacitance CgM between the gate electrode 20 and the first metal M1, or , The capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1 is suppressed, and the capacitance (inter-wiring capacitance) CMM2 generated between the second metals M2 is also suppressed, and the external component of the off capacitance is reduced. Cex is reduced.

(Third Embodiment)
Further, in the first embodiment, the low dielectric constant region 70 is provided with a width W70 that is less than or equal to the width W82 of the portion of the first insulating film 81 and the second insulating film 82 that covers the surface of the gate electrode 20. I explained about the case. However, when the width of the finger portion 21 of the gate electrode 20 is reduced, the low dielectric constant region 70 of the first insulating film 81 and the second insulating film 82 is formed as in the field effect transistor 10B shown in FIG. The width W70 may be larger than the width W82 of the portion covering the surface of the gate electrode 20.

(Fourth Embodiment)
Furthermore, in the first embodiment, the case where the airtightly sealed gap AG is provided in the opening P as the low dielectric constant region 70 has been described. However, the low dielectric constant region 70 is not limited to the void AG, and may be made of a material having a lower dielectric constant than the third insulating film 83 and the fourth insulating film 84 (insulating film through which the opening P penetrates). Specifically, for example, when the third insulating film 83 and the fourth insulating film 84 are silicon oxide (SiO ₂ , dielectric constant 3.9) films, the fifth insulating film 85 is SiOC (carbon added). It is also possible to use silicon oxide and a dielectric constant of 2.9) so that at least a part of the opening P is filled with the fifth insulating film 85. For example, as in the field effect transistor 10C shown in FIG. 34, the first region A1 and the second region A2 of the low dielectric constant region 70 have a lower dielectric constant than the third insulating film 83 and the fourth insulating film 84. The insulating film 85 may be embedded. Further, a void AG may be provided in the third region A3 of the low dielectric constant region 70.

(Fifth Embodiment)
In addition, in the first embodiment, the case where the low dielectric constant region 70 is extended in parallel with the finger portions 21 of the gate electrode 20 has been described. However, as in the field effect transistor 10D shown in FIGS. 35 to 37, the low dielectric constant region 70 is in the direction intersecting with the finger portion 21 of the gate electrode 20, for example, with respect to the finger portion 21 of the gate electrode 20. It may be extended in the vertical direction (X direction). This makes it possible to reduce the influence of misalignment between the gate electrode 20 and the opening P and the low dielectric constant region 70. Further, in this case, a plurality of low dielectric constant regions 70 may be arranged side by side along the extension direction (Y direction) of the finger portions 21 of the gate electrode 20.

38 to 42 show a method of manufacturing the field effect transistor 10D according to the present embodiment in the order of steps. Note that steps that are the same as those in the first embodiment will be described with reference to FIGS. 19 to 31.

First, as shown in FIGS. 38 and 39, the gate electrode 20 is formed on the upper surface side of the semiconductor layer 50 by the process shown in FIGS. After forming the source region 50S and the drain region 50D in the layer 50, the first insulating film 81 to the third insulating film 83, the contact plugs 60S and 60D, the first metal M1 and the fourth insulating film 84 are formed.

Next, as shown in FIGS. 40 to 42, a resist film R1 is formed on the fourth insulating film 84, and an opening P is formed by dry etching using the resist film R1 as a mask.

Subsequently, the resist film R1 is removed, and as shown in FIGS. 35 to 37, the fifth insulating film 85 is formed on the fourth insulating film 84, and the upper part of the opening P is closed by the fifth insulating film 85. Then, the airtightly sealed space AG is formed in the opening P. By the above, the field effect transistor 10D shown in FIGS. 35 to 37 is completed.

(Sixth Embodiment)
Furthermore, in the first embodiment, as shown in FIG. 14, the low dielectric constant region 70 (the void AG or the like) is provided above the finger portion 21 of the gate electrode 20 in the active region AA. I explained about the case. However, as in the field effect transistor 10E shown in FIG. 43, the low dielectric constant region 70 can be provided above the finger portion 21 or above at least a part of the coupling portion 22. Specifically, the low dielectric constant region 70 is preferably provided above the region of the connecting portion 22 that avoids the finger portions 31D and the connecting portion 32D of the drain electrode 30D. In FIG. 43, the low dielectric constant region 70 above the finger portions 21 of the gate electrode 20 is omitted.

(Application example)
FIG. 44 shows an example of a wireless communication device. The wireless communication device 3 is, for example, a mobile phone system having multiple functions such as voice, data communication, and LAN connection. The wireless communication device 3 includes, for example, an antenna ANT, a high frequency switch 1, a high power amplifier HPA, a high frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, and a data output unit. It has a DT and an interface unit I/F (for example, a wireless LAN (W-LAN; Wireless Local Area Network), Bluetooth (registered trademark), etc.). The high frequency switch 1 is composed of the high frequency switch 1 described in the first embodiment with reference to FIGS. 1 to 5. The high frequency integrated circuit RFIC and the baseband unit BB are connected by an interface unit I/F.

In this wireless communication device 3, at the time of transmission, that is, when a transmission signal is output from the transmission system of the wireless communication device 3 to the antenna ANT, the transmission signal output from the baseband unit BB is the high frequency integrated circuit RFIC, It is output to the antenna ANT via the high power amplifier HPA and the high frequency switch 1.

Upon reception, that is, when a signal received by the antenna ANT is input to the reception system of the wireless communication device 3, the reception signal is input to the baseband unit BB via the high frequency switch 1 and the high frequency integrated circuit RFIC. The signal processed by the baseband unit BB is output from the audio output unit MIC, the data output unit DT, and the output unit such as the interface unit I/F.

Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above embodiments, and various modifications can be made.

Further, for example, in the above embodiment, the configurations of the high frequency switch 1, the field effect transistor 10, and the wireless communication device 3 are specifically described, but these are not limited to those including all the illustrated components. Not something. It is also possible to replace some of the components with other components.

In addition, although the case where the field effect transistor 10 is applied to the high frequency switch 1 of the wireless communication device 3 has been described in the above embodiment, the field effect transistor 10 may be a high frequency switch (RF-SW) or a PA (Power Amplifier). ) And other high frequency devices.

Furthermore, the shape, material and thickness of each layer described in the above embodiment, film forming method, etc. are not limited, and other shape, material and thickness may be used, or other film forming method may be used. Good.

Furthermore, for example, in the above embodiment, the case where the support substrate 53 of the SOI substrate 55 is a high resistance silicon substrate has been described. However, the SOI substrate 55 may be a so-called SOS (Silicon on Sapphire) substrate having the support substrate 53 made of sapphire. Since the support substrate 53 made of sapphire is insulative, the field effect transistor 10 formed on the SOS substrate exhibits characteristics closer to those of a compound FET such as GaAs. The present disclosure is applicable not only to the SOI substrate or the SOS substrate but also to the case where the field effect transistor 10 is formed on the bulk substrate.

It should be noted that the effects described in the present specification are merely examples and are not limited, and there may be other effects.

The present technology may have the following configurations.
(1)
A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A contact plug provided on the source region and the drain region,
A first metal laminated on the contact plug,
A low dielectric constant region provided in the region between the first metals in the in-plane direction of the semiconductor layer and at least in the first region below the lower surface of the first metal in the stacking direction. Field effect transistor.
(2)
The electric field according to (1), wherein the low dielectric constant region is provided in the first region and a second region between a lower surface of the first metal and an upper surface of the first metal in the stacking direction. Effect transistor.
(3)
The field effect transistor according to (2), wherein the low dielectric constant region is provided in the first region, the second region, and a third region above an upper surface of the first metal in the stacking direction. ..
(4)
At least one insulating film provided on the semiconductor layer,
An opening provided from the upper surface of the at least one insulating film toward the upper surface of the gate electrode,
The field effect transistor according to (3), wherein the low dielectric constant region is provided in the opening.
(5)
The field effect transistor according to (4), wherein the at least one insulating film includes a plurality of insulating films having different etching rates.
(6)
The at least one layer of insulating film,
A first insulating film covering the surface of the gate electrode and the upper surface of the semiconductor layer;
A second insulating film covering the surface of the first insulating film;
A third insulating film provided between the surface of the second insulating film and the lower surface of the first metal;
Including,
The second insulating film is made of a material having an etching rate different from that of the first insulating film and the third insulating film,
The field effect transistor according to (4) or (5), wherein the opening penetrates at least the third insulating film and reaches the upper surface of the second insulating film.
(7)
The at least one insulating film further includes a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal,
The field effect transistor according to (6), wherein the opening reaches an upper surface of the second insulating film from an upper surface of the fourth insulating film.
(8)
The at least one insulating film further includes a fifth insulating film on the fourth insulating film,
At least a part of the opening is provided with a void as the low dielectric constant region,
The field effect transistor according to (7), wherein the upper portion of the void is closed by the fifth insulating film.
(9)
The field effect transistor according to (8), wherein the fifth insulating film covers the side surface and the bottom surface of the opening.
(10)
The low dielectric constant region is provided with a width that is less than or equal to the width of the portion of the first insulating film and the second insulating film that covers the surface of the gate electrode. The field effect transistor described.
(11)
The gate electrode is extended in one direction,
The field effect transistor according to any one of (1) to (10), wherein the contact plug, the first metal, and the low dielectric constant region extend in parallel to the gate electrode.
(12)
An element region in which the source region and the drain region are provided in the semiconductor layer,
A wiring region having a multilayer wiring portion,
An element isolation layer for partitioning the element region and the wiring region,
The field effect transistor according to any one of (1) to (11), wherein the low dielectric constant region is provided in the element region.
(13)
An active area including the element area and the wiring area;
An element isolation region provided outside the active region and provided with the element isolation layer,
The element isolation region has a gate contact connected to the gate electrode on the element isolation layer,
The field effect transistor according to (12), wherein the low dielectric constant region is provided so as to avoid the gate contact.
(14)
A second metal is further provided between the fourth insulating film and the fifth insulating film,
The at least one insulating film further includes a seventh insulating film covering an upper surface of the fourth insulating film and a surface of the second metal,
The field effect transistor according to (8), wherein the opening reaches an upper surface of the second insulating film from an upper surface of the seventh insulating film.
(15)
The low dielectric constant region is provided with a width larger than a width of a portion of the first insulating film and the second insulating film which covers the surface of the gate electrode, (6) to (9). The field effect transistor described in 1..
(16)
The fifth insulating film made of a material having a lower dielectric constant than the third insulating film and the fourth insulating film is buried as the low dielectric constant region in at least a part of the opening. Field effect transistor.
(17)
The gate electrode is extended in one direction,
The contact plug and the first metal are extended parallel to the gate electrode,
The field effect transistor according to any one of (1) to (16), wherein the low dielectric constant region extends in a direction intersecting with the gate electrode.
(18)
The gate electrode has a plurality of finger portions that extend in the same direction, and a connecting portion that connects the plurality of finger portions,
The field effect transistor according to any one of (1) to (17), wherein the low dielectric constant region is provided above the finger portion or above at least a part of the connecting portion.
(19)
The field effect transistor according to any one of (1) to (18), which is a field effect transistor for a high frequency device.
(20)
A step of forming a gate electrode on the upper surface side of the semiconductor layer,
Forming a source region and a drain region on the semiconductor layer with the gate electrode interposed therebetween;
Providing a contact plug on the source region and the drain region,
Stacking a first metal on the contact plug,
Providing a low dielectric constant region in a region between the first metals in the in-plane direction of the semiconductor layer, at least in a first region below a lower surface of the first metal in a stacking direction. Production method.

DESCRIPTION OF SYMBOLS 1... High frequency switch, 3... Wireless communication device, 10, 10A-10E... Field effect transistor, 20... Gate electrode, 21... Finger part, 22... Connection part, 23... Gate oxide film, 24... Gate contact plug, 25... Gate contact layer, 30S... Source electrode, 31S... Finger part, 32S... Connection part, 30D... Drain electrode, 31D... Finger part, 32D... Connection part, 50... Semiconductor layer, 50S... Source region, 50D... Drain region, 51S , 51D... Low resistance region, 52S, 52D... Extension region, 53... Support substrate, 54... Buried oxide film, 55... SOI substrate, 60S, 60D... Contact plug, 70... Low dielectric constant region, 80... At least one layer of insulation Film, 81... First insulating film, 82... Second insulating film, 83... Third insulating film, 84... Fourth insulating film, 85... Fifth insulating film, 86... Sixth insulating film, 87... Seventh insulating film , 90... Multi-layer wiring part, 91... First wiring layer, 92... Second wiring layer, 93... Contact plug, 100... Element isolation layer, A1... First region, A2... Second region, A3... Third region, AA... Active area, AA1... Element area, AA2... Wiring area, AB... Element isolation area, AG... Void, M1... First metal, M2... Second metal, P... Opening.

Claims (31)

A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region, the contact plug including a first conductive material;
A plurality of first metals each laminated on the plurality of contact plugs and including a second conductive material different from the first conductive material;
One or more insulating films provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided in at least a region below the lower surface of the first metal in the stacking direction;
A low dielectric constant provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided at least between the lower surfaces of the plurality of first metals and the upper surface of the gate electrode in the stacking direction. Rate area and
The insulating film of one or more layers,
The first contact plug and the second contact plug are provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction. A first portion occupying a region between a side surface of the contact plug and a side surface of the gate electrode;
A second portion provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction;
The low dielectric constant region is constituted by a void provided inside the second portion of the one or more insulating films ,
The one or more insulating films include a third insulating film located outside a side portion of the void and a fourth insulating film provided at least between the side portion of the void and the third insulating film. Field effect transistor. The field effect transistor according to claim 1, wherein the first portion of the insulating film of one or more layers fills a space between the gate electrode and the plurality of contact plugs in an in-plane direction of the semiconductor layer. The upper end of the gap, the field effect transistor of claim 1, wherein is formed by the second portion of the one or more insulating films. The electric field according to claim 1 , wherein the upper end of the void is formed by the second portion of the insulating film of one or more layers and is provided at a position below the lower surface of the plurality of first metals in the stacking direction. Effect transistor. It said one or more insulating film further comprises a first insulating film and the second insulating film,
The first insulating film extends at least along a side surface of the gate electrode,
At least a part of the first insulating film is provided between the second insulating film and the gate electrode,
The third insulating film, wherein with in-plane direction of the semiconductor layer provided in a region between the plurality of contact plugs, are found provided below the lower surface of the plurality of first metal in the stacking direction field effect transistor according to any one of claims 1 to 4. The upper end of the front Symbol voids, the conjunction is formed by a fourth insulating film, field effect transistors of which claim 1 is provided on the lower surface following positions of the plurality of first metal in the stacking direction. Said second portion of said one or more insulating films, at least, the fourth field of claim 1 comprising a portion which is provided between the third insulating film and the side of the gap of the insulating film Effect transistor. The second portion of the insulating film of one or more layers includes a portion of the fourth insulating film provided between a side portion of the void and the third insulating film, and a portion of the third insulating film. field effect transistor of claim 1 further comprising a part which is provided between the fourth insulating film and the first contact plug and the side surface of the second contact plug. The remainder of the fourth insulating film, the third on the insulating film, field effect transistor of claim 1, wherein is provided covering the plurality of first metal surface. Further comprising a gate contact connected to the gate electrode,
The gate contact is covered with one or more insulating layers
The field effect transistor according to any one of claims 1 to 9. Further comprising a gate contact connected to the gate electrode,
The low dielectric constant region is provided so as to avoid overlapping with the gate contact in the in-plane direction of the semiconductor layer.
The field effect transistor according to any one of claims 1 to 9. An active region including the gate electrode, the semiconductor layer, and the plurality of contact plugs;
Wherein a gate contact connected to the gate electrode, the field-effect transistor according to any one of claims 1 to 9 and a device isolation region provided outside of the active area. The gate electrode is extended in one direction,
Wherein the plurality of contact plugs, wherein the plurality of first metal and said low dielectric constant region, the field effect transistor according to any one of the claims 1 are extended in parallel to the gate electrode 12. The field effect transistor according to any one of claims 1 to 13, wherein the third insulating film has a concave portion extending from an upper surface of the third insulating film toward an upper surface of the gate electrode. The field effect transistor according to claim 14, wherein the void is provided at least in the recess. The field effect transistor according to claim 14, wherein the fourth insulating film covers a side surface and a bottom surface of the recess. The field effect transistor according to claim 14, wherein the width of the void is smaller than the width of the upper portion of the recess. The field effect transistor according to claim 14, wherein a width of an upper portion of the recess is smaller than a width of an upper surface of the gate electrode. The field effect transistor according to any one of claims 16 to 18, wherein the bottom surface of the recess is made of silicon (Si) and nitrogen (N). 20. The thickness of the fourth insulating film between the void and the side surface of the recess is smaller than the thickness of the fourth insulating film between the void and the bottom surface of the recess. 2. The field effect transistor according to item 1. The first insulating film, said second insulating film, at least one of said third insulating film and the fourth insulating film, any of 5 to claim is provided between the gate electrode and the air gap 20 2. The field effect transistor according to item 1. The field effect transistor according to claim 5 , wherein the second insulating film extends at least along a side surface of the gate electrode. At least a part of the upper surface of the gate electrode is a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer. The field effect transistor according to claim 1, wherein only one is provided above. Further comprising a plurality of second metals provided above each of the plurality of first metals,
The field effect transistor according to any one of claims 1 to 23, wherein the low dielectric constant region extends at least up to the upper surfaces of the plurality of second metals in the stacking direction. The gate electrode has a plurality of finger portions that extend in the same direction, and a connecting portion that connects the plurality of finger portions,
The field effect transistor according to any one of claims 1 to 24, wherein the low dielectric constant region is provided above the finger portion or above at least a part of the connecting portion. The field effect transistor according to any one of claims 1 to 25, which is a field effect transistor for a high frequency device. The field effect transistor according to any one of claims 1 to 26, wherein the first conductive material includes tungsten. The field effect transistor according to claim 1, wherein the second conductive material includes aluminum. A high frequency switch having a field effect transistor;
A high-frequency integrated circuit connected to the high-frequency switch,
The field effect transistor is
A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region, the contact plug including a first conductive material;
A plurality of first metals each laminated on the plurality of contact plugs and including a second conductive material different from the first conductive material;
One or more insulating films provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided in at least a region below the lower surface of the first metal in the stacking direction;
A low dielectric constant provided in the region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided at least between the lower surfaces of the plurality of first metals and the upper surface of the gate electrode in the stacking direction. Rate area and
The insulating film of one or more layers,
The first contact plug and the second contact plug are provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and below the lower surfaces of the plurality of first metals in the stacking direction. A first portion occupying a region between a side surface of the contact plug and a side surface of the gate electrode;
A second portion provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer and above the upper surface of the gate electrode in the stacking direction;
The low dielectric constant region is constituted by a void provided inside the second portion of the one or more insulating films ,
The one or more insulating films include a third insulating film located outside the side portion of the void, and a fourth insulating film provided at least between the side portion of the void and the third insulating film. Wireless communication device. The wireless communication device according to claim 29, further comprising a baseband unit connected to the high-frequency integrated circuit. 30. The wireless communication device according to claim 29, further comprising an antenna connected to the high frequency switch.

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