Classifications

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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/10—Deposition of organic active material
  • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
  • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
• • H—ELECTRICITY
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/10—Deposition of organic active material
  • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
  • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/10—Deposition of organic active material
  • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
  • H10K77/10—Substrates, e.g. flexible substrates

Definitions

• the present invention relates to a process for preparing improved electronic devices, in particular organic field effect transistors (OFETs), with patterned insulator and organic semiconductor layers.
• OFETs organic field effect transistors
• OFETs Organic field effect transistors
• OSC organic semiconductor
• the semiconductor layer may be patterned by conventional lithography using an etching step to remove the layer from unwanted areas.
• OSC organic semiconductors
• US 5,854,139 discusses patterning an oligothiophene OSC by illuminating the OSC layer through an optical mask.
• WO 2006/048092 A1 suggests a process for patterning the OSC layer by applying an oxidizing agent to the OSC layer outside the channel areas, and reports that this leads to an improved on/off ratio.
• Another method reported for patterning the OSC layer suggested in prior art is based on varying the surface energy (wettability) of the surface around a transistor device. This concept of directing or confining a deposited drop via a surface energy gradient is a well known principle and is reported as being especially suitable for inkjet printing processes, as described for example in Appl. Phys. Lett. 79, 3536 (2001).
• an OSC layer with a crystallization pattern comprising regions having a high degree of crystallinity that exhibit high charge carrier mobility and regions having a low degree of crystallinity or even being amorphous that exhibit low charge carrier mobility.
• This can be simply achieved by providing an insulator layer onto which the OSC layer is subsequently applied, wherein the insulator layer contains a cross-linkable material, and wherein the cross-linking density in specific regions can be varied for example by UV irradiation through a shadow mask.
• Coating the processed insulator layer with an OSC formulation results in the formation of OSC crystals on the surface of the insulator layer only in regions which have been subjected to increased UV irradiation. On the other regions of the insulator layer the coated OSC will be amorphous or have a lower degree of crystallinity.
• the invention relates to a process of preparing an organic electronic (OE) device, comprising the steps of
• sequence of the two exposure steps can also be reversed, depositing an organic semiconductor (OSC) layer onto at least a part of the insulator layer,
• OSC organic semiconductor
• the OSC layer is in direct contact with at least a part of the areas of the insulator layer having a higher degree of cross-linking of the dielectric material.
• the process comprises, before the first exposure step, the step of partially cross-linking the dielectric material in one or more, but not all, areas of the insulator layer, thereby providing a pattern of areas that are cross-linked and areas that are not cross-linked, wherein the cross-linking of the dielectric material is preferably sufficient to provide solvent resistance.
• the process according to this preferred embodiment further comprises, after the first and second exposure steps, the step of removing any remaining dielectric material that was not cross- linked in the previous steps, for example by a solvent rinse.
• the invention further relates to an organic electronic (OE) device
• a top gate or bottom gate organic field effect transistor OFET
• the OE device is selected from the group consisting of organic field effect transistors (OFET), thin film transistors (TFT), components of integrated circuitry (IC), radio frequency identification (RFID) tags, organic light emitting diodes (OLED), electroluminescent displays, flat panel displays, backlights, photodetectors, sensors, logic circuits, memory elements, capacitors, organic photovoltaic (OPV) cells, charge injection layers, Schottky diodes, planarising layers, antistatic films, conducting substrates or patterns, photoconductors, photoreceptors,
• OFET organic field effect transistors
• TFT thin film transistors
• RFID radio frequency identification
• OLED organic light emitting diodes
• electroluminescent displays flat panel displays
• backlights photodetectors
• sensors logic circuits
• memory elements flat panel displays
• OLED organic photovoltaic
• OMV organic photovoltaic
• Figure 1 schematically depicts a typical bottom gate, bottom contact OFET of prior art.
• Figure 1B schematically depicts a typical bottom gate, top contact OFET of prior art.
• Figure 2 schematically depicts a typical top gate OFET of prior art.
• Figure 3A exemplarily and schematically depicts a process for preparing a bottom gate, bottom contact OFET according to the present invention.
• Figure 3B exemplarily and schematically depicts a process for preparing a bottom gate, top contact OFET according to the present invention.
• Figure 4A shows a cross-polariser microscope photography of an OFET of Example 1.
• Figures 4B-4D show the transfer characteristics of an OFET of Example 1.
• Figure 5A shows cross-polariser microscope photography of an OFET of Comparison Example 1.
• FIGS 5B-5D show the transfer characteristics of an OFET of
• Figure 6 shows the transfer characteristics of an OFET of Example 1 in comparison with an OFET of Comparison Example 1.
• Figure 7 shows the transfer characteristics of an OFET of Example 3.
• dielectric and "insulating” or “insulator” are used above and below interchangeably.
• reference to an insulator layer also includes a dielectric layer and vice versa.
• interlayer means a layer in an organic electronic device which is provided between two other functional layers or components of the device, for example between the gate insulator layer and the gate electrode, or between the gate insulator layer and the semiconductor layer.
• the area between the source electrode and the drain electrode, which is being covered by or being superposed to a gate electrode in an OFET device, is also referred to as the "channel area”.
• polymer generally means a molecule of high relative molecular mass, the structure of which essentially comprises the multiple repetition of units derived, actually or conceptually, from molecules of low relative molecular mass (see Pure Appl. Chem., 1996, 68, 2289).
• repeating unit or “monomeric unit” means the constitutional repeating unit (CRU), which is the smallest constitutional unit the repetition of which a regular macromolecule, a regular oligomer molecule, a regular block or a regular chain (see Pure Appl. Chem., 1996, 68, 2291).
• radiation and “photoradiation” should be understood to include any type radiation of a specific wavelength or wavelength range that may be used to induce a cross-linking reaction in a cross-linkable material according to the present invention, for example UV radiation.
• a cross-linkable material according to the present invention is cross-linkable by exposure to UV radiation, and the photoradiation used in the process of the present invention is UV radiation.
• the photoradiation used in the process of the present invention is UV radiation.
• any embodiment of a process as described above and below which refers to UV radiation may also be adapted to another type of photoradiation, for example radiation with a wavelength in the visible or infrared (IR) range, depending on the type of cross-linkable materials used.
• radiation dosage means the amount of radiation power (W) over a given area (cm 2 ) applied to a sample for a given time (s).
• the dosage is given in units of J/cm 2 and is usually defined for a specific wavelength or over a specific range of wavelengths.
• area and region are used interchangeably to describe a certain part of a device layer like the insulator layer or the OSC layer.
• the process according to the present invention preferably uses materials based on cross-linking, like for example [2+2] cross-linking, which may be photoinduced or thermally induced or a combination of both, as
• insulators in particular as organic gate insulator (OGI), in an OE device, preferably an OFET, very preferably an OFET with bottom gate (BG) configuration.
• OGI organic gate insulator
• BG bottom gate
• the insulator layer exhibits a pattern of regions that have been exposed only to the first or second radiation dosage and regions that have been exposed both to the first and the second radiation dosage.
• Coating the processed and patterned insulator layer with a spin coated OSC formulation will then result in the formation of crystals of the OSC material on the surface of the insulator only in regions which have been exposed to an increased UV radiation dosage.
• the coated OSC material forms an amorphous or less crystalline layer.
• the method of creating an OSC layer with a crystallisation pattern according to the present invention is not based on changing the surface energy by photoirradiation, as disclosed for example in US 2007/0096088 A1. Also, the surface energy does not change significantly and there is no new surface chemistry introduced.
• the inventors of the present invention believe that the patterned crystallisation observed in the OSC layer as described above and below is related to the cross-linking density of the insulator layer onto which the OSC layer is deposited.
• a certain hardness is required for OSC crystals to be formed on the surface of the insulator, hereby the hardness is linked to the cross-linking density.
• the corresponding cross-linking density Rc where crystals begin to form is significantly higher than the cross-linking density Rs necessary to achieve insolubility of the insulator.
• the coated OSC formulations are resulting in amorphous noncrystalline films.
• cross-linkable polymeric insulator materials based e.g. on 2+2- coupling chemistry (or other bimolecular cross-linking reactions)
• the cross-linking density can be easily controlled by the amount of incident photons (e.g. the radiation dosage) provided to the system.
• the cross-linking chemistry is preferably based on individual and nearly independent bi-molecular 2+2 coupling reactions without any self-propagating effect and not on a chain reaction.
• the inventors of the present invention do further believe that the formation of OSC crystals is linked to the amount of swelling and/or penetration of the insulator layer surface by the OSC formulation deposited onto the OGI layer in a subsequent device manufacturing step.
• the process according to the present invention can be advantageously used for example to decrease the off-current in OFET devices, especially BG OFETs, by confining OSC crystal formation solely to the channel area.
• This allows area-coating techniques such as spin coating to recreate the low off-currents of patterned deposition methods such as UP.
• it can be used in combination with other patterning methods to increase resolution for example of flexographic printing. Thereby the resolution of those printing techniques will be lower than the transistor feature sizes, so that the process of the present invention can also be used for fine-tuning and/or improving positional accuracy. Therefore, it may be that no further layers, such as bank structures, are needed.
• UV irradiation usually enables positional patterning of the subsequent OSC layer (e.g. by solvent based deposition, usually using ink-jet printing) by varying the surface energy (or wettability) of the surface around a transistor device.
• This concept of directing or confining a deposited drop via a surface energy gradient is a well known principle and is described for example in Appl. Phys. Lett. 79, 3536 (2001).
• the wettability/surface energy of the substrate i.e. the OGI
• the wettability/surface energy of the substrate itself is not significantly affected by the photoradiation, as the irradiation does not lead to any chemical change except for the intended cross-linking reaction.
• the effect of the different radiation dosages is to produce regions with different cross-linking density of the insulator.
• the transistor characteristics are mainly determined by the hard cured regions with crystalline OSC morphology. As a result the transistor performance is very similar to that of a device obtained by physical patterning of the OGI and/or OSC layer.
• the OSC is deposited over the whole area of the device and not physically patterned by depositing the OSC only into the active transistor device area.
• the process can thus be described as "simulated" patterning, and is especially advantageous for low-resolution printing methods like e.g. flexo-printing or gravure-printing, where large areas are covered by the OSC, and where surface energy induced patterning concepts are not efficient in confining the relatively high amount of ink deposited.
• the method according to the present invention provides further
• the channel areas can be defined as the crystallisation area, and therefore, although the drop still covers a large region, crystallisation will only take place in the patterned channel region. This can lead to improved crystal morphology in devices prepared by ink-jet printing, and can eliminate at least some of the detrimental morphologies seen when ink-jetted drops undergo the so-called "coffee stain effect".
• Another advantage is that a low resolution process such as flexoprinting can be used to create high resolution patterned channels, without the complexity of removing the OSC material, or the cost of a higher resolution technique.
• the insulator layer - some areas of the insulator layer are not exposed to photoradiation, and are then developed at the end of the patterning process of the insulator layer, for example by removing the uncrosslinked dielectric material using a solvent rinse.
• This method is suitable to create vias through the dielectric material such that electrical contact can be made, - in the first irradiation step the radiation dosage is selected such that the cross-linking reaction in the cross-linkable dielectric material is only partial, i.e. not complete,
• some of the partially cross-linked areas of the insulator layer are further cross-linked or fully cross-linked, wherein full cross-linking may also be achieved by subsequent annealing of the insulator layer,
• the cross-linking density in the insulator layer is varied, yielding varying degrees of hardness and swelling coefficient in different areas of the insulator layer, which results in different degrees of crystallization of the OSC deposited on the respective different areas of the insulator layer,
• the areas of the insulator layer to which a higher radiation dosage is applied are the areas intended for a high crystallinity and high performance of the OSC deposited onto the insulator layer (i.e. opposite to the prior art concepts described above), - apart from the cross-linking reaction of the dielectric material of the insulator layer, preferably no further chemical reactions and/or novel groups are formed at the surface of the insulator layer,
• the polarity of the surface and the permittivity of the dielectric material of the insulator layer is preferably not changed to any significant extent during the process according to the present invention (a possible change in the surface energy of the insulator layer by applying varying radiation dosages is not intended, however minor changes in the surface energy are not excluded),
• the process is used for large area printing methods (where a physical patterning based on surface energy induced effects is not feasible or practical). Thereby a higher resolution of patterning can be achieved than that acheviable by the deposition technique itself.
• the first radiation exposure step is substituted by a thermal annealing step (in case the dielectric material is a thermally curable material) to partially cross-link the dielectric material.
• the second radiation step is then carried out by using photo-irradiation in the case of a dual photocurable/thermal curable system, or by using a laser to thermally pattern the substrate (in case the material is only thermally curable).
• the procedure of exposure to a first radiation dosage for partial cross-linking and then to a second dose for further/full cross-linking of the dielectric material is reversed.
• the radiation dosage is provided through a shadow mask, and induces complete or partial cross- linking of the unmasked (i.e. exposed) dielectric material.
• the radiation dosage is lower than in the first exposure step, and is for example a flood irradiation, to cross-link and thus insolubilise the areas that were masked in the first exposure step.
• partial cross-linking and “partially cross-linked” as used above and below mean that not all, but only a portion, of the cross-linkable moieties in the cross-linkable dielectric material will react by a cross- linking reaction, for example upon exposure to a first radiation dosage.
• “Further cross-linking " or “higher degree of cross-linking” means that at least some of the cross-linkable moieties, which have not reacted in the previous irradiation step, will react by a cross-linking reaction for example in a subsequent irradiation step and/or in an annealing step.
• the process according to the present invention comprises the following steps a) depositing a gate electrode for example of Al, onto a substrate, for example by evaporation,
• b1) optionally patterning the insulator layer to leave areas that contain cross-linked dielectric material and areas that do not contain cross-linked dielectric material, wherein the degree of cross-linking of the dielectric -j Q material is sufficient to provide solvent resistance, preferably by exposing the insulator layer to photoradiation through a photomask or shadow mask or by exposing the insulator layer to thermal energy using a thermal laser to heat only selected areas,
• step b1 (which has not yet been cross-linked in step b1), preferably by exposing the entire insulator layer, and preferably without exposing different parts of the insulator layer to different radiation dosages, thereby inducing a cross- linking reaction in the cross-linkable dielectric material, wherein the
• step c) preferably by photoirradiation through a photomask or shadow mask or by using a thermal laser, wherein the exposed areas are those areas where a crystalline OSC material in a subsequently superposed OSC layer is desired, preferably the channel area, as a result of which the insulator layer exhibits areas of high and low cross-linking density,
• d1) optionally removing any remaining dielectric material that was not cross-linked in the previous steps, for example by a solvent rinse, e) depositing source and drain electrodes, for example of Au or Ag, for example by evaporation, onto the insulator layer,
• step d) is carried out before step c), and/or optionally step f) is carried out before step e), and
• the area between the source electrode and the drain electrode is the channel area
• the OSC layer is in direct contact with the insulator layer at least in the channel area or at least in an area that is entirely superposed by the channel area.
• the source and drain electrodes are deposited on to OGI layer before the OSC layer, so that steps e) and f) are carried out in the sequence as described above.
• the OSC layer is deposited onto the OGI layer before the source and drain electrodes.
• step f) is carried out before step e).
• OSC crystals are then formed in step f) mainly (preferably only) on those regions of the insulator surface where the insulator material was exposed to the second radiation dosage in step d), and consequently has an increased cross-linking density. On other regions of the insulator surface the OSC material is amorphous or has lower crystallinity.
• step a) a step of cleaning the substrate is carried out before step a) and a surface treatment can be applied to increase adhesion between the substrate and insulator layer can be applied.
• Figure 1A is a schematic representation of a typical BG, bottom contact OFET according to prior art, including a gate electrode (2) provided on a substrate (1), a layer of dielectric material (3) (gate insulator layer), source (S) and drain (D) electrodes (5), a layer of OSC material (4), and an optional second insulator or protection layer (6) to shield or protect the OSC layer and the S/D electrodes from further layers or devices that may be later provided thereon or from environmental influence.
• the distance between the source and drain electrodes (5), as indicated by the double arrow, is the channel area.
• Figure 1B is a schematic representation of a typical BG, top contact
• OFET including a gate electrode (2) provided on a substrate (1), a layer of dielectric material (3) (gate insulator layer), a layer of OSC material (4), source (S) and drain (D) electrodes (5), and an optional protection layer (6) to shield or protect the OSC layer and the S/D electrodes from further layers or from environmental influence.
• Figure 2 is a schematic representation of a typical TG OFET according to prior art, including source and drain electrodes (5) provided on a substrate (1), a layer of OSC material (4), a layer of dielectric material (3) (gate insulator layer), a gate electrode (5), and an optional second insulator or protection layer (6) to shield the gate electrode from further layers or devices that may be later provided.
• FIG. 3A exemplarily and schematically illustrates a process for preparing a bottom gate, bottom contact OFET device in accordance with the present invention.
• the reference numbers of a layer provided in a single step as shown in Figure 3A are not always displayed in the next step.
• a gate electrode (20) is deposited onto a substrate (10), the surface of which has preferably been cleaned before depositing the gate electrode.
• a layer of cross-linkable dielectric material (30) is deposited onto the gate electrode to serve as gate insulator layer.
• a photo-patterning step b1) wherein the dielectric material is masked and subjected to photoradiation, so that only the unmasked parts are cross-linked. Any remaining parts of the masked dielectric material in this step, which are also not subjected to the two radiation doses in the next steps c) and d), can then later be removed by a developing process, for example by a solvent rinse.
• the dielectric material is completely masked from the two radiation doses in the next steps c) and d) so that only the unmasked parts are cross-linked. Any parts of the masked dielectric material following these steps, which are not subjected to the two radiation doses, can then later be removed by a developing process, for example washing by a solvent rinse.
• the dielectric material (30) is exposed to a first radiation dosage (indicated by the arrows) that induces cross-linking in the dielectric material, but wherein the radiation dosage is selected such that the cross- linking reaction is not complete, resulting in a partially cross-linked gate insulator layer (31).
• the gate insulator layer containing the partially cross- linked dielectric material (31) is covered by a photomask or shadow mask (70) and is then exposed to a second radiation dosage (indicated by the arrows).
• the photomask (70) has a pattern of regions which are
• step d) before step c), so that the first radiation dose is used for partial cross-linking and the second dose for futher/full cross-linking of the dielectric material, as described in the preferred embodiment above.
• step d1) is carried out where any remaining dielectric material that has not been cross-linked in the previous steps is removed, e.g. by washing away with a solvent rinse.
• source and drain electrodes (50) are deposited onto the gate insulator layer.
• a layer of an organic semiconductor (OSC) material is deposited onto the source/drain electrodes (50) and the gate insulator layer, optionally followed by an annealing step.
• OSC crystals are formed mainly, preferably only, in those regions of the OSC layer (42) that are in contact with the regions of the insulator layer surface (32) where the dielectric material was fully exposed to the second radiation dosage in step d) and consequently has a higher cross-linking density.
• the surface the OSC material is amorphous or less crystalline.
• FIG. 3B exemplarily and schematically illustrates a process for preparing a bottom gate, top contact OFET device in accordance with the present invention.
• Steps a)-d) are carried out as described above for the process of Figure 3A.
• a layer of OSC material is deposited onto the gate insulator layer, optionally followed by an annealing step.
• OSC crystals are formed mainly, preferably only, in those regions of the OSC layer (42) that are in contact with the regions of the insulator layer surface (32) where the dielectric material was fully exposed to the second radiation dosage in step d) and consequently has a higher cross-linking density.
• the surface the OSC material is amorphous.
• source and drain electrodes (50) are then deposited onto the OSC layer (41 , 42).
• one or more further insulator or protective layers are provided onto the OSC layer (not shown in Figure 3A and 3B).
• the photoradiation can also be replaced by thermal energy, and instead of a photomask a thermal laser can be used to heat only selected areas.
• the process according to the present invention is not limited to OFETs, but can be used in the manufacture of any OE device where an OSC layer is deposited onto an insulator layer so as to be in direct contact with at least a part of the insulator layer.
• the skilled person can easily make modifications or changes to the process as described above and below, in order to use it for the manufacture of other OE devices.
• a TG OFET device is manufactured using the patterned insulator layer, which is preferably an OGI, as a substrate.
• the patterned insulator layer which is preferably an OGI
• the OGI By coating a glass substrate with a layer of the OGI, and subsequent patterning using the process described above, crystallisation of the OSC can be induced only in the channel region.
• the effect can be used to reduce the off-current of the OFET device when compared to a standard non-patterned process.
• a preferred process of preparing a top gate OFET device comprises the following steps:
• insulator layer containing the cross-linkable dielectric material is deposited on a substrate, e.g. a glass or plastic substrate, e.g. by coating or printing,
• a layer of an OSC material is deposited onto the insulator layer and the source and drain electrodes, e.g. by coating or printing, resulting in a high degree of crystallinity of the OSC in the patterned channel area and amorphous morphology or a lower degree of crystallinity in the other areas of the device,
• an organic gate insulator (OGI) layer is deposited onto the
• a preferred dielectric material for use in the gate insulator layer comprises or consists of a material with a low permittivity of between 1.5 and 3.3 at 1000Hz and 20°C, like for example Cytop® 809m available from Asahi Glass,
• a gate electrode is formed on the OGI layer.
• the cross-linkable insulator layer is for example an OGI layer, but can also represent a dielectric interlayer that is provided between the OSC layer and other functional layers such as the OGI layer.
• Such an interlayer can also have additional functions, for example to promote or improve adhesion between the OGI and the OSC.
• the cross-linkable insulator layer is a gate insulator layer. In another preferred embodiment of the present invention, the cross-linkable insulator layer is an interlayer.
• a gate insulator layer for example comprising a conventional organic dielectric material, is deposited in a step b1) onto a substrate or onto a gate electrode as described above.
• a second insulator layer comprising a cross-linkable dielectric material insulator is deposited onto the gate insulator layer, and subjected to the first and second radiation dosage as described above for steps c) and d).
• Source and drain electrodes and an OSC layer are then deposited onto the second insulator layer as described above for steps e) and f).
• Especially preferred are the following embodiments:
• the OE device is a BG, top contact OFET,
• the OE device is a BG, bottom contact OFET,
• the OE device is a TG OFET
• the insulator layer is a gate insulator layer or an interlayer
• the OSC layer comprises an optionally substituted polyacene
• the second radiation dosage is higher than the first radiation dosage
• the first radiation dosage is the same as the second radiation dosage
• the radiation is UV radiation, preferably with a wavelength in the range from 250 to 400nm, more preferably from 300 to 400nm,
• the radiation is UVA radiation, preferably with a wavelength of 365nm,
• the radiation is UVB radiation, preferably with a wavelength ranging from 320 to 390nm,
• the radiation is UVC radiation, preferably with a wavelength of 254nm,
• the first and/ or second radiation dosage is from 0.1 mJ/cm 2 to 15
• J/cm 2 preferably from 0.1 to 5 J/cm 2 , for a wavelength from 300 to 400nm, depending on the cross-linkable material
• the insulator layer is selectively protected by a patterned protective layer or a photomask or shadow mask, which prevents selected regions of the insulator at least partially from being exposed to the second radiation dosage,
• the insulator layer is selectively protected by a patterned protective layer or a photomask or shadow mask, which prevents selected regions of the insulator at least partially from being exposed to the first radiation dosage,
• Thermally cross-linkable or dual UV/thermally cross-linkable dielectric materials can also be used.
• thermally cross-linkable dielectric materials techniques such as laser curing can be used to achieve patterning.
• the flood illumination step (either before of after the patterning step) can also be replaced by a thermal annealing step to achieve solvent resistance.
• the material for preparing the insulator layer is preferably selected from photocross-linkable or thermally cross-linkable dielectric polymers such as polyvinyl cinnamates or polycycloolefins comprising cross-linkable moieties, like epoxy, maleimide, coumarin or indane groups.
• Suitable and preferred materials are for example LisiconTMD203 or LisiconTMD206 (commercially available from Merck KGaA, Darmstadt, Germany).
• the deposition of individual functional layers in the process as described above and below, like the OSC layer and the insulator layer, is carried out using solution processing techniques.
• This can be done for example by applying a formulation, preferably a solution, comprising the OSC or dielectric material, respectively, and further comprising one or more organic solvents, onto the previously deposited layer, followed by evaporation of the solvent(s).
• Preferred deposition techniques include, without limitation, dip coating, spin coating, ink jet printing, letter-press printing, screen printing, doctor blade coating, roller printing, reverse-roller printing, offset lithography printing, flexographic printing, web printing, spray coating, brush coating, or pad printing.
• Very preferred solution deposition techniques are spin coating, flexographic printing and inkjet printing.
• the insulator layer is deposited by solution processing, very preferably using a solution of a cross-linkable material as described above and below in one or more organic solvents.
• the solvent used for depositing the dielectric material is orthogonal to the solvent used for depositing the OSC material, and vice versa.
• Suitable solvents are selected from solvents including but not limited to hydrocarbon solvents, aromatic solvents, cycloaliphatic cyclic ethers, cyclic ethers, acetated, esters, lactones, ketones, amides, cyclic
• solvents examples include cyclohexanone, mesitylene, xylene, 2- heptanone, toluene, tetrahydrofuran, MEK, MAK (2-heptanone),
• cyclohexylbenzene very preferably MAK, butyl phenyl ether or
• the total concentration of the respective functional material in the insulator formulation is from 0.1 to 30 wt.%, preferably from 1 to 5 wt. %.
• organic ketone solvents with a high boiling point are particularly preferred.
• the dielectric material is spun for example between 200 and 4000 rpm, preferably between 500 and 2000rpm for a period of for example 30 seconds to give a layer with a typical layer thickness between 0.1 and 1.5 ⁇ .
• the film can be heated at an elevated temperature to remove all residual volatile solvents.
• the cross-linkable dielectric material after deposition is preferably exposed to electron beam or electromagnetic (actinic) radiation, like for example X-ray, UV, IR or visible radiation.
• actinic radiation can used having a wavelength of from 50 nm to 700 nm, preferably from 200 to 450 nm, most preferably from 300 to 400 nm.
• Suitable radiation dosages are typically in the range from from 5 to 5,000 mJ/cm 2 .
• Suitable radiation sources include mercury, mercury/xenon, mercury/halogen and xenon lamps, argon or xenon laser sources, x-ray, or e-beam.
• the exposure to actinic radiation will induce a cross-linking reaction in the cross-linkable groups of the dielectric material in the exposed regions. It is also possible for example to use a light source having a wavelength outside the absorption band of the cross-linkable groups, and to add a radiation sensitive photosensitizer to the cross- linkable material.
• the dielectric material layer is annealed after exposure to radiation, for example at a temperature from 70°C to 130°C, for example for a period of from 1 to 30 minutes, preferably from 1 to 10 minutes.
• the annealing step at elevated temperature can be used to complete the cross-linking reaction that was induced by the exposure of the cross- linkable groups of the dielectric material to photoradiation.
• photoirradiation step a commercially available UV lamp and photomask can be used, and the annealing step can be carried out in an oven or on a hot plate.
• the thickness of a functional layer in an electronic device according to the present invention is preferably from 1 nm (in case of a monolayer) to 10 ⁇ , very preferably from 1 nm to 1 ⁇ , most preferably from 5 nm to 500 nm.
• Various substrates may be used for the fabrication of organic electronic devices, for example glass or plastics, plastics materials being preferred, examples including alkyd resins, allyl esters, benzocyclobutenes, butadiene-styrene, cellulose, cellulose acetate, epoxide, epoxy polymers, ethylene-chlorotrifluoro ethylene, ethylene-tetra-fluoroethylene, fibre glass enhanced plastic, fluorocarbon polymers, hexafluoropropylenevinylidene- fluoride copolymer, high density polyethylene, parylene, polyamide, polyimide, polyaramid, polydimethylsiloxane, polyethersulphone, polyethylene, polyethylenenaphthalate, polyethyleneterephthalate, polyketone, polymethylmethacrylate, polypropylene, polystyrene, polysulphone, polytetrafluoroethylene, polyurethanes, polyvinylchloride, silicone rubbers, and silicones.
• Preferred substrate materials are polyethyleneterephthalate, polyimide, and polyethylenenaphthalate.
• the substrate may be any plastic material, metal or glass coated with the above materials.
• the substrate should preferably be homogeneous to ensure good pattern definition.
• the substrate may also be uniformly pre-aligned by extruding, stretching, rubbing or by photochemical techniques to induce the orientation of the organic semiconductor in order to enhance carrier mobility.
• the electrodes can be deposited by liquid coating, such as spray-, dip-, web- or spin-coating, or by vacuum deposition or vapor deposition methods.
• Suitable electrode materials and deposition methods are known to the person skilled in the art.
• Suitable electrode materials include, without limitation, inorganic or organic materials, or composites of the two.
• suitable conductor or electrode materials include polyaniline, polypyrrole, PEDOT or doped conjugated polymers, further dispersions or pastes of graphite or particles of metal such as Au, Ag, Cu, Al, Ni or their mixtures as well as sputter coated or evaporated metals such as Cu, Cr, Pt/Pd or metal oxides such as indium tin oxide (ITO).
• Organometallic precursors may also be used deposited from a liquid phase.
• the OSC materials and methods for applying the OSC layer can be selected from standard materials and methods known to the person skilled in the art, and are described in the literature.
• the OFET layer is an OSC
• it may be an n- or p- type OSC, which can be deposited by vacuum or vapor
• OSCs have a FET mobility of greater than 1x10 "5 cmW 1 .
• the OSC is used for example as the active channel material in an OFET or a layer element of an organic rectifying diode.
• OSCs that are deposited by liquid coating to allow ambient processing are preferred.
• OSCs are preferably spray-, dip-, web- or spin-coated or deposited by any liquid coating technique. Ink-jet deposition is also suitable.
• the OSC may optionally be vacuum or vapor deposited.
• the semiconducting channel may also be a composite of two or more of the same types of semiconductors.
• a p-type channel material may, for example be mixed with n-type materials for the effect of doping the layer.
• Multilayer semiconductor layers may also be used.
• the semiconductor may be intrinsic near the insulator interface and a highly doped region can additionally be coated next to the intrinsic layer.
• the OSC may be a monomeric compound (also referred to as "small molecule", as compared to a polymer or macromolecule) or a polymeric compound, or a mixture, dispersion or blend containing one or more compounds selected from either or both of monomeric and polymeric compounds.
• the OSC is a semicrystalline, crystalline or polycrystalline compound.
• the OSC is a monomeric compound, where it is easier to achieve a significant variation in the degree of crystallinity. Further preferred is a polymeric semicrystalline OSC material.
• the OSC is preferably a conjugated aromatic molecule, and contains preferably at least three aromatic rings.
• Preferred monomeric OSCs contain 5, 6 or 7 membered aromatic rings, and more preferably contain 5 or 6 membered aromatic rings.
• Each of the aromatic rings optionally contains one or more hetero atoms selected from Se, Te, P, Si, B, As, N, O or S, preferably from N, O or S.
• the aromatic rings may be optionally substituted with alkyl, alkoxy, polyalkoxy, thioalkyl, acyl, aryl or substituted aryl groups, halogen, particularly fluorine, cyano, nitro or an optionally substituted secondary or tertiary alkylamine or arylamine represented by -N(R 3 )(R 4 ), where R 3 and R 4 each independently is H, optionally substituted alkyl, optionally substituted aryl, alkoxy or polyalkoxy groups. Where R 3 and R 4 is alkyl or aryl these may be optionally fluorinated.
• T 1 and T 2 each independently represent H, CI, F, -C ⁇ N or lower alkyl groups particularly C ⁇ alkyl groups;
• R * represents H, optionally substituted alkyl or optionally substituted aryl. Where R' is alkyl or aryl these may be optionally fluorinated.
• OSC materials that can be used in this invention include compounds, oligomers and derivatives of compounds selected from the group comprising conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly(phenylene vinylene), polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as tetracene, chrysene, pentacene, pyrene, perylene, coronene, or soluble, substituted derivatives of these; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P), p-quinquephenyl (p-5P), p-sexiphenyl (p-6P), or soluble substituted derivatives of these; conjugated heterocyclic polymers such as poly(3-substituted thiophene), poly(3,4-bisubstituted thiophene), optionally substituted polythieno[2,3- bjthiophen
• stilbene compounds triazines; substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines or fluoronaphthalocyanines; C 6 o and C70 fullerenes; ⁇ /, ⁇ / -dialkyl, substituted dialkyl, diaryl or substituted diaryl-1 ,4,5,8-naphthalenetetracarboxylic diimide and fluoro derivatives; N,N -dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9, 10-perylenetetracarboxylicdiimide;
• bathophenanthroline diphenoquinones; 1 ,3,4-oxadiazoles; 1 1 ,1 1 ,12,12- tetracyanonaptho-2,6-quinodimethane; a,a'-bis(dithieno[3,2-b2 , 1 3'- djthiophene); 2,8-dialkyl, substituted dialkyl, diaryl or dialkynyl
• anthradithiophene 2,2'-bibenzo[1 ,2-b:4,5-b']dithiophene.
• Preferred compounds are those from the above list and derivatives thereof which are soluble in organic solvents.
• Especially preferred OSC materials are polymers or copolymers
• thiophene-2,5-diyl comprising one or more repeating units selected from thiophene-2,5-diyl, 3-substituted thiophene-2,5-diyl, optionally substituted thieno[2,3- b]thiophene-2,5-diyl, optionally substituted thieno[3,2-b]thiophene-2,5-diyl, selenophene-2,5-diyl, or 3-substituted selenophene-2,5-diyl.
• OSC materials are are substituted oligoacenes such as pentacene, tetracene or anthracene, or heterocyclic derivatives thereof, like bis(trialkylsilylethynyl) oligoacenes or bis(trialkylsilylethynyl)
• the OSC layer comprises one or more organic binders to adjust the rheological properties as described for example in WO 2005/055248 A1 , in particular an organic binder which has a low permittivity, ⁇ , at 1,000 Hz and 20°C of 3.3 or less.
• the binder is selected for example from poly(a-methylstyrene),
• the binder may also be a semiconducting binder selected for example from polyarylamines, polyfluorenes, polythiophenes, polyspirobifluorenes, substituted polyvinylenephenylenes, polycarbazoles or polystilbenes, or copolymers thereof.
• ⁇ is the charge carrier mobility
• W is the length of the drain and source electrode (also known as
• L is the distance between the drain and source electrode (also known as “channel length")
• C is the capacitance per unit area of the gate dielectric
• V G is the gate voltage (in V)
• V D s is the source-drain voltage
• V 0 is the offset voltage
• oligomers and polymers means the weight average molecular weight M w , which can be determined by GPC in a suitable solvent against polystyrene standards.
• Example 1 Patterned BG OFET device using a high dose UVB treatment
• a bottom gate OFET is prepared as follows and as illustrated by Figure 3A: A substrate of Corning Eagle XG glass is sonicated in 3% Decon90 for 30min at 70°C, washed 2 times with water and sonicated in MeOH, then dried by spin off on the spin coater.
• Aluminium gate electrodes of 30nm thickness are evaporated onto the substrate (step a).
• a dielectric layer of LisiconTM D203 (available from Merck KGaA,
• step b is spun onto the substrate (1500 rpm for 30 s) and heated on a hotplate for 1 min at 120°C (step b).
• step c The entire substrate is exposed to UVB irradiation between 320-390 nm for 30 seconds at a power of 0.1 W/cm 2 (total dose is 3 J/cm2) (step c).
• step d The substrate is then exposed through a shadow mask to a second dose of UVB irradiation between 320-390 nm for 30s at a power of 0.1 W/cm2 (step d).
• the areas exposed in this step are those in which crystallisation is required.
• the substrate is treated with the surface treatment formulation LisiconTM M001 (available from Merck KGaA, Darmstadt, Germany) for 1min, washed with isopropyl alcohol and dried by spin off on the spin coater (step e).
• LisiconTM M001 available from Merck KGaA, Darmstadt, Germany
• the OSC Formulation LisiconTM S1200 (available from Merck KGaA, Darmstadt, Germany) is spun onto the substrate after above treatment and then annealed for 1 min at 100°C on a hotplate (step f).
• the device can be passivated as a final step.
• a bottom gate OFET device is constructed in an identical fashion to that in Example 1 , except that the shadow mask is not applied in step d, making the two exposure steps (c and d) identical, and thus equivalent to a single exposure of UVB irradiation for 60s at a power of 0.1 W/cm 2 .
• Figure 4A shows a patterned device prepared according to Example 1 and observed through a polarizing microscope. It can be seen that the areas which have received the increased UV dose show the formation of crystals, whereas the areas which have received the lower UV dosage show no crystal formation and appear black.
• Figure 5A illustrates a non patterned device prepared according to Comparison Example 1 and observed through a polarizing microscope, In this example there is no differentiation between the cross-linking density / UV dosage across the substrate, and hence the formation of crystals occurs over the entire substrate.
• Figures 4B-D show the typical transistor performance of a patterned device prepared according to Example 1.
• Figures 5B-D show the typical transistor performance of a non-patterned device prepared according to Comparison Example 1. It can be clearly seen that the off currents measured in the patterned device are lower that that seen in the unpatterened device. This positive effect is seen at no significant detrement to the linear and saturated mobility values, or the value of the on current.
• Patterned BG OFET device using a low dose UVA treatment The bottom gate OFET device in this example is constructed in an identical fashion to that in Example 1 , except that the dielectric layer material LisiconTMD203 is substituted by LisiconTMD206 in step b, the UV dose used in step c is UVA (365nm) at a power of 0.01 W/cm 2 for 30 seconds (0.3 J/cm 2 dose), and the UV dose used in step d is UVA
• Figure 6 shows the typical transistor performance of a device prepared by the method described in Example 2 with 365nm UVA radiation, which has been fabricated in such a way to produce both patterned and
• unpatterened areas half the substrate was irradiated without the use of a shadow mask.
• Measurement of the transistor characteristics shows the patterning to have an effect on reducing the off current to the detection limit of the apperatus.
• the unpatterned device shows a higher, and less stable value for the off current. There is no change in the measured on- current.
• Patterned TG OFET device using a high dose UVA dielectric as a patternable interlaver / substrate A patterned top gate OFET device is prepared as follows. A substrate of Corning 1737 glass is sonicated in 3% Decon90 for 30min at 70°C, washed 2 times with water and sonicated in MeOH, then dried by spin off on the spin coater. A dielectric layer of LisiconTMD203 (available from Merck KGaA, Darmstadt, Germany) is spun onto the substrate (1500 rpm for 30 s) and heated on a hotplate for 1 min at 120°C (step aa).
• LisiconTMD203 available from Merck KGaA, Darmstadt, Germany
• the entire substrate is exposed to UVB irradiation between 320-390 nm for 30 seconds at a power of 0.1 W/cm 2 (total dose is 3 J/cm 2 ).
• the substrate is then exposed through a shadow mask to a second dose of UVB irradiation between 320-390 nm for 30s at a power of 0.1 W/cm 2 (step bb).
• the areas exposed are those in which crystallisation is required.
• the substrate is treated with the surface treatment formulation LisiconTM M001 (available from Merck KGaA, Darmstadt, Germany) for 1min, washed with isopropyl alcohol and dried by spin off on the spin coater.
• the OSC Formulation LisiconTM S1200 (available from Merck KGaA, Darmstadt, Germany) is spun onto the substrate after the above treatment and then annealed for 1 min at 100°C on a hotplate (step dd).
• a dielectric layer of CYTOPTM (9% in FC-43, Asahi) is spun onto the cooled substrate (500 rpm for 10 s and 2000 rpm for 20 s) and heated on a hotplate for 2 min at 100°C (step ee).
• step ff a 30 nm gold layer is evaporated onto the interlayer as the gate electrode.
• Figure 7 illustrates the greatly improved off-current when a patterned TG device is produced.
• the comparative device is a standard top gate device, prepared on a cleaned glass substrate with no patterning interlayer, onto which the S/D electrodes were thermally evaporated.

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