WO2011160305A1 - Ac-dc电源转换器及其内的电流调制电路 - Google Patents

Ac-dc电源转换器及其内的电流调制电路 Download PDF

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Publication number
WO2011160305A1
WO2011160305A1 PCT/CN2010/074467 CN2010074467W WO2011160305A1 WO 2011160305 A1 WO2011160305 A1 WO 2011160305A1 CN 2010074467 W CN2010074467 W CN 2010074467W WO 2011160305 A1 WO2011160305 A1 WO 2011160305A1
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Prior art keywords
current
pmos transistor
source
gate
nmos transistor
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PCT/CN2010/074467
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English (en)
French (fr)
Inventor
陈敏
王钊
董贤辉
Original Assignee
北京中星微电子有限公司
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Application filed by 北京中星微电子有限公司 filed Critical 北京中星微电子有限公司
Priority to CN201080060222.2A priority Critical patent/CN102823125B/zh
Priority to PCT/CN2010/074467 priority patent/WO2011160305A1/zh
Publication of WO2011160305A1 publication Critical patent/WO2011160305A1/zh

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K2217/00Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018Special modifications or use of the back gate voltage of a FET

Definitions

  • the present invention relates to the field of circuit control, and more particularly to an AC-DC power converter and a current modulation circuit therefor.
  • the AC-DC power converter is used to convert an alternating current power source into a direct current power source through a transformer, the transformer including a main stage side coil and a secondary side coil, wherein an alternating current power source is input to the main stage side, and the secondary side outputs a direct current power source.
  • the AC-DC conversion circuit includes a power switch that controls conduction and deactivation of the main stage side at a certain switching frequency.
  • the AC-DC conversion circuit operates in a constant current mode (Constant Current)
  • L M is the main-stage side inductance
  • I lim is the limiting current
  • the main-stage I inductor current is equal to or proportional to the limiting current I lim when the power switch is turned off.
  • the energy consumed by the secondary side during one switching cycle of the power switch is:
  • the oscillating circuit 100 can generate an oscillating signal OSC out of a certain frequency, and a pulse width modulated signal of the power switch can be generated based on the oscillating signal.
  • the operating frequency of the power switch is equal to the frequency of the oscillating signal.
  • the oscillating signal output by the oscillating circuit is a sawtooth wave signal of 0 to V ref , and its frequency is:
  • R1 is the resistance value of the resistor R1
  • CI is the capacitance value of the capacitor CI
  • V ref is a reference voltage
  • V FB is the feedback voltage of the output voltage ⁇ , where V.
  • Ut K1 * V FB
  • Kl is a constant.
  • Fig. 2 shows a current limiting circuit 200 of the prior art (the current limiting circuit 200 is used to compare the main stage side) Sampling current of inductor current
  • the current I lim is limited, and when the sampling current I sx is greater than or equal to the limiting current I lim , the power switch is turned off by the output terminal OCP.
  • the limiting current I lim is provided by a reference current, and the reference current is Where ⁇ is the gate-to-source voltage difference of the MOS transistors MN1 and MN2.
  • the reference current ⁇ is mirror-copied ⁇ 2 times and then limits the current I lim , K2 is a constant: Substituting equation (7) into equation (6), you can get:
  • the current I is output. Ut with output voltage V. Ut has nothing to do with the output voltage V. Ut drops, system output current I. Ut does not change and can remain constant.
  • the operating frequency and the output voltage V are known. Ut is proportional, as the output voltage Vout decreases, the operating frequency will also decrease. Once the operating frequency ⁇ falls into the audio range, audio interference will occur in some audio fields, affecting normal applications. Therefore, it is necessary to propose an improved current modulating circuit to overcome the above problems.
  • One of the objects of the present invention is to provide an AC-DC power converter capable of realizing an increase in operating frequency as the output voltage of the system decreases in a constant current mode, thereby avoiding audio interference.
  • Another object of the present invention is to provide a current modulating circuit in an AC-DC power converter. In the constant current mode, the operating frequency can be increased as the output voltage of the system decreases, thereby avoiding audio interference.
  • a current modulation circuit of an AC-DC power converter is provided.
  • the current modulation circuit includes: an oscillator, a current limiting circuit, and a control circuit.
  • the oscillator generates a clock signal having a frequency that is inversely proportional to a feedback voltage that characterizes an output voltage of the AC-DC power converter.
  • the current limiting circuit compares the sampling current and the limiting current, and outputs an invalid overcurrent protection signal when the sampling current is less than the limiting current, and outputs an effective overcurrent when the sampling current is greater than the limiting current
  • a protection signal that characterizes an inductor current on a primary side of the AC-DC power converter, the limiting current being proportional to the feedback voltage.
  • the control circuit turns on the power switch on the main stage side of the AC-DC power converter based on the clock signal, and turns off the power switch when the overcurrent protection signal is valid.
  • the present invention provides an AC-DC power converter.
  • the AC-DC power converter includes: a power switch on a main stage side, a voltage sampling circuit, a current sampling circuit, and a current modulation circuit.
  • the voltage sampling circuit samples a feedback voltage characterizing the output voltage of the AC-DC power converter.
  • the current sampling circuit samples a sample current that characterizes the inductor current on the primary side.
  • the current modulation circuit includes: an oscillator that generates a clock signal whose frequency is inversely proportional to a feedback voltage; a current limiting circuit that compares the sampling current and the limiting current, the limiting current being proportional to the feedback voltage, wherein the sampling current is less than the sampling current When the current is limited, an invalid overcurrent protection signal is output, and when the sampling current is greater than the limiting current, an effective overcurrent protection signal is output; and the control circuit turns on the power switch based on the clock signal, The power switch is turned off when the stream protection signal is active.
  • the present invention has the following advantages:
  • the frequency of the clock signal generated by the oscillator is inversely proportional to the output voltage of the AC-DC power converter, and the current limiting circuit generates the AC-DC power converter.
  • the output voltage is proportional to the limiting current I Um .
  • FIG. 1 is a circuit diagram of an oscillator in the prior art
  • FIG. 2 is a circuit diagram of a current limiting circuit in the prior art
  • Figure 3 is a block diagram of a current modulating circuit for use in an AC-DC power converter in one embodiment of the present invention
  • Figure 4A is a circuit diagram of an oscillator in one embodiment of the present invention
  • Figure 4B is a circuit diagram of Figure 4A
  • FIG. 5 is a circuit diagram of a current limiting circuit in one embodiment of the present invention
  • FIG. 6 is a circuit diagram of a current limiting circuit in another embodiment of the present invention
  • FIG. 7 is a diagram 3 is a waveform diagram of each signal of the AC-DC current modulation circuit shown.
  • one embodiment or “an embodiment” as used herein means that a particular feature, structure, or characteristic relating to the described embodiments can be included in at least one implementation of the invention.
  • the appearances of the "in one embodiment” are not necessarily referring to the same embodiment, and are not necessarily a separate or alternative embodiment that is mutually exclusive. Further, the order of the modules in the method, flowchart or functional block diagram of one or more embodiments is indicated. It is not intended to refer to any particular order, nor to the invention.
  • the operating frequency can be inversely proportional to the output voltage, such that in the AC- When the output voltage Vout of the DC power converter drops, the operating frequency does not fall and rises.
  • is kept constant and satisfies the formula (4), and the current limit I lim and the output voltage V can be made in the present invention. "' is proportional.
  • the current modulation circuit 300 includes an oscillator 310, a current limiting circuit 320, and a control circuit 330.
  • the oscillator 310 generates a clock signal having a frequency inversely proportional to the feedback voltage V FB
  • the current limiting circuit 320 compares the sampling current I sx and the limiting current I lim , the sampling current I sx characterizing the inductor current on the main stage side, the limiting current I lim being proportional to the feedback voltage V FB at the sampling current
  • OCP Over Current Protection
  • the control circuit 330 turns on the power switch of the AC-DC power converter based on the clock signal CLK, and turns off the power switch when the overcurrent protection signal OCP is active.
  • the frequency of the clock signal CLK can be used as the operating frequency or switching frequency of the power switch, and the power switch can also be turned off when the sampling current I sx is greater than the limiting current I lim .
  • the operating frequency of the power switch is inversely proportional to the output voltage Vout, so that the output current / can still be guaranteed.
  • is independent of the output voltage Vout, so that a constant output current / can be guaranteed even when the output voltage Vout changes. ⁇ .
  • the oscillator 400 includes a constant current source I, a capacitor C2, an NMOS transistor MN3, a comparator comp, and a delay circuit DELAY.
  • Current source I and capacitor C2 are connected in series in series with the power supply and ground. Between.
  • the connection node of the current source I and the capacitor C2 is connected to the non-inverting input terminal of the comparator comp, the output terminal of the comparator comp is connected to the gate of the NMOS transistor MN3 via a delay circuit, and the inverting input terminal of the comparator comp is connected.
  • Feedback voltage V FB Feedback voltage
  • the drain of the NMOS transistor MN3 is connected to the non-inverting input terminal of the comparator comp, and the source of the NMOS transistor MN3 is connected to the ground.
  • the connection node of the current source I and the capacitor C2 can use an output terminal OSC out to output a triangular wave signal RAMP.
  • the connection node of the delay circuit and the gate of the NMOS transistor MN3 may have another output terminal to output the clock signal CLK.
  • the clock signal required by control circuit 330 may also be generated from triangular wave signal RAMP.
  • the current source I supplies a constant current to charge the capacitor C2.
  • the initial value of the charging voltage of the capacitor C2 is 0.
  • the charging voltage is lower than the feedback voltage VFB
  • the comparator comp outputs a low level
  • the clock signal CLK is a low level.
  • the NMOS transistor MN3 is turned off, and the current source I continuously charges the capacitor C2.
  • the comparator comp output jumps to a high level
  • the clock signal CLK is at a high level
  • the NMOS transistor MN3 is turned on.
  • the capacitor C2 is rapidly discharged through the NMOS transistor MN3.
  • the charging voltage is again lower than the feedback voltage VFB, and the comparator comp outputs a low level again.
  • the delay of the delay circuit causes the clock signal CLK to go to a high level for a period of time to become a low level.
  • the NMOS transistor MN3 is turned off again, and charging of the capacitor C2 is started again. This is repeated to form a triangular wave signal RAMP and a clock signal CLK.
  • Fig. 4B shows the waveforms of the respective signals of the oscillator 400.
  • the oscillator 400 outputs a sawtooth wave having a voltage amplitude of 0 to V FB .
  • V FB is the output voltage, the sampling voltage, where V.
  • Ut Kl* V FB , K1 is a constant, and I is the constant current value provided by current source I.
  • the charging current for charging the capacitor C2 is a constant current, and stops when the capacitor C2 is charged to the feedback voltage V FB . Therefore, the frequency of the output signal of the oscillator is no longer related to the output voltage V.
  • Ut Proportional, but inversely proportional to the output voltage ⁇ .
  • the constant current in the oscillator can also be obtained by using the replica reference current shown in FIG. 2, and the reference current is Where ⁇ is the gate-to-source voltage difference of the MOS transistors MN1 and MN2.
  • the reference current is mirrored and copied K3 times to obtain a constant current I, and K3 is the reproduction ratio.
  • FIG. 5 is a circuit diagram of current limiting circuit 500 in one embodiment of the present invention.
  • the current limiting circuit 500 includes a limiting current generating circuit 510 and a sampling current generating circuit 520.
  • the limit current generating circuit 510 generates a limit current I lim that is proportional to the feedback voltage V FB .
  • the sampling current generating circuit 520 generates a sampling current 1 ⁇ 2 which is proportional to the inductor current on the main stage side.
  • the limiting current I lim competes with the sampling current 1 ⁇ at the competing node.
  • the competing node When the limiting current I lim is greater than the sampling current I sx , the competing node outputs an invalid overcurrent protection signal OCP, and the limiting current I lim is smaller than the sampling current I At sx , the competing node outputs a valid overcurrent protection signal OCP.
  • the limiting current generating circuit 510 includes an operational amplifier OP (operating amplifier), a resistor R3, an NMOS transistor MN4, and PMOS transistors MPb5 and MPb6.
  • the non-inverting input terminal of the operational amplifier OP is connected to the feedback voltage V FB , and the output terminal is connected to the gate of the NMOS transistor MN4.
  • the source of the NMOS transistor MN4 is connected to the resistor R3.
  • the inverting input of the operational amplifier OP is connected to the connection node of the NMOS transistor MN4 and the resistor R3. The other end of the resistor R3 is grounded.
  • the drain of the PMOS transistor MPb5 is connected to the drain of the NMOS transistor MN4 and the gate of the PMOS transistor MPb5, and the source thereof is connected to the power supply V DD , and the gate thereof is connected to the gate of the PMOS transistor MPb6.
  • the source of the PMOS transistor MPb6 is connected to the power supply V DD , and the drain outputs the limiting current I lim .
  • the current on the current resistor R3 is ⁇ , and the current on the PMOS transistor MPb5 is also ⁇ .
  • the PMOS transistor MPb5 and the PMOS transistor MPb6 form a current mirror circuit.
  • K4 is the current replica ratio between the PMOS transistors MPb5 and MPb6.
  • the current I lim is limited to the output voltage V. Ut is proportional.
  • the sampling current generating circuit 520 includes NMOS transistors MN7 and MN8, and the NMOS transistors MN7 and MN8 form a current mirror circuit.
  • the current flowing through the NMOS transistor MN8 is the initial sampling current I sx , and is copied K5 times to obtain the sampling current I sx flowing through the NMOS transistor MN7 .
  • the initial sampling current I sx is proportional to the inductor current on the main stage side, K5 The ratio of current replication.
  • the maximum difference between the current limiting circuit and the prior art is that: the comparison current I lim is no longer a constant current, but an electrogram 6 proportional to the output voltage Vout is another implementation of the present invention.
  • a circuit diagram of the current limiting circuit 600 in the example The current limiting circuit 600 includes a limiting current generating circuit 610 and a sampling current generating circuit 620.
  • the current limiting circuit 600 shown in FIG. 6 and the current limiting circuit 500 shown in FIG. 5 are only in the difference in the configuration of the limiting current generating circuit 610 and the limiting current generating circuit 510.
  • the limit current generating circuit 610 includes a first limit current generating circuit, a second limit current generating circuit, and a mirror circuit.
  • the first limiting current generating circuit includes an NMOS transistor MN13, PMOS transistors MPbl7 and MPbl8, and a resistor R4.
  • the gate of the NMOS transistor MN13 is connected to the feedback voltage V FB , the source thereof is connected to the ground via the resistor R4, and the drain thereof is connected to the drain of the PMOS transistor MPM7.
  • the drain of the PMOS transistor MPbl7 is connected to the gate of the PMOS transistor MPbl7, the gate thereof is connected to the gate of the PMOS transistor MPbl8, and the source thereof is connected to the power supply V DD .
  • the source of the PMOS transistor MPblS is connected to the power supply V DD , and the drain outputs a first limiting current I liml .
  • the current flowing through the resistor R4 is Vfb R Z4 Vgs13
  • is the gate of the NMOS transistor MN13
  • the first limiting current I liml of the MPbl8 output is:
  • the second limiting current generating circuit includes NMOS transistors MN15 and MN22, PMOS transistors MPbl9, MPb20 and MPb21, and a resistor R5.
  • the source of the NMOS transistor MN22 is connected to the ground via a resistor R5, the gate thereof is connected to the drain of the NMOS transistor MN15, and the drain thereof is connected to the drain of the PMOS transistor MPb21.
  • the source of the NMOS transistor MN15 is connected to the ground, the gate thereof is connected to the source of the NMOS transistor MN22, and the drain thereof is connected to the drain of the PMOS transistor MPb20.
  • the gate of the PMOS transistor MPb20 is connected to the gate of the PMOS transistor MPb21, and its source is connected to the power supply.
  • the drain of the PMOS transistor MPb21 is connected to its gate, and its source is connected to the power supply.
  • the source of the PMOS transistor MPbl9 is connected to the power supply, the gate thereof is connected to the gate of the PMOS transistor MPb20, and the drain thereof outputs the second limiting current I lim2 . V,
  • the PMOS transistors MPbl9, MPb20 and MPb21 form a current mirror circuit, and the second limiting current I lim2 of the PMOS MPbl9 output is:
  • ⁇ 2 7 ⁇
  • ⁇ 7 is the current between PMOS tube MPbl9 and MPb21.
  • the mirroring circuit includes NMOS transistors MN14 and MN16, PMOS transistors MPb23 and MPb24.
  • the drain of the NMOS transistor MN14 is connected to the drains of the PMOS transistors MPbl9 and MPbl8 and the gate of the NMOS transistor MN14, the source thereof is grounded, and the gate thereof is connected to the gate of the NMOS transistor MN16.
  • the source of the NMOS transistor MN16 is grounded, and its drain is connected to the drain of the PMOS transistor MPb23.
  • the drain of the PMOS transistor MPb23 is connected to its gate, its gate is connected to the gate of the PMOS transistor MPb24, and its source is connected to the power supply.
  • the source of the PMOS transistor MPb24 is connected to the power supply, and its drain output limits the current I lim .
  • the current flowing through the NMOS transistor MN14 is the sum of the first limiting current I liml and the second limiting current Iiim2.
  • the NMOS transistors MN14 and MN16 form a current mirror circuit, and the PMOS transistors MPb24 and MPb23 form a current mirror circuit.
  • Figure 7 is a diagram showing the signals of the AC-DC current modulating circuit shown in Figure 3 in one embodiment.
  • the power switch is driven to turn on when it is at a high level, and is turned off at a low level.
  • the present invention can also provide an AC-DC power converter including a current modulating circuit as shown in FIG.
  • the invention has been described above with sufficient specificity in detail. It should be understood by those skilled in the art that the description of the embodiments is only exemplary, and all changes that are made without departing from the true spirit and scope of the invention should fall within the scope of the invention. The scope of the invention as defined by the appended claims is defined by the scope of the appended claims.

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Description

AC-DC电源转换器及其内的电流调制电路
技术领域
本发明涉及电路控制领域, 特别是涉及一种 AC-DC电源转换器 及其内的电流调制电路。
背景技术
AC-DC 电源转换器用来通过变压器将交流电源变换成直流电 源, 所述变压器包括主级侧线圈和次级侧线圈, 其中交流电源输入所 述主级侧, 所述次级侧输出直流电源。 所述 AC-DC转换电路包括有 功率开关, 所述功率开关以一定开关频率控制着主级侧的导通和关 断。
在所述 AC-DC转换电路工作于恒定电流模式 (Constant Current
Mode) 时, 所述主级侧在功率开关关断时所储存的能量 ^ "为:
1
Win lim ( 1 )
2
其中 LM为主级侧电感, Ilim为限制电流, 在功率开关关断时主级 I电感电流等于或正比于所述限制电流 Ilim。 所述次级侧在功率开关的一个开关周期内所消耗的能量^ ^为:
Figure imgf000003_0001
其中 „为功率开关的开关频率或工作频率, ,为次级侧的输出 电压, /„„,为次级侧的输出电流。 根据能量守恒可得:
Win * η = Wout (3 ) 将式 (1 ) 和 (2 ) 带入式 (3 ), 并进行变换后可得:
1 ? f
J =— Τ Τ2
2 lim ' γ (4) 在所述 AC-DC转换电路工作于恒定电流模式 (Constant Current Mode)时,无论输出电压 ^如何变化,都需要维持输出电流 恒定。 根据式(4), 为了保持系统输出电流 /。„,的恒定, 在限制电流 Ilim恒定 的前提下, 要求工作频率 f 与输出电压 成线性反比。
请参阅图 1所示, 其示出了现有技术中的一种振荡电路 100。 所 述振荡电路 100可以产生一定频率的振荡信号 OSC out, 基于所述振 荡信号可以生成功率开关的脉宽调制信号。这样, 功率开关的工作频 率等于所述振荡信号的频率。所述振荡电路输出的振荡信号为 0〜Vref 的锯齿波信号, 其频率 „为:
Figure imgf000004_0001
其中 Rl为电阻 Rl的电阻值, CI为电容 CI的电容值, Vref为一 基准电压, VFB为输出电压^的反馈电压, 其中 V。ut =K1* VFB, Kl 为常数。
将式 (5 ) 带入式 (4) 可得:
1 1 1
I = LMI (6)
Kl - Cl - Vref - Rl V0l K1 R1 C1 - V, 图 2所示,其示出了现有技术中的一种电流限制电路 200 ( 所述电流限制电路 200用来比较主级侧的电感电流的采样电流
Figure imgf000004_0002
限制电流 Ilim, 并在所述采样电流 Isx大于等于限制电流 Ilim时, 通过 输出端 OCP关断所述功率开关。 所述限制电流 Ilim是基准电流 提 供的, 所述基准电流 ^ "为
Figure imgf000004_0003
其中 Δ 为 MOS晶体管 MN1和 MN2的栅源电压差。 该基准电流 ^被镜像复制 Κ2倍后为限制电流 Ilim, K2为常数:
Figure imgf000005_0001
将式 (7) 代入式 (6), 可得:
2 M K1 - R22 - Rl - Cl - Vref 根据式(8)可知, 输出电流 I。ut与输出电压 V。ut无关, 因此随着 输出电压 V。ut的下降, 系统输出电流 I。ut不发生变化, 能够保持恒定。 然而, 根据式 (5 ) 可知, 工作频率 与输出电压 V。ut成正比, 随着 输出电压 Vout的下降, 工作频率 也会下降, 一旦工作频率 ·^下降 到音频范围内, 在某些音频领域会出现音频干扰, 影响正常的应用。 因此, 有必要提出一种改进的电流调制电路以克服上述问题。
发明内容
本部分的目的在于概述本发明的实施例的一些方面以及简要介 绍一些较佳实施例。在本部分以及本申请的说明书摘要和发明名称中 可能会做些简化或省略以避免使本部分、说明书摘要和发明名称的目 的模糊, 而这种简化或省略不能用于限制本发明的范围。
本发明的目的之一在于提供一种 AC-DC电源转换器, 在恒定电 流模式时, 能够实现随着系统输出电压的下降, 工作频率反而上升, 从而避免了音频干扰。 本发明的目的之二在于提供一种 AC-DC电源转换器内的电流调 制电路, 在恒定电流模式时, 能够实现随着系统输出电压的下降, 工 作频率反而上升, 从而避免了音频干扰。 为实现上述目的, 根据本发明的一个方面, 本发明提供了一种 AC-DC 电源转换器的电流调制电路。 所述电流调制电路包括: 振荡 器、 电流限制电路和控制电路。所述振荡器产生频率与反馈电压成反 比的时钟信号, 所述反馈电压表征 AC-DC电源转换器的输出电压。 所述电流限制电路, 比较采样电流和限制电流, 在所述采样电流小于 所述限制电流时, 输出无效的过流保护信号, 在所述采样电流大于所 述限制电流时,输出有效的过流保护信号,所述采样电流表征 AC-DC 电源转换器的主级侧的电感电流, 所述限制电流与反馈电压成正比。 所述控制电路基于所述时钟信号开启 AC-DC电源转换器的主级侧的 功率开关, 在所述过流保护信号有效时去关断所述功率开关。
根据本发明的另一个方面,本发明提供一种 AC-DC电源转换器。 所述 AC-DC电源转换器包括: 主级侧的功率开关、 电压采样电路、 电流采样电路和电流调制电路。 所述电压采样电路采样表征 AC-DC 电源转换器的输出电压的反馈电压。所述电流采样电路采样表征主级 侧的电感电流的采样电流。所述电流调制电路包括: 振荡器, 产生频 率与反馈电压成反比的时钟信号; 电流限制电路, 比较采样电流和限 制电流, 所述限制电流与反馈电压成正比, 在所述采样电流小于所述 限制电流时, 输出无效的过流保护信号, 在所述采样电流大于所述限 制电流时, 输出有效的过流保护信号; 控制电路, 基于所述时钟信号 开启所述功率开关, 在所述过流保护信号有效时去关断所述功率开 关。
与现有技术相比, 本发明具有以下优点:
本发明提出的 AC-DC电源转换器内的电流调制电路中, 振荡器 产生的时钟信号的频率 与 AC-DC电源转换器的输出电压成反比, 电流限制电路产生与 AC-DC电源转换器的输出电压成正比的限制电 流 IUm。 这样, 在 AC-DC 电源转换器处于恒定电流模式 (Constant Current Mode)时, AC-DC电源转换器的输出电流与输出电压没有关 系。 因此, 实现了随着输出电压下降, 输出电流恒定, AC-DC 转换 器的工作频率上升, 避免了音频干扰。 在结合参考附图及接下来的实施例的详细描述后,本发明的其它 目的、 特点和优点将会是显而易见的。 附图说明 参考附图及接下来的详细描述后, 本发明将更容易理解, 其中: 图 1是现有技术中的振荡器的电路图; 图 2是现有技术中的电流限制电路的电路图; 图 3是本发明的一个实施例中的用于 AC-DC电源转换器中的电 流调制电路的方框图; 图 4A是本发明的一个实施例中的振荡器的电路图; 图 4B是图 4A示出的振荡器的各信号的波形示意图; 图 5是本发明的一个实施例中的电流限制电路的电路图; 图 6是本发明的另一个实施例中的电流限制电路的电路图; 和 图 7是图 3示出的 AC-DC电流调制电路的各信号的波形示意图。
具体实施方式
本发明的详细描述主要通过程序、 步骤、 逻辑块、 过程或其他象 征性的描述来呈现, 其直接或间接地模拟本发明中的技术方案的运 作。所属领域内的技术人员使用此处的这些描述和陈述向所属领域内 的其他技术人员有效的介绍他们的工作本质。
此处所称的"一个实施例"或"实施例 "是指与所述实施例相关的 特定特征、结构或特性至少可包含于本发明至少一个实现方式中。在 本说明书中不同地方出现的 "在一个实施例中"并非必须都指同一个 实施例, 也不必须是与其他实施例互相排斥的单独或选择实施例。此 夕卜, 表示一个或多个实施例的方法、流程图或功能框图中的模块顺序 并非固定的指代任何特定顺序, 也不构成对本发明的限制。
对于 AC-DC电源转换器来说, 在其工作于恒定电流模式时, 为 了避免使工作频率 下降到音频范围内, 在本发明中可以使工作频 率 与输出电压^ ^成反比, 这样在 AC-DC 电源转换器的输出电压 Vout的下降时, 工作频率 不降反升。 此外, 为了使 AC-DC电源转 换器的输出电流 /。Μί保持恒定且满足所述公式 (4), 在本发明中可以 使限制电流 Ilim与输出电压 V。"'成正比。
请参阅图 3所示, 其为本发明的一个实施例中的用于 AC-DC电 源转换器中的电流调制电路 300的方框图。所述电流调制电路 300包 括振荡器 310、 电流限制电路 320和控制电路 330。
所述振荡器 310 产生频率与反馈电压 VFB成反比的时钟信号
CLK, 所述反馈电压 VFB表征所述 AC-DC 电源转换器的输出电压
Vout。
所述电流限制电路 320比较采样电流 Isx和限制电流 Ilim,所述采 样电流 Isx表征主级侧的电感电流,所述限制电流 Ilim与反馈电压 VFB 成正比,在所述采样电流 Isx小于所述限制电流 Ilim时,输出无效的过 流保护信号 OCP (Over Current Protection), 在所述采样电流 Isx大于 所述限制电流 Ilim时, 输出有效的过流保护信号 OCP。
所述控制电路 330基于所述时钟信号 CLK开启所述 AC-DC电源 转换器的功率开关, 在所述过流保护信号 OCP有效时去关断所述功 率开关。 这样可以将时钟信号 CLK的频率作为所述功率开关的工作 频率或开关频率, 同时也可以在所述采样电流 Isx大于所述限制电流 Ilim时去关断所述功率开关。
由于限制电流 Ilim与输出电压 Vout成正比,功率开关的工作频率 与输出电压 Vout成反比, 因此仍能保证输出电流 /。Μί与输出电压 Vout无关,从而在输出电压 Vout变化时仍能保证恒定的输出电流 /。Μί
图 4Α是本发明的一个实施例中的振荡器 400的电路图。 所述振 荡器 400包括恒定电流源 I、 电容 C2、 NMOS管 MN3、 比较器 comp 和延时电路 DELAY。电流源 I与电容 C2依次串联连接在电源和地之 间。 电流源 I与电容 C2的连接节点与比较器 comp的正相输入端相 接, 比较器 comp的输出端经由延时电路与 NMOS管 MN3的栅极相 接, 比较器 comp的反相输入端接反馈电压 VFB。 NMOS管 MN3的 漏极与比较器 comp的正相输入端相接, NMOS管 MN3的源级与地 相接。 电流源 I与电容 C2的连接节点可以用一个输出端 OSC out以 输出三角波信号 RAMP。延时电路与 NMOS管 MN3的栅极的连接节 点可以另一输出端以输出时钟信号 CLK。 在其他实施例中, 也可以 根据三角波信号 RAMP生成控制电路 330需要的时钟信号。
所述电流源 I提供恒定电流给电容 C2进行充电,电容 C2的充电 电压的初始值为 0, 此时充电电压低于反馈电压 VFB, 比较器 comp 输出低电平, 时钟信号 CLK为低电平, NMOS管 MN3截止, 电流 源 I对电容 C2进行持续充电。 随着电流源 I对电容 C2的持续充电, 电容 C2的充电电压高于或等于反馈电压 VFB, 比较器 comp输出跳 变为高电平, 时钟信号 CLK为高电平, NMOS管 MN3导通, 对电 容 C2通过 NMOS管 MN3进行快速放电。 对电容 C2放电后, 充电 电压又重新低于所述反馈电压 VFB, 比较器 comp又输出低电平, 由 于延迟电路的延迟使时钟信号 CLK持续一段时间高电平后才变为低 电平, NMOS管 MN3重新截止, 再一次开始对电容 C2的充电。 这 样周而复始, 形成三角波信号 RAMP和时钟信号 CLK。 图 4B示出 了振荡器 400的各信号的波形。
所述振荡器 400输出电压幅度为 0〜VFB的锯齿波。 所述振荡器 的三角波信号 RAMP和时钟信号 CLK的频率为: f = = ^ (9)
W C2 - VFB C2 - Vout
VFB为输出电压 ,的采样电压,其中 V。ut =Kl* VFB, K1为常数, I为电流源 I提供的恒定电流值。 本实施例中振荡器与现有技术的区别点在于: 对电容 C2进行充 电的充电电流是一个恒定电流, 并且对电容 C2充电到反馈电压 VFB 时停止。 因此, 振荡器的输出信号的频率 ·^不再与输出电压 V。ut成 正比, 而是与输出电压 ^成反比。 这样, 在 AC-DC电源转换器的 输出电压 Vout的下降时, 工作频率 不降反升, 从而避免了使工作 频率 /™下降到音频范围内。 所述振荡器中的恒定电流也可以采用图 2 示出的复制基准电流 的方式得到, 所述基准电流 ^为
Figure imgf000010_0001
其中 Δ 为 MOS晶体管 MN1和 MN2的栅源电压差。 该基准电 流 被镜像复制 K3倍后得到恒定电流 I, K3为复制比例
( 10)
R2
图 5是本发明的一个实施例中的电流限制电路 500的电路图。所 述电流限制电路 500包括限制电流产生电路 510和采样电流产生电路 520。 所述限制电流产生电路 510产生与反馈电压 VFB成正比的限制 电流 Ilim。 所述采样电流产生电路 520产生与主级侧的电感电流成正 比的采样电流 ½。 所述限制电流 Ilim与采样电流 1^在竞争节点进行 电流竞争,在限制电流 Ilim大于采样电流 Isx时,竞争节点输出无效的 过流保护信号 OCP, 在限制电流 Ilim小于采样电流 Isx时, 竞争节点 输出有效的过流保护信号 OCP。
所述限制电流产生电路 510 包括运算放大器 OP ( operational amplifier)、 电阻 R3、 NMOS管 MN4、 PMOS管 MPb5和 MPb6。 所 述运算放大器 OP的正相输入端接所述反馈电压 VFB,输出端接 NMOS 管 MN4的栅极。 NMOS管 MN4的源极与电阻 R3相接。运算放大器 OP的反相输入端与 NMOS管 MN4和电阻 R3的连接节点相连。 电 阻 R3的另一端接地。 PMOS管 MPb5的漏极与 NMOS管 MN4的漏 极及 PMOS管 MPb5的栅极相连, 其源极接电源 VDD相连, 其栅极 与 PMOS管 MPb6的栅极相连。 PMOS管 MPb6的源极接电源 VDD 相连, 漏极输出所述限制电流 Ilim
流 电阻 R3上的电流为 ^, PMOS管 MPb5上的电流也为 ^。
R3 R3
PMOS管 MPb5与 PMOS管 MPb6形成电流镜电路。 PMOS管 MPb6输出的限制电流 Ilim为: lYim=K4--^≡^ (11)
K1-R3
K4为 PMOS管 MPb5与 MPb6之间的电流复制比例。 这样, 限 制电流 Ilim与输出电压 V。ut成正比。 所述采样电流产生电路 520包括 NMOS管 MN7和 MN8,NMOS 管 MN7和 MN8形成电流镜电路。 流过 NMOS管 MN8的电流为初 次采样电流 Isx,被复制 K5倍后得到流经 NMOS管 MN7的采样电流 Isx, 所述初次采样电流 Isx,与主级侧的电感电流成正比, K5 为电流 复制比例。 将公式 (9)、 (10) 和 (11) 代入公式 (4), 可得:
1 ? f
J =— Τ τ2 n.J sw
1 out » -^Af Jlim'/
Figure imgf000011_0001
1 , K3''AV.
-LM -K42 - (12) 2 M ' K1-R3J -C2-R2 可见, 输出电流 与输出电压 ,无关, 只与器件的物理尺寸和 参数相关, 实现了输出电流的恒定, 很好的完成了电流调制。
在本实施例中, 电流限制电路与现有技术的最大区别点在于: 比 较电流 Ilim不再是一恒定电流,而是一个与输出电压 Vout成正比的电 图 6是本发明的另一个实施例中的电流限制电路 600的电路图, 所述电流限制电路 600包括有限制电流产生电路 610和采样电流产生 电路 620。 图 6示出的电流限制电路 600与图 5示出的电流限制电路 500仅在于: 限制电流产生电路 610和限制电流产生电路 510的结构 的不同。
所述限制电流产生电路 610包括第一限制电流产生电路、第二限 制电流产生电路和镜像电路。
所述第一限制电流产生电路包括有 NMOS管 MN13、 PMOS管 MPbl7和 MPbl8、电阻 R4。 NMOS管 MN13的栅极接反馈电压 VFB, 其源极经过电阻 R4与地相连, 其漏极与 PMOS管 MPM7的漏极相 连。 PMOS管 MPbl7的漏极与 PMOS管 MPbl7的栅极相连, 其栅极 与 PMOS管 MPbl8的栅极相连, 其源极与电源 VDD相连。 PMOS管 MPblS的源极与电源 VDD相连, 漏极输出第一限制电流 Iliml。 电阻 R4上流经的电流为 Vfb R Z4Vgs13, ^为 NMOS管 MN13的栅
Figure imgf000012_0001
MPbl8 输出的第一限制电流 Iliml为:
I liml" K6 '
R4
K6为 PMOS管 MPbl8与 MPbl7之间的电流复制比例。 所述第二限制电流产生电路包括 NMOS 管 MN15 和 MN22、 PMOS管 MPbl9、 MPb20和 MPb21、 电阻 R5。 NMOS管 MN22的 源极经由电阻 R5与地相连, 其栅极与 NMOS管 MN15的漏极相连, 其漏极与 PMOS管 MPb21的漏极相连。 NMOS管 MN15的源极与地 相连, 其栅极与 NMOS管 MN22 的源极相连, 其漏极与 PMOS管 MPb20的漏极相连。 PMOS管 MPb20的栅极与 PMOS管 MPb21的 栅极相连, 其源极接电源。 PMOS管 MPb21 的漏极与其栅极相连, 其源极接电源。 PMOS管 MPbl9的源极接电源, 其栅极接 PMOS管 MPb20的栅极, 其漏极输出第二限制电流 Ilim2。 V,
电阻 R5上流经的电流为
R5
PMOS管 MPbl9、 MPb20和 MPb21形成电流镜电路, PMOS MPbl9输出的第二限制电流 Ilim2为:
Ιΐύη2= 7·ϋ, Κ7为 PMOS管 MPbl9与 MPb21之间的电流复
R5
制比例 所述镜像电路包括 NMOS管 MN14和 MN16、 PMOS管 MPb23 和 MPb24。所述 NMOS管 MN14的漏极与 PMOS管 MPbl9和 MPbl8 的漏极以及 NMOS 管 MN14 的栅极相连, 其源极接地, 其栅极接 NMOS管 MN16的栅极。 NMOS管 MN16的源极接地,其漏极接 PMOS 管 MPb23的漏极。 PMOS管 MPb23的漏极与其栅极相连, 其栅极与 PMOS管 MPb24的栅极相连, 其源极接电源。 PMOS管 MPb24的源 极接电源, 其漏极输出限制电流 Ilim。 流过 NMOS管 MN14的电流为第一限制电流 Iliml和第二限制电 流 Iiim2的和。 NMOS管 MN14和 MN16形成电流镜电路, PMOS管 MPb24和 MPb23形成电流镜电路。 PMOS管 MPb24输出的限制电流
Ilim为:
Ilim= K8 ( Ilimi+ Ilim2 ) = K8■ K6 -
Figure imgf000013_0001
Κ8为 PMOS管 MPb24与 NMOS管 MN14之间的电流复制比例 , 取 R4=R5、 K6=K7、 Vgsl3= Vgsl5 , 有:
Iiim= Κ8 · Κ6 · ^ = Κ8 · Κ6 - V
R4 K1 - R4
这样, 同样可以实现限制电流 Ilim与输出电压 v。ut成正比。
图 7是图 3示出的 AC-DC电流调制电路的各信号在一个实施例 去驱动所述功率开关, 使其在高电平时导通, 在低电平是截止。 本发明还可以提供一种 AC-DC电源转换器, 其包括如图 3所示 的电流调制电路。 上文对本发明进行了足够详细的具有一定特殊性的描述。所属领 域内的普通技术人员应该理解, 实施例中的描述仅仅是示例性的, 在 不偏离本发明的真实精神和范围的前提下做出所有改变都应该属于 本发明的保护范围。本发明所要求保护的范围是由所述的权利要求书 进行限定的, 而不是由实施例中的上述描述来限定的。

Claims

权 利 要 求
1、 一种 AC-DC电源转换器的电流调制电路, 其包括: 振荡器, 产生频率与反馈电压成反比的时钟信号, 所述反馈电压 表征 AC-DC电源转换器的输出电压; 电流限制电路, 比较采样电流和限制电流, 所述采样电流表征
AC-DC 电源转换器的主级侧的电感电流, 所述限制电流与反馈电压 成正比, 在所述采样电流小于所述限制电流时, 输出无效的过流保护 信号, 在所述采样电流大于所述限制电流时, 输出有效的过流保护信 号; 和
控制电路, 基于所述时钟信号开启 AC-DC电源转换器的主级侧 的功率开关, 在所述过流保护信号有效时去关断所述功率开关。
2、 根据权利要求 1所述的电路, 其特征在于: 所述振荡器包括 恒定电流源、 充电电容、 NMOS放电管、 比较器和延时电路,
所述电流源与充电电容依次串联连接在电源和地之间,所述电流 源与充电电容的连接节点与所述比较器的正相输入端相接,所述比较 器的输出端经由延时电路与所述 NMOS放电管的栅极相接, 所述比 较器的反相输入端接所述反馈电压, 所述 NMOS放电管的漏极与所 述比较器的正相输入端相接, 所述 NMOS放电管的源级与地相接, 所述电流源与电容的连接节点作为输出端以输出三角波信号。
3、 根据权利要求 2所述的电路, 其特征在于: 所述延时电路与
NMOS放电管的栅极的连接节点作为另一输出端以输出时钟信号。
4、 根据权利要求 1所述的电路, 其特征在于: 所述电流限制电 路包括限制电流产生电路和采样电流产生电路,
所述限制电流产生电路产生与反馈电压成正比的限制电流,所述 采样电流产生电路产生与主级侧的电感电流成正比的采样电流, 所述限制电流与所述采样电流在竞争节点进行电流竞争,在限制 电流大于采样电流时, 竞争节点输出无效的过流保护信号, 在限制电 流小于采样电流时, 竞争节点输出有效的过流保护信号。
5、 根据权利要求 4所述的电路, 其特征在于:
所述限制电流产生电路包括运算放大器、第三电阻、第四 NMOS 管、 第五 PMOS管和第六 PMOS管,
所述运算放大器的正相输入端接所述反馈电压, 输出端接第四
NMOS管的栅极, 第四 NMOS管的源极与第三电阻相接, 运算放大 器的反相输入端与第四 NMOS管和第三电阻的连接节点相连, 第三 电阻的另一端接地, 第五 PMOS管的漏极与第四 NMOS管的漏极及 第五 PMOS管的栅极相连, 第五 PMOS管的源极接电源相连, 第五 PMOS管的栅极与第六 PMOS管的栅极相连, 第六 PMOS管的源极 接电源相连, 第六 PMOS管的漏极输出所述限制电流。
6、 根据权利要求 4所述的电路, 其特征在于:
所述限制电流产生电路包括第一限制电流产生电路、第二限制电 流产生电路和镜像电路,
所述第一限制电流产生电路包括有第十三 NMOS 管、 第十七
PMOS管、 第十八 PMOS管和第四电阻, 第十三 NMOS管的栅极接 反馈电压, 第十三 NMOS管的源极经过第四电阻与地相连, 第十三 NMOS管的漏极与第十七 PMOS管的漏极相连, 第十七 PMOS管的 漏极与第十七 PMOS管的栅极相连, 第十七 PMOS管的栅极与第十 八 PMOS管的栅极相连, 第十七 PMOS管的源极与电源相连, 第十 八 PMOS管的源极与电源相连, 第十八 PMOS管的漏极输出第一限 制电流; 所述第二限制电流产生电路包括第十五 NMOS 管、 第二十二 NMOS管、 第十九 PMOS管、 第二十 PMOS管、 第二 ^一 PMOS管 和第五电阻, 第二十二 NMOS 管的源极经由第五电阻与地相连, 第二十二 NMOS管栅极与第十五 NMOS管的漏极相连,第二十二 NMOS管的 漏极与第二十一 PMOS管的漏极相连, 第十五 NMOS管的源极与地相连, 第十五 NMOS管的栅极与第 二十二 NMOS管的源极相连, 第十五 NMOS管漏极与第二十 PMOS 管的漏极相连, 第二十 PMOS管的栅极与第二十一 PMOS管的栅极 相连, 第二十 PMOS管源极接电源, 第二十一 PMOS管的漏极与其 栅极相连, 第二十一 PMOS管的源极接电源, 第十九 PMOS管的源 极接电源, 第十九 PMOS管的栅极接第二十 PMOS管的栅极, 第十 九 PMOS管的漏极输出第二限制电流; 所述镜像电路包括第十四 NMOS管和第十六 NMOS管、 第二十 三 PMOS管和第二十四 PMOS管, 第十四 NMOS管的漏极与第十九 PMOS管和第十八 PMOS管的漏极以及第十四 NMOS管的栅极相连, 第十四 NMOS 管的源极接地, 第十四 NMOS 管的栅极接第十六 NMOS管的栅极, 第十六 NMOS管的源极接地, 第十六 NMOS管的 漏极接第二十三 PMOS管的漏极, 第二十三 PMOS管的漏极与其栅 极相连,第二十三 PMOS管的栅极与第二十四 PMOS管的栅极相连, 第二十三 PMOS管的源极接电源,第二十四 PMOS管的源极接电源, 第二十四 PMOS管的漏极输出所述限制电流,
第四电阻等于第五电阻, 第十三 NMOS管的栅源电压等于第十 五 NMOS管的栅源电压, 第十八 PMOS管与第十七 PMOS管之间的 电流复制比例等于第十九 PMOS管与第二 ^一 PMOS管之间的电流 复制比例。
7、 根据权利要求 4所述的电路, 其特征在于: 所述采样电流产 生电路包括形成电流镜的第七 NMOS管和第八 NMOS管, 流过第八 NMOS管的电流为初次采样电流,初次采样电流经过镜像复制后得到 流经第七 NMOS管的采样电流, 所述初次采样电流与主级侧的电感 电流成正比。
8、 一种 AC-DC电源转换器, 其包括:
主级侧的功率开关; 电压采样电路, 采样表征 AC-DC电源转换器的输出电压的反馈 电压;
电流采样电路, 采样表征主级侧的电感电流的采样电流; 电流调制电路包括:
振荡器, 产生频率与反馈电压成反比的时钟信号; 电流限制电路, 比较采样电流和限制电流, 所述限制电流与 反馈电压成正比, 在所述采样电流小于所述限制电流时, 输出无效的 过流保护信号, 在所述采样电流大于所述限制电流时, 输出有效的过 流保护信号; 和
控制电路, 基于所述时钟信号开启所述功率开关, 在所述过 流保护信号有效时去关断所述功率开关。
9、 根据权利要求 8所述的电源转换器, 其特征在于: 所述振荡 器包括恒定电流源、 充电电容、 NMOS放电管、 比较器和延时电路, 所述电流源与充电电容依次串联连接在电源和地之间,所述电流 源与充电电容的连接节点与所述比较器的正相输入端相接,所述比较 器的输出端经由延时电路与所述 NMOS放电管的栅极相接, 所述比 较器的反相输入端接所述反馈电压, 所述 NMOS放电管的漏极与所 述比较器的正相输入端相接, 所述 NMOS放电管的源级与地相接, 所述电流源与电容的连接节点作为输出端以输出三角波信号。
10、 根据权利要求 9所述的电源转换器, 其特征在于: 所述延时 电路与 NMOS放电管的栅极的连接节点作为另一输出端以输出时钟 信号。
11、 根据权利要求 8所述的电源转换器, 其特征在于: 所述电流 限制电路包括限制电流产生电路,
所述限制电流产生电路基于反馈电压产生与反馈电压成正比的 限制电流, 所述限制电流与所述采样电流在竞争节点进行电流竞争, 在限制电流大于采样电流时, 竞争节点输出无效的过流保护信号, 在 限制电流小于采样电流时, 竞争节点输出有效的过流保护信号。
12、 根据权利要求 11所述的电源转换器, 其特征在于: 所述限制电流产生电路包括运算放大器、第三电阻、第四 NMOS 管、 第五 PMOS管和第六 PMOS管,
所述运算放大器的正相输入端接所述反馈电压, 输出端接第四 NMOS管的栅极, 第四 NMOS管的源极与第三电阻相接, 运算放大 器的反相输入端与第四 NMOS管和第三电阻的连接节点相连, 第三 电阻的另一端接地, 第五 PMOS管的漏极与第四 NMOS管的漏极及 第五 PMOS管的栅极相连, 第五 PMOS管的源极接电源相连, 第五 PMOS管的栅极与第六 PMOS管的栅极相连, 第六 PMOS管的源极 接电源相连, 第六 PMOS管的漏极输出所述限制电流。
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