WO2011155442A1

WO2011155442A1 - Amplification-type solid state imaging device

Info

Publication number: WO2011155442A1
Application number: PCT/JP2011/062937
Authority: WO
Inventors: 恭志渡辺
Original assignee: 株式会社ブルックマンテクノロジ
Priority date: 2010-06-11
Filing date: 2011-06-06
Publication date: 2011-12-15
Also published as: JPWO2011155442A1; JP4846076B1

Abstract

An amplification-type solid state imaging device is provided with a pixel array formed from a plurality of pixels (10), and a control circuit. Each pixel (10) is provided with: a light receiving element (PD); a first amplification transistor (SF1) which amplifies and outputs a signal from the light receiving element (PD); capacities (CmR, CmS) which maintain the signal from the first amplification transistor (SF1); capacity-switch transistors (SwR, SwS) which control the input and output of the capacities (CmR, CmS); and a second amplification transistor (SF2) which amplifies and outputs the signal from the capacities (CmR, CmS). After sequentially turning on the capacity-switch transistors (SwR, SwS), and sequentially entering a signal from the first amplification transistor (SF1) into the capacities (CmR, CmS), the control circuit sequentially turns on the capacity-switch transistors (SwR, SwS), and sequentially reads out the signals entered in the capacities (CmR, CmS).

Description

Amplification type solid-state imaging device

The present invention relates to an amplification type solid-state imaging device having a capacitance in a pixel.

Generally, an amplification type solid-state imaging device has a pixel unit provided with an amplification function and a scanning circuit arranged around the pixel unit, and one that reads out pixel data from the pixel unit by the scanning circuit is widespread doing.

As an example of such an amplification type solid-state imaging device, an APS (Active Pixel Sensor) type constituted by a CMOS (Complementary Metal Oxide Semiconductor) that is advantageous for integrating a pixel portion with peripheral driving circuits and signal processing circuits. Image sensors are known. Among such APS type image sensors, in recent years, a four-transistor type capable of obtaining high image quality is becoming mainstream.

FIG. 26 is a circuit diagram showing a configuration of a pixel 100 of an amplification type solid-state imaging device according to the prior art. The pixel 100 is a conventional four-transistor pixel provided with four N-channel MOS (Metal Oxide Semiconductor) field effect transistors.

In FIG. 26, the light receiving element PD is usually formed of an embedded light receiving element, and the signal charge is transferred from the light receiving element PD to the floating diffusion region FD by the transfer transistor TX. Before the signal charge is transferred from the light receiving element PD, the floating diffusion region FD is reset by the reset transistor RT to the power supply voltage Vdd which is the drain voltage of the reset transistor RT or the source voltage of the corresponding reset transistor RT. Next, the transfer transistor TX is turned on to transfer the signal charge from the light receiving element PD to the floating diffusion region FD. The voltage of the floating diffusion region FD after the reset and the signal charge transfer is amplified by the amplification transistor SF, and read out to the read signal line sig3 through the selection transistor SL. A constant current load transistor CL is connected to one end of the read signal line sig3, and an output voltage Vo is obtained from the drain of the constant current load transistor CL.

In the case of configuring a two-dimensional image sensor forming an amplification type solid-state imaging device including a pixel array in which the pixels 100 in FIG. 26 are arranged in a matrix, each pixel 100 is read out row by row. The pixel 100 outputs the charges accumulated in the light receiving element PD as signal charges to the signal processing circuit (not shown) in the subsequent stage until the time when the readout is performed after the previous readout is performed. The signals are sequentially shifted temporally for each row, and when an object with motion is imaged, the image is distorted according to the motion.

In order to solve such a problem, there is proposed a collective exposure technology in which each pixel is provided with a capacity, all the pixels are read out at the same time, and written in each capacity, and then the information in each capacity is read out sequentially. It is done. However, in this case, there is a problem that noise increases between writing and reading of the signal from the light receiving element to the capacitor and the S / N ratio decreases. For this reason, a technique for amplifying the signal of the light receiving element and writing it in the capacitor is proposed, and FIGS. 27 and 28 are circuit diagrams showing an example of this (see, for example, Patent Document 1).

FIG. 27 is a circuit diagram showing the configuration of a pixel 110 of an amplification type solid-state imaging device according to the prior art. The pixel 110 further includes a first amplification transistor SF1, a constant current load transistor VB, a current control switch transistor SW, a write switch transistor Wr, and a capacitance Cm, as compared with the pixel 100 shown in FIG. Is configured. In the pixel 110 of FIG. 27, the second amplification transistor SF2 may correspond to the amplification transistor SF of FIG. 26, and the current control switch transistor SW may be provided on the power supply side.

In the operation of the two-dimensional image sensor configured using the pixel 110 of FIG. 27, first, all the pixels 110 are operated collectively to write the signal from the light receiving element PD in the capacitor Cm. That is, after the current control switch transistor SW is turned on, the write switch transistor Wr is turned on, and the signal from the light receiving element PD amplified by the first amplification transistor SF1 is written to the capacitor Cm. Thereafter, the write switch transistor Wr is turned off, and then the current control switch transistor SW is turned off, whereby the batch write operation is completed.

Then, the read operation is performed sequentially for each row. That is, the operation of reading out the signal held in the capacitor Cm to the read signal line sig3 via the second amplification transistor SF2 and the selection transistor SL is sequentially performed for each row. The constant current load transistor CL is connected to one end of the read signal line sig3, and the output voltage Vo is sequentially obtained for each row.

FIG. 28 is a circuit diagram showing a configuration of a pixel 120 of an amplification type solid-state imaging device according to the prior art. The pixel 120 is formed by duplicating each of the write switch transistor, the capacitor, the second amplification transistor, and the selection transistor in comparison with the pixel 110 illustrated in FIG. 27, and the write switch transistors Wr1 and Wr2; Capacitors Cm1 and Cm2, second amplification transistors SF21 and SF22, and select transistors SL1 and SL2 are provided. Thus, when the two-dimensional image sensor is configured using the pixels 120, all the pixels are operated collectively, and the voltage of the floating diffusion region FD after the reset operation (referred to as a reset signal) and the charge from the light receiving element PD. The voltage (referred to as an optical signal) of the floating diffusion region FD after the transfer of the voltage V.sub.2 can be held in the two capacitors Cm1 and Cm2, respectively. Further, the read operation is sequentially performed row by row. That is, the operation of reading out the reset signal and the light signal held by the two capacitors Cm1 and Cm2 to the read signal lines sig3 and sig4 via the second amplification transistors SF21 and SF22 and the selection transistors SL1 and SL2 is performed for each row It will be done sequentially. The output voltages Vo1 and Vo2 are sequentially obtained for each row by the constant current load transistors CL1 and CL2 connected to one end of the read signal lines sig3 and sig4, and the signal processing circuit (not shown) in the subsequent stage outputs the output voltage Vo1. By performing correlated double sampling (CDS: Correlated Double Sampling) processing (hereinafter referred to as CDS processing) for calculating the difference from the output voltage Vo2, reset noise in the floating diffusion region FD and the first amplification transistor It is possible to remove fixed pattern noise caused by the variation of the threshold value of SF1.

A technique shown in FIG. 29 is disclosed as another example of a batch exposure technique of amplifying a signal of a light receiving element and writing the signal in a capacitor (see Non-Patent Document 1). FIG. 29 is a circuit diagram showing a configuration of a pixel 130 of an amplification type solid-state imaging device according to the prior art. The writing operation when the two-dimensional image sensor is configured using the pixels 130 is performed by operating all the pixels 130 at one time. First, the constant current load transistor PC is turned on, then the switch transistors Smp1 and Smp2 are both turned on, the reset signal after the reset operation is held in the capacitor CmR, and then only the switch transistor Smp1 is turned on. Is transferred to the capacitor CmS.

Then, read operations are sequentially performed row by row. First, the reset signal held in the capacitor CmR is applied to the gate of the second amplification transistor SF2 with both the switch transistors Smp1 and Smp2 turned off, and then only the switch transistor Smp2 is turned on and light held in the capacitor CmS A signal is applied to the gate of the second amplification transistor SF2. The second amplification transistor SF2 outputs the reset signal and the light signal to the readout signal line sig3 via the selection transistor SL, and this operation is sequentially performed for each row. After that, as in the case of the pixel 120 in FIG. 28, the signal processing circuit (not shown) in the subsequent stage performs the CDS processing, thereby resetting noise, the first amplification transistor SF1, and the second amplification transistor SF2. Fixed pattern noise due to the variation of the threshold of In addition, the pixel 130 has a simple configuration including two switch transistors, two capacitors, and one second amplification transistor, and eight transistors per pixel.

JP 2005-65074 A

However, the configuration shown in FIG. 28 has the following problems.
(A) When the write operation is performed on the capacitance in the pixel by operating all the pixels collectively, the current control switch transistor SW is turned on, so that the first amplification transistor SF1 is constant via the constant current load transistor VB. Since the current I1 flows, the current flowing through the entire two-dimensional image sensor is equal to the number of pixels of the current I1 and a large direct current flows.
(B) Eleven transistors are required in one pixel, the area of the light receiving element PD is reduced, the sensitivity is lowered, and the pixel layout is complicated.

Further, in the case of the configuration of FIG. 29, the constant current load transistor PC is simultaneously turned on in all the pixels, and the same problem as the above (a) occurs, and the following problems occur.
(C) When the switch transistor Smp2 is turned on and the optical signal held in the capacitor CmS is read out to the gate of the second amplification transistor SF2, the voltage of the optical signal is divided into two capacitors CmR and CmS If the capacitance values are the same, the voltage of the optical signal drops to 1⁄2. That is, the S / N ratio decreases.

The object of the present invention is to solve the above problems, and with a simple circuit configuration, the area of the light receiving element can be increased by reducing the number of transistors in the pixel, and the current when writing a signal in the capacitor can be suppressed. It is an object of the present invention to provide an amplification type solid-state imaging device capable of maintaining a high S / N ratio without a voltage drop when reading out a signal from a capacitor and obtaining stable operation and high performance.

An amplification type solid-state imaging device according to the present invention includes a pixel array configured by arranging a plurality of pixels having a plurality of capacities in a matrix.
An amplification type solid-state imaging device comprising: a control circuit for performing operation control on each pixel constituting the pixel array;
Each pixel is
A photoelectric conversion unit that generates and outputs a signal according to the received light;
A first amplification transistor that amplifies and outputs a signal input from the photoelectric conversion unit to a gate;
A reset transistor that resets a gate voltage of the first amplification transistor;
A plurality of capacitors for holding a signal output from the first amplification transistor to the first signal line;
Respective capacitances provided corresponding to the plurality of capacitances and provided between the first signal line and the plurality of capacitances and performing input / output control between the first signal line and the plurality of capacitances Multiple capacitive switches, one per unit,
A second amplification transistor that amplifies a signal input from the first signal line to the gate and outputs the amplified signal to a second signal line;
An initialization transistor is connected to the first signal line and outputs a predetermined first voltage to the first signal line.

In the amplification type solid-state imaging device, the control circuit may
(1) The plurality of capacitors are initialized to the first voltage by turning on the initialization transistor and turning on the plurality of capacitance switches.
(2) By sequentially turning on the plurality of capacitance switches corresponding to the plurality of capacitances, capacitance switches corresponding to the first signal line and the capacitance to be written are the amplified signals from the first amplification transistor. Perform a write operation to sequentially write to the capacity via
(3) By sequentially turning on the plurality of capacitance switches corresponding to the plurality of capacitances, the capacitance switch corresponding to the capacitance to be read out, the signal written to each of the capacitances, the first signal line, and It is characterized in that control is performed so as to execute a read operation for sequentially reading out the second signal line via a second amplification transistor.

Furthermore, in the amplification type solid-state imaging device, the control circuit is configured to configure all the pixel arrays in a period in which the first amplification transistor shifts from a saturation region operation to a subthreshold region operation and becomes a metastable state. The write operation is simultaneously performed on the pixel.

Still further, in the amplification type solid-state imaging device, the signal includes a reset signal,
The control circuit applies a second voltage at which the first amplification transistor is turned on to the drain of the reset transistor to turn on the reset transistor, thereby the reset transistor corresponding to the second voltage. A source voltage of the first amplification transistor is applied to the gate of the first amplification transistor to output a reset signal corresponding to the second voltage to the first signal line, and then the first amplification transistor is turned off. Performing the write operation to apply the third voltage to the gate of the first amplification transistor by applying a voltage of 3 to the drain of the reset transistor and turning on the reset transistor. It is characterized by

In the amplification type solid-state imaging device, the signal includes a reset signal,
The pixel further includes an output switch provided between the first amplification transistor and a first signal line.
The control circuit applies a second voltage that turns on the first amplification transistor to the gate of the first amplification transistor by turning on the reset transistor, and turns on the output switch. Thus, after the reset signal corresponding to the second voltage is output to the first signal line, the write operation is performed to turn off the output switch.

Furthermore, in the amplification type solid-state imaging device, the signal further includes an optical signal,
The pixel further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The plurality of capacitors include a first capacitor for holding the reset signal and a second capacitor for holding the optical signal,
The control circuit applies the light signal from the photoelectric conversion unit to the gate of the first amplification transistor by writing the reset signal to the first capacitor and then turning on the transfer transistor. The write operation may be performed to write the optical signal to the second capacitor.

Still further, in the amplification type solid-state imaging device, the signal further includes an optical signal,
The pixel further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The plurality of capacitors include a first capacitor for holding the reset signal and a second capacitor for holding the optical signal,
The control circuit turns on the output switch to write the reset signal to the first capacitor, and then turns on the transfer transistor to amplify the optical signal from the photoelectric conversion unit to the first amplification. After the light signal is applied to the gate of the transistor, the write operation is performed to output the light signal to the first signal line and to write the light signal to the second capacitor.

In the amplification type solid-state imaging device, the signal further includes an optical signal,
The photoelectric conversion unit is a PN light receiving element, and outputs a light signal according to the received light to the gate of the first amplification transistor,
The plurality of capacitors may be a third capacitor for holding the optical signal, a fourth capacitor for holding the reset signal when processing an odd-numbered frame, and the reset when processing an even-numbered frame. And a fifth capacitance for holding the signal,
The control circuit applies the light signal from the photoelectric conversion unit to the gate of the first amplification transistor by turning on the output switch to write the light signal to the third capacitance. The write operation is performed to write the reset signal to the fourth capacitor when processing odd-numbered frames and to write the reset signal to the fifth capacitor when processing even-numbered frames It is characterized by

Furthermore, in the amplification type solid-state imaging device, when processing an odd-numbered frame, the control circuit reads the light signal from the third capacitance and reads the reset signal from the fifth capacitance. When processing the second frame, the read operation is performed so as to read the light signal from the third capacitor and read the reset signal from the fourth capacitor.

Still further, in the amplification type solid-state imaging device, the control circuit executes the reading operation so as to sequentially read a reset signal and an optical signal for each row of the pixel array,
In the read operation, the second voltage is applied to the drain of the reset transistor between the read operation of the first row and the read operation of the second row next to the first row, After the light signal from the photoelectric conversion unit is discharged to the drain of the reset transistor by turning on the transfer transistor and the reset transistor, the transfer transistor is turned off, and the reset transistor is turned on. Is applied to the drain of the reset transistor to control the reset transistor to turn off.

In the amplification type solid-state imaging device, the control circuit executes the readout operation so as to sequentially read out the reset signal and the light signal for each row of the pixel array,
In the read operation, the photoelectric conversion is performed by turning on the transfer transistor and the reset transistor between the read operation of the first row and the read operation of the second row next to the first row. After the light signal from the conversion unit is discharged to the drain of the reset transistor, control is performed to turn off the transfer transistor and turn off the reset transistor.

Furthermore, in the amplification type solid-state imaging device, the control circuit executes the reading operation so as to sequentially read a reset signal and an optical signal for each row of the pixel array,
In the read operation, the photoelectric conversion is performed by turning on the output switch and the reset transistor between the read operation of the first row and the read operation of the second row next to the first row. After the light signal from the conversion unit is discharged to the drain of the reset transistor, the reset transistor is turned off, and when processing an odd-numbered frame, the reset signal is written to the fourth capacitor, and the even-numbered When processing a frame, the reset signal is written to the fifth capacitor, and the output switch is controlled to be turned off.

Still further, in the amplification type solid-state imaging device, the control circuit executes the reading operation so as to sequentially read a reset signal and an optical signal for each row of the pixel array,
In the read operation, the gate of the second amplification transistor is set to a fourth voltage at which the second amplification transistor is turned off by turning on the initialization transistor in each pixel in a row where readout is not performed. It is characterized in that it controls to initialize.

In the amplification type solid-state imaging device, the pixel further includes a selection transistor provided between the second amplification transistor and the second signal line.
The control circuit is controlled to output the light signal or the reset signal held in the capacitor to the second signal line by turning on the selection transistor.

Furthermore, in the amplification type solid-state imaging device,
The signal input to the gate of the first amplification transistor includes a reset signal,
Each of the pixels further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The control circuit controls the off time of the transfer transistor such that the accumulation time of the photoelectric conversion unit has two modes of a long time accumulation mode and a short time accumulation mode within one frame period,
The plurality of capacitors are a sixth capacitor for holding the reset signal, a seventh capacitor for holding the light signal in the long time accumulation mode, and an eighth capacitor for holding the light signal in the short time accumulation mode. And an amplification type solid-state imaging device.

Furthermore, in the amplification type solid-state imaging device,
The control circuit
(1) After setting the gate voltage of the reset transistor to a high level, the reset signal is written to the sixth capacitor,
(2) After setting the gate voltage of the reset transistor to a middle level lower than the high level, an optical signal of the long-time accumulation mode is written to the seventh capacitance.
(3) The write operation is performed by writing the light signal in the short time accumulation mode to the eighth capacitor after setting the gate voltage of the reset transistor to a low level lower than the middle level. An amplification type solid-state imaging device characterized by

Furthermore, in the amplification type solid-state imaging device,
The amplification type solid-state imaging device is
Correlated double that performs correlated double sampling based on the reset signal, the light signal of the long time accumulation mode, and the light signal of the short time accumulation mode, which are output from the pixel through the second signal line Equipped with a sampling circuit,
The correlated double sampling circuit is
(A) calculating a first differential voltage obtained by subtracting the reset signal from the light signal in the long-term accumulation mode in the first correlated double sampling operation;
(B) calculating a second differential voltage formed by subtracting the light signal of the long time accumulation mode from the light signal of the short time accumulation mode in the second correlated double sampling operation; Calculating a value of the ratio of the period of the long-term accumulation mode to the period of time, and calculating a multiplication value obtained by multiplying the second differential voltage by the value of the ratio;
(C) An amplification type solid-state imaging device characterized in that the first differential voltage and the multiplication value are selectively switched according to the amount of light received and output as an optical signal.

Furthermore, in the amplification type solid-state imaging device,
The control circuit
(1) After setting the gate voltage of the reset transistor to a high level, the reset signal is written to the sixth capacitor,
(2) After setting the gate voltage of the reset transistor to a low level lower than the high level, the optical signal in the long time accumulation mode is written to the seventh capacitor, and then the gate voltage of the reset transistor is Set to the high level,
(3) After setting the gate voltage of the reset transistor to the low level, the write operation is performed by writing an optical signal in the short-time accumulation mode to the eighth capacitor. It is a solid-state imaging device.

Furthermore, in the amplification type solid-state imaging device,
The amplification type solid-state imaging device is
A correlated double sampling circuit that performs correlated double sampling based on the reset signal and the light signal output from the pixel through the second signal line,
(A) calculating a first differential voltage obtained by subtracting the reset signal from the light signal in the long-term accumulation mode in the first correlated double sampling operation;
(B) calculating a third differential voltage obtained by subtracting the reset signal from the light signal in the short-time accumulation mode in the second correlated double sampling operation, and calculating the third difference voltage in the short-time accumulation mode Calculating a value of a ratio of a time accumulation mode period, and calculating a multiplication value obtained by multiplying the third difference voltage by the value of the ratio;
(C) An amplification type solid-state imaging device characterized in that the first differential voltage and the multiplication value are selectively switched according to the amount of light received and output as an optical signal.

Furthermore, in the amplification type solid-state imaging device,
The upper limit value of the first differential voltage is set to be a minimum value of the variation range of the light signals in the long time accumulation mode of all the pixels or a value smaller than the minimum value by a predetermined margin value. It is an amplification type solid-state imaging device.

According to the amplification type solid-state imaging device of the present invention, since the pixel does not have a constant current load and writing and reading are performed by a common switch, the number of transistors in the pixel can be reduced. In order to perform the write operation to the plurality of capacitors serving as the load of the first amplification transistor, the plurality of capacitors are first initialized to a predetermined voltage, for example, a ground voltage or a positive voltage close thereto, and then the plurality of capacitors A stable operation can be performed by performing the write operation by the charge current to the capacitor and controlling the selection of the specific capacitor and the write time by the capacitor switch. Further, at the time of reading from the plurality of capacitors, a voltage at which the transistor is deactivated is applied to the gate of the first amplification transistor to turn it off, and selection and reading time of a particular capacitor are controlled by the capacitor switch. Thus, signals from the plurality of capacitors can be given to the gate of the second amplification transistor and read out to the outside of the pixel.

Further, according to the amplification type solid-state imaging device of the present invention, two capacitances in each pixel are simultaneously operated on the pixel array configured of the pixels having the reset transistor, the embedded light receiving element, and the transfer transistor. After the write operation of the reset signal and the light signal are performed on one side and the other side, respectively, the respective capacitances of the respective pixels are sequentially read out to the gate of the second amplification transistor. At the same time, an operation of writing to each of the capacitors and an operation of sequentially reading out of each of the capacitors can be performed. At the time of reading, a third voltage is applied to the gate of the first amplification transistor to be deactivated, or an output switch is provided between the first amplification transistor and the first signal line to be turned off. The influence of the first amplification transistor is prevented. In addition, the correlated double sampling (CDS) method can be applied by taking a difference between the reset signal and the light signal for each pixel read out sequentially, and in the first and second amplification transistors, Fixed pattern noise due to variations in threshold voltage and reset noise to the gate of the first amplification transistor can be suppressed, and a low noise image signal can be obtained.

Furthermore, according to the amplification type solid-state imaging device of the present invention, the output switch is turned on by simultaneously operating the pixel array including the reset transistor and the pixel having the PN light receiving element at the time of writing. The write operation of the light signal in one of the three capacitors in each pixel, the reset signal of the odd frame in the other one, and the reset signal of the even frame in the remaining capacitance is performed, The readout from each capacitor to the gate of the second amplification transistor is sequentially performed with the output switch off, and the operation of writing all the pixels simultaneously to the respective capacitors and the operation of sequentially reading out the respective capacitors are performed simultaneously. Can. Also, in each frame, the light signal of the frame with noise correlation and the reset signal of the previous frame are read out in pairs, so that the CDS method can be applied by taking the difference between the signals, It is possible to suppress fixed pattern noise due to variations in threshold voltage in each of the second amplification transistors and reset noise to the gate in the first amplification transistor, and obtain an image signal with low noise. it can.

Still further, according to the amplification type solid-state imaging device of the present invention, the second amplification transistor in the non-selected row is inactivated when reading out signals in row sequence from the pixel array. Since the gate voltage of the amplification transistor is controlled by the initialization transistor, it is not necessary to provide a selection transistor between the second amplification transistor and the signal line, thereby further reducing the components in the pixel. It is possible to improve the performance such as the increase of the area of the light receiving portion.

Furthermore, according to the amplification type solid-state imaging device of the present invention, the maximum amount of charge that can be accumulated in the floating diffusion region without the charge transferred by the transfer transistor increasing due to an increase in the amount of incident light to the light receiving element. The amount can be increased significantly. That is, the low sensitivity short-term accumulated charge can be used to accumulate even stronger incident light amount, and the signal maintaining linearity is read, and the maximum allowable incident light amount is expanded by combining these two types of signals. It is possible to perform wide dynamic range operation.

Furthermore, according to the amplification type solid-state imaging device of the present invention, correlated double sampling (CDS) operation can be performed for both the long-time accumulation mode optical signal and the short-time accumulation mode optical signal, thereby suppressing reset noise. Noise can be realized. That is, it is possible to obtain an optical signal in the long time accumulation mode in which the reset noise common to both is removed. Similarly, with regard to the light signal in the short time accumulation mode, it is possible to obtain the light signal in the short time accumulation mode in which the reset noise common to both is removed.

Furthermore, according to the amplification type solid-state imaging device of the present invention, since the signal is clipped so as to be smaller than the minimum value of variation for all pixels, a wide dynamic range image signal without fixed pattern noise can be obtained.

Further, according to the amplification type solid-state imaging device of the present invention, since it is possible to perform the CDS operation in a pseudo manner, it is possible to remove the offset variation which fluctuates for each pixel. In addition, in the fifth embodiment, in particular, the handling charge amount can be doubled as compared with those of the other embodiments.

Further, according to the amplification type solid-state imaging device of the present invention, the collective exposure (global shutter) operation and the wide dynamic range operation can be simultaneously performed. Furthermore, in the wide dynamic range operation, each frame can be operated continuously and is also applicable to moving pictures. Furthermore, in wide dynamic range operation all signals required for wide dynamic range operation can be obtained simultaneously without frame memory. In addition, both the light signal in the long time accumulation mode and the light signal in the short time accumulation mode can be reset noise free, and a wide dynamic range signal with a high SN ratio can be obtained.

It is a circuit diagram showing composition of pixel 10 of an amplification type solid imaging device concerning a 1st embodiment of the present invention. It is a block diagram which shows the structure of a two-dimensional image sensor provided with pixel array A10 which arranged the pixel 10 of FIG. 1 in the matrix form. It is a 1st part of the timing chart which shows operation | movement of the two-dimensional image sensor of FIG. It is a 2nd part of the timing chart which shows operation | movement of the two-dimensional image sensor of FIG. It is a timing chart which shows shutter operation of the two-dimensional image sensor of FIG. It is a circuit diagram showing composition of pixel 20 of an amplification type solid imaging device concerning a 2nd embodiment of the present invention. It is a circuit diagram showing composition of pixel 30 of an amplification type solid imaging device concerning a 3rd embodiment of the present invention. FIG. 8 is a first portion of a timing chart illustrating the operation of a two-dimensional image sensor provided with a pixel array having the pixels 30 of FIG. 7. 9 is a second portion of a timing chart illustrating the operation of a two-dimensional image sensor comprising a pixel array having the pixels 30 of FIG. 7; It is a circuit diagram showing composition of pixel 40 of an amplification type solid imaging device concerning a 4th embodiment of the present invention. 11 is a first portion of a timing chart showing an operation in one frame period of a two-dimensional image sensor provided with a pixel array having the pixel 40 of FIG. 11 is a second portion of a timing chart showing an operation in one frame period of a two-dimensional image sensor provided with a pixel array having the pixel 40 of FIG. It is a timing chart which shows the operation | movement in two frame periods of a two-dimensional image sensor provided with the pixel array which has the pixel 40 of FIG. It is a timing chart which shows shutter operation of a two-dimensional image sensor provided with the pixel array which has pixel 40 of FIG. It is a timing chart which shows the shutter operation | movement in two frame periods of a two-dimensional image sensor provided with the pixel array which has the pixel 40 of FIG. It is a circuit diagram showing composition of pixel 50 of an amplification type solid imaging device concerning a 5th embodiment of the present invention. FIG. 17 is a timing chart showing a write operation of the amplification type solid-state imaging device of FIG. 16; 17 is a timing chart showing the read operation of the amplification type solid-state imaging device of FIG. 16; FIG. 17 is an electric potential diagram schematically showing signal charges generated in a light receiving element by incident light, gate potentials of transfer transistors and reset transistors, and potentials of floating diffusion regions in the amplification type solid-state imaging device of FIG. 16; FIG. 17 is a graph showing an amount of signal charge with respect to accumulation time indicating wide dynamic range operation in which the maximum allowable incident light amount is expanded in the amplification type solid-state imaging device of FIG. 16; FIG. 17 is a graph showing an amount of signal charge with respect to accumulation time showing a wide dynamic range operation in which fixed pattern noise is eliminated in the amplification type solid-state imaging device of FIG. 16; FIG. 21 is a circuit diagram showing a configuration of a pixel 60 of an amplification type solid state imaging device according to a first modified example of the fifth embodiment of the present invention. It is a circuit diagram showing composition of pixel 70 of an amplification type solid imaging device concerning the 2nd modification of a 5th embodiment of the present invention. In the amplification type solid-state imaging device of FIG. 23, the gate voltage V _RT of the reset transistor RT is set to three levels of the middle level V _{RT (M)} between the high level V _{RT (H)} and the low level V _{RT (L)} . It is a timing chart which shows operation in the case. FIG. 24 is a timing chart showing an operation in the case where the gate voltage V _RT of the reset transistor RT is set to two levels of high level V _{RT (H)} and low level V _{RT (L)} in the amplification type solid-state imaging device of FIG. It is a circuit diagram showing composition of pixel 100 of an amplification type solid imaging device concerning a prior art. It is a circuit diagram showing composition of pixel 110 of an amplification type solid imaging device concerning a prior art. It is a circuit diagram showing composition of pixel 120 of an amplification type solid imaging device concerning a prior art. It is a circuit diagram showing composition of pixel 130 of an amplification type solid imaging device concerning a prior art.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.

First Embodiment
FIG. 1 is a circuit diagram showing a configuration of a pixel 10 of an amplification type solid-state imaging device according to a first embodiment of the present invention. As shown in FIG. 1, the pixel 10 includes a light receiving element PD formed of an embedded light receiving element, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a first signal line sig1, and a capacitance CmR. , CmS, capacitance switch transistors SwR and SwS, an initialization transistor IT, a second amplification transistor SF2, a selection transistor SL, and a second signal line sig2. Although the case where each of the above-mentioned transistors is an N-channel MOS field effect transistor will be discussed below, the same applies to the case where each transistor is a P-channel MOS field effect transistor by reversing the polarity.

The amplification type solid-state imaging device according to the first embodiment includes a pixel array A10 configured by arranging a plurality of pixels 10 having capacitances CmR and CmS in a matrix, and each pixel 10 configuring the pixel array A10. A control circuit for performing operation control (including a row decoder circuit 14, a row drive circuit 15, a column signal processing circuit 17, and a column decoder circuit 18 as described in detail with reference to FIG. 2) is provided. In the amplification type solid-state imaging device, each pixel 10 generates a signal corresponding to the received light and outputs the signal, and an N channel MOS that amplifies and outputs the signal input from the light receiving element PD to the gate A first amplification transistor SF1 formed of a field effect transistor, a reset transistor RT for resetting the gate voltage of the first amplification transistor SF1, and a first amplification Capacitances CmR and CmS for holding signals output from transistor SF1 to first signal line sig1, and corresponding to capacitances CmR and CmS and provided between first signal line sig1 and capacitances CmR and CmS, respectively , Capacitive switch transistors SwR and SwS that perform input / output control between the first signal line sig1 and the capacitors CmR and CmS, and a signal input to the gate from the first signal line sig1 to be amplified and a second signal A second amplification transistor SF2 formed of an N-channel MOS field effect transistor outputting to the line sig2, and an initialization transistor IT connected to the first signal line sig1 and outputting a predetermined voltage Vs to the first signal line sig1; The control circuit comprises
(1) The capacitors CmR and CmS are initialized to the voltage Vs by turning on the initialization transistor IT and turning on the capacitance switch transistors SwR and SwS,
(2) During the period in which the first amplification transistor SF1 shifts from the saturation region operation to the subthreshold region operation and enters the metastable state, capacitances CmR and CmS are simultaneously applied to all the pixels 10 constituting the pixel array A10. By sequentially turning on the corresponding capacitive switch transistors SwR and SwS, the amplified signal from the first amplification transistor SF1 is transferred to the first signal line sig1 and the capacitive switch transistors SwR and SwS corresponding to the capacitors CmR and CmS to be written. Execute a write operation to sequentially write to the capacitors CmR and CmS via
(3) The capacitance switch transistors SwR and SwS corresponding to the capacitances CmR and CmS are sequentially turned on to sequentially turn on the signals written to the respective capacitances CmR and CmS, and the capacitance switch transistors SwR and SwS corresponding to the capacitances CmR and CmS to be read out. The second signal line sig2 is controlled to be read out sequentially through the first signal line sig1 and the second amplification transistor SF2.

In FIG. 1, the anode of the light receiving element PD is connected to the ground voltage, and the cathode of the light receiving element PD is connected to the source of the transfer transistor TX. The gate of the transfer transistor TX is connected to the row drive circuit 15 described in detail with reference to FIG. 2, and the drain of the transfer transistor TX is connected to the gate of the first amplification transistor SF1 and the source of the reset transistor. . Here, a region where the drain of the transfer transistor TX, the gate of the first amplification transistor SF1, and the source of the reset transistor are connected is referred to as a floating diffusion region FD. The gate of the reset transistor is connected to the row drive circuit 15, and a drive signal Vrd, which is a reset drain voltage from the row drive circuit 15, is applied to the drain of the reset transistor. The drain of the first amplification transistor SF1 is connected to the power supply voltage Vdd, and the source of the first amplification transistor SF1 is connected to the drain of the capacitive switch transistor SwR via the first signal line sig1. It is connected to the drain, the source of the initialization transistor IT, and the gate of the second amplification transistor SF2. The gate of the capacitive switch transistor SwR is connected to the row drive circuit 15, the source of the capacitive switch transistor SwR is connected to one end of the capacitor CmR, and the other end of the capacitor CmR is connected to the ground voltage. The gate of the capacitive switch transistor SwS is connected to the row drive circuit 15, the source of the capacitive switch transistor SwS is connected to one end of the capacitor CmS, and the other end of the capacitor CmS is connected to the ground voltage. The gate of the initialization transistor IT is connected to the row drive circuit 15, and the drain of the initialization transistor IT is connected to the ground voltage or a voltage Vs which is a positive voltage close to the ground voltage. The drain of the second amplification transistor SF2 is connected to the power supply voltage Vdd, and the source of the second amplification transistor SF2 is connected to the drain of the selection transistor SL. The gate of the selection transistor SL is connected to the row drive circuit 15, and the source of the selection transistor SL is connected to the second signal line sig2.

One end of the second signal line sig2 is connected to the drain of the constant current load transistor CL. The drain of the constant current load transistor CL is also connected to a column signal processing circuit 17 which will be described in detail with reference to FIG. 2 and outputs an output voltage Vo to the column signal processing circuit 17. The gate of the constant current load transistor CL is connected to, for example, a DC voltage so that the constant current load transistor CL becomes a constant current load when the output voltage Vo is read. The source of the constant current load transistor CL is connected to the ground voltage.

Also, refer to the voltage of the floating diffusion region FD and the voltage _{V FD,} the first voltage signal line sig1 called voltage _{V sig1} means a voltage of the capacitor CmR voltage _{V CmR,} and the voltage a voltage _{V CmS} capacity CmS The voltage of the second signal line sig2 is referred to as a voltage V _sig2 .

FIG. 2 is a block diagram showing a configuration of an amplification type solid-state imaging device (also referred to as a two-dimensional image sensor) including a pixel array A10 in which the pixels 10 of FIG. 1 are arranged in a matrix. The pixel array A10 is configured to include a plurality of pixels 10, and the two-dimensional image sensor includes the pixel array A10, a row decoder circuit 14, a row driving circuit 15, a column signal processing circuit 17, and a column decoder circuit 18. It is configured with.

In FIG. 2, the row decoder circuit 14 outputs a selection signal for selecting a specific row of the pixel array A 10 to the row drive circuit 15. The row drive circuit 15 outputs the following seven types of drive signals to the pixels 10 of the row selected by the row decoder circuit 14 through the seven drive lines 16.
(1) Drive signal Vrd: A drive signal applied to the drain of the reset transistor RT to determine the voltage of the drain of the reset transistor RT, such as voltage VH (for example +3 V) or voltage VL (for example +0.5 V) There is a value of
(2) Drive signal V _TX : A drive signal applied to the gate of the transfer transistor TX to turn the transfer transistor TX on and off, and when the drive signal V _TX is high level V _{TX (H)} , the transfer transistor TX is turned on and driven When the signal V _TX is at the low level V _{RT (L)} , the transfer transistor TX is turned off.
(3) Drive signal V _RT : A drive signal applied to the gate of the reset transistor RT to turn the reset transistor RT on and off. When the drive signal V _RT is at high level, the reset transistor RT is turned on and the drive signal V _RT is low. When it is at level, the reset transistor RT is turned off.
(4) Drive signal V _SwR : A drive signal applied to the gate of the capacitive switch transistor SwR to turn on / off the capacitive switch transistor SwR. When the drive signal V _SwR is at high level, the capacitive switch transistor SwR is turned on. _{When SwR} is at low level, the capacitance switch transistor SwR is turned off.
(5) Drive signal V _SwS : A drive signal applied to the gate of the capacitive switch transistor SwS to turn on / off the capacitive switch transistor SwS. When the drive signal V _SwS is at high level, the capacitive switch transistor SwS is turned on. _{When SwS} is at low level, the capacitance switch transistor SwS is turned off.
(6) Drive signal V _IT : A drive signal applied to the gate of the initialization transistor IT to turn on and off the initialization transistor IT. When the drive signal V _IT is at high level, the initialization transistor IT is turned on, and the drive signal V IT is turned on. _{When IT} is low, the initialization transistor IT is turned off.
(7) Drive signal V _SL : A drive signal applied to the gate of the selection transistor SL to turn the selection transistor SL on and off. When the drive signal V _SL is at high level, the selection transistor SL is turned on and the drive signal V _SL is low. When it is at level, the selection transistor SL is turned off.

As described above, since the row drive circuit 15 outputs the drive signal for each row of the pixel array A10, the drive signal output to the pixels 10 in the i-th row of the pixel array A10 is It shall be represented by connecting). For example, the drive signal V _SwS output to the pixel 10 in the i-th row is _expressed as a drive signal V _SwS (i). Moreover, when not connecting (i) mentioned above, suppose that the drive signal output to the pixel 10 of all the rows of pixel array A10 is represented. Furthermore, using the same notation applies to the voltage _{_{_{_{V FD, V sig1, V CmR}}}} , V CmS, V sig2 in the pixel 10 described with reference to FIG. That is, when (i) is connected, it represents the voltage at the pixel 10 of the i-th row of the pixel array A10, and when (i) is not connected, it represents the voltage at the pixels 10 of all the rows of the pixel array A10. Do. For example, the voltage V _CmS (i) represents the voltage of the capacitance CmS of the pixel 10 in the i-th row of the pixel array A10, and the voltage V _sig1 represents the first signal line sig1 of the pixels 10 in all the rows of the pixel array A10. Indicates the voltage of

The pixel 10 operates in response to the drive signal from the row drive circuit 15, and outputs a reset signal and an optical signal to be described later to the column signal processing circuit 17 via the second signal line sig2. The column signal processing circuit 17 removes so-called reset noise by sampling both the reset signal and the light signal (data signal) and subtracting the reset signal from the light signal, so-called known correlated double sampling processing (hereinafter referred to as CDS). Processing, and at least one of CDS processing, analog signal processing, and digital signal processing is performed on the reset signal and the light signal from the pixel 10, and the column In response to a control signal from the decoder circuit 18, the processed signal is output to a circuit (not shown) outside the amplification type solid-state imaging device through the horizontal signal line 19. The power supply line 11 is connected to the power supply line of the entire amplification type solid-state imaging device, and applies the power supply voltage Vdd to the drain of the first amplification transistor SF1 and the drain of the second amplification transistor SF2.

The row decoder circuit 14, the row drive circuit 15, the column signal processing circuit 17, and the column decoder circuit 18 constitute a control circuit, and control signals input to the row decoder circuit 14 and the column decoder circuit 18 and the control The circuitry that generates the signal is not shown.

3 is a first part of a timing chart showing the operation of the two-dimensional image sensor of FIG. 2, and FIG. 4 is a second part of the timing chart showing the operation of the two-dimensional image sensor of FIG. The operation of the two-dimensional image sensor of FIG. 2 will be described with reference to FIGS. 3 and 4.

3 and 4, the drive signal _{_{_{_{Vrd, V RT, V TX,}}}} V SwR (i), V SwS (i), V IT (i), V SL (i), V SwR (i + 1), V SwS ( i + 1), V _IT (i + 1), and V _SL (i + 1) are drive signals output from the row drive circuit 15 described above to the pixel 10. The voltages V _FD , V _{sig 1} (i), V _{Cm R} (i), V _{Cm S} (i), V _sig 1 (i + 1), V _{Cm R} (i + 1), V _{Cm S} (i + 1), and V _{sig 2} are the pixels 10 described above. The voltage at

The operation of the two-dimensional image sensor provided with the pixel array A10 includes an initialization operation for initializing all the pixels 10 of the pixel array A10 and a reset operation in which all the pixels 10 of the pixel array A10 operate collectively. The write phase for executing the operation of writing the signal in the capacitor SwR and the light signal in the capacitor SwS, and the pixels 10 of the pixel array A10 operate row by row to read the reset signal from the capacitor SwR and And a read phase for performing a read operation. Further, the write phase and the read phase are collectively referred to as a frame period. In the present embodiment, one frame includes image data of one screen in the progressive scanning method.

First, the initialization operation will be described. Here, the operation of the pixels 10 included in the i-th row of the pixel array A10 will be described, but the pixels 10 included in other rows operate in the same manner. In the initialization operation, the drive signal V _IT (i) is set to high level in a state where the capacitive switch transistors SwR and Sw S are turned on by setting the drive signals V _SwR (i) and V _SwS (i) to high level. Thus, the initialization transistor IT is turned on to initialize the voltages V _CmR (i) and V _CmS (i) of the capacitors CmR and CmS to the voltage Vs. Note that, as described later, the same initialization operation as the above-described operation is also performed at the end of the read phase row by row.

Next, the write phase will be described. In the write phase, all the pixels 10 of the pixel array A10 simultaneously operate at once. Here, the operation of the pixels 10 included in the i-th row of the pixel array A10 will be described, but the pixels 10 included in other rows operate in the same manner.

In the period T1 from time t1, the driving signal V _RT Although the reset transistor RT is a high level is turned on, since the time of the drive signal Vrd is a high voltage VH, the voltage V _FD voltage of the floating diffusion region FD The voltage is reset to the source voltage of the reset transistor RT corresponding to VH or VH, and the first amplification transistor SF1 is turned on. The voltage V _sig1 (i) is an output voltage of the source follower circuit including the first amplification transistor SF1 and having a gain G1 (G1 <1), and the variation of the voltage V _sig1 (i) is an input of the source follower circuit The voltage V _FD changes by G1 times, and the waveform of the voltage V _sig1 (i) is similar to the waveform of the voltage V _FD .

Next, in a period T2 from time t2, the drive signal V _SwR (i) is set to the high level to turn on the capacitance switch transistor SwR, but the voltage V _CmR (i) of the capacitance CmR is the voltage Vs by the above-described initialization operation. since it is, when the voltage V _FD of the floating diffusion region FD is reset to the voltage VH, the first amplification transistor SF1 is turned on, the charge current towards the source of the first amplification transistor SF1 to capacity CmR The current CmR is charged. When the capacitance CmR is charged and the voltage of the source of the first amplification transistor SF1 rises, the operation of the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, and the charging current hardly flows. The voltage V _CmR (i) of the capacitance CmR becomes a substantially stable voltage VsigR. That is, a period T2 in which the capacitance switch transistor SwR is on is a period until the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region.

Next, in a period T3 from time t3, the drive signal V _TX is set to the high level to turn on the transfer transistor TX, and the signal charge generated in the light receiving element PD by the incident light is transferred to the floating diffusion region FD. At this time, the voltage V _FD of the floating diffusion region FD changes in accordance with the amount of signal charge. If the signal charge is not present, the voltage _{V FD} If next voltage VsigS1, signal charge exists, the voltage _{V FD} becomes a voltage VsigS2. Hereinafter, the voltage generated by the signal charge is referred to as a voltage VsigS (VsigS2 ≦ VsigS ≦ VsigS1).

Thereafter, in a period T4 from time t4, the drive signal V _SwS (i) is set to the high level to turn on the capacitance switch transistor SwS, and a charging current flows from the source of the first amplification transistor SF1 toward the capacitance CmS. The capacitance CmS is charged. When the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, the voltage V _CmS (i) of the capacitor CmS becomes a substantially stable voltage VsigS.

Finally, in the period T5 from time t5, the driving signal V _RT is a high level reset transistor RT is turned on again, because this time the drive signal Vrd is at a low voltage VL, the voltage of the floating diffusion region FD V _{The FD} is reset to the voltage VL, and the first amplification transistor SF1 is turned off. That is, the first amplification transistor SF1 is in the off state until the next write phase is subsequently entered.

The voltage VsigR held by the capacitor CmR represents the voltage (reset signal) of the floating diffusion region FD when the reset transistor RT is turned on by the write operation in the above-described write phase, and the voltage VsigS held by the capacitor CmS is This represents the voltage (light signal) of the floating diffusion region FD when the transfer transistor TX is turned on to transfer the signal charge from the light receiving element PD to the floating diffusion region FD.

Further, noise generated when charging the capacitors CmR and CmS in the above-described write operation is noise generated when charging the capacitor Cm in the pixel 110 of FIG. 17 according to the prior art, and the pixel of FIG. Compared to noise generated when charging the capacitances Cm1 and Cm2 at 120 and noise generated when charging the capacitances CmR and CmS in the pixel 130 of FIG. 19 according to the prior art, energy is reduced by half. . That is, when the capacitance values of the capacitors Cm, Cm1, Cm2, CmR, and CmS of the

pixels

110, 120, and 130 according to the prior art are the capacitance value C, the noise generated when charging these capacitors is It is represented by 1).

Here, k represents a Boltzmann constant, and T represents an absolute temperature.

On the other hand, when the capacitance value of the capacitances CmR and CmS of the pixel 10 according to the first embodiment is the capacitance value C, when charging these capacitances, the first amplification transistor SF1 operates in the subthreshold region, The generated noise is expressed by the following equation (2).

Here, k represents a Boltzmann constant, and T represents an absolute temperature. That is, the pixel 10 can reduce noise compared to the pixel according to the prior art.

Next, the read phase will be described. In the readout phase, the respective rows of the pixel array A10 are sequentially driven in units of one horizontal scanning period (1H) described later. Here, as described above, since the voltage V _FD of the floating diffusion region FD is reset to the voltage VL in the period T5 of the writing phase, the first amplification transistor SF1 is in the off state in the reading phase. The voltage V _sig2 of the second signal line is the output voltage of the source follower circuit that includes the second amplification transistor SF2 and has the gain G2 (G2 <1), and the variation of the voltage V _sig2 is the source follower circuit of becomes G2 fold change in voltage _{V sig1} of the first signal line of each row is the input voltage (i), the waveform of the voltage _{V sig2,} a similar to the waveform of the voltage _{V sig1} (i).

First, the pixels 10 included in the i-th row of the pixel array A10 will be described. First, in period T6 from time t6, the drive signal V _IT (i) is set to the high level, the initialization transistor IT is turned on, and the voltage of the gate of the second amplification transistor SF2, that is, the voltage V _sig1 (i) It is reset to the voltage Vs.

Next, in a period T7 from time t7, the drive signal V _SL (i) is set to the high level, the selection transistor SL is turned on, and the second amplification transistor SF2 is activated, and the drive signal V _SwR (i) The capacitor switch transistor SwR is turned high and the capacitor switch transistor SwR is turned on, and the voltage VsigR representing the reset signal is transferred from the capacitor CmR to the second signal line via the first signal line sig1, the second amplification transistor SF2, and the selection transistor SL. It is output to sig2.

Next, in period T8 from time t8, the initialization transistor IT is turned on while the capacitance switch transistor SwR is on, and the voltage V _CmR (i) of the capacitance CmR is initialized to the voltage Vs.

Next, in a period T9 from time t9, the drive signal V _SwS (i) is turned high while the selection transistor SL is in the on state, the capacitance switch transistor SwS is turned on, and the voltage VsigS representing the optical signal is The signal is output to the second signal line sig2 via the first signal line sig1, the second amplification transistor SF2, and the selection transistor SL.

Finally, in a period T10 from time t10, the initialization transistor IT is turned on while the capacitance switch transistor SwS is on, and the voltage V _CmS (i) of the capacitance CmS is initialized to the voltage Vs. Thereafter, the same operation as the above-described read operation is performed on the pixels 10 included in the (i + 1) th row of the pixel array A10.

As described in the read operation, the above-described initialization operation is performed row by row in periods T8 and T10. Hereinafter, a period from time t6 when the readout of the i-th row is executed to the end of the period T10 is referred to as a readout period Trd (i) of the i-th row. A period from time t6 when the read operation of the i-th row is started to time t6a when the read operation of the (i + 1) th row is started is referred to as one horizontal scanning period (1H).

In the above operation, it is desirable that the capacitance values of the capacitors CmR and CmS be as large as possible in design because of the relationship of the equation (2). At the same time, if the capacitances of the capacitors CmR and CmS are sufficiently large compared to the gate capacitance of the second amplification transistor SF2, the voltage values read out in the periods T7 and T9 are written to the respective capacitors CmR and CmS. The voltage value at the time of reading is almost the same as the voltage value at the time of reading. By this, the pixel 10 of FIG. 1 can take a large voltage value of the reset signal and the light signal as compared with the pixel 130 of FIG. 19, so the S / N ratio is improved, and according to equation (2) Noise is reduced.

For example, the column signal processing circuit 17 shown in FIG. 2 performs CDS processing for obtaining a difference between the voltage VsigR and the voltage VsigS on the reset signal and the light signal read from the pixel 10 by the reading operation in the reading phase described above. . With respect to reset noise in the floating diffusion region FD, and fixed pattern noise caused by variations in threshold values of the first amplification transistor SF1 and the second amplification transistor SF2, there is a correlation between the voltage VsigR and the voltage VsigS. These noises are removed by executing the CDS processing, and a high quality image signal can be obtained.

In the timing charts of FIGS. 3 and 4, the signal charge transferred from the light receiving element PD to the floating diffusion region FD is a period from the end time of the period T3 in the write phase to the end time of the period T3 in the next write phase, ie Although the signal charge is accumulated in the light receiving element PD during the full frame period, a shutter operation capable of shortening the time for accumulating the signal charge (hereinafter referred to as exposure accumulation time (Tint)) to an arbitrary length is also possible. .

FIG. 5 is a timing chart showing the shutter operation of the two-dimensional image sensor of FIG. Here, the drive signal _Vrd shown in FIG. _{_{_{5, V RT, V TX,}}} V SwR (i), V SwS (i), V IT (i), V SL (i), V SwR (i + 1), V SwS (I + 1), V _IT (i + 1), and V _SL (i + 1) are the same as those described in the timing charts of FIGS. 3 and 4. Further, the same reference numerals are given to the times and periods indicating the same times and periods as those in FIGS. 3 and 4.

In the shutter phase, all the pixels of the pixel array A10 operate collectively, and an operation for discharging the signal charge accumulated in the light receiving element PD (hereinafter referred to as a shutter operation) is performed. The shutter phase for performing the shutter operation may be set to an arbitrary period which does not overlap with the readout period Trd of each row in the readout phase. In the timing chart of FIG. 5, the shutter phase is from time t11 to time t15, and is set between the readout period Trd (i) of the i-th row pixel and the readout period Trd (i + 1) of the i + 1 th row pixel. ing. The readout phase of the portion other than the shutter phase is the same as the readout phase described above.

First, during the period from time t11 to time t12, the the driving signal _{V TX} and the drive signal _{V RT} is a high level transfer transistors TX and the reset transistor RT is turned on, the drive signal Vrd at this time a high voltage VH Because of this, the signal charge stored in the light receiving element PD is discharged to the drain of the reset transistor RT via the floating diffusion region FD.

Next, at time t12, the drive signal V _TX is set to low level, and the transfer transistor TX is turned off. Next, at time t13, the voltage of the floating diffusion region FD becomes the voltage VL by changing the drive signal Vrd from the voltage VH to the voltage VL. Next, at time t14, the drive signal V _RT is set to low level, the reset transistor RT is turned off, and the voltage of the floating diffusion region FD is held at the voltage VL at which the first amplification transistor SF1 is turned off. to enable.

A period from when the transfer transistor TX is turned off at time t12 in the shutter phase to when the period T3 in the next write phase ends and the transfer transistor TX is turned off is an effective exposure accumulation period Tint. The length of the exposure accumulation period Tint can be changed by changing the time to set the shutter phase in the read phase.

As described above, according to the first embodiment, one embedded light receiving element PD and eight transistors TX, RT, SF1, SwR, SwS, IT, SF2, SL, and two capacitances in one pixel are used. Only by using CmR and CmS, it is possible to configure a two-dimensional image sensor capable of collective exposure and obtaining high image quality by CDS processing. In addition, when the reset signal and the light signal are written in the capacitors CmR and CmS, respectively, only a transient charging current flows in the capacitors CmR and CmS, and a large DC current does not flow. Furthermore, when the reset signal and the optical signal are read out from the capacitors CmR and CmS, respectively, the voltage representing the signal does not decrease, so the S / N ratio can be improved.

Second embodiment.
FIG. 6 is a circuit diagram showing a configuration of a pixel 20 of the amplification type solid-state imaging device according to the second embodiment of the present invention. The pixel 20 is different from the pixel 10 of FIG. 1 in that the selection transistor SL is not provided and that the voltage Vs is set to a voltage value at which the second amplification transistor SF2 is turned off. Is the same as the pixel 10, and the description thereof is omitted. The configuration of a two-dimensional image sensor including a pixel array in which the pixels 20 are arranged in a matrix is the same as that in which the pixels 10 in FIG. Furthermore, the timing chart showing the operation of the two-dimensional image sensor provided with the pixel array having the pixels 20 is the drive signal _VSL (i), _VSL (i + 1) for the selection transistor in the timing charts of FIG. 3 and FIG. It is the same as that of deleting.

The operation of the two-dimensional image sensor provided with the pixel 20 will be described with reference to FIGS. 3 and 4. During the periods T7 and T9, the reset signal held by the capacitor CmR and the light signal held by the capacitor CmS are applied to the gate of the second amplification transistor SF2 only when the capacitance switch transistors SwR and SwS are turned on. The second amplification transistor SF2 is activated. Further, in the periods T6, T8 and T10, the initialization transistor IT is turned on, and the voltage V _sig1 (i) of the gate of the second amplification transistor SF2 becomes the voltage Vs, and the second amplification transistor SF2 is turned off. Furthermore, after the period T10, the second amplification transistor SF2 is maintained in the off state (non-selection mode). Therefore, the two-dimensional image sensor according to the second embodiment operates in the same manner as the two-dimensional image sensor according to the first embodiment. In addition, the two-dimensional image sensor according to the second embodiment can execute the shutter operation in the same manner as in the first embodiment.

As described above, according to the second embodiment, one embedded light receiving element PD, seven transistors TX, RT, SF1, SwR, SwS, IT, SF2 and two capacitances CmR, Only by using CmS, it is possible to configure a two-dimensional image sensor capable of collective exposure and obtaining high image quality by CDS processing. In addition, when the reset signal and the light signal are written in the capacitors CmR and CmS, respectively, only a transient charging current flows in the capacitors CmR and CmS, and a large DC current does not flow. Furthermore, when the reset signal and the light signal are read out from the capacitors CmR and CmS, the voltage representing the signal does not decrease, so the S / N ratio can be improved. Furthermore, since the number of transistors is smaller compared to the first embodiment, the circuit can be miniaturized to increase the area of the light receiving element PD.

Third embodiment.
FIG. 7 is a circuit diagram showing a configuration of a pixel 30 of an amplification type solid-state imaging device according to a third embodiment of the present invention. The pixel 30 is configured to include the output switch transistor SwO between the first amplification transistor SF1 and the first signal line sig1 as compared to the pixel 10, and the drain of the reset transistor is the first amplification transistor SF1. And the drain of the second amplification transistor SF2 are commonly connected to the power supply voltage Vdd, and the other components are the same as those of the pixel 10, and the description thereof will be omitted. The configuration of a two-dimensional image sensor including a pixel array in which the pixels 30 are arranged in a matrix is the same as that in which the pixels 10 in FIG. The drive signal V _SwO from the row drive circuit 15 is input to the gate of the output switch transistor SwO, and the output switch transistor SwO is turned on when the drive signal V _SwO is at high level, and the output switch when the drive signal V _SwO is at low level The transistor SwO is turned off.

FIG. 8 is a first portion of a timing chart illustrating the operation of a two-dimensional image sensor comprising a pixel array having the pixels 30 of FIG. 7, and FIG. 9 comprises a pixel array having the pixels 30 of FIG. It is a 2nd part of the timing chart which shows operation | movement of a two-dimensional image sensor. Compared with the timing charts of FIG. 3 and FIG. 4, the timing charts of FIG. 8 and FIG. 9 delete the drive signal _Vrd and add the drive signal V _SwO , the waveform of the voltage V _FD , and the voltage V _{The waveforms of sig1} (i) and V _sig1 (i + 1) are different.

The drive signal V _SwO is set to a high level during a period from when the reset transistor RT is first turned on (time t1) to next turned on (time t5) in the write phase, whereby the output switch transistor SwO is turned on. The source of the first amplification transistor SF1 is connected to the first signal line to enable writing of the reset signal and the light signal to the capacitances CmR and CmS via the capacitance switch transistors SwR and SwS.

Further, the waveform of the voltage V _FD of the floating diffusion region FD is the same from time t1 to time t5 as compared with FIGS. 3 and 4 and is different after time t5. In the period T5, the reset transistor RT is turned on, the voltage _{V FD} of the floating diffusion region FD is higher voltage VH. Even when the voltage V _FD is a high voltage VH, in the read phase, the output switch transistor SwO is in the OFF state, so the first amplification transistor SF1 does not affect the read operation. Therefore, in the read phase, voltages V _sig1 (i) and V _sig1 (i + 1), drive signals V _SwR (i) and V _SwR (i + 1), and drive signals V _SwS (i) and V _{SwS shown in FIGS.} (I + 1), voltage V _CmR (i), V _CmR (i + 1), voltage V _CmS (i), V _CmS (i + 1), drive signal V _IT (i), V _IT (i + 1), and drive signal V _SL ( i) and V _SL (i + 1) are the same as those in FIGS. 3 and 4. Therefore, the two-dimensional image sensor according to the third embodiment operates in the same manner as the two-dimensional image sensor according to the first embodiment. Further, the shutter operation of the two-dimensional image sensor according to the third embodiment is the same as that of the shutter operation of the first embodiment except the operation related to the drive signal Vrd.

As described above, according to the third embodiment, one embedded light receiving element PD, nine transistors TX, RT, SF1, SwO, SwR, SwS, IT, SF2, SL, and 2 in one pixel. It is possible to configure a two-dimensional image sensor capable of collective exposure and achieving high image quality by CDS processing only by using two capacitors CmR and CmS. In addition, when the reset signal and the light signal are written in the capacitors CmR and CmS, respectively, only a transient charging current flows in the capacitors CmR and CmS, and a large DC current does not flow. Furthermore, when the reset signal and the light signal are read out from the capacitors CmR and CmS, the voltage representing the signal does not decrease, so the S / N ratio can be improved.

In the third embodiment, the selection transistor SL is provided to configure the pixel 30, but the present invention is not limited thereto, and the pixel 30 is configured without including the selection transistor SL as in the second embodiment. In this case, the number of transistors in the pixel 30 is eight, and the circuit can be miniaturized to increase the area of the light receiving element PD.

Fourth Embodiment
FIG. 10 is a circuit diagram showing a configuration of a pixel 40 of an amplification type solid-state imaging device according to a fourth embodiment of the present invention. The

pixels

10, 20, and 30 according to the first, second, and third embodiments described above include the embedded light receiving element type light receiving element PD and the transfer transistor TX, but the fourth embodiment relates to the fourth embodiment. The pixel 40 does not include a transfer transistor and includes a PN light receiving element type light receiving element PD.

As shown in FIG. 10, the pixel 40 includes a light receiving element PD formed of a PN light receiving element, a reset transistor RT, a first amplification transistor SF1, a first signal line sig1, an output switch transistor SwO, and a capacitance CmR1. , CmR2, and CmS, capacitance switch transistors SwR1, SwR2, and SwS, an initialization transistor IT, a second amplification transistor SF2, a selection transistor SL, and a second signal line sig2. The configuration of a two-dimensional image sensor including a pixel array in which the pixels 40 are arranged in a matrix is the same as that in which the pixels 10 in FIG. Hereinafter, a pixel array in which the pixels 40 are arranged in a matrix is referred to as a pixel array A40.

In FIG. 10, the anode of the light receiving element PD is connected to the ground voltage, and the cathode of the light receiving element PD is connected to the gate of the first amplification transistor SF1 and the source of the reset transistor. The gate of the reset transistor is connected to the row drive circuit 15 described above with reference to FIG. 2, and the drain of the reset transistor is connected to the power supply voltage Vdd. The drain of the first amplification transistor SF1 is connected to the power supply voltage Vdd, and the source of the first amplification transistor SF1 is connected to the source of the output switch transistor SwO. The gate of the output switch transistor SwO is connected to the row drive circuit 15, and the drain of the output switch transistor SwO is the drain of the capacitive switch transistor SwR1 and the drain of the capacitive switch transistor SwR2 via the first signal line sig1. It is connected to the drain of the capacitive switch transistor SwS, the source of the initialization transistor IT, and the gate of the second amplification transistor SF2. The gate of the capacitive switch transistor SwR1 is connected to the row drive circuit 15, the source of the capacitive switch transistor SwR1 is connected to one end of the capacitor CmR1, and the other end of the capacitor CmR1 is connected to the ground voltage. The gate of the capacitive switch transistor SwR2 is connected to the row drive circuit 15, the source of the capacitive switch transistor SwR2 is connected to one end of the capacitor CmR2, and the other end of the capacitor CmR2 is connected to the ground voltage. The gate of the capacitive switch transistor SwS is connected to the row drive circuit 15, the source of the capacitive switch transistor SwS is connected to one end of the capacitor CmS, and the other end of the capacitor CmS is connected to the ground voltage. The gate of the initialization transistor IT is connected to the row drive circuit 15, and the drain of the initialization transistor IT is connected to the ground voltage or a voltage Vs which is a positive voltage close to the ground voltage. The drain of the second amplification transistor SF2 is connected to the power supply voltage Vdd, and the source of the second amplification transistor SF2 is connected to the drain of the selection transistor SL. The gate of the selection transistor SL is connected to the row drive circuit 15, and the source of the selection transistor SL is connected to the second signal line sig2.

One end of the second signal line sig2 is connected to the drain of the constant current load transistor CL. The drain of the constant current load transistor CL is also connected to the column signal processing circuit 17 described above with reference to FIG. 2 and outputs an output voltage Vo to the column signal processing circuit 17. The gate of the constant current load transistor CL is connected to, for example, a DC voltage so that the constant current load transistor CL becomes a constant current load when the output voltage Vo is read. The source of the constant current load transistor CL is connected to the ground voltage.

Also, refer to cathode voltage of the light-receiving element PD and the voltage _{V PD,} a first voltage of the signal line sig1 called voltage _{V sig1,} capacitance voltage CMR1 called voltage _{V CMR1} the voltage a voltage of the capacitor CMR2 _{V CMR2} The voltage of the capacitor CmS is called the voltage V _CmS, and the voltage of the second signal line sig2 is called the voltage V _sig2 .

Further, drive signals output from the row drive circuit 15 to the pixels 40 are shown below.
(1) Drive signal V _RT : A drive signal applied to the gate of the reset transistor RT to turn the reset transistor RT on and off. When the drive signal V _RT is at high level, the reset transistor RT is turned on and the drive signal V _RT is low. When it is at level, the reset transistor RT is turned off.
(2) Drive signal V _SwO : A drive signal applied to the gate of the output switch transistor SwO to turn on / off the output switch transistor SwO. When the drive signal V _SwO is at high level, the output switch transistor SwO is turned on, and the drive signal V SwO is turned on. _{When SwO} is at low level, the output switch transistor SwO is turned off.
(3) Drive signal V _SwR1 : A drive signal applied to the gate of the capacitive switch transistor SwR1 to turn on / off the capacitive switch transistor SwR1. When the drive signal V _SwR1 is at high level, the capacitive switch transistor SwR1 is turned on. _{When SwR1} is at low level, the capacitance switch transistor SwR1 is turned off.
(4) Drive signal V _SwR2 : A drive signal applied to the gate of the capacitive switch transistor SwR2 to turn on / off the capacitive switch transistor SwR2, and when the drive signal V _SwR2 is at high level, the capacitive switch transistor SwR2 is turned on. _{When SwR2} is at low level, the capacitance switch transistor SwR2 is turned off.
(5) Drive signal V _SwS : A drive signal applied to the gate of the capacitive switch transistor SwS to turn on / off the capacitive switch transistor SwS. When the drive signal V _SwS is at high level, the capacitive switch transistor SwS is turned on. _{When SwS} is at low level, the capacitance switch transistor SwS is turned off.
(6) Drive signal V _IT : A drive signal applied to the gate of the initialization transistor IT to turn on and off the initialization transistor IT. When the drive signal V _IT is at high level, the initialization transistor IT is turned on, and the drive signal V IT is turned on. _{When IT} is low, the initialization transistor IT is turned off.
(7) Drive signal V _SL : A drive signal applied to the gate of the selection transistor SL to turn the selection transistor SL on and off. When the drive signal V _SL is at high level, the selection transistor SL is turned on and the drive signal V _SL is low. When it is at level, the selection transistor SL is turned off.

As described above, since the row drive circuit 15 outputs a drive signal for each row of the pixel array A40, the drive signal to be output to the pixels 40 in the i-th row of the pixel array A40 is It shall be represented by connecting). For example, the drive signal V _SwS output to the pixel 40 in the i-th row is _expressed as a drive signal V _SwS (i). Further, in the case where (i) described above is not connected, the drive signal output to the pixels 40 in all the rows of the pixel array A 40 is represented. Furthermore, the same notation is used for the voltages V _PD , V _sig1 , V _CmR1 , V _CmR2 , V _CmS , and V _sig2 in the pixel 40 described with reference to FIG. That is, when (i) is connected, the voltage at the pixel 40 in the i-th row of the pixel array A 40 is represented, and when (i) is not connected, the voltage at the pixels 40 in all the rows of the pixel array A 40 is represented. Do. For example, the voltage V _CmS (i) represents the voltage of the capacitance CmS of the pixel 40 in the i-th row of the pixel array A 40, and the voltage V _sig1 represents the first signal line sig 1 of the pixels 40 in all the rows of the pixel array A 40. Indicates the voltage of

The operation of the two-dimensional image sensor provided with the pixel array A 40 having the pixel 40 of FIG. 10 will be described with reference to the timing charts of FIG. 11 to FIG.

FIG. 11 is a first portion of a timing chart showing the operation in one frame period of a two-dimensional image sensor having a pixel array having the pixels 40 of FIG. 10, and FIG. 12 has the pixels 40 of FIG. It is a 2nd part of the timing chart which shows operation | movement in one frame period of a two-dimensional image sensor provided with a pixel array.

In FIGS. 11 and 12, the drive signals V _RT , V _SwO , V _SwR1 (i), V _SwR2 (i), V _SwS (i), V _IT (i), V _SL (i), V _SwR1 (i + 1) , V _SwR2 (i + 1), V _SwS (i + 1), V _IT (i + 1), and V _SL (i + 1) are drive signals output from the row drive circuit 15 to the pixel 40. Also, voltages V _PD , V _{sig 1} (i), V _{Cm R 1} (i), V _{C m R 2} (i), V _{C m S} (i), V _sig 1 (i + 1), V _{C m R} 1 (i + 1), V _{C m R 2} (i + 1), V _{Cm S} (I + 1) and V _sig2 are voltages at the pixel 40 described above.

The operation of the two-dimensional image sensor provided with the pixel array A40 includes an initialization operation for initializing all the pixels 40 of the pixel array A40 and a reset operation in which all the pixels 40 of the pixel array A40 operate collectively. A write phase for writing a signal in the capacitor SwR1 or the capacitor SwR2 and a write phase for writing an optical signal in the capacitor SwS, and the pixels 40 of the pixel array A40 operate row by row to read a reset signal from the capacitor SwR1 or the capacitor SwR2 and It comprises the read phase which performs the operation which reads an optical signal from capacity SwS. Further, the write phase and the read phase are collectively referred to as a frame period. In the present embodiment, one frame includes image data of one screen in the progressive scanning method.

First, the initialization operation will be described. Here, the operation of the pixels 40 included in the i-th row of the pixel array A 40 will be described, but the pixels 40 included in other rows operate similarly. In the initialization operation, the driving signal _{_{V SwR1 (i), V SwR2}} (i), while on the volume switch transistor SWR1, SWR2, SwS by the _{V SwS} (i) the high level, the drive signal _{V IT} ( The initialization transistor IT is turned on by setting i) high level to initialize the voltages V _CmR1 (i), V _CmR2 (i) and V _CmS (i) of the capacitors CmR1, CmR2 and CmS to the voltage Vs . Note that, as described later, the same initialization operation as the above-described operation is also performed at the end of the read phase row by row.

Next, the write phase will be described. In the write phase, all the pixels 40 of the pixel array A 40 simultaneously operate at once. Here, the operation of the pixels 40 included in the i-th row of the pixel array A 40 will be described, but the pixels 40 included in other rows operate similarly. Also, since the operation of the frame to be processed in the writing phase is different between the odd-numbered frame (hereinafter referred to as odd frame) and the even-numbered frame (hereinafter referred to as even frame), The case of processing a frame will be described, and then the case of processing an even frame will be described.

At time t1, the drive signal V _SwO is set to the high level, the output switch transistor SwO is turned on, and the source of the first amplification transistor SF1 is connected to the drains of the three capacitive switch transistors SwR1, SwR2, and SwS.

In a period T2 from time t2, the voltage V _PD of the gate of the first amplification transistor SF1 is a voltage generated by the signal charge accumulated by the light receiving element PD by the incident light. At this time, the voltage V _PD changes in accordance with the amount of signal charge. When there is no signal charge, the voltage V _PD is the voltage VsigS 1, and when there is a signal charge, the voltage V _PD is the voltage VsigS 2. Hereinafter, the voltage generated by the signal charge is referred to as a voltage VsigS (VsigS2 ≦ VsigS ≦ VsigS1). Here, the voltage V _sig1 (i) is an output voltage of a source follower circuit including the first amplification transistor SF1 and having a gain G3 (G3 <1), and the variation of the voltage V _sig1 (i) is a source follower The amount of change of the input voltage V _PD of the circuit is G3 times as large as that of the voltage V _sig1 (i), and the waveform of the voltage V _sig1 (i) is similar to the waveform of the voltage V _PD . At this time, the drive signal V _SwS is set to the high level and the switch transistor SwS is turned on. However, the voltage V _CmS (i) of the capacitor CmS is the voltage Vs by the above-described initializing operation. Is turned on, a charging current flows from the source of the first amplification transistor SF1 toward the capacitance CmS, and the capacitance CmS is charged. When the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, the voltage V _CmS (i) of the capacitor CmS becomes a substantially stable voltage VsigS. That is, a period T2 during which the capacitive switch transistor SwS is on is a period until the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region. Further, the voltage VsigS corresponds to a voltage (optical signal) generated by the signal charge accumulated by incident light by the light receiving element PD.

Next, in a period T3 from time t3, the drive signal V _RT is set to the high level, the reset transistor RT is turned on, and the voltage V _PD is reset to the power supply voltage Vdd or the source voltage of the corresponding reset transistor RT. In other words, the signal charge accumulated in the light receiving element PD is discharged to the power supply, and the light receiving element PD is reset.

Thereafter, in a period T4 from time t4, the drive signal V _SwR1 (i) is set to the high level, the capacitance switch transistor SwR1 is turned on, and a charging current flows from the source of the first amplification transistor SF1 to the capacitance CmR1. When the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, the voltage V _CmR1 (i) of the capacitor CmR1 becomes a substantially stable voltage VsigR. The voltage VsigR corresponds to the voltage (reset signal) of the cathode of the light receiving element PD when the reset transistor RT is turned on.

Next, at time t5, the drive signal V _SwO is set to low level, the output switch transistor SwO is turned off, and the source of the first amplification transistor SF1 is disconnected from the drains of the three capacitance switch transistors SwR1, SwR2, and SwS. .

On the other hand, when the frame to be processed is an even frame, the only difference is that the reset signal is written to the capacitor CmR2 compared to when the frame to be processed is an odd frame. That is, in the period T4 as described above, the driving signal _{V SWR1} (i) is changed to a drive signal _{V SWR2} (i), to change the volume switch transistor SWR1 to the capacitor switching transistor SWR2, change the volume CmR1 the capacity CMR2, and When the voltage V _CmR1 (i) is changed to the voltage V _CmR2 (i), the operation in the even frame is performed.

Next, the read phase will be described. In the reading phase, the respective rows of the pixel array A40 are sequentially driven in units of one horizontal scanning period (1H) described later. Here, as described above, since the output switch transistor SwO is turned off at time t5 of the write phase, the first amplification transistor SF1 and the three capacitive switch transistors SwR1, SwR2, and SwS are not connected. The voltage V _sig2 of the second signal line is the output voltage of the source follower circuit provided with the second amplification transistor SF2 and having the gain G4 (G4 <1), and the variation of the voltage V _sig2 is the source follower circuit of becomes G4 times the variation input voltage at which the voltage of the first signal line row _{V sig1} (i), the waveform of the voltage _{V sig2,} a similar to the waveform of the voltage _{V sig1} (i). In addition, since frames to be processed in the read phase are different between the odd frame and the even frame, the case of processing the odd frame will be described first, and then the case of processing the even frame will be described.

First, the pixels 40 included in the i-th row of the pixel array A 40 will be described. First, in period T6 from time t6, the drive signal V _IT (i) is set to the high level, the initialization transistor IT is turned on, and the voltage of the gate of the second amplification transistor SF2, that is, the voltage V _sig1 (i) It is reset to the voltage Vs.

Next, in a period T7 from time t7, the drive signal V _SL (i) is set to the high level, the selection transistor SL is turned on, and the second amplification transistor SF2 is activated, and the drive signal V _SwR2 (i) The capacitor switch transistor SwR2 is turned high and the capacitor switch transistor SwR2 is turned on, and the voltage VsigR representing the reset signal is transferred from the capacitor CmR2 to the second signal line sig2 through the first signal line sig1, the second amplification transistor SF2, and the selection transistor SL. Output to

Next, in period T8 from time t8, the initialization transistor IT is turned on while the capacitance switch transistor SwR2 is on, and the voltage V _CmR2 (i) of the capacitance CmR2 is initialized to the voltage Vs.

Finally, in a period T10 from time t10, the initialization transistor IT is turned on while the capacitance switch transistor SwS is on, and the voltage V _CmS (i) of the capacitance CmS is initialized to the voltage Vs. Thereafter, the same operation as the above-described read operation is performed on the pixels 40 included in the (i + 1) th row of the pixel array A40.

On the other hand, when the frame to be processed is an even frame, the only difference is that the reset signal is read out from the capacitor CmR1 compared to when the frame to be processed is an odd frame. That is, changes in the period T7 and time T8 described above, the driving signal _{V SWR2} (i) is changed to a drive signal _{V SWR1} (i), to change the volume switch transistor SWR2 the capacitance switching transistor SWR1, the capacity CmR2 the capacity CmR1 and, and by changing the voltage _{V CMR2} (i) to a voltage _{V CMR1} (i), the operation when the even-numbered frame.

The optical signal written to the capacitor CmS in the above-described write operation discharges the signal charge accumulated in the light receiving element PD to the power supply in the period T3 in the writing phase one frame before to the signal charge accumulated in the light receiving element PD. Equivalent to. Therefore, the light signal of the odd frame has noise correlation with the reset signal of the even frame one frame before, and the light signal of the even frame has noise correlation with the reset signal of the odd frame one frame before. As described above, in the write phase, when processing an odd frame, write the optical signal to the capacitor CmS, write the reset signal to the capacitor CmR1, and process the even frame, the optical signal to the capacitor CmS. , And writes a reset signal to the capacitor CmR2. On the other hand, when an odd frame is being processed in the read phase, the optical signal written to the capacitor CmS in the write process of the frame and the reset signal written to the capacitor CmR2 in the write process one frame earlier are read When an even frame is being processed, the optical signal written to the capacitor CmS in the writing process of the frame and the reset signal written to the capacitor CmR1 in the writing process of one frame before are read. This makes it possible to read out the noise-correlated optical signal and the reset signal in pairs.

FIG. 13 is a timing chart showing the operation in two frame periods of the two-dimensional image sensor provided with the pixel array having the pixels 40 of FIG. The timing chart of FIG. 13 shows the write operation and the read operation for the capacitances CmS, CmR1, and CmR2 in two frame periods of a frame period for processing an odd frame and a frame period for processing an even frame. The same reference numerals are attached to the times and periods indicating the same times and periods as those in FIG.

First, in the write phase of the odd-numbered frame, an optical signal is written to the capacitor CmS, and a reset signal obtained by resetting the light receiving element PD is written to the capacitor CmR1. Next, in the read phase of the odd-numbered frame, the reset signal written to the capacitor CmR2 in the write operation one frame before and the optical signal written to the capacitor CmS are read. Next, in the write phase of the even frame, the optical signal is written to the capacitor CmS, and the reset signal obtained by resetting the light receiving element PD is written to the capacitor CmR2. Next, in the reading of the even frame, the reset signal written to the capacitor CmR1 in the write operation one frame before and the optical signal written to the capacitor CmS are read. At this time, the exposure accumulation time (Tint) is a period after the reset signal is written to the capacitor CmR1 and after the light signal is written to the capacitor CmS.

Since the reset signal and the light signal read from the pixel 40 become a pair with noise correlation by the write operation and the read operation described above, for example, the difference between the voltage VsigR and the voltage VsigS in the column signal processing circuit 17 of FIG. If the CDS processing is performed, fixed pattern noise caused by variations in the reset noise in the light receiving element PD and the threshold variation of the first amplification transistor SF1 and the second amplification transistor SF2 is removed, and high image quality is achieved. Can be obtained.

In the timing charts of FIG. 11, FIG. 12 and FIG. 13, the light signal is a voltage corresponding to the signal charge accumulated in the light receiving element PD in the period from the write phase to the next write phase, It is also possible to use a shutter operation to shorten the time for accumulating signal charges (hereinafter referred to as exposure accumulation time (Tint)) to an arbitrary length.

FIG. 14 is a timing chart showing the shutter operation of the two-dimensional image sensor provided with the pixel array having the pixels 40 of FIG. Here, the drive signals V _SwO , V _RT , V _SwR1 (i), V _SwR2 (i), V _SwS (i), V _IT (i), V _SL (i), V _{Sw R1} (i + 1) shown in _FIG. , V _SwR2 (i + 1), V _SwS (i + 1), V _IT (i + 1), and V _SL (i + 1) are the same as those described in the timing charts of FIGS. The same reference numerals are given to the times and periods indicating the same times and periods as those in FIGS. 11 and 12.

In the shutter phase, all the pixels 40 of the pixel array A 40 operate collectively to discharge the signal charge accumulated in the light receiving element PD, and write a reset signal in which the light receiving element PD is reset to the capacitance CmR1 or CmR2. An operation (hereinafter referred to as a shutter operation) is performed. In the first embodiment, the reset signal is not written to the capacitor CmR in the shutter operation, but in the present embodiment, the writing of the reset signal is also performed. The shutter phase may be set to an arbitrary period so as not to overlap with the readout period Trd of each row in the readout phase. In the timing chart of FIG. 14, the shutter phase is from time t15 to time t18, and is set between the readout period Trd (i) of the pixel in the i-th row and the readout period Trd (i + 1) of the pixel in the i + 1th row. ing. The readout phase of the portion other than the shutter phase is the same as the readout phase described above.

Further, since the frames processed in the shutter phase are different between the odd frame and the even frame, the case of the odd frame will be described first, and then the case of the even frame will be described.

First, in the period from time t15 to time t16, the drive signal V _SwO and the drive signal V _RT are set to the high level, and the output switch transistor SwO and the reset transistor RT are turned on to reset the charge accumulated in the light receiving element PD. It is drained to the drain of RT.

Next, in the period from time t17 to time t18, the drive signal V _SwR1 (i) is kept high while the drive signal V _SwO is high, and the capacitance switch transistor SwR1 is turned on, so that the source of the first amplification transistor SF1 is turned on. When the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, the voltage of the capacitor CmR1 becomes a substantially stable voltage VsigR, which causes a reset. It corresponds to a signal. A period from the end of the writing of the reset signal to the capacitor SwR1 at time t18 in the shutter phase to the end of the period T2 in the next writing phase and the turning off of the capacitive switch transistor SwS is an effective exposure accumulation period Tint. The voltage due to the signal charge stored in the light receiving element PD in this period is written to the capacitor SwS in the next write phase. The length of the exposure accumulation period Tint can be changed by changing the time to set the shutter phase in the read phase.

On the other hand, when the frame to be processed is an even frame, the only difference is that the reset signal is written to the capacitor CmR2 compared to when the frame to be processed is an odd frame. That is, during the period from time t17 as described above until time 18, the driving signal _{V SWR1} (i) is changed to a drive signal _{V SWR2} (i), to change the volume switch transistor SWR1 to the capacitor switching transistor SWR2, volume capacity CmR1 If it changes to CmR2, it becomes operation at the time of an even frame.

Next, the write phase will be described. The write phase described here is different from the write phase when the above-described shutter operation is not performed, in that the reset signal is not written to the capacitor. In the write phase, an operation is performed in which all the pixels of the pixel array A40 simultaneously write the signal charge accumulated in the light receiving element PD as a light signal in the capacitor CmS.

First, at time t1, the drive signal V _SwO is set to the high level, and the output switch transistor SwO is turned on. Next, in a period T2 from time t2, the drive signal V _SwS is set to the high level, the capacitance switch transistor SwS is turned on, and a charge current flows from the source of the first amplification transistor SF1 to the capacitance CmS, and the capacitance CmS is Be charged. When the first amplification transistor SF1 shifts from the operation in the saturation region to the operation in the subthreshold region, the voltage of the capacitor CmS becomes a substantially stable voltage VsigS, and the voltage VsigS corresponds to an optical signal.

The optical signal written to the capacitor CmS in the above-described write operation discharges the signal charge accumulated in the light receiving element PD to the power supply in the shutter phase in the reading phase one frame before to the signal charge accumulated in the light receiving element PD. Equivalent to. Therefore, the light signal of the odd frame has noise correlation with the reset signal of the even frame one frame before, and the light signal of the even frame has noise correlation with the reset signal of the odd frame one frame before.

FIG. 15 is a timing chart showing the shutter operation in two frame periods of the two-dimensional image sensor provided with the pixel array having the pixel 40 of FIG. The timing chart of FIG. 15 shows the write operation and the read operation for the capacitances CmS, CmR1, and CmR2 in two frame periods of a frame period for processing an odd frame and a frame period for processing an even frame. The same reference numerals are attached to the times and periods indicating the same times and periods as in 14.

First, an optical signal is written to the capacitor CmS in the write phase of the odd frame. Next, in the read phase of the odd frame, the reset signal written to the capacitor CmR2 in the write operation one frame before and the optical signal written to the capacitor CmS are read, and all pixels are collectively operated at a specific time during the read phase. The reset signal that resets the light receiving element PD is written to the capacitor CmR1. Next, in the write phase of the even frame, the optical signal is written to the capacitor CmS. Next, in the read phase of the even frame, the reset signal written to the capacitor CmR1 in the write operation one frame before and the optical signal written to the capacitor CmS are read, and the reset signal that resets the light receiving element PD is sent to the capacitor CmR2. Write. Therefore, the reset signal and the light signal read out from the pixel 40 form a noise correlated pair. At this time, the exposure accumulation time (Tint) is a period after the reset signal is written to the capacitor CmR1 and after the light signal is written to the capacitor CmS.

As described above, according to the fourth embodiment, one PN light receiving element PD, nine transistors RT, SF1, SwO, SwR1, SwR2, SwS, IT, SF2, SL, and 3 in one pixel. A two-dimensional image sensor capable of batch exposure and obtaining high image quality by the CDS process can be configured only by using two capacitors CmR1, CmR2, and CmS. Further, when the reset signal and the optical signal are written in the capacitors CmR1, CmR2 and CmS, respectively, only a transient charging current flows in the capacitors CmR1, CmR2 and CmS, and a large DC current does not flow. Furthermore, when the reset signal and the optical signal are read out from the capacitors CmR1, CmR2 and CmS, respectively, the voltage representing the signal does not decrease, so the S / N ratio can be improved.

In the fourth embodiment, the selection transistor SL is provided to configure the pixel 40. However, the present invention is not limited to this, and the pixel 40 is configured without the selection transistor SL as in the second embodiment. In this case, the number of transistors in the pixel 40 is eight, and the circuit can be miniaturized to increase the area of the light receiving element PD.

Fifth Embodiment
FIG. 16 is a circuit diagram showing a configuration of a pixel 50 of an amplification type solid state imaging device according to a fifth embodiment of the present invention. As shown in FIG. 1, the pixel 10 includes a light receiving element PD formed of an embedded light receiving element, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a first signal line sig1, and a capacitance 16 is configured to include CmR and CmS, capacitance switch transistors SwR and SwS, an initialization transistor IT, a second amplification transistor SF2, a selection transistor SL, and a second signal line sig2. A pixel 50 shown is characterized in that capacitors CmS1 and CmS2 and capacitor switch transistors SwS1 and SwS2 are provided instead of the capacitor CmS and the capacitor switch transistor SwS which constitute the pixel 10 shown in FIG.

FIG. 17 is a timing chart showing the write operation of the two-dimensional image sensor of FIG. Note that all the pixels operate at once as in the embodiment described above in the writing operation. Hereinafter, the operation of the circuit of FIG. 16 will be described with reference to FIG.

In FIG. 17, in a period Tw0 from time tw0, the drive signal V _TX is fixed to the high level V _{TX (H)} , and the transfer transistor TX is turned on. Thus, the PD is reset by transferring the charge from the light receiving element PD to the floating diffusion region FD, and the charge generated by the incident light thereafter is accumulated in the PD.

Next, in a period Tw1 from time tw1, the drive signal V _RT is set to the high level V _{RT (H)} , and the reset transistor RT is turned on. At this time, since the drive signal Vrd is at the high level, a high level signal is input to the gate voltage of the first amplification transistor SF1 through the floating diffusion region FD, and thus the first amplification transistor SF1 is turned on. It will be

Next, in a period Tw2 from time tw2, the drive signal V _SwR (i) is fixed at the high level, and the capacitive switch transistor SwR is turned on to set the potential of the floating diffusion region FD to the capacitance via the first amplification transistor SF1. Written to CmR.

Next, in period Tw3 from time tw3, the drive signal V _TX is fixed at the high level V _{TX (H)} to turn on the transfer transistor TX, and during the period Tint1 (hereinafter referred to as a long exposure period). The charge accumulated in the light receiving element PD is transferred (first charge transfer operation). At this time, the gate voltage _{V RT} of the reset transistor RT is a high level _{V RT (H)} and an intermediate middle level _{V RT} of a low level _{_{V RT (L) (M)}} . That is, V _{RT (H)} <V _{RT (M)} <V _{RT (L)} . After charge transfer, the gate voltage V _RT of the reset transistor RT is held at the low level V _{RT (L)} . The end of the period Tw3 is the start of the period Tint2 (hereinafter, referred to as a short exposure period). Here, middle level V _{RT (M)} may be a potential in the range between high level V _{RT (H)} and low level V _{RT (L)} , for example, high level V _{RT (H)} A value of 90% to 10% may be set as the middle level V _{RT (M)} .

Next, in a period Tw4 from time tw4 after the transfer transistor TX is turned off, the drive signal V _SwS1 (i) is fixed at the high level to turn on the capacitance switch transistor SwS1, thereby the first transferred charge The potential of the floating diffusion region FD resulting from the above is written to the capacitor CmS1 via the first amplification transistor SF1.

Next, in period Tw5 from time tw5, drive signal V _TX is fixed at high level V _{TX (H)} , and transfer transistor TX is turned on to transfer the charge accumulated in PD during period Tint2 (second time Charge transfer operation). During this time, the gate voltage of the reset transistor RT is at the low level V _{RT (L)} .

Next, in a period Tw6 from time tw6 after the transfer transistor TX is turned off, the drive signal V _SwS1 (i) is fixed at the high level to turn on the capacitance switch transistor SwS1, thereby the charge transferred for the second time The potential of the floating diffusion region FD resulting from the above is written to the capacitor CmS2 via the first amplification transistor SF1.

Finally, in a period Tw7 from time tw7, the reset transistor RT is turned on in a state where the drain voltage Vrd of the reset transistor RT is at a low level, and the potential of the floating diffusion region FD is reset to a low level. The amplification transistor SF1 is turned off.

Next, the signal read operation will be described.

FIG. 18 is a timing chart showing the read operation of the amplification type solid-state imaging device of FIG.

In FIG. 18, first, in period Tr0 from time tr0, drive signal V.sub.IT _(i) is fixed at high level to turn on initialization transistor IT (i) to reset the gate of second amplification transistor SF2 to voltage Vs. Do. Then, after the drive signal _{V SL (i)} is turned on a fixed selection transistor SL (i) to the high level, the reset signal recorded by turning on the capacitance switching transistor SWR (i) the capacitance CmR (i) first The signal applied to the gate of the second amplification transistor SF2 as a gate voltage and the signal amplified by the second amplification transistor SF2 is read out to the signal line sig2.

In the period Tr1 in the second half of time tr1 of the ON period of the capacitor switching transistor SWR (i), the driving signal _{V IT (i)} are fixed to the high level to turn on the initialization transistor IT (i), capacity CmR (i) To make the next frame recordable. Next, the drive signal V _{SwS1 (i)} is fixed at high level, the capacitance switch transistor SwS1 (i) is turned on, and the long exposure signal recorded in the capacitor CmS1 (i) is gate voltage to the gate of the second amplification transistor SF2. The signal amplified by the second amplification transistor SF2 is read out to the signal line sig2.

In period Tr2 from time tr2 of the second half of the on period of capacitive switch transistor SwS1 (i), drive signal V _{SwS1 (i)} is fixed at high level, and capacitive switch transistor SwS1 remains in the on state, and drive signal V _{IT (i )} Is fixed at high level to turn on the initialization transistor IT (i), initialize the capacitance CmS1 (i), and make the next frame ready for recording. Likewise, the capacitive switch transistor SwS2 (i) is turned on to apply the short exposure signal recorded in the capacitor CmS2 (i) to the gate of the second amplification transistor SF2 as a gate voltage, and the second amplification transistor SF2 The amplified signal is read out to the signal line sig2.

Further, in the period Tr3 in the second half of time tr3 similarly capacity switching transistor SWs2 (i) on-period, the drive signal _{V SwS2 (i)} is still the driving signal _{V IT} capacity switching transistors SWs2 is fixed to the high level is turned on _(I) is fixed at the high level, the initialization transistor IT is turned on, and the voltage V _CmR (i) related to the capacitance CmS2 (i) is initialized to the voltage Vs. Then, recording is made possible in the next frame. The select transistor SL (i) is turned off before (or after) the time tr3, and the read operation of the i-th row is finished.

The reason for controlling the gate voltage V _RT of the reset transistor RT at the low level, the middle level, and the high level as described above will be described below.

FIG. 19 is a potential diagram schematically showing signal charges generated in the light receiving element by incident light, gate potentials of the transfer transistor and the reset transistor, and potential of the floating diffusion region in the amplification type solid-state imaging device of FIG. In FIG. 19, V _{TX (L)} and V _{TX (H)} indicate that the gate potential V _TX of the transfer transistor _TX is low level and high level, respectively, and V _{RT (L)} , V _{RT (M)} and V _{RT (H)} is the gate voltage _{V RT} is low level and reset transistor RT, indicating that middle level is a high level.

In FIG. 19, first, the gate potential V _RT of the reset transistor RT is set to the high level to reset the potential of the floating diffusion region FD to the power supply Vdd, and then the gate potential V _RT of the reset transistor RT is set to the middle level V _{RT (M).} the gate potential _{V TX} of the transfer transistor TX and the high level _{V TX (H)} to transfer long accumulated charges to the floating diffusion region FD. When the charge amount of incident light is increased transfer increases, plateau state charge amount Q1 constant value excess charge overflows from the reset transistor RT for resetting the gate potential of the transistor RT V _RT is middle level V _{RT (M)} It becomes.

Then, the gate potential _{V RT} of the reset transistor RT and the low level _{V RT _(L),} when the _{_{V TX (H) <V RT}} (L), the maximum amount of charge that can be accumulated in the floating diffusion region FD section reset transistor RT The amount of charge (Q1 + Q2) defined by V _{RT (L)} , which is a low level of the gate potential V _RT , is increased. In this state, by setting the gate potential V _TX of the second transfer transistor TX to the high level V _{TX (H)} , the stored charge for a short time is transferred to the floating diffusion region FD. Therefore, the accumulated charge for a short time is added to the long-term accumulated charge equal to or less than the charge amount Q1. If the charge amount of the PD section exceeds Q1 + Q2, since V _{RT (} _H) <V _{RT (L)} causes RT to overflow from a low level, backflow to the PD side is prevented and an afterimage does not occur. .

FIG. 20 is a graph showing the signal charge amount with respect to the accumulation time showing the wide dynamic range operation in which the maximum allowable incident light amount is expanded in the amplification type solid-state imaging device of FIG. Here, the horizontal axis represents the accumulation time, and the vertical axis represents the signal charge amount. The long time accumulation period is T _L , the short time accumulation period is T _S, and each of the lines 80 to 83 has the gate potential V _{RT of the} reset transistor _RT. Indicates the amount of charge that can be accumulated in the floating diffusion region FD when the middle level V _{TX (M)} is set. Here, as the amount of light incident on the light receiving element PD increases, the

lines

80, 81, 82, 83 change in order.

In FIG. 20, as shown by the short broken line 80, while the incident light quantity is small, the accumulated charge does not reach a peak with the charge quantity Q1 for a long time, and a signal with high sensitivity and maintained linearity can be read out. On the other hand, as shown by the

lines

81, 82, and 83, when the incident light amount increases, the accumulated charge for a long time becomes flat with the charge amount Q1, but the low sensitivity stored charge for a short time accumulates up to the charge amount Q2 It is possible to store up to which time the signal with maintained linearity is read out. By combining these two types of signals, it becomes possible to perform a wide dynamic range operation in which the maximum allowable incident light amount is expanded.

Another advantage of this operation is that both the long-time accumulation mode optical signal and the short-time accumulation mode optical signal can perform correlated double sampling (CDS) operation and suppress reset noise to realize low noise. is there. First, for the optical signal in the long-time accumulation mode, the voltage V _R after resetting the potential of the floating diffusion region FD to V _dd by setting the gate potential V _RT of the reset transistor RT to the high level V _{RT (H) first} Since the voltage V _S1 generated by the signal charge in the long-time accumulation mode after the first charge transfer performed immediately after the first charge transfer recorded in CmR is recorded in the capacitor Cm _S1 , the CDS circuit is read after reading each signal voltage. If the differential voltage (V _S1 -V _R ) between the two is taken at 17a, it is possible to obtain an optical signal in a long-time accumulation mode in which the reset noise common to both is removed. Similarly, for the optical signal of the short-time accumulation mode, charges due to the amount of incident light of the short-time accumulation mode, the voltage V _S1 of the floating diffusion region FD portion before storage start due to the incidence of the short-time accumulation mode is recorded in the volume CmS1 Since the voltage V _S2 generated by the signal charge in the short-time accumulation mode after the second charge transfer is recorded in the capacitor Cm _S2 , the differential voltage between both of them in the CDS circuit 17 a is read after each signal voltage is read. By taking V _S2 −V _S1 ), it is possible to obtain an optical signal in a short-time accumulation mode in which the reset noise common to both is removed.

The method of obtaining the wide dynamic range signal S _WD based on the above idea will be described below. Here, the ratio of the long time exposure period Tint1 to the short time exposure period Tint2 is Tint1 / Tint2 = K. The signals obtained by the two CDS operations are respectively S1 = V _S1 −V _R and S2 = V _S2 −V _S1 . When the S1, corresponding to the charge amount Q1 and S1 _0, represented by the following equation wide dynamic range signal _{S WD} (3).

The above equation (3) selectively outputs the difference voltage S1 and the multiplication value (K × S2) according to the light amount of the received light by the CDS circuit 17a and outputs it as an optical signal. It shows. By this selective switching, it is possible to obtain a wide dynamic range signal in which the linearity is maintained in a wide light amount range from a region where the light amount is small to a large region.

In addition, the dynamic range expansion ratio M is smaller than that in the normal operation in which the charge amount (Q1 + Q2) is a full range and the time (Tint1 + Tint2) obtained by adding the long exposure period and the short exposure period is a single accumulation time. Assuming that the amount Q1 = the amount of charge Q2, it is represented by the following equation (4).

Therefore, when the ratio K between the long exposure period Tint1 and the short exposure period Tint2 is 199, the dynamic range expansion ratio M is 100.

The charge amount Q1, which is the long-term accumulated signal ceiling level shown in FIG. 19 and FIG. 20, varies somewhat for each pixel, and there is a possibility that fixed pattern noise may occur if Equation (1) is used as S1 common to the entire screen.

FIG. 21 is a graph showing an amount of signal charge with respect to an accumulation time showing a wide dynamic range operation in which fixed pattern noise is eliminated in the amplification type solid-state imaging device of FIG. Here, the horizontal axis represents the accumulation time, and the vertical axis represents the signal charge amount. The long time accumulation period is T _L , the short time accumulation period is T _S, and lines 85 and 86 indicate the gate potential V _RT of the reset transistor _RT at the middle level. This represents the amount of charge that can be accumulated in the floating diffusion region FD in the case of V _{TX (M)} . Here, the solid line 85 shows an example at a certain light amount when the variation of the charge amount Q1 is maximum, and the dashed dotted line 86 shows an example at another light amount when the variation of the charge amount Q1 is minimum. A long broken line 87 represents a level at which the signal charge amount S1 is clipped to a constant value.

In FIG. 21, in order to avoid fixed pattern noise, the upper limit value of the Si signal is set to the potential V _CL by clipping the S1 signal to the potential V _CL smaller by the margin value Δq than the minimum value of the variation range ΔQ for all pixels. . Thereby, a wide dynamic range image signal without fixed pattern noise can be obtained. Here, the margin value Δq may be zero, but for example, it is preferable to set a so-called slight difference margin value Δq which is 5% to 10% of V _CL .

FIG. 22 is a circuit diagram showing a configuration of a pixel 60 of an amplification type solid-state imaging device according to a first modified example of the fifth embodiment of the present invention. In FIG. 16, the signal is read out from each capacitance and capacitance switch to the second signal line sig2 by the second amplification transistor SF2 via the selection transistor SL, but similarly to FIG. May be read out. This case is shown in FIG. As shown in FIG. 1, the pixel 10 includes a light receiving element PD formed of an embedded light receiving element, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a first signal line sig1, and a capacitance The configuration includes CmR and CmS, capacitance switch transistors SwR and SwS, an initialization transistor IT, a second amplification transistor SF2, a selection transistor SL, and a second signal line sig2. The pixel 60 shown is characterized by including capacitors CmS1 and CmS2 and capacitor switch transistors SwS1 and SwS2 instead of the capacitor CmS and the capacitor switch transistor SwS which constitute the pixel 10 shown in FIG. 1, and not including the selection transistor SL. Furthermore, in FIG. 22, the voltage Vs is characterized in that it is set to a voltage value at which the second amplification transistor SF2 is turned off.

The configuration of a two-dimensional image sensor including a pixel array in which the pixels 60 are arranged in a matrix is the same as that in which the pixels 10 in FIG. Furthermore, the timing chart showing the operation of the two-dimensional image sensor provided with the pixel array having the pixels 60 is the same as that of the timing chart of FIG. 18 except that the drive signal V _{SL (i)} for the selection transistor .

FIG. 23 is a circuit diagram showing a configuration of a pixel 70 of an amplification type solid-state imaging device according to a second modified example of the fifth embodiment of the present invention. In FIG. 16, as a method of turning off the gate signal of the first amplification transistor SF1 when reading out a signal from each capacitor, the floating diffusion region FD potential is reset to a low level as in FIG. The output switch SwO may be used for the first signal line sig1. This case is shown in FIG. As shown in FIG. 1, the pixel 10 includes a light receiving element PD formed of an embedded light receiving element, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a first signal line sig1, and a capacitance The configuration includes CmR and CmS, capacitance switch transistors SwR and SwS, an initialization transistor IT, a second amplification transistor SF2, a selection transistor SL, and a second signal line sig2. The pixel 60 shown includes the capacitors CmS1 and CmS2 and the capacitor switch transistors SwS1 and SwS2 instead of the capacitor CmS and the capacitor switch transistor SwS that constitute the pixel 10 shown in FIG. 1, and further, the source of the first amplification transistor SF1 and the first With the output switch SwO between the signal line sig1 of Characterized in that the common in-voltage power supply voltage Vdd.

FIG. 24 shows high level V _{RT (H)} and low level V _{RT (L)} of the gate voltage V _RT of the reset transistor RT and middle level V _{RT (M)} between them in the amplification type solid-state imaging device of FIG. Is a timing chart showing the operation in the case of three levels. 17 differs from FIG. 17 in that the output switch SwO is turned on in the write operation period, and the output switch SwO is turned off in the read period. Therefore, in period Tw7 from time tw7 in FIG. 17, the reset transistor RT is turned on in a state where the drain voltage Vrd of the reset transistor RT is at the low level, and the potential of the floating diffusion region FD is reset to the low level. The operation of turning off the first amplification transistor SF1 is omitted. Other than that, the operation in FIG. 17 is similarly applicable.

FIG. 25 is a timing chart showing an operation in the case where the gate voltage V _RT of the reset transistor RT is set to two levels of high level V _{RT (H)} and low level V _{RT (L)} in the amplification type solid-state imaging device of FIG. It is a chart. The portions corresponding to FIG. 24 are indicated by the same symbols. The difference from FIG. 24 is that the reset transistor RT has two levels, that is, the high level V _{RT (H)} and the low level V _{RT (L)} , and from time tw8 newly added as a period Tw1 from time tw1. The high level V _{RT (H)} is totaled twice only in the period Tw8 of

In FIG. 25, the same operation is performed from time tw0 to tw2. That is, in a period Tw0 from time tw0, the drive signal V _TX is fixed to the high level V _{TX (H)} , and the transfer transistor TX is turned on. Thus, the charge is transferred from the light receiving element PD to the floating diffusion region FD to reset the light receiving element PD, and the charge generated by the incident light thereafter is accumulated in the light receiving element PD.

Next, in a period Tw1 from time tw1, the drive signal V _RT is set to the high level V _{RT (H)} , and the reset transistor RT is turned on. Therefore, the floating diffusion region FD after the period Tw1 is at the reset level.

Next, in a period Tw2 from time tw2, the drive signal V _{SwR (i)} is fixed at the high level and the capacitance switch transistor SwR is turned on, whereby a voltage corresponding to the reset level of the floating diffusion region FD is written to the capacitance CmR.

Next, since the gate voltage V _RT of the reset transistor _RT is at the low level V _{RT (L) in the} first transfer operation period in which the long-time accumulation signal is read in the period Tw3 to the period Tw3, the maximum allowable signal charge amount is expanded to Q1 + Q2. Do. However, since the floating diffusion region FD has no room to receive any more charge, the floating diffusion region FD is reset again in a period Tw8 from time tw8. Thereafter, the short-time accumulation signal is read out by the second transfer operation in the period Tw5 from the time tw5.

The CDS operation in this case is performed as follows. First, for the optical signal in the long-time accumulation mode, at the time of the first reset operation, that is, after resetting the potential of the floating diffusion region FD to V _dd with the gate potential V _RT of the reset transistor _RT as the high level V _{RT (H).} Voltage V _R is recorded in the capacitance C m _R , and the voltage V _S1 generated by the signal charge in the long-term accumulation mode after the first charge transfer performed immediately after is recorded in the capacitance C m _{S 1} . After that, if the differential voltage (V _S1 -V _R ) between the two is taken in the CDS circuit 17a, it is possible to obtain a long time accumulation signal from which the reset noise common to both is removed. On the other hand, for the short-time accumulation signal, the reset level of the floating diffusion area FD before the start of accumulation is not read, so the short-time accumulation mode after the second charge transfer recorded in the capacitor CmS2 in the CDS circuit 17a. The differential voltage (V _S2 −V _R ) between the voltage V _S2 generated by the signal charge in V and the voltage V _R at the time of the first reset operation is taken to perform the CDS operation in a pseudo manner. In this case, although the offset variation which fluctuates for each pixel is removed, the reset noise remains. Using these two signals, a wide dynamic range signal is obtained by the same signal processing as described above. In the case of this method, compared to the methods described in FIG. 16 to FIG. 24, the handling charge amount is doubled.

As described above, according to the fifth embodiment, the following features can be newly provided. That is,
(1) The simultaneous exposure (global shutter) operation and the wide dynamic range operation can be performed simultaneously.
(2) In this wide dynamic range operation, it is possible to operate continuously for each frame, and is also applicable to moving pictures.
(3) In the wide dynamic range operation, all the signals necessary for the wide dynamic range operation can be obtained simultaneously without the frame memory.
(4) Further, except in the case of FIG. 25, both the long time accumulation signal and the short time accumulation signal can be reset noise free, and a wide dynamic range signal having a high SN ratio can be obtained.

In the first to fifth embodiments, each transistor in a pixel is an N-channel MOS field effect transistor. However, this is an example, and the present invention is not limited to this. Also in the case of a channel MOS field effect transistor, it is possible to configure a pixel that operates in the same manner by reversing the polarity of voltage and current. Although the case where the signal charge of the light receiving element PD is an electron has been described, even in the case where the signal charge is a hole, the polarity change due to signal accumulation is only reversed, and a pixel operating in the same manner is configured. Can.

As described above in detail, according to the amplification type solid-state imaging device according to the present invention, since the pixel does not have a constant current load and writing and reading are performed by a common switch, the number of transistors in the pixel is reduced. can do. In order to perform the write operation to the plurality of capacitors serving as the load of the first amplification transistor, the plurality of capacitors are first initialized to a predetermined voltage, for example, a ground voltage or a positive voltage close thereto, and then the plurality of capacitors A stable operation can be performed by performing the write operation by the charge current to the capacitor and controlling the selection of the specific capacitor and the write time by the capacitor switch. Further, at the time of reading from the plurality of capacitors, a voltage at which the transistor is deactivated is applied to the gate of the first amplification transistor to turn it off, and selection and reading time of a particular capacitor are controlled by the capacitor switch. Thus, signals from the plurality of capacitors can be given to the gate of the second amplification transistor and read out to the outside of the pixel.

10, 20, 30, 40, 50, 60, 70, 100, 110, 120, 130 ... pixels,
A10 ... pixel array,
PD: light receiving element,
TX: transfer transistor,
RT: reset transistor,
SF1 first amplification transistor,
SF2 second amplification transistor
IT: Initialization transistor,
SwR, SwS, SwS1, SwS2, SwR1, SwR2: Capacitance switch transistors,
SwO ... output switch transistor,
CmR, CmS, CmS1, CmS2, CmR1, CmR2 ... capacity,
sig1 ... first signal line,
sig2 ... second signal line,
CL: Constant current load transistor,
11 ... Power supply line,
14 row decoder circuit,
15 row drive circuit,
16 ... drive line,
17: Column signal processing circuit,
17a ... CDS circuit,
18: Column decoder circuit,
19: Horizontal signal line.

Claims

A pixel array configured by arranging a plurality of pixels having a plurality of capacities in a matrix;
An amplification type solid-state imaging device comprising: a control circuit for performing operation control on each pixel constituting the pixel array;
Each pixel is
A photoelectric conversion unit that generates and outputs a signal according to the received light;
A first amplification transistor that amplifies and outputs a signal input from the photoelectric conversion unit to a gate;
A reset transistor that resets a gate voltage of the first amplification transistor;
A plurality of capacitors for holding a signal output from the first amplification transistor to the first signal line;
Respective capacitances provided corresponding to the plurality of capacitances and provided between the first signal line and the plurality of capacitances and performing input / output control between the first signal line and the plurality of capacitances Multiple capacitive switches, one per unit,
A second amplification transistor that amplifies a signal input from the first signal line to the gate and outputs the amplified signal to a second signal line;
An amplification type solid-state imaging device comprising: an initialization transistor connected to the first signal line and outputting a predetermined first voltage to the first signal line.
The control circuit
(1) The plurality of capacitors are initialized to the first voltage by turning on the initialization transistor and turning on the plurality of capacitance switches.
(2) By sequentially turning on the plurality of capacitance switches corresponding to the plurality of capacitances, capacitance switches corresponding to the first signal line and the capacitance to be written are the amplified signals from the first amplification transistor. Perform a write operation to sequentially write to the capacity via
(3) By sequentially turning on the plurality of capacitance switches corresponding to the plurality of capacitances, the capacitance switch corresponding to the capacitance to be read out, the signal written to each of the capacitances, the first signal line, and 2. The amplification type solid-state imaging device according to claim 1, wherein a readout operation for sequentially reading out the second signal line is performed via a second amplification transistor.
The control circuit performs the write operation simultaneously on all the pixels forming the pixel array in a period in which the first amplification transistor shifts from a saturation region operation to a subthreshold region operation and enters a metastable state. The amplification type solid-state imaging device according to claim 1 or 2, wherein
The signal input to the gate of the first amplification transistor includes a reset signal,
The control circuit applies a second voltage at which the first amplification transistor is turned on to the drain of the reset transistor to turn on the reset transistor, thereby the reset transistor corresponding to the second voltage. A source voltage of the first amplification transistor is applied to the gate of the first amplification transistor to output a reset signal corresponding to the second voltage to the first signal line, and then the first amplification transistor is turned off. Performing the write operation to apply the third voltage to the gate of the first amplification transistor by applying a voltage of 3 to the drain of the reset transistor and turning on the reset transistor. The amplification type solid-state imaging device according to any one of claims 1 to 3, characterized in that
The signal input to the gate of the first amplification transistor includes a reset signal,
The pixel further includes an output switch provided between the first amplification transistor and a first signal line.
The control circuit applies a second voltage that turns on the first amplification transistor to the gate of the first amplification transistor by turning on the reset transistor, and turns on the output switch. 4. The method according to claim 1, wherein the write operation is performed so as to turn off the output switch after outputting the reset signal corresponding to the second voltage to the first signal line. The amplification type solid-state imaging device according to any one of the above.
The signal input to the gate of the first amplification transistor includes an optical signal,
The pixel further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The plurality of capacitors include a first capacitor for holding the reset signal and a second capacitor for holding the optical signal,
The control circuit applies the light signal from the photoelectric conversion unit to the gate of the first amplification transistor by writing the reset signal to the first capacitor and then turning on the transfer transistor. 5. The amplification type solid-state imaging device according to claim 4, wherein the writing operation is performed so as to write the light signal to the second capacitor.
The signal input to the gate of the first amplification transistor includes an optical signal,
The pixel further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The plurality of capacitors include a first capacitor for holding the reset signal and a second capacitor for holding the optical signal,
The control circuit turns on the output switch to write the reset signal to the first capacitor, and then turns on the transfer transistor to amplify the optical signal from the photoelectric conversion unit to the first amplification. After the light signal is applied to the gate of the transistor, the write operation is performed to output the light signal to the first signal line and to write the light signal to the second capacitor. The amplification type solid-state imaging device of description.
The signal input to the gate of the first amplification transistor includes an optical signal,
The photoelectric conversion unit is a PN light receiving element, and outputs a light signal according to the received light to the gate of the first amplification transistor,
The plurality of capacitors may be a third capacitor for holding the optical signal, a fourth capacitor for holding the reset signal when processing an odd-numbered frame, and the reset when processing an even-numbered frame. And a fifth capacitance for holding the signal,
The control circuit applies the light signal from the photoelectric conversion unit to the gate of the first amplification transistor by turning on the output switch to write the light signal to the third capacitance. The write operation is performed to write the reset signal to the fourth capacitor when processing odd-numbered frames and to write the reset signal to the fifth capacitor when processing even-numbered frames The amplification type solid-state imaging device according to claim 5, characterized in that:
The control circuit reads the light signal from the third capacitor and reads the reset signal from the fifth capacitor when processing an odd-numbered frame, and processes the even-numbered frame. 9. The amplification type solid-state imaging device according to claim 8, wherein the read operation is performed so as to read an optical signal from the third capacitor and read the reset signal from the fourth capacitor.
The control circuit executes the read operation so as to sequentially read the reset signal and the light signal for each row of the pixel array,
In the read operation, the second voltage is applied to the drain of the reset transistor between the read operation of the first row and the read operation of the second row next to the first row, After the light signal from the photoelectric conversion unit is discharged to the drain of the reset transistor by turning on the transfer transistor and the reset transistor, the transfer transistor is turned off, and the reset transistor is turned on. 7. The amplification type solid-state imaging device according to claim 6, wherein a voltage of V is applied to a drain of the reset transistor to control the reset transistor to turn off.
The control circuit executes the read operation so as to sequentially read the reset signal and the light signal for each row of the pixel array,
In the read operation, the photoelectric conversion is performed by turning on the transfer transistor and the reset transistor between the read operation of the first row and the read operation of the second row next to the first row. 8. The amplification type solid-state imaging according to claim 7, wherein after the light signal from the conversion unit is discharged to the drain of the reset transistor, the transfer transistor is turned off and the reset transistor is turned off. apparatus.
The control circuit executes the read operation so as to sequentially read the reset signal and the light signal for each row of the pixel array,
In the read operation, the photoelectric conversion is performed by turning on the output switch and the reset transistor between the read operation of the first row and the read operation of the second row next to the first row. After the light signal from the conversion unit is discharged to the drain of the reset transistor, the reset transistor is turned off, and when processing an odd-numbered frame, the reset signal is written to the fourth capacitor, and the even-numbered 10. The amplification type solid-state imaging device according to claim 8, wherein the reset signal is written to the fifth capacity when processing a frame, and the output switch is controlled to be turned off.
The control circuit executes the read operation so as to sequentially read the reset signal and the light signal for each row of the pixel array,
In the read operation, the gate of the second amplification transistor is set to a fourth voltage at which the second amplification transistor is turned off by turning on the initialization transistor in each pixel in a row where readout is not performed. The amplification type solid-state imaging device according to any one of claims 1 to 12, which is controlled to be initialized.
The pixel further includes a selection transistor provided between the second amplification transistor and the second signal line.
13. The device according to claim 1, wherein the control circuit performs control to output an optical signal or reset signal held in the capacitor to the second signal line by turning on the selection transistor. One of them is an amplification type solid state imaging device.
The signal input to the gate of the first amplification transistor includes a reset signal,
Each of the pixels further includes a transfer transistor provided between the photoelectric conversion unit and the gate of the first amplification transistor.
The photoelectric conversion unit is an embedded light receiving element, and outputs an optical signal according to the received light to the gate of the first amplification transistor via the transfer transistor.
The control circuit controls the off time of the transfer transistor such that the accumulation time of the photoelectric conversion unit has two modes of a long time accumulation mode and a short time accumulation mode within one frame period,
The plurality of capacitors are a sixth capacitor for holding the reset signal, a seventh capacitor for holding the light signal in the long time accumulation mode, and an eighth capacitor for holding the light signal in the short time accumulation mode. The amplification type solid-state imaging device according to claim 1 or 2, further comprising:
The control circuit
(1) After setting the gate voltage of the reset transistor to a high level, the reset signal is written to the sixth capacitor,
(2) After setting the gate voltage of the reset transistor to a middle level lower than the high level, an optical signal of the long-time accumulation mode is written to the seventh capacitance.
(3) The write operation is performed by writing the light signal in the short time accumulation mode to the eighth capacitor after setting the gate voltage of the reset transistor to a low level lower than the middle level. The amplification type solid-state imaging device according to claim 15, characterized in that
The amplification type solid-state imaging device is
Correlated double that performs correlated double sampling based on the reset signal, the light signal of the long time accumulation mode, and the light signal of the short time accumulation mode, which are output from the pixel through the second signal line Equipped with a sampling circuit,
The correlated double sampling circuit is
(A) calculating a first differential voltage obtained by subtracting the reset signal from the light signal in the long-term accumulation mode in the first correlated double sampling operation;
(B) calculating a second differential voltage formed by subtracting the light signal of the long time accumulation mode from the light signal of the short time accumulation mode in the second correlated double sampling operation; Calculating a value of the ratio of the period of the long-term accumulation mode to the period of time, and calculating a multiplication value obtained by multiplying the second differential voltage by the value of the ratio;
(C) The amplification type solid-state imaging according to claim 16, wherein the first differential voltage and the multiplication value are selectively switched according to the light amount of the received light and output as an optical signal. apparatus.
The control circuit
(1) After setting the gate voltage of the reset transistor to a high level, the reset signal is written to the sixth capacitor,
(2) After setting the gate voltage of the reset transistor to a low level lower than the high level, the optical signal in the long time accumulation mode is written to the seventh capacitor, and then the gate voltage of the reset transistor is Set to the high level,
(3) After setting the gate voltage of the reset transistor to the low level, the write operation is performed by writing an optical signal in the short time accumulation mode to the eighth capacitor. 15. The amplification type solid-state imaging device according to 15.
The amplification type solid-state imaging device is
A correlated double sampling circuit that performs correlated double sampling based on the reset signal and the light signal output from the pixel through the second signal line,
(A) calculating a first differential voltage obtained by subtracting the reset signal from the light signal in the long-term accumulation mode in the first correlated double sampling operation;
(B) calculating a third differential voltage obtained by subtracting the reset signal from the light signal in the short-time accumulation mode in the second correlated double sampling operation, and calculating the third difference voltage in the short-time accumulation mode Calculating a value of a ratio of a time accumulation mode period, and calculating a multiplication value obtained by multiplying the third difference voltage by the value of the ratio;
(C) The amplification type solid-state imaging according to claim 18, wherein the first differential voltage and the multiplication value are selectively switched according to the light amount of the received light and output as an optical signal. apparatus.
The upper limit value of the first differential voltage is set to be a minimum value of the variation range of the light signals in the long time accumulation mode of all the pixels or a value smaller than the minimum value by a predetermined margin value. The amplification type solid-state imaging device according to claim 17.