JP2020129759A - Signal processing circuit and solid state imaging device - Google Patents

Abstract

To provide a signal processing circuit capable of performing signal reading-out processing of a pixel having a different exposure time without requiring a complex scanning circuit, and provide a solid state imaging device.SOLUTION: In a signal processing circuit comprising: a pulse generation circuit that generates a pulse in response to a charging amount of a detection object; and a counter circuit that counts the pulse, a prescribed time for performing a detection operation of the charging amount is segmented into a plurality of periods, and an output signal of the counter circuit in each period to be segmented is integrally output after the termination of the prescribed time. In a solid state imaging device comprising the signal processing circuit that converts a signal charging obtained by performing a photo-electric conversion to analog/digital in each pixel, one frame period is segmented into one or a plurality of periods in each pixel, and the output signal in each period to be segmented is integrally output in each pixel after the termination of the one frame period.SELECTED DRAWING: Figure 1

Description

The present invention relates to a signal processing circuit and a solid-state image sensor, and more particularly, to a signal processing circuit that performs analog/digital (A/D) conversion of signal charges photoelectrically converted in each pixel of a solid-state image sensor (image sensor), and uses the same. The present invention relates to a solid-state image sensor.

Exposure time, readout speed, and phase can be controlled for each pixel for the purpose of high frame rate, wide dynamic range, and high S/N (Signal/Noise) of solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors. An image sensor that controls the spatiotemporal exposure has been proposed (Non-Patent Document 1). By shooting with different exposure times and phases for each pixel and performing signal processing for reconstruction, image noise and motion blur are removed, and high frame rate, wide dynamic range, high S/N images are obtained. can get.

Tomohiro Yamazaki et al., “Image Sensor with Spatio-Temporal Exposure Control Function and Imaging/Processing Method for Improving Image Quality”, Journal of Image Information and Media Engineers, (2015), Vol.69, No.3, pp.J106- J112

In the image sensor of Non-Patent Document 1, since the pixels are photographed with different exposure times/phases, the read timing differs for each pixel. Therefore, the row decoder, the column decoder, the row scanning control circuit, and the column scanning control circuit individually reset and read the pixels for each pixel, but the row/column scanning circuit (which is adopted in a normal image sensor) There is a problem that scanning of pixels is more complicated, a circuit scale of a decoder or the like becomes larger, and a reading time becomes longer than a method of sequentially reading pixel signals for each frame by a shift register). Further, the shorter the exposure time is, the larger the number of times the pixel needs to be read out, so the total number of pixels read out differs for each scan of the pixel array, and the signal processing for reconstruction becomes complicated.

Therefore, an object of the present invention made in view of the above problems is to provide a signal processing circuit and a solid-state imaging device capable of performing signal readout processing of pixels with different exposure times without requiring a complicated scanning circuit. Especially.

In order to solve the above problems, the signal processing circuit according to the present invention is a signal processing circuit including a pulse generation circuit that generates a pulse corresponding to the amount of charge to be detected, and a counter circuit that counts the pulse. The predetermined time for performing the charge amount detection operation is divided into a plurality of periods, and the output signals of the counter circuit in each divided period are collectively output after the end of the predetermined time. ..

Further, it is preferable that the signal processing circuit includes the counter circuit composed of a plurality of blocks including a plurality of bit counters, and selects the different blocks for each period to count the pulses.

Further, in the signal processing circuit, the counter circuit includes a plurality of blocks including a plurality of bit counters and a plurality of switches that select the blocks, and the switches are controlled by a control signal to operate in each period. It is desirable to select the block.

In order to solve the above problems, a solid-state image sensor according to the present invention is a solid-state image sensor including a photoelectric conversion element and the signal processing circuit in each pixel, and a predetermined value for performing the charge amount detection operation. The time is characterized by being one frame period.

In order to solve the above problems, a solid-state image sensor according to the present invention is a solid-state image sensor including a signal processing circuit that performs analog/digital conversion of photoelectrically converted signal charges on a pixel-by-pixel basis. Alternatively, it is characterized in that it is divided into a plurality of periods and the output signal of each divided period is collectively output for each pixel after the end of the one frame period.

Further, in the solid-state imaging device, each pixel includes a memory that stores a pattern of division of one frame period, and one frame period is divided into one or a plurality of periods based on the pattern stored in the memory. It is desirable to do.

Further, in the solid-state image pickup device, it is desirable that pixels having different patterns of division for one frame period are regularly arranged.

Further, in the solid-state imaging device, it is desirable that pixels having different patterns in one frame period are arranged aperiodically.

Further, the solid-state imaging device extracts a feature amount of a motion of an output image of the solid-state imaging device, the first pixel having a large motion divides one frame period into short periods, and the second pixel having a small motion. Preferably divides one frame period into a period longer than the first pixel.

Further, in the solid-state imaging device, it is preferable that the circuit elements forming each pixel are formed on different substrates and the substrates are three-dimensionally laminated.

According to the signal processing circuit and the solid-state imaging device of the present invention, it is possible to perform signal reading processing of pixels having different exposure times without requiring a complicated scanning circuit.

It is a figure which shows an example of the signal processing circuit of this invention. It is a timing chart of a photodiode voltage and a pulse output. It is a figure which shows an example of the counter circuit of a signal processing circuit. It is a figure which shows one Embodiment of an exposure time pattern. It is an example of a circuit diagram of a counter circuit of a pixel which is exposed for a long time (L). It is an example of a circuit diagram of a counter circuit of a pixel that performs medium-time exposure (M). It is an example of a circuit diagram of a counter circuit of a pixel that performs short-time exposure (S). It is a figure which shows an example of the solid-state image sensor of this invention. It is a figure which shows an example of a structure of switch control of a pixel. It is a figure which shows another example of a structure of switch control of a pixel. It is a figure which shows an example of the mounting structure of the solid-state image sensor of this invention. It is a figure which shows other embodiment of an exposure time pattern. It is a figure which shows the example which sets the exposure time pattern of each pixel adaptively.

Hereinafter, embodiments of the present invention will be described.

An example of the signal processing circuit of the present invention is shown in FIG. The signal processing circuit of FIG. 1 corresponds to one pixel of the solid-state image sensor, and constitutes a 1-bit A/D conversion circuit (1 bit ADC). The signal processing circuit of FIG. 1 and its operation will be described below.

The signal processing circuit of FIG. 1 includes a voltage detection node 11 of a photodiode (PD) 10, a reset transistor (T _R ) 20, an inverter circuit (inverter chain) 30, and a counter circuit 40. Among these, the voltage detection node 11, the reset transistor (T _R ) 20, and the inverter circuit 30 constitute a pulse generation circuit that generates a pulse corresponding to the amount of photoelectrically converted charge (the amount of charge to be detected). Hereinafter, each component will be described.

The photodiode (PD) 10 functions as a photoelectric conversion element, and the voltage detection node 11 changes its potential (V _PD ) due to the electric charge (or photocurrent) generated when light enters the photodiode 10. To do. Note that the voltage detection node 11 can use the electrode of the photodiode (PD) 10 as it is, but the electrode of the capacitor (not shown) for storing charge is used as the voltage detection node 11 and the photodiode ( The charge generated by the PD) 10 may be transferred to a capacitor for voltage detection. The voltage (V _PD ) at the voltage detection node 11 is input to the inverter circuit 30.

The reset transistor (T _R ) 20 is controlled by the output voltage (V _OUT ) of the inverter circuit 30 and is turned on (conducted) to apply the reset voltage (V _RST ) to the voltage detection node 11 (electrode of the photodiode 10). Apply. In this way, the reset transistor (T _R ) 20 functions as reset means.

The inverter circuit 30 is a multi-stage inverting circuit in which inverters (Inv1, Inv2,... Inv2n+1) that are inverting circuits are connected in odd stages. Each inverter is composed of, for example, a CMOS inverter. The potential V _PD of the voltage detection node 11 of the photodiode 10 is input to the first stage inverter (Inv1). The first stage of the inverter circuit (inverter chain) 30 may be a comparator instead of the inverter Inv1. The output of the inverter circuit 30 is input to the counter circuit 40 as the output (V _OUT ) of the pulse generation circuit and is also applied to the gate electrode of the reset transistor 20.

The counter circuit 40 counts the number of pulses of the output (V _OUT ) of the pulse generating circuit. Details of the counter circuit 40 will be described later. The counter circuit 40 of the present invention reads out the bit value determined for each frame period and is reset.

Next, the operation of the pulse generation circuit of the signal processing circuit of FIG. 1 will be described with reference to the photodiode voltage (voltage detection node voltage) and pulse output timing chart of FIG.

(1) The description will be given from the time when the reset of the photodiode 10 is released. That is, with the potential V _PD of the voltage detection node 11 of the photodiode 10 being reset (V _RST ), the input of the first stage inverter (Inv1) is High and the output is Low, and the output of the second stage inverter (Inv2) is output. Is High, the output of the final-stage inverter (Inv2n+1), that is, the output (V _OUT ) of the inverter circuit 30 is Low, and the reset transistor (T _R ) 20 is in the OFF state. This is the first state on the time axis of the timing chart of FIG. 2, and this is the initialized state.

(2) When light enters the photodiode 10, electrons generated by photoelectric conversion are accumulated in the photodiode 10 and the potential of the electrode (voltage detection node) 11 of the photodiode 10 is lowered.

(3) When the voltage (V _PD ) at the voltage detection node 11 of the photodiode 10 reaches the inversion threshold voltage (V _TH ) of the first-stage inverter (Inv1), the output of the inverter (Inv1) is inverted to High. The inverters are connected in an odd number of stages (2n+1 stages), the outputs are sequentially inverted and transmitted, and the output of the final stage inverter (Inv2n+1) (the output of the inverter circuit 30), that is, the output of the pulse generation circuit (V _OUT ) becomes High. The inverters are connected in 2n+1 stages instead of one stage in order to stabilize the circuit operation by utilizing the delay due to the inverters of a plurality of stages.

(4) When the output (V _OUT ) of the inverter circuit 30 becomes High, the reset transistor 20 is turned on (ON), the reset voltage (V _RST ) is applied to the electrode of the photodiode 10, and the photodiode 10 (and The voltage detection node 11) is reset again.

(5) When the photodiode 10 is reset, the input of the first stage inverter (Inv1) becomes High, the output (V _OUT ) of the inverter circuit becomes Low, and the process returns to (1). Thus, a pulse is generated at the output (V _OUT ).

(6) After that, the above (1) to (5) are repeated, and the output of the inverter circuit (inverter chain) 30 repeats High and Low. Therefore, the inverter circuit 30 (that is, the pulse generation circuit) repeatedly outputs pulses. When the amount of light incident on the photodiode 10 is large, the amount of photoelectrically converted charges is large, the potential change of the voltage detection node 11 of the photodiode 10 is fast, and the inversion timing of the inverter circuit 30 is fast. Therefore, during the exposure time of the image, a number of pulses proportional to the light quantity are generated at the output (V _OUT ) of the pulse generation circuit.

The counter circuit 40 counts (integrates) the pulses generated during the exposure time. The counter circuit 40 of the present invention can cope with various exposure times, and after the end of one frame period, all the output signals of the counter circuit 40 are read and the count is reset.

Thus, the analog/digital conversion circuit that outputs the pulse count value (bit value) proportional to the signal charge amount is configured. Since the signal processing circuit of the 1-bit A/D conversion circuit (1 bit ADC) performs A/D conversion in the immediate vicinity of the photodiode (PD), it is less susceptible to noise during signal transmission and can be input. Unlike the conventional solid-state image sensor, the light amount is not limited by the storage capacity of the photodiode (PD), so that the dynamic range can be expanded.

According to the present invention, since it is possible to capture images with different exposure times/phases for each pixel, the signal processing circuit (in particular, the counter circuit 40) of each pixel is operated corresponding to various exposure times. Further, the exposure time is variable.

FIG. 3 shows an example of the counter circuit 40 of the signal processing circuit. FIG. 3 shows the right side of the output terminal (V _OUT terminal) of the inverter circuit 30 of FIG. A plurality of 1-bit counters are connected, and 32 1-bit counters (counter 1 to counter 32) are used here. Each of the counters 1 to 32 counts the pulse and outputs each bit value. After passing through one counter, the number of pulses is halved, and they can be connected in series to form a maximum 32 bit counter circuit. The 1-bit counter can be composed of, for example, a flip-flop or the like.

In the present embodiment, the switches SW1 to SW7 are provided so as to divide the 32 counters into blocks of eight, that is, as blocks of the 8-bit counter. As will be described later, switches for changing the exposure time are provided. Control to turn on and off. The arrangement of the counters and the switches is an example, and the counter circuit 40 may further include counters in multiple stages according to the number of pulses generated in one frame period, and each of the blocks separated by switches ( The number of counters (constituting a plurality of bit counters) can be set appropriately.

By using the counter circuit 40 of FIG. 3, one frame period, that is, the predetermined time for performing the charge amount detection operation can be divided (divided) into a plurality of periods, and a long exposure (L), medium and It is possible to set three types of exposure time patterns of time exposure (M) and short time exposure (S).

FIG. 4 shows an embodiment of the exposure time pattern. In FIG. 4, the switch name that is turned on is shown as the switch state in each exposure time pattern. All switches not mentioned are turned off. Here, the frame period (for example, 1/30 second) is T. In the long-time exposure (L), the same switch state is set for the entire frame period, and one frame period is set as one section period (may be referred to as “one period section”). In the medium-time exposure (M), the switch state changes every half frame period, and one frame period is divided into two periods. In the short-time exposure (S), the switch state changes every 1/4 of the frame period, and one frame period is divided into four periods. In the present embodiment, the maximum number of divisions of the exposure time (that is, the number of blocks of the counter) is 4, but if the number of blocks is increased by increasing the number of counters or the number of switches, the types of patterns of exposure time also increase. To do.

The signal processing circuit of the present invention detects the signal charge by dividing (dividing) one frame period into a plurality of periods with various patterns, and outputs signals (bit value of each counter) of each divided period. ) Can be collectively read after the end of one frame period. That is, regardless of the pattern of the exposure time in one frame period, for example, 32 counter outputs of FIG. 3 are continuously output in 32 bits, or 32 counter outputs are used in parallel by using a plurality of signal read lines. Can be output continuously. As a result, it is possible to select pixels by the conventional XY scanning and read the output bits of the pixels collectively (collectively).

FIG. 5 is an example of a circuit diagram (connection state) of the counter circuit 40 of a pixel which is exposed for a long time (L). A 32-bit counter is configured by connecting 32 counters in series. The number of pulses generated in one frame period is counted to obtain a 32-bit signal. A 32-bit signal is output after the end of one frame period, and then the counter value is reset.

FIG. 6 is an example of a circuit diagram (connection state) of the counter circuit 40 of the pixel that performs medium-time exposure (M). FIG. 6A shows a state of the first half (0 to T/2) of one frame period, and FIG. 6B shows a state of the second half (T/2 to T) of the one frame period. In FIG. 6A, the counters 1 to 16 are connected in series to form a 16-bit counter, and the number of pulses generated in the first half (T/2) of one frame period is counted. Obtain a 16-bit signal. In FIG. 6B, the counters 17 to 32 are connected in series to form a 16-bit counter, and the number of pulses generated in the latter half (T/2) of one frame period is counted. A 16-bit signal is obtained. After the end of one frame period, a signal of 2×16 bits (32 bits in total) is output during the medium time exposure, and then the counter value is reset.

FIG. 7 is an example of a circuit diagram (connection state) of the counter circuit 40 of a pixel that performs short-time exposure (S). 7A shows the state of the first ¼ period (0 to T/4) of the frame period, and FIG. 7B shows the state of the next ¼ period (T/4 to T/2). In FIG. 7A, only the switch SW1 is turned on, and eight counters 1 to 8 are connected in series to form an 8-bit counter, which is 1/4 (T) of one frame period. The number of pulses generated in /4) is counted and an 8-bit signal is obtained. In FIG. 7B, only the switch SW2 is turned on, and eight counters 9 to 16 are connected in series to form an 8-bit counter, which is 1/4 (T) of one frame period. The number of pulses generated in /4) is counted and an 8-bit signal is obtained.

Although not shown, only the switch SW3 is turned on and the eight counters 17 to 24 are connected in series during the next ¼ period (T/2 to 3T/4), so that 8 bits of 8 bits are connected. A counter is formed and the number of pulses generated in 1/4 (T/4) of one frame period is counted to obtain an 8-bit signal. Similarly, in the next 1/4 period (3T/4 to T), only the switch SW4 is turned on, and eight counters 25 to 32 are connected in series to form an 8-bit counter. The number of pulses generated in 1/4 (T/4) of one frame period is counted to obtain an 8-bit signal. After the end of one frame period, signals of short exposure 4 times×8 bits (total of 32 bits) are collectively output, and then the counter value is reset.

That is, the counter circuit 40 of the signal processing circuit of the present invention includes a plurality of (four) blocks including a plurality of bit counters (8 bit counters) and a plurality of switches SW1 to SW7, and controls the switches with a control signal. A block that operates in each period obtained by dividing one frame period is selected. Further, the counter output is collectively output after the end of one frame period.

FIG. 8 shows an example of the solid-state image sensor of the present invention. The above-described signal processing circuit is used for each pixel 50 of the solid-state image sensor 100 of FIG. The symbols L, M, and S described in each pixel indicate the exposure time pattern described in FIG. Although various pixels having different exposure time patterns are regularly arranged in FIG. 8, this arrangement may be irregular.

A vertical shift register 60 and a horizontal shift register 70 for row/column scanning are arranged around the pixel array, and the counter value of each pixel is read by the XY address method after the end of one frame period. That is, the vertical shift register 60 sequentially scans the row scanning lines 61, outputs the bit output of the counter circuit 40 of each pixel 50 to the readout line 71 for each row, and then performs the column scanning by the horizontal shift register 70. The 32-bit output of each pixel 50 can be sequentially read. Note that the signal line for transmitting the output of each pixel 50 is shown as one line in the figure, but the output bit may be read in parallel by using a plurality of signal lines as necessary.

The subsequent reset of the counter value may be performed sequentially by the XY address method as in the reading, but may be reset simultaneously for all pixels without scanning. The latter reset method is preferable in order to avoid that the exposure time and the phase differ from pixel to pixel due to scanning.

As described above, in the solid-state imaging device of the present invention, the bit output of each pixel can be simultaneously read by using the same scanning circuit as the conventional one, although the exposure time is different for each pixel.

The pixel exposure time pattern (L, M, S) may be arranged periodically, for example, as shown in FIG. 8, different exposure times may be used for different areas, or may be arranged randomly. With the aperiodic arrangement, spatially coded exposure can be performed. A signal processing device such as a PC (personal computer) or a processor outside the solid-state image sensor uses a layout information of the exposure time pattern (L, M, S) of each pixel to obtain a high frame rate, a wide dynamic range, and a high S. Signal processing for reconstructing a 32-bit signal to obtain a /N image can be performed.

FIG. 9 shows an example of a configuration of pixel switch control. The pixel 50 in FIG. 9 includes a 1-bit A/D conversion circuit (ADC) 51, a memory 52, and a switch (SW) control unit 53 for each pixel. The ADC 51 has the same configuration as the signal processing circuit (1-bit type A/D conversion circuit) described with reference to FIGS. 1 to 3.

The memory 52 stores the pattern (L, M, S) of the exposure time of each pixel. DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) can be used as the memory 52.

The switch (SW) control unit 53 constitutes a logic circuit that turns ON/OFF each switch SW of the counter circuit 40 of the ADC 51, and outputs a switch control (SW control) signal. The switch control unit 53 reads the exposure time pattern (one-frame period division pattern) held in the memory 52, and based on the pattern, performs switch control a plurality of times in one frame in accordance with the sequence shown in FIG. Then, the counter circuit 40 is controlled.

FIG. 10 is another example of the configuration of pixel switch control. The pixel 50 in FIG. 10 includes a 1-bit A/D conversion circuit (ADC) 51 and a memory 52 in the pixel, but the switch (SW) control unit 54 is provided outside the pixel.

Although the SW control unit 54 may be arranged for each pixel as shown in FIG. 9, it may be common to all pixels. Therefore, in order to avoid an increase in the pixel area, as shown in FIG. Alternatively, the SW control unit 54 may be arranged for each one of a plurality of pixels or one for each row to control the plurality of pixels. Note that if the SW control unit 54 is shared between pixels on a two-dimensional plane, the number of wirings increases, so it is desirable to arrange the SW control unit 54 directly under the pixel using a three-dimensional integration technique.

FIG. 11 is a diagram showing an example of the mounting structure of the solid-state imaging device of the present invention. The solid-state imaging device 100 of FIG. 11 is one in which each circuit element forming a pixel is formed on a different substrate and is three-dimensionally laminated.

In FIG. 11, the solid-state imaging device 100 is composed of a photoelectric conversion layer (light receiving layer) 110, a pulse generation circuit layer 120, a counter circuit layer 130, and a control signal supply layer 140. Each layer is divided in pixel units (for example, 16 divisions in the figure), and each divided section is vertically connected (connection wiring is not shown), and the solid-state imaging device 100 is configured as a whole. ..

That is, the photoelectric conversion element (photodiode) 10 is formed in the uppermost light receiving layer 110, the reset means 20 and the inverter circuit 30 are formed in the second pulse generation circuit layer 120, and the counter circuit 40 is formed in the counter circuit layer 130. To form. Then, a switch control signal supply circuit (memory 52, SW control units 53 and 54), a scanning circuit, etc. are formed in the control signal supply layer 140 of the lowermost layer, and each circuit is connected in the vertical direction, for example, from the lowermost layer 140. You can retrieve the output.

As described above, a counter circuit and a switch control signal supply circuit are formed on a substrate different from that of a 1-bit ADC, three-dimensionally stacked, and three-dimensionally wired for each pixel, thereby realizing a high-definition solid-state imaging device. it can.

FIG. 12 shows another embodiment of the pattern of the exposure time. Similar to FIG. 4, the switch name that is turned on is shown as the switch state in each exposure time pattern. In the pixel of the solid-state imaging device of the present invention, as shown in FIG. 12, a plurality of patterns having different exposure times can be mixed in one pixel (one frame period can be divided into periods having different lengths). .. Particularly, the second row is an example in which one pixel is subjected to short-time exposure (S)-medium-time exposure (M')-short-time exposure (S). The medium time exposure (M') is different in phase (exposure timing) from the medium time exposure (M) described in the first line. Thus, it is possible to perform exposure with different phases even at the same time, and the signal processing for reconstruction contributes to a high frame rate, a wide dynamic range, and a high S/N ratio. The third line is an example of performing medium-long exposure (ML) and short-time exposure (S), and the medium-long exposure (ML) corresponds to 3/4 (3T/4) exposure of one frame. Furthermore, by increasing the number of counters and switches, it is possible to increase the types of exposure time patterns.

In this way, a different exposure time pattern (a pattern of one frame period division) is set for each pixel, and these pixels are arranged, for example, as shown in FIG. 8 to form a solid-state image sensor. It is also possible to mix and use the pixels of the exposure time pattern shown in FIG. 12 and the pixels of the exposure time pattern shown in FIG.

The exposure time pattern (L, M, S) may be fixed for the entire period or may be dynamically changed. FIG. 13 is an example of adaptively setting the exposure time pattern of each pixel.

The output image of the solid-state imaging device 100 is input to an image processing unit 200 including a PC (personal computer), a microprocessor, an FPGA (field-programmable gate array), etc., and the image processing unit 200 moves the image such as a motion vector. The feature amount of is extracted. For example, when the movement in the central area of the image is large, the movement in the neighboring area is medium, and the movement in the peripheral area is small, the movement is divided into three stages according to the arrangement information of the pixels in which the movement is detected. Patterns of short-time exposure (S), medium-time exposure (M), and long-time exposure (L) are set in each pixel 50 in descending order and written in the pixel memory. This writing operation may be performed for each frame or may be performed for a plurality of frames.

It should be noted that the division into three stages is an example and may be divided into two stages. That is, at least a pixel having a large motion (first pixel) is divided into a number of short periods for one frame period for short-time exposure, and a pixel having a small motion (second pixel) makes one frame period one or a few. It may be divided into long exposures. By setting the exposure time in this way, it is possible to operate the pixels 50 in a moving portion at high speed and efficiently increase the dynamic resolution. The image processing unit 200 is not limited to an external device of the solid-state image sensor 100 such as a PC, and may be integrated under the pixel area by using a three-dimensional integration technique and integrated with the solid-state image sensor 100.

According to the signal processing circuit of the present invention, even if a different exposure time pattern is set for each pixel, all output signals from short-time exposure to long-time exposure are held in the pixel, and the number of bits of each pixel is For example, since it is unified with 32 bits, it is not necessary to read out a plurality of times in one frame period, and it is possible to output all at once. Therefore, the scanning circuit used in a normal solid-state image sensor can be used, and the reading time can be minimized. Since all pixels are read out as in the case of a normal solid-state image sensor, the amount of data in each frame is constant and the signal processing for reconstruction becomes easy.

As a method of using the signal processing circuit of the present invention, even if a pattern of different exposure times is not used for each pixel, for example, by operating all the pixels for short-time exposure (S), all the pixels once per frame By reading, a signal obtained by multiple exposures can be obtained. Conventionally, in order to perform short-time exposure, it was necessary to read all pixels a plurality of times in one frame, but the exposure time is shortened by increasing the time for reading all pixels. On the other hand, in this method, all pixels are read out once per frame as in the case of a normal solid-state image sensor, so that the exposure time can be secured.

In the signal processing circuit of the present invention, the bit allocated to the counter decreases as the exposure becomes shorter, so that there is a trade-off relationship between high speed and bit depth (gradation). Therefore, it is desirable to set the number of counters in advance so that a sufficient bit depth can be obtained even if the counters are divided by short-time exposure. By increasing the number of counters in a plane, the pixel size increases. However, by using a three-dimensional integration technique, the counter is divided into a plurality of layers and the upper and lower layers are connected to each pixel by・High integration is possible. Alternatively, even if there is a trade-off relationship between high speed and bit depth, a method of performing differentiating signal processing by setting different exposure time patterns for each pixel is superior in high speed or bit depth. Since the signal of the pixel complements the signal of the other pixels, there is also an effect that the trade-off can be eliminated in the solid-state image pickup device as a whole.

Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications and changes can be made without departing from the scope of the claims. For example, it is possible to combine a plurality of constituent blocks described in the embodiment into one or divide one constituent block.

10 Photodiode 11 Voltage detection node 20 Reset transistor 30 Inverter circuit 40 Counter circuit 50 Pixel 51 1-bit type A/D conversion circuit 52 Memories 53, 54 Switch control unit 60 Vertical shift register 61 Row scanning line 70 Horizontal shift register 71 Read line 100 solid-state imaging device 110 photoelectric conversion layer 120 pulse generation circuit layer 130 counter circuit layer 140 control signal supply layer 200 image processing unit

Claims (10)

A pulse generation circuit that generates a pulse corresponding to the amount of electric charge to be detected,
In a signal processing circuit comprising a counter circuit for counting the pulses,
The predetermined time for performing the charge amount detecting operation is divided into a plurality of periods, and the output signal of the counter circuit in each divided period is collectively output after the end of the predetermined time, Signal processing circuit. The signal processing circuit according to claim 1,
A signal processing circuit, characterized in that the counter circuit is composed of a plurality of blocks composed of a plurality of bit counters, the different blocks are selected for each period, and the pulses are counted. The signal processing circuit according to claim 1,
The counter circuit includes a plurality of blocks including a plurality of bit counters and a plurality of switches that select the blocks, and controls the switches with a control signal to select the blocks that operate in each period. And a signal processing circuit. A solid-state imaging device comprising a photoelectric conversion element and the signal processing circuit according to any one of claims 1 to 3 in each pixel,
The solid-state imaging device, wherein the predetermined time for performing the charge amount detecting operation is one frame period. In a solid-state image sensor including a signal processing circuit that performs analog/digital conversion of photoelectrically converted signal charges for each pixel,
One frame period is divided into one or a plurality of periods for each pixel, and the output signal of each divided period is collectively output for each pixel after the end of the one frame period. .. The solid-state image sensor according to claim 4 or 5,
Each pixel is provided with a memory that stores a pattern of division of one frame period, and one frame period is divided into one or a plurality of periods based on the pattern stored in the memory. Image sensor. The solid-state image sensor according to any one of claims 4 to 6,
A solid-state image pickup device, characterized in that pixels having different patterns for one frame period are arranged regularly. The solid-state image sensor according to any one of claims 4 to 6,
A solid-state image pickup device, characterized in that pixels having different patterns for one frame period are arranged aperiodically. The solid-state image sensor according to any one of claims 4 to 6,
The feature quantity of the motion of the output image of the solid-state image sensor is extracted, the first pixel having large motion divides one frame period into short periods, and the second pixel having small motion divides one frame period into the first frame period A solid-state imaging device, characterized by being divided into periods longer than one pixel. The solid-state image sensor according to any one of claims 4 to 9,
A solid-state image pickup device, characterized in that circuit elements constituting each pixel are formed on different substrates, and the substrates are three-dimensionally laminated.

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