WO2011145549A1 - Structure provided with wiring structure, and mems relay - Google Patents

Structure provided with wiring structure, and mems relay Download PDF

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Publication number
WO2011145549A1
WO2011145549A1 PCT/JP2011/061159 JP2011061159W WO2011145549A1 WO 2011145549 A1 WO2011145549 A1 WO 2011145549A1 JP 2011061159 W JP2011061159 W JP 2011061159W WO 2011145549 A1 WO2011145549 A1 WO 2011145549A1
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WO
WIPO (PCT)
Prior art keywords
substrate
base substrate
ground
wiring
signal line
Prior art date
Application number
PCT/JP2011/061159
Other languages
French (fr)
Japanese (ja)
Inventor
孝明 吉原
徹 馬場
成正 岩本
健雄 白井
浩司 横山
雅和 足立
敦 諏訪
太 西村
健 橋本
嘉城 早崎
Original Assignee
パナソニック電工株式会社
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Publication of WO2011145549A1 publication Critical patent/WO2011145549A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H50/00Details of electromagnetic relays
    • H01H50/005Details of electromagnetic relays using micromechanics
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/09Packages
    • B81B2207/091Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094Feed-through, via
    • B81B2207/096Feed-through, via through the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H1/00Contacts
    • H01H1/0036Switches making use of microelectromechanical systems [MEMS]
    • H01H2001/0042Bistable switches, i.e. having two stable positions requiring only actuating energy for switching between them, e.g. with snap membrane or by permanent magnet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H50/00Details of electromagnetic relays
    • H01H50/005Details of electromagnetic relays using micromechanics
    • H01H2050/007Relays of the polarised type, e.g. the MEMS relay beam having a preferential magnetisation direction

Definitions

  • the present invention relates to a structure having a wiring structure and a MEMS (micro-electromechanical mechanicals) relay.
  • MEMS micro-electromechanical mechanicals
  • the microrelay includes a base substrate 1 ′, a movable portion forming substrate 2 ′ disposed on one surface side of the base substrate 1 ′, and a cover substrate 3 disposed on the base substrate 1 ′ side of the movable portion forming substrate 2 ′.
  • the base substrate 1 ′ is provided with a pair of signal lines 13 ′ and 13 ′ at both ends in the longitudinal direction on the one surface side.
  • the movable part forming substrate 2 ′ includes a rectangular frame-shaped frame part 21 ′ fixed to the one surface side of the base substrate 1 ′, and four support spring parts 224 disposed inside the frame part 21 ′. And a movable portion 24 ′ that is swingably supported by the frame portion 21 ′.
  • the movable part forming substrate 2 ′ has contact holding pieces 226 ′ supported by the movable part 24 ′ via two contact pressure spring parts 225 ′, and the contact holding part 226 ′ has a pair of contact holding pieces 226 ′.
  • Movable contacts (not shown) that are in contact with and away from the fixed contacts 14 ′ and 14 ′ at one end portions of the signal lines 13 ′ and 13 ′ are provided. Further, the peripheral portion of the cover substrate 3 ′ is fixed to the frame portion 21 ′.
  • the base substrate 1 ′ and the cover substrate 3 ′ are formed using a glass substrate, and the movable part forming substrate 2 ′ is formed using a silicon substrate.
  • a storage portion 116 ′ for storing the electromagnet device 4 ′ is formed on the base substrate 1 ′.
  • the electromagnet device 4 generates a magnetic flux in accordance with the excitation current to the coils 42' and 42 'wound around the yoke 40'.
  • an armature (not shown) that is driven to swing freely by the electromagnet device 4 ′ is laminated on the base substrate 1 ′ side of the movable portion 24 ′ in the movable portion forming substrate 2 ′.
  • FIG. 18 a structure having a wiring structure including a signal line 13 ′ is shown in FIG. 18 for the purpose of reducing transmission loss of a high frequency signal as compared with a microstrip type line or a coplanar type line.
  • the ground conductor 5 ′ surrounding the signal line 13 ′ is formed across the base substrate 1 ′, the movable part forming substrate 2 ′, and the cover substrate 3 ′.
  • the middle substrate (intermediate substrate) among the three substrates (base substrate 1 ′, movable portion forming substrate 2 ′, and cover substrate 3 ′).
  • a cavity 27 ′ that exposes the signal line 13 ′ on the one surface of the base substrate 1 ′ is formed on a certain movable portion forming substrate 2 ′ by anisotropic etching that enables vertical deep drilling.
  • the ground conductor 5 ′ is provided on the base substrate 1 ′ and the first ground wirings 51 ′ and 51 ′ disposed on both sides in the width direction of the signal line 13 ′ on the one surface of the base substrate 1 ′.
  • Second ground wirings 52 ′, 52 ′ made of vias electrically connected to the first ground wirings 51 ′, 51 ′, and second ground wirings disposed on the other surface of the base substrate 1 ′.
  • the signal line 13 ′ and the signal line 13 ′ in plan view on the side facing the base substrate 1 ′ in the cover substrate 3 ′ and the third ground wiring 53 ′ that electrically connects 52 ′ and 52 ′.
  • a fourth ground wiring 54 ′ having a width straddling the first ground wirings 51 ′, 51 ′ on both sides, and the wall portions 28 ′, 28 ′ of the cavity 27 ′ on the movable part forming substrate 2 ′ are arranged.
  • First ground wiring 51 ′, 1 'and the fourth ground wiring 54' fifth ground wire 55 for electrically connecting the '55' are constructed out with.
  • the angle formed between the wall surfaces 28 ′, 28 ′ of the cavity 27 ′ and the one surface of the base substrate 1 ′ is approximately 90 degrees. It was difficult to form the fifth ground wirings 55 ′ and 55 ′.
  • the wall surfaces 28 ′ and 28 ′ are inclined surfaces, there is a problem that the planar size of the structure is increased and the planar size of the MEMS relay is increased.
  • the present invention has been made in view of the above reasons, and its purpose is to form a grounding conductor that can reduce transmission loss while suppressing an increase in the planar size of the structure and surrounds a signal line. It is an object of the present invention to provide a structure and a MEMS relay having an easy wiring structure.
  • a structure including a wiring structure includes a base substrate having a signal line formed on one surface side, a cover substrate disposed opposite to the one surface side of the base substrate, and the base substrate and the cover substrate.
  • An intermediate substrate having a hollow portion that is interposed and exposed in the thickness direction, and a ground conductor that is formed across the base substrate, the intermediate substrate, and the cover substrate and surrounds the signal line;
  • a second ground wiring comprising vias, a third ground wiring electrically connecting the second ground wirings on the other surface side of the base substrate and parallel to the signal lines, and a base substrate in the cover substrate
  • a fourth ground wiring having a width across the signal line and the first ground wiring on both sides of the signal line in plan view on the opposite side, and the first ground formed on both sides of the cavity in the intermediate substrate It is characterized by
  • the intermediate substrate, the base substrate, and the cover substrate are bonded to each other through metal layers formed on opposing surfaces.
  • the intermediate substrate, the base substrate, and the cover substrate are preferably formed by surface activation bonding of the metal layers.
  • an insulating film is provided between the intermediate substrate 2 and the fifth ground wiring.
  • the MEMS relay of the present invention is a MEMS relay having a structure having the wiring structure, wherein the base substrate has a pair of the signal lines on the one surface side, and the intermediate substrate has an opening portion.
  • the cavity portion that is provided in parallel with the opening portion and that corresponds to each of the signal lines, and a communication portion that connects the opening portion and the cavity portion are formed, and are interposed between the base substrate and the cover substrate.
  • a contact holding piece having a movable contact that contacts and separates from the fixed contact, and the structure is provided with drive means for driving the movable portion to be swingable.
  • the driving means includes an armature made of a magnetic material laminated on the cover substrate side in the movable portion main body, and an electromagnet device that is provided on the cover substrate and drives the armature to be swingable. It is preferable to be made.
  • the structure having the wiring structure of the present invention it is possible to reduce transmission loss while suppressing an increase in the planar size of the structure, and it is easy to form a ground conductor.
  • the MEMS relay of the present invention it is possible to provide a MEMS relay that can reduce transmission loss while suppressing an increase in planar size and that can easily form a ground conductor surrounding a signal line.
  • FIG. 1 shows a structure including a wiring structure according to an embodiment, where (a) is a schematic plan view of a main part, (b) is a schematic cross-sectional view along AA ′ in (a), and (c) is a cross-sectional view along BB in (a).
  • 'It is a schematic sectional view. It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above.
  • FIGS. 1 to 5 a structure having a wiring structure and a method for forming the structure will be described with reference to FIGS. 1 to 5, and a MEMS relay as an example of a MEMS device having the structure will be described with reference to FIGS. The description will be given with reference.
  • the structure including the wiring structure of the present embodiment is arranged so that a base substrate 1 having a signal line (transmission line) 13 formed on one surface side is opposed to one surface side of the base substrate 1.
  • the cover substrate 3, the intermediate substrate 2 between the base substrate 1 and the cover substrate 3, and the cavity 27 that exposes the signal line 13 is provided in the thickness direction; the base substrate 1 and the intermediate substrate 2; And a grounding conductor 5 formed over the cover substrate 3 and surrounding the signal line 13.
  • the outer sizes of the base substrate 1 and the cover substrate 3 are set to the same outer size as that of the intermediate substrate 2.
  • the base substrate 1, the intermediate substrate 2, and the cover substrate 3 each have a thickness.
  • the thicknesses of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are the same as the direction in which the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are arranged. Accordingly, the thickness direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the thickness of the base substrate 1, intermediate substrate 2, and cover substrate 3.
  • the base substrate 1, the intermediate substrate 2, and the cover substrate 3 have a length and a width, respectively.
  • the lengths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the thickness direction of the base substrate 1. Therefore, the length direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the length of the base substrate 1, intermediate substrate 2, and cover substrate 3.
  • the widths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the thickness direction of the base substrate 1.
  • the widths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the length direction of the base substrate 1. Therefore, the width direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the width of the base substrate 1, intermediate substrate 2, and cover substrate 3.
  • the base substrate 1 is formed using a first substrate 10 made of a glass substrate which is a kind of insulating substrate.
  • the first substrate 10 is not limited to a glass substrate.
  • a silicon substrate having a high resistivity for example, a resistivity of 100 ⁇ cm or more
  • a low-temperature co-fired ceramic substrate Low Temperature Co-fired Ceramic Substrate: LTCC substrate
  • the glass material of the glass substrate used as the first substrate 10 may be soda glass, alkali-free glass, quartz glass, or borosilicate glass such as Pyrex (registered trademark) or Tempax (registered trademark).
  • a glass material having a low dielectric constant is preferred.
  • the signal line 13 is composed of a metal layer (for example, an Au layer) patterned in a straight line.
  • the signal line 13 is made of Au, but is not limited to Au.
  • the intermediate substrate 2 is formed using the semiconductor substrate 20.
  • the intermediate substrate 2 constitutes a movable part forming substrate of the MEMS relay as will be described later.
  • the semiconductor substrate 20 according to a desired three-dimensional structure of the movable part forming substrate, for example, silicon substrate and a silicon layer / insulating layer (SiO 2 layer) / SOI having a three-layer structure of the silicon layer and (silicon On insulator) substrate, a silicon layer / insulating layer (SiO 2 layer) / silicon layer / insulating layer (SiO 2 A double SOI substrate having a five-layer structure (double SOI structure) / layer of silicon) may be used.
  • the cover substrate 3 is formed by using the second substrate 30 made of the second glass substrate, but the second substrate 30 is not limited to the glass substrate, like the first substrate 10, A high resistivity silicon substrate or LTCC substrate may be used.
  • the ground conductor 5 described above includes first ground wirings 51 and 51 parallel to the signal line 13 on both sides in the width direction of the signal line 13 (left and right direction in FIG. 1A) on the one surface side of the base substrate 1.
  • the second ground wirings 52 and 52 formed in the base substrate 1 and electrically connected to the first ground wirings 51 and 51 and including the vias parallel to the signal line 13, and on the other surface side of the base substrate 1
  • the second ground wirings 52, 52 are electrically connected to each other, the third ground wiring 53 parallel to the signal line 13, and the signal line 13 and the signal line 13 in plan view on the side of the cover substrate 3 facing the base substrate 1.
  • a fourth ground wiring 54 having a width across the first ground wirings 51, 51 on both sides of the signal line 13, and each first ground wiring formed on both sides of the cavity 27 in the intermediate substrate 2. 51 and and a fifth ground wire 55, 55 of electrically connected to the through slit lines and the fourth ground wiring 54.
  • the ground conductor 5 surrounds the signal line 13 in a cross section orthogonal to the length direction of the signal line 13.
  • the first ground lines 51 and 51 are formed on one surface of the first substrate 10, similarly to the signal line 13.
  • Each of the first ground lines 51 and 51 is configured by a metal layer (for example, an Au layer) patterned so as to be parallel to the signal line 13.
  • a metal layer for example, an Au layer
  • Au is adopted, but not limited to Au, for example, Al, Cu, etc. may be adopted.
  • the second ground wirings 5, 52 are formed inside via holes 11, 11 penetrating in the thickness direction of the first substrate 10.
  • the material of the second ground wirings 52 and 52 and the third ground wiring 53 is Cu, but is not limited to Cu.
  • Ni, Au, or the like may be employed.
  • the fourth ground wiring 54 is constituted by a metal layer (for example, Au layer) patterned so as to be parallel to the signal line 13.
  • a metal layer for example, Au layer
  • Au is adopted as the material of the fourth ground wiring 54.
  • the material is not limited to Au, and for example, Al, Cu or the like may be adopted.
  • the fifth ground wirings 55 and 55 are formed inside the through slit 20a penetrating in the thickness direction of the semiconductor substrate 20, and the fifth ground wirings 55 and 55 and the through slits 20a and 20a are formed. A part of an insulating film 20b made of a silicon oxide film (thermal oxide film) formed across both surfaces in the thickness direction of the semiconductor substrate 20 and the inner surface of the through slit 20a is interposed therebetween. In short, the fifth ground wirings 55 and 55 are electrically insulated from the semiconductor substrate 20.
  • the through slits 20 a and 20 a have a uniform opening width in a cross section perpendicular to the direction in which the signal line 13 runs (longitudinal direction of the signal line 13) regardless of the position in the thickness direction of the semiconductor substrate 20. Is formed.
  • the opening width in a cross section orthogonal to the direction in which the signal line 13 runs is uniform regardless of the position in the thickness direction of the semiconductor substrate 20. It is formed as follows. In short, the cavity 27 has a rectangular cross section perpendicular to the direction in which the signal line 13 runs.
  • the fifth ground wirings 55, 55 are formed on the base substrate 1 side of the semiconductor substrate 20 and are connected to the first ground wirings 51, 51 via the connection metal layer 25. 51 is electrically connected.
  • bonding metal layers 26 and 26 are formed on the sides of the connecting metal layers 25 and 25, and the bonding metal layers 26 and 26 are formed on the base substrate 1.
  • the joining metal layers 16 and 16 of the base substrate 1 are formed of the same material as the first ground wirings 51 and 51 and have the same film thickness as the first ground wirings 51 and 51.
  • the fifth ground wirings 55 and 55 are electrically connected to the fourth ground wiring 54 via a connection metal layer 29 formed on the cover substrate 3 side of the semiconductor substrate 20 and joined to the fourth ground wiring 54. It is connected to the.
  • each of the connecting metal layers 25 and 29 and the bonding metal layer 26 is electrically insulated from the semiconductor substrate 20 by the above-described insulating film 20b.
  • Each of the connecting metal layers 25 and 29 and the bonding metal layer 26 is composed of a laminated film of a Ti film formed on the insulating film 20b and an Au film formed on the Ti film.
  • a connecting metal layer 25 and a bonding metal layer 26 on the base substrate 1 side of the substrate 20 are formed simultaneously.
  • the thickness of the Ti film on the insulating film 20b is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm.
  • these numerical values are only examples and are particularly limited. Not what you want.
  • a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 20b
  • the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used.
  • the connecting metal layer 25 and the bonding metal layer 26 may employ an Al film or a Cu film instead of the Au film.
  • the signal line 13 described above is electrically connected to the via 15 penetrating in the thickness direction of the first substrate 10.
  • the via 15 to which the signal line 13 is bonded is formed inside a via hole 12 having a circular shape in plan view and penetrating in the thickness direction of the first substrate 10, and the other surface of the first substrate 10.
  • the signal line 13 is connected to the via 15 at one end in the longitudinal direction of the signal line 13, but a via connected to the other end may be formed.
  • FIGS. (A) to (d) are cross-sectional views taken along the line BB ′ of FIG. The schematic cross section of the part corresponding to is shown.
  • a first substrate 10 made of a glass substrate as shown in FIG. 2 (a) is prepared, and then via holes 11, 11, 12 penetrating in the thickness direction of the first substrate 10 are formed on the first substrate 10.
  • a structure shown in FIG. 2B is obtained by performing a via hole forming process formed by sandblasting or the like from the other surface side.
  • the formation method of the via holes 11, 11, and 12 is not limited to the sandblast method, and may be laser processing, machining, or etching, for example.
  • the via holes 11, 11, and 12 may be formed using a photolithography technique and an etching technique.
  • the second ground wirings 52 and 52, the third ground wiring 53, the via 15 and the metal material for example, Cu, which closes the via holes 11, 11 and 12 serving as the basis of the external connection electrode 17.
  • a metal layer (hereinafter referred to as an Au layer or the like serving as a basis for the first ground wirings 51 and 51 and the bonding metal layers 16 and 16 is formed on the one surface side of the first substrate 10.
  • 3 (a) is performed by performing a metal layer forming step (hereinafter referred to as a first metal layer forming step) for forming 18 by a sputtering method or a vapor deposition method, for example. Get the structure.
  • a resist layer 119 having an opening corresponding to a region where the signal line 13 is to be formed is formed on the one surface side of the first substrate 10, and the signal line 13 made of a metal material (for example, Au) is formed. 3 is obtained by plating, and after obtaining the structure shown in FIG. 3C, the resist layer 119 is removed to obtain the base substrate 1 having the structure shown in FIG.
  • the method for forming the signal line 13 is not limited to the plating method, and for example, the signal line 13 may be formed using a lift-off method.
  • a semiconductor substrate 20 as shown in FIG. 4A is prepared, and then the semiconductor substrate 20 is penetrated in the thickness direction by using a photolithography technique and an etching technique.
  • the through slit forming step of forming the through slits 20a, 20a the structure shown in FIG. 4B is obtained.
  • the etching of the semiconductor substrate 20 in the through slit forming step is performed by a dry etching apparatus capable of highly anisotropic etching (perpendicular deep drilling) such as an inductively coupled plasma (ICP) type etching apparatus. Just do it.
  • ICP inductively coupled plasma
  • an insulating film 20b made of a silicon oxide film (thermal oxide film) straddling one surface and the other surface of the semiconductor substrate 20 and the inner surfaces of the through slits 20a and 20a is formed by a thermal oxidation method.
  • the structure shown in FIG. 4C is obtained by performing the through slit wiring forming process of forming the fifth ground wiring 55, 55 made of the through slit wiring by a plating method.
  • each through slit 20a, 20a is enriched by a part of the insulating film 20b and the fifth ground wiring 55, 55 made of a metal material (for example, Cu, Ni, Au, etc.).
  • the fifth ground wirings 55 and 55 are formed so as to be blocked.
  • a metal layer (hereinafter, referred to as a second metal layer) 290 formed of a laminated film of a Ti film and an Au film serving as a base of the connection metal layer 29 is applied to the entire surface of the semiconductor substrate 20 on the one surface side by a sputtering method. And a lamination of a Ti film and an Au film serving as a basis for the connection metal layers 25 and 25 and the bonding metal layers 26 and 26 over the entire surface of the semiconductor substrate 20 on the other surface side.
  • a structure shown in FIG. 4D is obtained by performing a second metal layer forming step of forming a metal layer (hereinafter referred to as a third metal layer) 250 made of a film by sputtering, vapor deposition, CVD, or the like. Get.
  • the second metal layer using the photolithography technique and the etching technique is left so that portions corresponding to the connection metal layers 29 and 29 of the second metal layer 290 on the one surface side of the semiconductor substrate 20 remain.
  • 290 is patterned, and the photolithography technique is performed so that portions corresponding to the connection metal layers 25 and 25 and the bonding metal layers 26 and 26 remain in the third metal layer 250 on the other surface side of the semiconductor substrate 20.
  • the structure shown in FIG. 5A is obtained by performing a second metal layer patterning step of patterning the third metal layer 250 using an etching technique.
  • the cavity 27 is formed by etching the semiconductor substrate 20 from the one surface side using the mask layer 270 formed for forming the cavity using the photolithography technique on the one surface side of the semiconductor substrate 20 as a mask.
  • the cavity portion forming step is performed, and the mask layer 270 is removed to obtain the structure shown in FIG.
  • the etching of the semiconductor substrate 20 in the cavity forming step is performed by a dry etching apparatus capable of highly anisotropic etching (perpendicular deep drilling) such as an inductively coupled plasma (ICP) type etching apparatus. Just do it.
  • the first intermediate substrate 2 is bonded to the cover substrate 3 on which the fourth ground wiring 54 is formed on one surface side (the intermediate substrate 2 side) of the second substrate 30.
  • the bonding step By performing the bonding step, the structure shown in FIG. 5C is obtained.
  • the connection metal layer 29 of the intermediate substrate 2 and the fourth ground wiring 54 of the cover substrate 3 are bonded and electrically connected.
  • a second bonding step for bonding the intermediate substrate 2 and the base substrate 1 is performed to obtain a structure having the wiring structure shown in FIG.
  • the bonding metal layer 26 of the intermediate substrate 2 and the bonding metal layer 16 of the base substrate 1 are bonded, and the connection metal layer 25 of the intermediate substrate 2 and the base substrate 1 are bonded.
  • the first ground wiring 51 is joined and electrically connected.
  • each bonding surface is cleaned and activated by irradiating the bonding surfaces with argon plasma, ion beam or atomic beam in vacuum before bonding. Then, the bonding surfaces are brought into contact with each other, and a room temperature bonding method in which the bonding surfaces are directly bonded at a normal temperature (for example, 25 ° C.) is employed. Stress and the like can be greatly reduced.
  • first bonding step and the second bonding step are not limited to the normal temperature bonding method, and after normalizing and activating each of the bonding surfaces described above, the bonding surfaces are brought into contact with each other and a specified temperature (normal temperature higher than normal temperature) (for example, you may make it join directly at 80 degreeC.
  • the manufacturing method of the MEMS relay having the structure provided with the wiring structure in the present embodiment all the processes until the second bonding process is completed are performed for each of the intermediate substrate 2, the base substrate 1 and the cover substrate 3 at the wafer level.
  • a wafer level package structure including a plurality of MEMS relays is formed, and a dividing step of dividing the wafer level package structure into individual MEMS relays is performed.
  • the outer sizes of the base substrate 1 and the cover substrate 3 can be easily adjusted to the outer size of the intermediate substrate 2, and mass productivity can be improved.
  • the ground conductor 5 surrounding the signal line 13 is parallel to the signal line 13 on both sides in the width direction of the signal line 13 on the one surface side of the base substrate 1.
  • First ground wirings 51, 51, and second ground wirings 52, 52 formed on the base substrate 1 and electrically connected to the first ground wirings 51, 51 and made of vias parallel to the signal lines 13,
  • the second ground wirings 52, 52 are electrically connected to each other on the other surface side of the base substrate 1, and the third ground wiring 53 parallel to the signal line 13 is opposed to the base substrate 1 in the cover substrate 3.
  • a fourth ground wiring 54 having a width across the signal line 13 and the first ground wirings 51, 51 on both sides of the signal line 13 in plan view, and a cavity in the intermediate substrate 2. 27, and is formed of fifth ground wirings 55 and 55 formed of through slit wirings that are formed on both sides of the first wiring 27 and electrically connect the first ground wirings 51 and 51 to the fourth ground wiring 54, Since the fifth ground wirings 55 and 55 can be easily formed as compared to the case where the fifth ground wirings 55 and 55 are formed on the wall surfaces 28 and 28 of the cavity portion 27 having an angle of about 90 degrees with the one surface. Transmission loss can be reduced while suppressing an increase in the planar size of the structure, and formation of the ground conductor 5 surrounding the signal line 13 is facilitated.
  • the structure includes a base substrate 1, a cover substrate 3, an intermediate substrate 2, and a ground conductor.
  • the base substrate 1 is provided with a signal line 13 on one surface side thereof.
  • the cover substrate 3 is disposed at a position facing the one surface side of the base substrate 1.
  • the intermediate substrate 2 is disposed so as to be interposed between the base substrate 1 and the cover substrate 3.
  • the intermediate substrate 2 has a thickness.
  • the intermediate substrate 2 is provided with a cavity 27 formed so as to penetrate in the thickness direction.
  • the hollow portion 27 is provided to expose the signal line 13.
  • the intermediate substrate 2 is disposed between the base substrate 1 and the cover substrate 3 so that the signal line 13 is located in the cavity 27.
  • the ground conductor is formed over the base substrate 1, the intermediate substrate 2, and the cover substrate 3 so as to surround the signal line 13.
  • the ground conductor has a first ground wiring 51, a second ground wiring 52, a third ground wiring 53, a fourth ground wiring 54, and a fifth ground wiring 55.
  • the first ground wiring 51 is parallel to the signal line 13 on both sides in the width direction of the signal line 13 on the one surface side of the base substrate 1.
  • the second ground wiring 52 is formed on the base substrate 1 and is electrically connected to each first ground wiring 51 and includes a via parallel to the signal line 13.
  • the second ground wiring 52 is formed on the base substrate 1 so as to be located in the via hole parallel to the signal line 13 and is electrically connected to each first ground wiring 51.
  • the third ground wiring 53 is electrically connected to the second ground wirings 52 on the other surface side of the base substrate 1 and is parallel to the signal line 13.
  • the fourth ground wiring 54 has a width dimension straddling the signal line 13 and the first ground wiring 51 on both sides of the signal line 13 in a plan view on the side of the cover substrate 3 facing the base substrate 1.
  • the fifth ground wiring 55 is formed of a through-slit wiring that is formed on both sides of the cavity 27 in the intermediate substrate 2 and electrically connects the first ground wiring 51 and the fourth ground wiring 54.
  • the fifth ground wiring 55 is configured by a through slit wiring arranged in the through slit 20 a provided so as to be located on both sides of the cavity portion 27 in the intermediate substrate 2.
  • the through slit wiring electrically connects the first ground wiring 51 and the fourth ground wiring 54.
  • the intermediate substrate 2, the base substrate 1, and the cover substrate 3 are formed on the metal layers formed on the opposing surfaces (in the intermediate substrate 2, the connection metal layers 25 and 29, the bonding metal layer 26. Each of them constitutes a metal layer.
  • the first ground wiring 51 and the bonding metal layer 16 each constitute a metal layer
  • the fourth ground wiring 54 constitutes a metal layer.
  • the fifth ground wirings 55 and 55 of the intermediate substrate 2, the first ground wirings 51 and 51 of the base substrate 1, and the fourth ground wiring 54 of the cover substrate 3. Can be easily electrically connected.
  • the intermediate substrate 2, the base substrate 1, and the cover substrate 3 are directly bonded after the metal layers activate each other's bonding surfaces (that is, surface activated bonding). Therefore, it is possible to bond the intermediate substrate 2 to the base substrate 1 and the cover substrate 3 at room temperature, and the stress caused by thermal expansion at the time of bonding is a line between the intermediate substrate 2, the base substrate 1 and the cover substrate 3. Stress generated at the time of joining due to the difference in expansion coefficient can be reduced.
  • an electrical insulating film having electrical insulation is provided between the intermediate substrate 2 and the fifth ground wiring 55.
  • the base substrate 1 is formed in a rectangular plate shape, and a pair of signal lines 13 and 13 are formed at both ends in the longitudinal direction on the one surface side.
  • the pair of signal lines 13 and 13 have the length direction aligned with the short direction of the base substrate 1 and are aligned on a straight line.
  • the base substrate 1 has a pair of signal lines 13 and 13 at one end and is electrically connected to vias 15 and 15 that overlap in the thickness direction, and fixed contacts 14 and 14 are provided at the other end. Yes.
  • the base substrate 1 is electrically connected to a pair of signal lines 13 and 13 via external vias 15 and 15 and external connection electrodes 17 and 17 formed on the other surface side of the base substrate 1. .
  • Each fixed contact 14 is a metal film made of a metal material having good conductivity such as Cu or Au, and is formed using a sputtering method, an electroplating method, a vacuum deposition method, or the like.
  • Each fixed contact 14 is not limited to a single layer structure, and may have a multilayer structure. Further, the material of the fixed contact 14 is not limited to Cu or Au, and for example, Cu, Au, Ag, Cr, Ti, Pt, Ru, Rh, Co, Ni, and alloys thereof may be employed.
  • the via hole 12 in which the above-described via 15 is provided inside the base substrate 1 is formed in a tapered shape in which the opening area gradually increases as it approaches the other surface from the one surface of the base substrate 1.
  • the via 15 is formed along the inner surface of the via hole 12 and closes the via hole 12 on the one surface side of the base substrate 1.
  • the intermediate substrate 2 (hereinafter also referred to as the movable portion forming substrate 2) is provided with an opening 22 formed in the central portion of the semiconductor substrate 20 and a pair of signal lines 13 and 13 arranged in parallel to the opening 22 respectively.
  • the corresponding cavity portions 27, 27 and the communication portions 23, 23 for communicating the openings 22 with the respective cavity portions 27, 27 are formed, and the frame portion 21 interposed between the base substrate 1 and the cover substrate 3, and the frame A movable portion 24 disposed inside the portion 21 and supported by the frame portion 21 in a swingable manner, and both ends in the longitudinal direction of a rectangular plate-shaped movable portion main body 24 a disposed in the opening 22 of the movable portion 24.
  • a contact holding piece 24b having a movable contact 214 (see FIG.
  • the movable contact 214 is a metal film made of a metal material having good conductivity such as Cu or Au, like the fixed contact 14, and uses a sputtering method, an electroplating method, a vacuum deposition method, or the like. Is formed.
  • the movable contact 214 is not limited to a single layer structure, and may be a multilayer structure, for example, a laminated film of a Ti film and an Au film.
  • the material of the movable contact 214 is not limited to Cu or Au, and for example, Cu, Au, Ag, Cr, Ti, Pt, Ru, Rh, Co, Ni, or an alloy thereof may be employed.
  • the movable part forming substrate 2 has a fulcrum projecting piece 24c projecting at the center of each of both ends in the short direction of the movable part main body 24a, and the fulcrum projecting piece 24c is opposed to the cover substrate 3.
  • a fulcrum protrusion 24d is provided so as to function as a fulcrum for the swinging operation (seesaw operation) of the movable portion 24.
  • the fulcrum protrusion 24d is interposed between the fulcrum protrusion 24c and the cover substrate 3, and the movable portion 24 is supported by the cover substrate 3 via the fulcrum protrusion 24d.
  • the portion of the frame 21 between the opening 22 and the cavities 27 and 27 regulates the movement of the movable portion 24 in the direction along the longitudinal direction of the movable portion forming substrate 2.
  • a movement restricting unit 231 is configured.
  • the movable part 24 is supported by the frame part 21 via four support spring parts 224 so as to be swingable.
  • the support springs 224 are formed at two locations spaced apart in the longitudinal direction of the movable part main body 24a on both side surfaces in the short side direction of the movable part main body 24a.
  • one end of each support spring portion 224 is continuously and integrally connected to the movable portion main body 24 a, and the other end portion is continuously and integrally connected to the inner peripheral surface of the frame portion 21.
  • the support spring part 224 is lengthened by forming the part between the said one end part and the said other end part in the planar shape in the meandering shape in the same plane.
  • the MEMS relay includes an armature 6 made of a magnetic material laminated on the cover substrate 3 side of the movable portion main body 24a as a driving means for driving the movable portion 24, and an armature 6 provided on the cover substrate 3.
  • An electromagnetic drive type driving means is provided which is composed of an electromagnet device 4 which is driven to swing.
  • the drive means is not limited to the electromagnetic drive type that drives the movable part 24 by electromagnetic force, but may be an electrostatic drive type that drives the movable part 24 by electrostatic force, or the movable part 24 by a piezoelectric element (electromechanical element). It may be a piezoelectric drive type.
  • the armature 6 is formed into a rectangular plate by machining a magnetic material such as electromagnetic soft iron, electromagnetic stainless steel, and permalloy, and is fixed to the movable portion main body 24a by a method such as adhesion, welding, hot welding, or brazing. Has been.
  • a reciprocal 60 is provided on the side of the movable portion main body 24a facing the base substrate 1.
  • the movable part main body 24 a is thinner than the frame part 21, and the thickness dimension of the armature 6 is appropriately set between the armature 6 and the cover substrate 3 in a state where the movable part forming substrate 2 and the cover substrate 3 are fixed. It is set so that a void is formed. Further, the thickness dimension of the sequential 60 is set so that an appropriate gap is formed between the movable portion 24 and the base substrate 1.
  • the distance between the movable portion main body 24a and the base substrate 1 is defined by the thickness of the silicon layer on the base substrate 1 side.
  • the distance (insulating distance) between the fixed contact 14 and the movable contact 214 in a state where the fixed contact 14 and the movable contacts 214 and 214 are open can be set with high accuracy.
  • the distance between the movable part main body 24a and the cover substrate 3 can be defined by the thickness of the silicon layer on the cover substrate 3 side, and the distance (magnetic gap length) between the armature 6 and the electromagnet device 4 can be set with high accuracy. It becomes possible to do.
  • substrate 2 is joining metal layer 238 (refer FIG. 6 and FIG. 9A) for joining to the cover board
  • a bonding metal layer 218 (see FIG. 9B) for bonding to the base substrate 1 is formed over the entire circumference of the frame portion 21 on the other surface side.
  • a bonding metal layer (not shown) to be bonded to the bonding metal layer 238 is formed over the entire circumference of the cover substrate 3 on the side facing the movable portion forming substrate 2.
  • a joining metal layer 118 see FIG.
  • the joining method of the movable part forming substrate 2, the base substrate 1, and the cover substrate 3 is not limited to the above-described room temperature joining method, and for example, an anodic joining method may be employed.
  • the cover substrate 3 is formed with a storage portion 36 for storing the above-described electromagnet device 4 in the center.
  • a storage portion opening 34 through which the electromagnet device 4 is inserted is formed in the central portion of the second substrate 30.
  • a closing plate 32 that closes the storage portion opening 34 is fixed to one surface side of the second substrate 2 on the movable portion forming substrate 2 side.
  • a space surrounded by the inner peripheral surface of the storage portion opening 34 and the closing plate 32 forms a storage portion 36.
  • the space surrounded by the base substrate 1, the frame portion 21 of the movable portion forming substrate 2, and the cover substrate 3 is an airtight space.
  • the storage portion opening 34 has a tapered shape in which the opening area gradually increases as it approaches the other surface from the one surface of the second substrate 30.
  • the cover substrate 3 is easy to insert the electromagnet device 4 from the side opposite to the movable portion forming substrate 2 side, and the opening area of the storage portion opening 34 on the one surface of the second substrate 30 is compared. Can be made smaller.
  • the storage portion opening 34 described above may be formed by, for example, a sandblasting method or an etching method.
  • the closing plate 32 is made of a thin plate such as a silicon plate or a glass plate having a thickness of about 5 to 50 ⁇ m (preferably about 20 ⁇ m). Such a blocking plate 32 is formed, for example, by thinning a silicon substrate or a glass substrate by polishing or etching.
  • the electromagnet device 4 includes a yoke 40 and two coils 42 and 42 wound around the yoke 40.
  • the yoke 40 extends in the direction of approaching the closing plate 32 from each of the elongated rectangular plate-shaped coil winding portion 40a around which both the coils 42 and 42 are directly wound, and both ends in the longitudinal direction of the coil winding portion 40a.
  • a rectangular plate-like permanent magnet 41 disposed so as to overlap the central portion of the direction.
  • the yoke 40 is formed by processing an iron plate such as electromagnetic soft iron by bending, casting, pressing, or the like, and the cross sections of both leg pieces 40b, 40b are formed in a rectangular shape.
  • the above-described electromagnet device 4 generates an electromagnetic force when an excitation current is applied to the two coils 42 and 42, and the armature 6 fixed to the movable portion 24 can be attracted by the electromagnetic force. it can.
  • the magnetic pole surfaces on both sides in the overlapping direction (thickness direction) with the coil winding portion 40a are magnetized with different polarities, and one magnetic pole surface abuts on the coil winding portion 40a of the yoke 40.
  • the thickness dimension is set so that the other magnetic pole surface is located on the same plane as the tip surfaces of the leg pieces 40b, 40b of the yoke 40.
  • the above-described electromagnet device 4 is housed in the housing portion 36 in such a manner that the front end surfaces of both leg pieces 40b, 40b of the yoke 40 described later and the other magnetic pole surface of the permanent magnet 41 abut against the closing plate 32. Yes.
  • the other magnetic pole surface of the permanent magnet 41 in the electromagnet device 4 and the tip surfaces of the leg pieces 40b, 40b of the yoke 40 can be positioned on the same plane, so that there is a gap between the electromagnet device 4 and the armature 6.
  • the accuracy of the gap length can be increased.
  • the electromagnet device 4 includes a terminal block 46 in which a pair of coil terminals 45 and 45 protrude from both leg pieces 44b and 44b of a terminal holding portion 44 made of an insulating resin and having a U-shaped cross section.
  • the central piece 44a of the terminal holding portion 44 is disposed on the opposite side of the coil winding portion 40a from the permanent magnet 41 side so as to be orthogonal to the coil winding portion 40a of the yoke 40.
  • the terminals of the coils 42, 42 are connected to the coil terminals 45, 45, and a current flows through both the coils 42, 42 by applying a voltage between the pair of coil terminals 45, 45.
  • the cover substrate 3 has wiring patterns (conductor patterns) 37, 37 made of a metal film to which the coil terminals 45, 45 are electrically connected on the surface opposite to the movable part forming substrate 2 side.
  • coil terminals 45 and 45 are joined and electrically connected to one end portions of the wiring patterns 37 and 37 by soldering or the like.
  • the other end portions of the wiring patterns 37 and 37 are electrically connected to driving external connection electrodes 19 and 19 (see FIG. 7A) provided on the other surface side of the base substrate 1. Yes.
  • the wiring patterns 37 and 37 and the driving external connection electrodes 19 and 19 are energized vias 315, 215 and 115 formed in the cover substrate 3, the movable portion forming substrate 2 and the base substrate 1, respectively.
  • the via 315 of the cover substrate 3 and the via 215 of the movable part forming substrate 2 are connection metal layers (not shown) formed on the opposing surfaces of the cover substrate 3 and the movable part forming substrate 2. They are electrically connected by joining them together.
  • the via 215 of the movable part forming substrate 2 and the via 115 of the base substrate 1 are a connection metal layer (not shown) formed on the mutually facing surface side of the movable part forming substrate 2 and the base substrate 1. ) Are electrically connected by joining each other.
  • the movable contact 214 fixed to the contact holding piece 24b on one end side of the contact 24a contacts the pair of fixed contacts 14 and 14 facing the movable contact 214 with a predetermined contact pressure (that is, a pair of fixed contacts). 14 and 14 are short-circuited via the movable contact 214). Even if energization of the coils 42 and 42 is stopped in this state, the attractive force is maintained by the magnetic flux generated by the permanent magnet 41, and the state is maintained as it is.
  • the MEMS relay of the present embodiment is a polar type electromagnet device in which the electromagnet device 4 that drives the armature 6 includes a permanent magnet 41, and constitutes a latching type relay.
  • the electromagnet device 4 a non-polar electromagnet device that does not include the permanent magnet 41 may be used.
  • the via hole 12 in which the via 15 described above is formed is formed in a tapered shape in which the opening area gradually increases from the one surface of the first substrate 10 toward the other surface. As compared with the case of forming a vertical hole in a uniform case, it can be easily formed. Further, when the via hole 12 is formed in a vertical hole shape, there is a concern that the via 15 cannot be formed inside the via hole 12. On the other hand, if the via hole 12 is formed in a tapered shape, the via 15 is formed by a manufacturing process in which the seed layer for plating is formed by sputtering or the like and then the via 15 is formed by electroplating. be able to.
  • the thickness of the first substrate 10 is not particularly limited, but may be set as appropriate within a range of about 200 ⁇ m to 1000 ⁇ m, for example.
  • the tapered via hole 12 is formed in the first substrate 10, the area occupied by the via hole 12 in a plan view becomes large, and the miniaturization of the MEMS relay is limited.
  • FIGS. 10A to 10D if the via hole 12 has a shape in which the opening area gradually decreases from the both sides in the thickness direction of the first substrate 10 toward the specified intermediate position.
  • the area occupied by the via hole 12 can be reduced, and the MEMS relay can be reduced in size.
  • 10 (a) and FIGS. 10 (b), (c), and (d) are different in the shape of the via hole 12, and FIG. 10 (b), FIG. 10 (c), and FIG. Are different in the shape of the via 15.
  • 10A to 10D has a circular opening shape, and the minimum diameter is set in a range of about 20 ⁇ m to 150 ⁇ m, and the maximum diameter is set in a range of about 150 ⁇ m to 500 ⁇ m. It does not specifically limit to these numerical values.
  • the specified intermediate position having the minimum diameter is biased to one side in the thickness direction of the first substrate 10, whereas FIGS.
  • the specified intermediate position that is the minimum diameter is substantially the center in the thickness direction of the first substrate 10, and therefore the maximum diameter is made smaller than in the case of FIG. Can do.
  • FIG. 10C since the via hole 12 is filled with the via 15, airtightness can be ensured.
  • FIG. 10D since the via hole 12 is closed only in the vicinity of a prescribed intermediate position that is the minimum diameter of the via hole 12, the inner peripheral surface of the via hole 12 and the via 15 are caused by thermal stress. It is possible to suppress the formation of a gap between them, and to improve the heat stress resistance.
  • the via 15 In order to form the via 15 as shown in FIG. 10 (b), first, sandblasting is performed on the first substrate 10 from the one surface side and the other surface side of the first substrate 10, respectively. A via hole 12 is formed (see FIG. 11A). Thereafter, a metal layer 171 made of a metal material (for example, Cu, Au, etc.) used as a seed layer for electroplating is sputtered on the one surface and the other surface of the first substrate 10 and the inner surface of the via hole 12. It forms by a vapor deposition method, an electroless plating method, etc. (refer FIG.11 (b)). Subsequently, the via 15 may be formed by electroplating using the metal layer 171 as a seed layer (see FIG. 11C).
  • a metal material for example, Cu, Au, etc.
  • the thickness of the metal layer 171 may be set as appropriate within a range of about 0.01 ⁇ m to 1 ⁇ m.
  • via holes 12 are formed by dry etching, and then a silicon oxide film is formed on both surfaces of the silicon substrate and the inner surfaces of the via holes 12 by a thermal oxidation method or the like. After that, an insulating film made of a metal layer 171 may be formed.
  • the first substrate 10 is subjected to sandblasting from the one surface side and the other surface side of the first substrate 10.
  • a via hole 12 is formed (see FIG. 12A).
  • a metal layer 171 serving as a seed layer for electroplating is formed on the one surface and other surface of the first substrate 10 and the inner surface of the via hole 12 by sputtering, vapor deposition, electroless plating, or the like.
  • a fourth substrate 173 is prepared in which a metal layer 172 serving as a seed layer for electroplating is formed by sputtering, vapor deposition, electroless plating, or the like (see FIG. 12B).
  • the fourth substrate 173 is bonded to the first substrate 10 (see FIG. 12C).
  • the via 15 is formed by electroplating using the metal layers 171 and 172 as seed layers (see FIG. 12D), and then the fourth substrate 173 is peeled off from the first substrate 10 (FIG. 12). (See (e)).
  • a via hole 12 is formed by dry etching, and then both sides of the silicon substrate and the via hole 12 are formed by a thermal oxidation method or the like.
  • An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
  • via holes 12 are formed in the first substrate 10 by performing sandblasting from the one surface side and the other surface side of the first substrate 10 (see FIG. 13A). Thereafter, a metal layer 171 serving as a seed layer for electroplating is formed on the one surface of the first substrate 10 and the inner surface of the tapered portion on the one surface side of the via hole 12 by a sputtering method, a vapor deposition method, or the like. It is formed by an electrolytic plating method or the like (see FIG. 13B). Subsequently, a conductor portion 15a constituting a part of the via 15 is formed by a first electroplating step in which electroplating is performed using the metal layer 171 as a seed layer (see FIG. 13C).
  • a metal layer 181 serving as a seed layer for electroplating is formed on the other surface of the first substrate 10 and the inner surface of the tapered portion on the other surface side of the via hole 12 by a sputtering method, a vapor deposition method, or the like. It is formed by an electrolytic plating method or the like (see FIG. 13D). Subsequently, a conductor portion 15b constituting a part of the via 15 is formed by a second electroplating process in which electroplating is performed using the metal layer 181 as a seed layer (see FIG. 13E).
  • a conductor portion 15c that forms the via 15 together with the conductor portions 15a and 15b on the inner surface of the via hole 12 and closes the via hole 12 is formed (see FIG. 13F).
  • a via hole 12 is formed by dry etching, and then both sides of the silicon substrate and the via hole 12 are formed by a thermal oxidation method or the like.
  • An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
  • a copper plating solution for via filling in which a plating accelerator and a plating inhibitor are added to a copper sulfate plating solution is used.
  • the plating accelerator has a function of adhering to the surfaces of the metal layers 171 and 181 inside the via hole 12 to promote plating
  • the plating inhibitor is the one surface side of the first substrate 10. On the other surface side, it has a function of adhering to the surfaces of the metal layers 171 and 181 and suppressing plating. Therefore, by adding a plating accelerator and a plating inhibitor as additives in the plating solution, the thickness of the conductor portions 15a, 15b, 15c formed inside the via hole 12 by the action of these additives is increased.
  • the plating accelerator bis (3-sulfopropyl) disulfide (SPS) is used as the plating accelerator, and polyethylene glycol (PEG) having a molecular weight of 3000 to 8000 is used as the plating accelerator.
  • SPS bis (3-sulfopropyl) disulfide
  • PEG polyethylene glycol
  • these materials are particularly limited. Not what you want.
  • the effect by a plating accelerator and a plating inhibitor can be heightened by speeding up the speed which stirs the copper plating solution for via filling.
  • via holes 12 are formed in the first substrate 10 by performing sandblasting from the one surface side and the other surface side of the first substrate 10 (see FIG. 14A). Thereafter, a metal layer 171 serving as a seed layer for electroplating is formed on the one surface and other surface of the first substrate 10 and the inner surface of the via hole 12 by sputtering, vapor deposition, electroless plating, or the like ( (Refer FIG.14 (b)). Subsequently, by performing an electroplating process using a copper plating solution for via filling, conductor portions 15a and 15b constituting a part of the via 15 are formed (see FIG. 14C), and subsequently, electroplating is performed.
  • the via 15 is formed together with the conductors 15a and 15b on the inner surface of the via hole 12, and the conductor 15c for closing the via hole 12 is formed (see FIG. 14D).
  • the minimum diameter of the via hole 12 can be reduced in order to shorten the electroplating time and to close the via hole 12 with a smaller amount of copper plating. preferable.
  • the via holes 12 are formed by dry etching, and then both sides of the silicon substrate and the via holes 12 are formed by a thermal oxidation method or the like. An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
  • a bottomed hole (concave portion) 12a is formed in the first substrate 10 by performing sandblasting from the one surface side of the first substrate 10 to a predetermined depth corresponding to the prescribed intermediate position (see FIG. 15 (a)).
  • a metal layer 172 serving as a seed layer for electroplating is formed on the one surface of the first substrate 10 and the inner surface of the bottomed hole 12a by sputtering, vapor deposition, electroless plating, or the like (FIG. 15B). )reference).
  • a conductor portion 15f constituting a part of the via 15 is formed by a first electroplating step in which electroplating is performed using the metal layer 172 as a seed layer (see FIG.
  • a portion of the first substrate 10 that overlaps the bottomed hole 12a on the other surface is sandblasted until the conductor portion 15f is exposed from the other surface, thereby forming the via hole 12 together with the bottomed hole 12a.
  • 12b is formed on the first substrate 10 (see FIG. 15D).
  • a metal layer 182 serving as a seed layer for electroplating is formed on the other surface of the first substrate 10 and the inner surface of the tapered portion on the other surface side of the via hole 12 by sputtering, vapor deposition, It is formed by an electrolytic plating method or the like (see FIG. 15 (e)).
  • a conductor portion 15g constituting the via 15 is formed together with the above-described conductor portion 15f by a second electroplating step in which electroplating is performed using the metal layer 182 as a seed layer (see FIG. 15F).
  • a pair of signal lines 13 and 13 are provided at both ends in the longitudinal direction on the one surface side of the base substrate 1, and the intermediate substrate (movable portion forming substrate) 2 is provided.
  • the opening portion 22 and the cavity portions 27, 27 arranged in parallel to the opening portion 22 and corresponding to the pair of signal lines 13, 13, respectively, and the communication portion for communicating the opening portion 22 with the cavity portions 27, 27.
  • 24b and the above-described structure is provided with drive means for swingably driving the movable portion 24. Therefore, it is possible to reduce transmission loss while suppressing an increase in planar size and A MEMS relay in which the ground conductor 5 surrounding the signal line 13 can be easily formed can be provided.
  • the electromagnet device is mounted on the base substrate 1 'as in the conventional example shown in FIGS. Since the distance between the electromagnet device 4 and the signal lines 13 and 13 can be increased as compared with the case where the housing portion 116 ′ for housing 4 ′ is provided, transmission loss occurs due to the magnetic flux generated by the electromagnet device 4. Can be suppressed.
  • the thickness dimension of the base substrate 1 is reduced as compared with the case where the electromagnet device 4 ′ is accommodated in the base substrate 1 ′ as in the configuration shown in FIGS. Therefore, the length of the via 15 that electrically connects the signal line 13 and the external connection electrode 17 (see FIG. 1C) can be shortened, and the high-frequency characteristics can be improved.
  • the via holes 11, 11, and 12 can be reduced in size as compared with the case where the glass substrate is used.
  • the planar size of the body and the MEMS relay can be reduced, and the high frequency characteristics can be improved.
  • desired wirings first ground wirings 51 and 51, second ground wirings 52 and 52, third ground wirings 53 and 53, The vias 15
  • the manufacturing process can be simplified.

Abstract

A ground conductor comprises: first ground wirings formed on one surface side of a base substrate, and at both sides in the width direction of a signal line; second ground wirings comprised of via-holes formed on the base substrate and electrically connected to each of the first ground wirings; a third ground wiring that electrically connects the second ground wirings with each other at the other surface side of the base substrate (1), and that is parallel to the signal line; a fourth ground wiring that is formed on a cover substrate, at a face opposing the base substrate; and fifth ground wirings that are formed on an intermediate substrate (2) at both sides of a cavity section, and that are comprised of penetrating slit wirings that electrically connect each of the first ground wirings and the fourth ground wiring.

Description

配線構造を備えた構造体およびMEMSリレーStructure having wiring structure and MEMS relay
 本発明は、配線構造を備えた構造体およびMEMS(micro electro mechanicalsystems)リレーに関するものである。 The present invention relates to a structure having a wiring structure and a MEMS (micro-electromechanical mechanicals) relay.
 従来から、高周波信号伝送用のMEMSリレーとして、図16および図17に示す構成のマイクロリレーが提案されている(特許文献1参照)。このマイクロリレーは、ベース基板1’と、ベース基板1’の一表面側に配置された可動部形成基板2’と、可動部形成基板2’におけるベース基板1’側に配置されたカバー基板3’とを備えている。 Conventionally, a microrelay having a configuration shown in FIGS. 16 and 17 has been proposed as a MEMS relay for high-frequency signal transmission (see Patent Document 1). The microrelay includes a base substrate 1 ′, a movable portion forming substrate 2 ′ disposed on one surface side of the base substrate 1 ′, and a cover substrate 3 disposed on the base substrate 1 ′ side of the movable portion forming substrate 2 ′. 'And features.
 ここで、ベース基板1’は、上記一表面側において長手方向の両端部それぞれに各一対の信号線13’,13’が設けられている。また、可動部形成基板2’は、ベース基板1’の上記一表面側に固着される矩形枠状のフレーム部21’と、フレーム部21’の内側に配置されて4本の支持ばね部224’を介してフレーム部21’に揺動自在に支持された可動部24’とを有している。また、可動部形成基板2’は、可動部24’にそれぞれ2本の接圧ばね部225’を介して支持された接点保持片226’を有し、この接点保持部226’に、一対の信号線13’,13’の各一端部の固定接点14’,14’に接離する可動接点(図示せず)が設けられている。また、カバー基板3’は、周部がフレーム部21’に固着されている。なお、ベース基板1’およびカバー基板3’は、ガラス基板を用いて形成され、可動部形成基板2’は、シリコン基板を用いて形成されている。 Here, the base substrate 1 ′ is provided with a pair of signal lines 13 ′ and 13 ′ at both ends in the longitudinal direction on the one surface side. In addition, the movable part forming substrate 2 ′ includes a rectangular frame-shaped frame part 21 ′ fixed to the one surface side of the base substrate 1 ′, and four support spring parts 224 disposed inside the frame part 21 ′. And a movable portion 24 ′ that is swingably supported by the frame portion 21 ′. Further, the movable part forming substrate 2 ′ has contact holding pieces 226 ′ supported by the movable part 24 ′ via two contact pressure spring parts 225 ′, and the contact holding part 226 ′ has a pair of contact holding pieces 226 ′. Movable contacts (not shown) that are in contact with and away from the fixed contacts 14 ′ and 14 ′ at one end portions of the signal lines 13 ′ and 13 ′ are provided. Further, the peripheral portion of the cover substrate 3 ′ is fixed to the frame portion 21 ′. The base substrate 1 ′ and the cover substrate 3 ′ are formed using a glass substrate, and the movable part forming substrate 2 ′ is formed using a silicon substrate.
 上述のマイクロリレーは、ベース基板1’に、電磁石装置4’を収納する収納部116’が形成されている。この電磁石装置4’は、ヨーク40’に巻回されたコイル42’,42’への励磁電流に応じて磁束を発生する。一方、可動部形成基板2’における可動部24’のベース基板1’側に、電磁石装置4’により揺動自在に駆動されるアーマチュア(図示せず)が積層されている。 In the above-described micro relay, a storage portion 116 ′ for storing the electromagnet device 4 ′ is formed on the base substrate 1 ′. The electromagnet device 4 'generates a magnetic flux in accordance with the excitation current to the coils 42' and 42 'wound around the yoke 40'. On the other hand, an armature (not shown) that is driven to swing freely by the electromagnet device 4 ′ is laminated on the base substrate 1 ′ side of the movable portion 24 ′ in the movable portion forming substrate 2 ′.
 ところで、上述のマイクロリレーにおいて、信号線13’を含む配線構造を備えた構造体に関して、マイクロストリップ型線路やコプレーナ型線路に比べて高周波信号の伝送損失を低減する目的で、図18に示すように、信号線13’を囲む接地導体5’をベース基板1’と可動部形成基板2’とカバー基板3’とに亘って形成した配線構造を採用することが考えられる。 By the way, in the above-described micro relay, a structure having a wiring structure including a signal line 13 ′ is shown in FIG. 18 for the purpose of reducing transmission loss of a high frequency signal as compared with a microstrip type line or a coplanar type line. In addition, it is conceivable to employ a wiring structure in which the ground conductor 5 ′ surrounding the signal line 13 ′ is formed across the base substrate 1 ′, the movable part forming substrate 2 ′, and the cover substrate 3 ′.
特開2005-216541号公報JP 2005-216541 A
 ところで、図18に示した構成の配線構造を備えた構造体では、3枚の基板(ベース基板1’、可動部形成基板2’、カバー基板3’)のうち真ん中の基板(中間基板)である可動部形成基板2’に、ベース基板1’の上記一表面上の信号線13’を露出させる空洞部27’を、垂直深堀が可能な異方性エッチングにより形成してある。また、接地導体5’を、ベース基板1’の上記一表面上で信号線13’の幅方向の両側に配置された第1のグラウンド配線51’,51’と、ベース基板1’に設けられて各第1のグラウンド配線51’,51’に電気的に接続されるビアからなる第2のグラウンド配線52’,52’と、ベース基板1’の他表面上に配置され第2のグラウンド配線52’,52’同士を電気的に接続する第3のグラウンド配線53’と、カバー基板3’におけるベース基板1’との対向面側で平面視において信号線13’と当該信号線13’の両側の第1のグラウンド配線51’,51’とに跨る幅寸法を有する第4のグラウンド配線54’と、可動部形成基板2’において空洞部27’の壁面28’,28’に配置され各第1のグラウンド配線51’,51’と第4のグラウンド配線54’とを電気的に接続する第5のグラウンド配線55’,55’とで構成してある。 By the way, in the structure having the wiring structure having the configuration shown in FIG. 18, the middle substrate (intermediate substrate) among the three substrates (base substrate 1 ′, movable portion forming substrate 2 ′, and cover substrate 3 ′). A cavity 27 ′ that exposes the signal line 13 ′ on the one surface of the base substrate 1 ′ is formed on a certain movable portion forming substrate 2 ′ by anisotropic etching that enables vertical deep drilling. In addition, the ground conductor 5 ′ is provided on the base substrate 1 ′ and the first ground wirings 51 ′ and 51 ′ disposed on both sides in the width direction of the signal line 13 ′ on the one surface of the base substrate 1 ′. Second ground wirings 52 ′, 52 ′ made of vias electrically connected to the first ground wirings 51 ′, 51 ′, and second ground wirings disposed on the other surface of the base substrate 1 ′. The signal line 13 ′ and the signal line 13 ′ in plan view on the side facing the base substrate 1 ′ in the cover substrate 3 ′ and the third ground wiring 53 ′ that electrically connects 52 ′ and 52 ′. A fourth ground wiring 54 ′ having a width straddling the first ground wirings 51 ′, 51 ′ on both sides, and the wall portions 28 ′, 28 ′ of the cavity 27 ′ on the movable part forming substrate 2 ′ are arranged. First ground wiring 51 ′, 1 'and the fourth ground wiring 54' fifth ground wire 55 for electrically connecting the '55' are constructed out with.
 しかしながら、図18に示した構成では、可動部形成基板2’において空洞部27’の壁面28’,28’とベース基板1’の上記一表面とのなす角度が略90度となっているので、第5のグラウンド配線55’,55’を形成するのが難しかった。そこで、壁面28’,28’を傾斜面とすることも考えられるが、構造体の平面サイズが大型化してしまい、MEMSリレーの平面サイズが大型化してしまうという問題がある。 However, in the configuration shown in FIG. 18, in the movable part forming substrate 2 ′, the angle formed between the wall surfaces 28 ′, 28 ′ of the cavity 27 ′ and the one surface of the base substrate 1 ′ is approximately 90 degrees. It was difficult to form the fifth ground wirings 55 ′ and 55 ′. Thus, although it is conceivable that the wall surfaces 28 ′ and 28 ′ are inclined surfaces, there is a problem that the planar size of the structure is increased and the planar size of the MEMS relay is increased.
 本発明は上記事由に鑑みて為されたものであり、その目的は、構造体の平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ信号線を囲む接地導体の形成が容易な配線構造を備えた構造体およびMEMSリレーを提供することにある。 The present invention has been made in view of the above reasons, and its purpose is to form a grounding conductor that can reduce transmission loss while suppressing an increase in the planar size of the structure and surrounds a signal line. It is an object of the present invention to provide a structure and a MEMS relay having an easy wiring structure.
 本発明の配線構造を備えた構造体は、信号線が一表面側に形成されたベース基板と、ベース基板の一表面側に対向配置されたカバー基板と、ベース基板とカバー基板との間に介在し信号線を露出させる空洞部が厚み方向に貫設された中間基板と、ベース基板と中間基板とカバー基板とに亘って形成され信号線を囲む接地導体とを備え、当該接地導体は、ベース基板の前記一表面側において信号線の幅方向の両側で信号線に並行する第1のグラウンド配線と、ベース基板に形成されて各第1のグラウンド配線に電気的に接続され信号線に並行するビアからなる第2のグラウンド配線と、ベース基板の他表面側において第2のグラウンド配線同士を電気的に接続し信号線に並行する第3のグラウンド配線と、カバー基板におけるベース基板との対向面側で平面視において信号線と当該信号線の両側の第1のグラウンド配線とに跨る幅寸法を有する第4のグラウンド配線と、中間基板において空洞部の両側に形成され各第1のグラウンド配線と第4のグラウンド配線とを電気的に接続する貫通スリット配線からなる第5のグラウンド配線とで構成されてなることを特徴とする。 A structure including a wiring structure according to the present invention includes a base substrate having a signal line formed on one surface side, a cover substrate disposed opposite to the one surface side of the base substrate, and the base substrate and the cover substrate. An intermediate substrate having a hollow portion that is interposed and exposed in the thickness direction, and a ground conductor that is formed across the base substrate, the intermediate substrate, and the cover substrate and surrounds the signal line; A first ground line parallel to the signal line on both sides in the width direction of the signal line on the one surface side of the base substrate, and formed in the base substrate and electrically connected to each first ground line and parallel to the signal line A second ground wiring comprising vias, a third ground wiring electrically connecting the second ground wirings on the other surface side of the base substrate and parallel to the signal lines, and a base substrate in the cover substrate A fourth ground wiring having a width across the signal line and the first ground wiring on both sides of the signal line in plan view on the opposite side, and the first ground formed on both sides of the cavity in the intermediate substrate It is characterized by comprising a fifth ground wiring composed of a through slit wiring that electrically connects the wiring and the fourth ground wiring.
 この配線構造を備えた構造体において、前記中間基板と前記ベース基板および前記カバー基板とは、互いの対向面に形成された金属層同士を介して接合されてなることが好ましい。 In the structure provided with this wiring structure, it is preferable that the intermediate substrate, the base substrate, and the cover substrate are bonded to each other through metal layers formed on opposing surfaces.
 この配線構造を備えた構造体において、前記中間基板と前記ベース基板および前記カバー基板とは、前記金属層同士が表面活性化接合されてなることが好ましい。 In the structure including this wiring structure, the intermediate substrate, the base substrate, and the cover substrate are preferably formed by surface activation bonding of the metal layers.
 中間基板2と第5グラウンド配線との間には、絶縁膜が設けられていることが好ましい。 It is preferable that an insulating film is provided between the intermediate substrate 2 and the fifth ground wiring.
 本発明のMEMSリレーは、前記配線構造を備えた構造体を有するMEMSリレーであって、前記ベース基板は、前記一表面側に、一対の前記信号線を有し、前記中間基板は、開口部および当該開口部に並設され前記各信号線それぞれに対応する前記空洞部および当該開口部と前記各空洞部とを連通させる連通部が形成され前記ベース基板と前記カバー基板との間に介在するフレーム部と、フレーム部の内側に配置されてフレーム部に揺動自在に支持された可動部と、可動部のうち開口部内に配置される可動部本体から延設されて一対の前記信号線それぞれに設けられた固定接点に接離する可動接点を有する接点保持片とを備え、前記構造体に、可動部を揺動自在に駆動する駆動手段が設けられてなることを特徴とする。 The MEMS relay of the present invention is a MEMS relay having a structure having the wiring structure, wherein the base substrate has a pair of the signal lines on the one surface side, and the intermediate substrate has an opening portion. In addition, the cavity portion that is provided in parallel with the opening portion and that corresponds to each of the signal lines, and a communication portion that connects the opening portion and the cavity portion are formed, and are interposed between the base substrate and the cover substrate. A frame portion, a movable portion disposed inside the frame portion and supported to be swingable by the frame portion, and a pair of the signal lines extending from the movable portion main body disposed in the opening portion of the movable portions. And a contact holding piece having a movable contact that contacts and separates from the fixed contact, and the structure is provided with drive means for driving the movable portion to be swingable.
 このMEMSリレーにおいて、前記駆動手段は、前記可動部本体における前記カバー基板側に積層された磁性材料からなるアーマチュアと、前記カバー基板に設けられ前記アーマチュアを揺動自在に駆動する電磁石装置とで構成されてなることが好ましい。 In this MEMS relay, the driving means includes an armature made of a magnetic material laminated on the cover substrate side in the movable portion main body, and an electromagnet device that is provided on the cover substrate and drives the armature to be swingable. It is preferable to be made.
 本発明の配線構造を備えた構造体においては、構造体の平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ接地導体の形成が容易になる。 In the structure having the wiring structure of the present invention, it is possible to reduce transmission loss while suppressing an increase in the planar size of the structure, and it is easy to form a ground conductor.
 本発明のMEMSリレーにおいては、平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ信号線を囲む接地導体の形成が容易なMEMSリレーを提供することができる。 In the MEMS relay of the present invention, it is possible to provide a MEMS relay that can reduce transmission loss while suppressing an increase in planar size and that can easily form a ground conductor surrounding a signal line.
実施形態における配線構造を備えた構造体を示し、(a)は要部概略平面図、(b)は(a)のA-A’概略断面図、(c)は(a)のB-B’概略断面図である。1 shows a structure including a wiring structure according to an embodiment, where (a) is a schematic plan view of a main part, (b) is a schematic cross-sectional view along AA ′ in (a), and (c) is a cross-sectional view along BB in (a). 'It is a schematic sectional view. 同上の配線構造を備えた構造体の製造方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. 同上の配線構造を備えた構造体の製造方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. 同上の配線構造を備えた構造体の製造方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. 同上の配線構造を備えた構造体の製造方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the manufacturing method of the structure provided with the wiring structure same as the above. 同上におけるMEMSリレーの概略分解斜視図である。It is a general | schematic disassembled perspective view of the MEMS relay same as the above. 同上におけるMEMSリレーを示し、(a),(b)は一部破断した概略斜視図である。The MEMS relay in the same as above is shown, (a), (b) is a schematic perspective view partly broken. 同上におけるMEMSリレーの概略斜視図である。It is a schematic perspective view of the MEMS relay same as the above. 同上におけるMEMSリレーの中間基板を示し、(a)は概略平面図、(b)は概略下面図である。The intermediate board of the MEMS relay same as the above is shown, (a) is a schematic plan view, (b) is a schematic bottom view. 同上におけるMEMSリレーの要部の他の構成例を示し、(a)~(d)は互いに異なる構成例の概略断面図である。The other example of a structure of the principal part of a MEMS relay same as the above is shown, (a)-(d) is a schematic sectional drawing of a structure example mutually different. 同上におけるMEMSリレーの要部の他の構成例の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the other structural example of the principal part of the MEMS relay same as the above. 同上におけるMEMSリレーの要部の他の構成例の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the other structural example of the principal part of the MEMS relay same as the above. 同上におけるMEMSリレーの要部の他の構成例の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the other structural example of the principal part of the MEMS relay same as the above. 同上におけるMEMSリレーの要部の他の構成例の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the other structural example of the principal part of the MEMS relay same as the above. 同上におけるMEMSリレーの要部の他の構成例の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the other structural example of the principal part of the MEMS relay same as the above. 従来例におけるMEMSリレーを示す概略分解斜視図である。It is a general | schematic disassembled perspective view which shows the MEMS relay in a prior art example. 同上におけるMEMSリレーの概略斜視図である。It is a schematic perspective view of the MEMS relay same as the above. 配線構造を備えた構造体の構成例の概略断面図である。It is a schematic sectional drawing of the structural example of the structure provided with the wiring structure.
 本実施形態では、配線構造を備えた構造体およびその形成方法について図1~5を参照しながら説明した後で、当該構造体を有するMEMSデバイスの一例であるMEMSリレーについて図6~図9を参照しながら説明する。 In the present embodiment, a structure having a wiring structure and a method for forming the structure will be described with reference to FIGS. 1 to 5, and a MEMS relay as an example of a MEMS device having the structure will be described with reference to FIGS. The description will be given with reference.
 本実施形態の配線構造を備えた構造体は、図1に示すように、信号線(伝送線路)13が一表面側に形成されたベース基板1と、ベース基板1の一表面側に対向配置されたカバー基板3と、ベース基板1とカバー基板3との間に介在し信号線13を露出させる空洞部27が厚み方向に貫設された中間基板2と、ベース基板1と中間基板2とカバー基板3とに亘って形成され信号線13を囲む接地導体5とを備えている。なお、本実施形態では、ベース基板1およびカバー基板3の外形サイズを中間基板2の外形サイズと同じ外形サイズに設定してある。 As shown in FIG. 1, the structure including the wiring structure of the present embodiment is arranged so that a base substrate 1 having a signal line (transmission line) 13 formed on one surface side is opposed to one surface side of the base substrate 1. The cover substrate 3, the intermediate substrate 2 between the base substrate 1 and the cover substrate 3, and the cavity 27 that exposes the signal line 13 is provided in the thickness direction; the base substrate 1 and the intermediate substrate 2; And a grounding conductor 5 formed over the cover substrate 3 and surrounding the signal line 13. In the present embodiment, the outer sizes of the base substrate 1 and the cover substrate 3 are set to the same outer size as that of the intermediate substrate 2.
 また、ベース基板1,中間基板2,カバー基板3は、それぞれ厚みを有している。ベース基板1,中間基板2,カバー基板3の厚みは、ベース基板1,中間基板2,カバー基板3が並べられている方向と同じである。したがって、ベース基板1,中間基板2,カバー基板3の厚み方向は、前記ベース基板1,中間基板2,カバー基板3の厚みに沿った方向として定義される。 Further, the base substrate 1, the intermediate substrate 2, and the cover substrate 3 each have a thickness. The thicknesses of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are the same as the direction in which the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are arranged. Accordingly, the thickness direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the thickness of the base substrate 1, intermediate substrate 2, and cover substrate 3.
 また、ベース基板1,中間基板2,カバー基板3は、それぞれ、長さ及び幅を有している。ベース基板1,中間基板2,カバー基板3の長さは、ベース基板1の厚み方向に直交する。したがって、ベース基板1,中間基板2,カバー基板3の長さ方向は、ベース基板1,中間基板2,カバー基板3の長さに沿った方向として定義される。また、ベース基板1,中間基板2,カバー基板3の幅は、ベース基板1の厚み方向に直交している。そして、ベース基板1,中間基板2,カバー基板3の幅は、ベース基板1の長さ方向に直交している。したがって、ベース基板1,中間基板2,カバー基板3の幅方向は、ベース基板1,中間基板2,カバー基板3の幅に沿った方向として定義される。 The base substrate 1, the intermediate substrate 2, and the cover substrate 3 have a length and a width, respectively. The lengths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the thickness direction of the base substrate 1. Therefore, the length direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the length of the base substrate 1, intermediate substrate 2, and cover substrate 3. The widths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the thickness direction of the base substrate 1. The widths of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 are orthogonal to the length direction of the base substrate 1. Therefore, the width direction of the base substrate 1, the intermediate substrate 2, and the cover substrate 3 is defined as a direction along the width of the base substrate 1, intermediate substrate 2, and cover substrate 3.
 ここにおいて、ベース基板1は、絶縁性基板の一種であるガラス基板からなる第1の基板10を用いて形成されている。第1の基板10は、ガラス基板に限らず、例えば、高抵抗率(例えば、抵抗率が100Ωcm以上)のシリコン基板や、低温同時焼成セラミック基板(Low Temperature Co-fired Ceramic Substrate:LTCC基板)を用いてもよい。なお、第1の基板10として用いるガラス基板のガラス材料としては、ソーダガラス、無アルカリガラス、石英ガラスでもよいし、パイレックス(登録商標)やテンパックス(登録商標)などの硼珪酸ガラスでもよいが、誘電率が低いガラス材料が好ましい。 Here, the base substrate 1 is formed using a first substrate 10 made of a glass substrate which is a kind of insulating substrate. The first substrate 10 is not limited to a glass substrate. For example, a silicon substrate having a high resistivity (for example, a resistivity of 100 Ωcm or more) or a low-temperature co-fired ceramic substrate (Low Temperature Co-fired Ceramic Substrate: LTCC substrate) is used. It may be used. The glass material of the glass substrate used as the first substrate 10 may be soda glass, alkali-free glass, quartz glass, or borosilicate glass such as Pyrex (registered trademark) or Tempax (registered trademark). A glass material having a low dielectric constant is preferred.
 また、信号線13は、直線状にパターニングされた金属層(例えば、Au層)により構成されている。信号線13の材料としては、Auを採用しているが、Auに限らず、例えば、Au、Ni、Cu、Pd、Rh、Pt、Ir、Osの群から選択される1種あるいはこれらの合金を採用してもよい。 Further, the signal line 13 is composed of a metal layer (for example, an Au layer) patterned in a straight line. The signal line 13 is made of Au, but is not limited to Au. For example, one type selected from the group of Au, Ni, Cu, Pd, Rh, Pt, Ir, and Os, or an alloy thereof. May be adopted.
 また、中間基板2は、半導体基板20を用いて形成されている。ここにおいて、中間基板2は、後述のようにMEMSリレーの可動部形成基板を構成するものであり、当該可動部形成基板の所望の3次元構造などに応じて、半導体基板20として、例えば、シリコン基板や、シリコン層/絶縁層(SiO2層)/シリコン層の3層構造を有するSOI(Silicon  On  Insulator)基板や、シリコン層/絶縁層(SiO2層)/シリコン層/絶縁層(SiO2層)/シリコン層の5層構造(ダブルSOI構造)を有するダブルSOI基板などを用いればよい。 The intermediate substrate 2 is formed using the semiconductor substrate 20. Here, the intermediate substrate 2 constitutes a movable part forming substrate of the MEMS relay as will be described later. As the semiconductor substrate 20 according to a desired three-dimensional structure of the movable part forming substrate, for example, silicon substrate and a silicon layer / insulating layer (SiO 2 layer) / SOI having a three-layer structure of the silicon layer and (silicon On insulator) substrate, a silicon layer / insulating layer (SiO 2 layer) / silicon layer / insulating layer (SiO 2 A double SOI substrate having a five-layer structure (double SOI structure) / layer of silicon) may be used.
 また、カバー基板3は、第2のガラス基板からなる第2の基板30を用いて形成されているが、第2の基板30は、第1の基板10と同様に、ガラス基板に限らず、高抵抗率のシリコン基板や、LTCC基板を用いてもよい。 Further, the cover substrate 3 is formed by using the second substrate 30 made of the second glass substrate, but the second substrate 30 is not limited to the glass substrate, like the first substrate 10, A high resistivity silicon substrate or LTCC substrate may be used.
 上述の接地導体5は、ベース基板1の上記一表面側において信号線13の幅方向(図1(a)の左右方向)の両側で信号線13に並行する第1のグラウンド配線51,51と、ベース基板1に形成されて各第1のグラウンド配線51,51に電気的に接続され信号線13に並行するビアからなる第2のグラウンド配線52,52と、ベース基板1の他表面側において第2のグラウンド配線52,52同士を電気的に接続し信号線13に並行する第3のグラウンド配線53と、カバー基板3におけるベース基板1との対向面側で平面視において信号線13と当該信号線13の両側の第1のグラウンド配線51,51とに跨る幅寸法を有する第4のグラウンド配線54と、中間基板2において空洞部27の両側に形成され各第1のグラウンド配線51,51と第4のグラウンド配線54とを電気的に接続する貫通スリット配線からなる第5のグラウンド配線55,55とを有している。しかして、接地導体5は、信号線13の長さ方向に直交する断面において信号線13を囲んでいる。 The ground conductor 5 described above includes first ground wirings 51 and 51 parallel to the signal line 13 on both sides in the width direction of the signal line 13 (left and right direction in FIG. 1A) on the one surface side of the base substrate 1. The second ground wirings 52 and 52 formed in the base substrate 1 and electrically connected to the first ground wirings 51 and 51 and including the vias parallel to the signal line 13, and on the other surface side of the base substrate 1 The second ground wirings 52, 52 are electrically connected to each other, the third ground wiring 53 parallel to the signal line 13, and the signal line 13 and the signal line 13 in plan view on the side of the cover substrate 3 facing the base substrate 1. A fourth ground wiring 54 having a width across the first ground wirings 51, 51 on both sides of the signal line 13, and each first ground wiring formed on both sides of the cavity 27 in the intermediate substrate 2. 51 and and a fifth ground wire 55, 55 of electrically connected to the through slit lines and the fourth ground wiring 54. Thus, the ground conductor 5 surrounds the signal line 13 in a cross section orthogonal to the length direction of the signal line 13.
 ここで、第1のグラウンド配線51,51は、信号線13と同様に、第1の基板10の一表面上に形成されている。各第1のグラウンド配線51,51は、信号線13に並行するようにパターニングされた金属層(例えば、Au層)により構成されている。第1のグラウンド配線51,51の材料としては、Auを採用しているが、Auに限らず、例えば、Al、Cuなどを採用してもよい。 Here, the first ground lines 51 and 51 are formed on one surface of the first substrate 10, similarly to the signal line 13. Each of the first ground lines 51 and 51 is configured by a metal layer (for example, an Au layer) patterned so as to be parallel to the signal line 13. As the material of the first ground wirings 51, 51, Au is adopted, but not limited to Au, for example, Al, Cu, etc. may be adopted.
 また、第2のグラウンド配線5,52は、第1の基板10の厚み方向に貫設されたビアホール11,11の内側に形成されている。第2のグラウンド配線52,52および第3のグラウンド配線53の材料としては、Cuを採用しているが、Cuに限らず、例えば、Ni、Auなどを採用してもよい。 Further, the second ground wirings 5, 52 are formed inside via holes 11, 11 penetrating in the thickness direction of the first substrate 10. The material of the second ground wirings 52 and 52 and the third ground wiring 53 is Cu, but is not limited to Cu. For example, Ni, Au, or the like may be employed.
 また、第4のグラウンド配線54は、信号線13に並行するようにパターニングされた金属層(例えば、Au層)により構成されている。第4のグラウンド配線54の材料としては、Auを採用しているが、Auに限らず、例えば、Al、Cuなどを採用してもよい。 Further, the fourth ground wiring 54 is constituted by a metal layer (for example, Au layer) patterned so as to be parallel to the signal line 13. As the material of the fourth ground wiring 54, Au is adopted. However, the material is not limited to Au, and for example, Al, Cu or the like may be adopted.
 また、第5のグラウンド配線55,55の材料としては、Cuを採用しているが、Cuに限らず、例えば、Ni、Auなどを採用してもよい。ここにおいて、第5のグラウンド配線55,55は、半導体基板20の厚み方向に貫設された貫通スリット20aの内側に形成されており、各第5のグラウンド配線55,55と貫通スリット20a,20aとの間には、半導体基板20の厚み方向の両面と貫通スリット20aの内面とに跨って形成されたシリコン酸化膜(熱酸化膜)からなる絶縁膜20bの一部が介在している。要するに、各第5のグラウンド配線55,55は、半導体基板20とは電気的に絶縁されている。また、各貫通スリット20a,20aは、信号線13の走る方向(信号線13の長手方向)に直交する断面における開口幅が、半導体基板20の厚み方向の位置によらず一様となるように形成されている。また、半導体基板20の空洞部27についても、信号線13の走る方向(信号線13の長手方向)に直交する断面における開口幅が、半導体基板20の厚み方向の位置によらず一様となるように形成されている。要するに、空洞部27は、信号線13の走る方向に直交する断面が矩形状となっている。 Further, although Cu is adopted as the material of the fifth ground wirings 55, 55, not limited to Cu, for example, Ni, Au, or the like may be adopted. Here, the fifth ground wirings 55 and 55 are formed inside the through slit 20a penetrating in the thickness direction of the semiconductor substrate 20, and the fifth ground wirings 55 and 55 and the through slits 20a and 20a are formed. A part of an insulating film 20b made of a silicon oxide film (thermal oxide film) formed across both surfaces in the thickness direction of the semiconductor substrate 20 and the inner surface of the through slit 20a is interposed therebetween. In short, the fifth ground wirings 55 and 55 are electrically insulated from the semiconductor substrate 20. In addition, the through slits 20 a and 20 a have a uniform opening width in a cross section perpendicular to the direction in which the signal line 13 runs (longitudinal direction of the signal line 13) regardless of the position in the thickness direction of the semiconductor substrate 20. Is formed. In addition, with respect to the cavity 27 of the semiconductor substrate 20, the opening width in a cross section orthogonal to the direction in which the signal line 13 runs (longitudinal direction of the signal line 13) is uniform regardless of the position in the thickness direction of the semiconductor substrate 20. It is formed as follows. In short, the cavity 27 has a rectangular cross section perpendicular to the direction in which the signal line 13 runs.
 また、第5のグラウンド配線55,55は、半導体基板20におけるベース基板1側に形成され第1のグラウンド配線51,51と接合された接続用金属層25を介して第1のグラウンド配線51,51と電気的に接続されている。ここで、半導体基板20におけるベース基板1側には、接続用金属層25,25の側方に接合用金属層26,26が形成されており、当該接合用金属層26,26がベース基板1において第1のグラウンド配線51,51の側方に形成された接合用金属層16,16と接合されている。ベース基板1の接合用金属層16,16は、第1のグラウンド配線51,51と同じ材料で、第1のグラウンド配線51,51と同時に同じ膜厚で形成されている。 Further, the fifth ground wirings 55, 55 are formed on the base substrate 1 side of the semiconductor substrate 20 and are connected to the first ground wirings 51, 51 via the connection metal layer 25. 51 is electrically connected. Here, on the base substrate 1 side of the semiconductor substrate 20, bonding metal layers 26 and 26 are formed on the sides of the connecting metal layers 25 and 25, and the bonding metal layers 26 and 26 are formed on the base substrate 1. Are joined to the joining metal layers 16 and 16 formed on the sides of the first ground wirings 51 and 51. The joining metal layers 16 and 16 of the base substrate 1 are formed of the same material as the first ground wirings 51 and 51 and have the same film thickness as the first ground wirings 51 and 51.
 また、第5のグラウンド配線55,55は、半導体基板20におけるカバー基板3側に形成され第4のグラウンド配線54と接合された接続用金属層29を介して第4のグラウンド配線54と電気的に接続されている。ここにおいて、各接続用金属層25,29および接合用金属層26は、上述の絶縁膜20bにより半導体基板20と電気的に絶縁されている。また、各接続用金属層25,29および接合用金属層26は、絶縁膜20b上に形成されたTi膜と当該Ti膜上に形成されたAu膜との積層膜により構成されており、半導体基板20におけるベース基板1側の接続用金属層25と接合用金属層26とが同時に形成されている。なお、本実施形態では、絶縁膜20b上のTi膜の膜厚を15~50nm、Ti膜上のAu膜の膜厚を500nmに設定してあるが、これらの数値は一例であって特に限定するものではない。また、各Au膜と絶縁膜20bとの間に密着性改善用の密着層としてTi膜を介在させてあるが、密着層の材料はTiに限らず、例えば、Cr、Nb、Zr、TiN、TaNなどでもよい。また、接続用金属層25および接合用金属層26は、Au膜の代わりに、Al膜やCu膜を採用してもよい。 The fifth ground wirings 55 and 55 are electrically connected to the fourth ground wiring 54 via a connection metal layer 29 formed on the cover substrate 3 side of the semiconductor substrate 20 and joined to the fourth ground wiring 54. It is connected to the. Here, each of the connecting metal layers 25 and 29 and the bonding metal layer 26 is electrically insulated from the semiconductor substrate 20 by the above-described insulating film 20b. Each of the connecting metal layers 25 and 29 and the bonding metal layer 26 is composed of a laminated film of a Ti film formed on the insulating film 20b and an Au film formed on the Ti film. A connecting metal layer 25 and a bonding metal layer 26 on the base substrate 1 side of the substrate 20 are formed simultaneously. In this embodiment, the thickness of the Ti film on the insulating film 20b is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Further, although a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 20b, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. The connecting metal layer 25 and the bonding metal layer 26 may employ an Al film or a Cu film instead of the Au film.
 ところで、本実施形態では、上述の信号線13が、第1の基板10の厚み方向に貫設されたビア15と電気的に接続されている。ここで、信号線13が接合されるビア15は、第1の基板10の厚み方向に貫設された平面視円形状のビアホール12の内側に形成されており、第1の基板10の他表面側で、ビアホール12の周部に形成された外部接続電極17と電気的に接続されている。また、本実施形態では、信号線13が当該信号線13の長手方向の一端部でビア15と接続されているが、他端部に接続されるビアを形成してもよい。 By the way, in the present embodiment, the signal line 13 described above is electrically connected to the via 15 penetrating in the thickness direction of the first substrate 10. Here, the via 15 to which the signal line 13 is bonded is formed inside a via hole 12 having a circular shape in plan view and penetrating in the thickness direction of the first substrate 10, and the other surface of the first substrate 10. On the side, it is electrically connected to the external connection electrode 17 formed on the periphery of the via hole 12. In the present embodiment, the signal line 13 is connected to the via 15 at one end in the longitudinal direction of the signal line 13, but a via connected to the other end may be formed.
 以下、上述の配線構造を備えた構造体の形成方法について図2~図5を参照しながら説明するが、各図の(a)~(d)は図1(a)のB-B’断面に対応する部分の概略断面を示している。 Hereinafter, a method for forming a structure having the above-described wiring structure will be described with reference to FIGS. 2 to 5. FIGS. (A) to (d) are cross-sectional views taken along the line BB ′ of FIG. The schematic cross section of the part corresponding to is shown.
 まず、図2(a)に示すようなガラス基板からなる第1の基板10を用意し、その後、第1の基板10の厚み方向に貫通するビアホール11,11,12を第1の基板10の他表面側からサンドブラスト法などにより形成するビアホール形成工程を行うことによって、図2(b)に示す構造を得る。ここで、ビアホール11,11,12の形成方法は、サンドブラスト法に限らず、例えば、レーザ加工、機械加工、エッチングでもよい。なお、第1の基板10として、シリコン基板を用いている場合には、フォトリソグラフィ技術およびエッチング技術を利用してビアホール11,11,12を形成すればよい。 First, a first substrate 10 made of a glass substrate as shown in FIG. 2 (a) is prepared, and then via holes 11, 11, 12 penetrating in the thickness direction of the first substrate 10 are formed on the first substrate 10. A structure shown in FIG. 2B is obtained by performing a via hole forming process formed by sandblasting or the like from the other surface side. Here, the formation method of the via holes 11, 11, and 12 is not limited to the sandblast method, and may be laser processing, machining, or etching, for example. In the case where a silicon substrate is used as the first substrate 10, the via holes 11, 11, and 12 may be formed using a photolithography technique and an etching technique.
 上述のビアホール形成工程の後、第2のグラウンド配線52,52、第3のグラウンド配線53、ビア15および外部接続電極17の基礎となりビアホール11,11,12を閉塞する金属材料(例えば、Cu、Ni、Auなど)からなる金属部170を、第1の基板10のビアホール11,11,12の内面および第1の基板10の上記他表面に、めっき法により形成するめっき工程を行うことによって、図2(c)に示す構造を得る。 After the above-described via hole forming step, the second ground wirings 52 and 52, the third ground wiring 53, the via 15 and the metal material (for example, Cu, which closes the via holes 11, 11 and 12 serving as the basis of the external connection electrode 17). By performing a plating step of forming a metal part 170 made of Ni, Au, etc. on the inner surfaces of the via holes 11, 11, 12 of the first substrate 10 and the other surface of the first substrate 10 by a plating method, The structure shown in FIG.
 その後、金属部170のうち第1の基板10の上記他表面側(裏面側)の不要部をエッチング除去することで、それぞれ金属部170の一部からなる第2のグラウンド配線52,52、第3のグラウンド配線53およびビア15を形成する裏面側パターニング工程を行うことによって、図2(d)に示す構造を得る。この裏面側パターニング工程により形成されたビア15は、第2のグラウンド配線52,52および第3のグラウンド配線53から分離されている。なお、ビア15は、第1の基板10の上記他表面におけるビアホール12の周部の外部接続電極17と連続一体に形成されている。 Thereafter, unnecessary portions on the other surface side (back surface side) of the first substrate 10 in the metal portion 170 are removed by etching, whereby second ground wirings 52 and 52 each including a part of the metal portion 170, The structure shown in FIG. 2D is obtained by performing the back surface side patterning process for forming the third ground wiring 53 and the via 15. The via 15 formed by this back surface side patterning process is separated from the second ground wirings 52 and 52 and the third ground wiring 53. The via 15 is formed continuously and integrally with the external connection electrode 17 on the periphery of the via hole 12 on the other surface of the first substrate 10.
 上述の裏面側パターニング工程の後、第1の基板10の上記一表面側に、第1のグラウンド配線51,51および接合用金属層16,16の基礎となるAu層などからなる金属層(以下、第1の金属層と称する)18を例えばスパッタ法や蒸着法などによって形成する金属層形成工程(以下、第1の金属層形成工程と称する)を行うことによって、図3(a)に示す構造を得る。 After the back side patterning step described above, a metal layer (hereinafter referred to as an Au layer or the like serving as a basis for the first ground wirings 51 and 51 and the bonding metal layers 16 and 16 is formed on the one surface side of the first substrate 10. 3 (a) is performed by performing a metal layer forming step (hereinafter referred to as a first metal layer forming step) for forming 18 by a sputtering method or a vapor deposition method, for example. Get the structure.
 その後、第1の金属層18のうち第1の基板10の上記一表面側(表面側)の不要部をエッチング除去することで、それぞれ第1の金属層18の一部からなる第1のグラウンド配線51,51および接合用金属層16,16を形成する裏面側パターニング工程を行うことによって、図3(b)に示す構造を得る。 Thereafter, unnecessary portions on the one surface side (surface side) of the first substrate 10 in the first metal layer 18 are removed by etching, whereby first grounds each consisting of a part of the first metal layer 18 are obtained. The structure shown in FIG. 3B is obtained by performing a back surface side patterning process for forming the wirings 51 and 51 and the bonding metal layers 16 and 16.
 次に、第1の基板10の上記一表面側に、信号線13の形成予定領域に対応する部位が開口されたレジスト層119を形成し、金属材料(例えば、Auなど)からなる信号線13をめっき法により形成することによって、図3(c)に示す構造を得てから、レジスト層119を除去することによって、図3(d)に示す構造のベース基板1を得る。なお、信号線13の形成方法は、めっき法に限らず、例えば、リフトオフ法を利用して形成してもよい。 Next, a resist layer 119 having an opening corresponding to a region where the signal line 13 is to be formed is formed on the one surface side of the first substrate 10, and the signal line 13 made of a metal material (for example, Au) is formed. 3 is obtained by plating, and after obtaining the structure shown in FIG. 3C, the resist layer 119 is removed to obtain the base substrate 1 having the structure shown in FIG. The method for forming the signal line 13 is not limited to the plating method, and for example, the signal line 13 may be formed using a lift-off method.
 一方、中間基板2の形成にあたっては、まず、図4(a)に示すような半導体基板20を用意し、その後、フォトリソグラフィ技術およびエッチング技術などを利用して、半導体基板20の厚み方向に貫通する貫通スリット20a,20aを形成する貫通スリット形成工程を行うことによって、図4(b)に示す構造を得る。ここにおいて、貫通スリット形成工程での半導体基板20のエッチングは、例えば、誘導結合プラズマ(ICP)型のエッチング装置などの異方性の高いエッチングが可能(垂直深堀が可能)なドライエッチング装置により行えばよい。 On the other hand, in forming the intermediate substrate 2, first, a semiconductor substrate 20 as shown in FIG. 4A is prepared, and then the semiconductor substrate 20 is penetrated in the thickness direction by using a photolithography technique and an etching technique. By performing the through slit forming step of forming the through slits 20a, 20a, the structure shown in FIG. 4B is obtained. Here, the etching of the semiconductor substrate 20 in the through slit forming step is performed by a dry etching apparatus capable of highly anisotropic etching (perpendicular deep drilling) such as an inductively coupled plasma (ICP) type etching apparatus. Just do it.
 上述の貫通スリット形成工程の後、半導体基板20の一表面および他表面と各貫通スリット20a,20aの内面とに跨るシリコン酸化膜(熱酸化膜)からなる絶縁膜20bを熱酸化法により形成する絶縁膜形成工程を行ってから、貫通スリット配線からなる第5のグラウンド配線55,55をめっき法により形成する貫通スリット配線形成工程を行うことによって、図4(c)に示す構造を得る。この貫通スリット配線形成工程では、各貫通スリット20a,20aの内側が絶縁膜20bの一部および金属材料(例えば、Cu、Ni、Auなど)からなる第5のグラウンド配線55,55により充実されて閉塞されるように、第5のグラウンド配線55,55を形成している。 After the above-described through slit forming step, an insulating film 20b made of a silicon oxide film (thermal oxide film) straddling one surface and the other surface of the semiconductor substrate 20 and the inner surfaces of the through slits 20a and 20a is formed by a thermal oxidation method. After performing the insulating film forming process, the structure shown in FIG. 4C is obtained by performing the through slit wiring forming process of forming the fifth ground wiring 55, 55 made of the through slit wiring by a plating method. In this through slit wiring forming step, the inside of each through slit 20a, 20a is enriched by a part of the insulating film 20b and the fifth ground wiring 55, 55 made of a metal material (for example, Cu, Ni, Au, etc.). The fifth ground wirings 55 and 55 are formed so as to be blocked.
 その後、半導体基板20の上記一表面側の全面に接続用金属層29の基礎となるTi膜とAu膜との積層膜からなる金属層(以下、第2の金属層と称する)290をスパッタ法や蒸着法やCVD法などにより形成するとともに、半導体基板20の上記他表面側の全面に接続用金属層25,25および接合用金属層26,26の基礎となるTi膜とAu膜との積層膜からなる金属層(以下、第3の金属層と称する)250をスパッタ法や蒸着法やCVD法などにより形成する第2の金属層形成工程を行うことによって、図4(d)に示す構造を得る。 Thereafter, a metal layer (hereinafter, referred to as a second metal layer) 290 formed of a laminated film of a Ti film and an Au film serving as a base of the connection metal layer 29 is applied to the entire surface of the semiconductor substrate 20 on the one surface side by a sputtering method. And a lamination of a Ti film and an Au film serving as a basis for the connection metal layers 25 and 25 and the bonding metal layers 26 and 26 over the entire surface of the semiconductor substrate 20 on the other surface side. A structure shown in FIG. 4D is obtained by performing a second metal layer forming step of forming a metal layer (hereinafter referred to as a third metal layer) 250 made of a film by sputtering, vapor deposition, CVD, or the like. Get.
 その後、半導体基板20の上記一表面側の第2の金属層290のうち接続用金属層29,29それぞれに対応する部位が残るようにフォトリソグラフィ技術およびエッチング技術を利用して第2の金属層290をパターニングするとともに、半導体基板20の上記他表面側の第3の金属層250のうち接続用金属層25,25および接合用金属層26,26それぞれに対応する部位が残るようにフォトリソグラフィ技術およびエッチング技術を利用して第3の金属層250をパターニングする第2の金属層パターニング工程を行うことによって、図5(a)に示す構造を得る。 Thereafter, the second metal layer using the photolithography technique and the etching technique is left so that portions corresponding to the connection metal layers 29 and 29 of the second metal layer 290 on the one surface side of the semiconductor substrate 20 remain. 290 is patterned, and the photolithography technique is performed so that portions corresponding to the connection metal layers 25 and 25 and the bonding metal layers 26 and 26 remain in the third metal layer 250 on the other surface side of the semiconductor substrate 20. And the structure shown in FIG. 5A is obtained by performing a second metal layer patterning step of patterning the third metal layer 250 using an etching technique.
 その後、半導体基板20の上記一表面側にフォトリソグラフィ技術を利用して空洞部形成用に形成したマスク層270をマスクとして、半導体基板20を上記一表面側からエッチングすることにより空洞部27を形成する空洞部形成工程を行い、マスク層270を除去することによって、図5(b)に示す構造を得る。ここにおいて、空洞部形成工程での半導体基板20のエッチングは、例えば、誘導結合プラズマ(ICP)型のエッチング装置などの異方性の高いエッチングが可能(垂直深堀が可能)なドライエッチング装置により行えばよい。 Thereafter, the cavity 27 is formed by etching the semiconductor substrate 20 from the one surface side using the mask layer 270 formed for forming the cavity using the photolithography technique on the one surface side of the semiconductor substrate 20 as a mask. The cavity portion forming step is performed, and the mask layer 270 is removed to obtain the structure shown in FIG. Here, the etching of the semiconductor substrate 20 in the cavity forming step is performed by a dry etching apparatus capable of highly anisotropic etching (perpendicular deep drilling) such as an inductively coupled plasma (ICP) type etching apparatus. Just do it.
 上述の空洞部形成工程の後、中間基板2と、第2の基板30の一表面側(中間基板2側)に第4のグラウンド配線54が形成されたカバー基板3とを接合する第1の接合工程を行うことによって、図5(c)に示す構造を得る。ここで、第1の接合工程では、中間基板2の接続用金属層29とカバー基板3の第4のグラウンド配線54とが接合されて電気的に接続される。 After the cavity forming step described above, the first intermediate substrate 2 is bonded to the cover substrate 3 on which the fourth ground wiring 54 is formed on one surface side (the intermediate substrate 2 side) of the second substrate 30. By performing the bonding step, the structure shown in FIG. 5C is obtained. Here, in the first bonding step, the connection metal layer 29 of the intermediate substrate 2 and the fourth ground wiring 54 of the cover substrate 3 are bonded and electrically connected.
 上述の第1の接合工程の後、中間基板2とベース基板1とを接合する第2の接合工程を行うことによって、図5(d)に示す配線構造を備えた構造体が得られる。ここで、第2の接合工程では、中間基板2の接合用金属層26とベース基板1の接合用金属層16とが接合されるとともに、中間基板2の接続用金属層25とベース基板1の第1のグラウンド配線51とが接合されて電気的に接続される。 After the first bonding step described above, a second bonding step for bonding the intermediate substrate 2 and the base substrate 1 is performed to obtain a structure having the wiring structure shown in FIG. Here, in the second bonding step, the bonding metal layer 26 of the intermediate substrate 2 and the bonding metal layer 16 of the base substrate 1 are bonded, and the connection metal layer 25 of the intermediate substrate 2 and the base substrate 1 are bonded. The first ground wiring 51 is joined and electrically connected.
 上述の第1の接合工程、第2の接合工程では、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、常温(例えば、25℃)下で直接接合する常温接合法を採用しているので、接合時のベース基板1、中間基板2、カバー基板3の膨張収縮や応力などを大幅に低減することができる。なお、第1の接合工程、第2の接合工程は、常温接合法に限らず、上述の各接合表面の正常化・活性化を行ってから、接合表面を接触させ常温よりも高い規定温度(例えば、80℃)で直接接合するようにしてもよい。 In the first bonding step and the second bonding step described above, each bonding surface is cleaned and activated by irradiating the bonding surfaces with argon plasma, ion beam or atomic beam in vacuum before bonding. Then, the bonding surfaces are brought into contact with each other, and a room temperature bonding method in which the bonding surfaces are directly bonded at a normal temperature (for example, 25 ° C.) is employed. Stress and the like can be greatly reduced. Note that the first bonding step and the second bonding step are not limited to the normal temperature bonding method, and after normalizing and activating each of the bonding surfaces described above, the bonding surfaces are brought into contact with each other and a specified temperature (normal temperature higher than normal temperature) ( For example, you may make it join directly at 80 degreeC.
 ところで、本実施形態における配線構造を備えた構造体を有するMEMSリレーの製造方法では、第2の接合工程が終了するまでの全工程を中間基板2、ベース基板1およびカバー基板3それぞれについてウェハレベルで行うことでMEMSリレーを複数備えたウェハレベルパッケージ構造体を形成するようにし、当該ウェハレベルパッケージ構造体から個々のMEMSリレーに分割する分割工程を行うようにしている。しかして、ベース基板1およびカバー基板3の外形サイズを中間基板2の外形サイズに容易に合わせることができるとともに、量産性を高めることができる。 By the way, in the manufacturing method of the MEMS relay having the structure provided with the wiring structure in the present embodiment, all the processes until the second bonding process is completed are performed for each of the intermediate substrate 2, the base substrate 1 and the cover substrate 3 at the wafer level. In this way, a wafer level package structure including a plurality of MEMS relays is formed, and a dividing step of dividing the wafer level package structure into individual MEMS relays is performed. Thus, the outer sizes of the base substrate 1 and the cover substrate 3 can be easily adjusted to the outer size of the intermediate substrate 2, and mass productivity can be improved.
 以上説明した本実施形態の配線構造を備えた構造体では、信号線13を囲む接地導体5が、ベース基板1の上記一表面側において信号線13の幅方向の両側で信号線13に並行する第1のグラウンド配線51,51と、ベース基板1に形成されて各第1のグラウンド配線51,51に電気的に接続され信号線13に並行するビアからなる第2のグラウンド配線52,52と、ベース基板1の上記他表面側において第2のグラウンド配線52,52同士を電気的に接続し信号線13に並行する第3のグラウンド配線53と、カバー基板3におけるベース基板1との対向面側で平面視において信号線13と当該信号線13の両側の第1のグラウンド配線51,51とに跨る幅寸法を有する第4のグラウンド配線54と、中間基板2において空洞部27の両側に形成され各第1のグラウンド配線51,51と第4のグラウンド配線54とを電気的に接続する貫通スリット配線からなる第5のグラウンド配線55,55とで構成されているので、第5のグラウンド配線55,55を、ベース基板1の上記一表面とのなす角度が略90度の空洞部27の壁面28,28に形成する場合に比べて容易に形成することができるから、構造体の平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ信号線13を囲む接地導体5の形成が容易になる。 In the structure including the wiring structure of the present embodiment described above, the ground conductor 5 surrounding the signal line 13 is parallel to the signal line 13 on both sides in the width direction of the signal line 13 on the one surface side of the base substrate 1. First ground wirings 51, 51, and second ground wirings 52, 52 formed on the base substrate 1 and electrically connected to the first ground wirings 51, 51 and made of vias parallel to the signal lines 13, The second ground wirings 52, 52 are electrically connected to each other on the other surface side of the base substrate 1, and the third ground wiring 53 parallel to the signal line 13 is opposed to the base substrate 1 in the cover substrate 3. And a fourth ground wiring 54 having a width across the signal line 13 and the first ground wirings 51, 51 on both sides of the signal line 13 in plan view, and a cavity in the intermediate substrate 2. 27, and is formed of fifth ground wirings 55 and 55 formed of through slit wirings that are formed on both sides of the first wiring 27 and electrically connect the first ground wirings 51 and 51 to the fourth ground wiring 54, Since the fifth ground wirings 55 and 55 can be easily formed as compared to the case where the fifth ground wirings 55 and 55 are formed on the wall surfaces 28 and 28 of the cavity portion 27 having an angle of about 90 degrees with the one surface. Transmission loss can be reduced while suppressing an increase in the planar size of the structure, and formation of the ground conductor 5 surrounding the signal line 13 is facilitated.
 すなわち、構造体は、ベース基板1と、カバー基板3と、中間基板2と、接地導体とを備える。ベース基板1は、その一表面側に、信号線13が設けられている。カバー基板3は、ベース基板1の一表面側と対向する位置に配置されている。中間基板2は、ベース基板1とカバー基板3との間に介在するように配置されている。中間基板2は、厚みを有している。中間基板2は、厚み方向に貫通して形成された空洞部27が設けられている。 That is, the structure includes a base substrate 1, a cover substrate 3, an intermediate substrate 2, and a ground conductor. The base substrate 1 is provided with a signal line 13 on one surface side thereof. The cover substrate 3 is disposed at a position facing the one surface side of the base substrate 1. The intermediate substrate 2 is disposed so as to be interposed between the base substrate 1 and the cover substrate 3. The intermediate substrate 2 has a thickness. The intermediate substrate 2 is provided with a cavity 27 formed so as to penetrate in the thickness direction.
 空洞部27は、信号線13を露出させるために設けられている。言い換えると、中間基板2は、信号線13が空洞部27に位置するように、ベース基板1とカバー基板3との間に配置されている。 The hollow portion 27 is provided to expose the signal line 13. In other words, the intermediate substrate 2 is disposed between the base substrate 1 and the cover substrate 3 so that the signal line 13 is located in the cavity 27.
 接地導体は、信号線13を囲むように、ベース基板1と中間基板2とカバー基板3とに亘って形成されている。接地導体は、第1のグラウンド配線51と、第2のグラウンド配線52と、第3のグラウンド配線53と、第4のグラウンド配線54と、第5のグラウンド配線55とを有している。 The ground conductor is formed over the base substrate 1, the intermediate substrate 2, and the cover substrate 3 so as to surround the signal line 13. The ground conductor has a first ground wiring 51, a second ground wiring 52, a third ground wiring 53, a fourth ground wiring 54, and a fifth ground wiring 55.
 第1のグラウンド配線51は、ベース基板1の前記一表面側において信号線13の幅方向の両側で信号線13に並行している。 The first ground wiring 51 is parallel to the signal line 13 on both sides in the width direction of the signal line 13 on the one surface side of the base substrate 1.
 第2のグラウンド配線52は、ベース基板1に形成されて各第1のグラウンド配線51に電気的に接続され信号線13に並行するビアからなる。言い換えると、第2のグラウンド配線52は、信号線13に並行するビアホール内に位置するようにベース基板1に形成されて、各第1のグラウンド配線51に電気的に接続されている。 The second ground wiring 52 is formed on the base substrate 1 and is electrically connected to each first ground wiring 51 and includes a via parallel to the signal line 13. In other words, the second ground wiring 52 is formed on the base substrate 1 so as to be located in the via hole parallel to the signal line 13 and is electrically connected to each first ground wiring 51.
 第3のグラウンド配線53は、ベース基板1の他表面側において第2のグラウンド配線52同士を電気的に接続し信号線13に並行する。 The third ground wiring 53 is electrically connected to the second ground wirings 52 on the other surface side of the base substrate 1 and is parallel to the signal line 13.
 第4のグラウンド配線54は、カバー基板3におけるベース基板1との対向面側で平面視において信号線13と当該信号線13の両側の第1のグラウンド配線51とに跨る幅寸法を有する。 The fourth ground wiring 54 has a width dimension straddling the signal line 13 and the first ground wiring 51 on both sides of the signal line 13 in a plan view on the side of the cover substrate 3 facing the base substrate 1.
 第5のグラウンド配線55は、中間基板2において空洞部27の両側に形成され各第1のグラウンド配線51と第4のグラウンド配線54とを電気的に接続する貫通スリット配線からなる。言い換えると、第5のグラウンド配線55は、中間基板2において空洞部27の両側に位置するように設けられた貫通スリット20a内に配置された貫通スリット配線で構成されている。貫通スリット配線は、第1のグラウンド配線51と第4のグラウンド配線54とを電気的に接続する。 The fifth ground wiring 55 is formed of a through-slit wiring that is formed on both sides of the cavity 27 in the intermediate substrate 2 and electrically connects the first ground wiring 51 and the fourth ground wiring 54. In other words, the fifth ground wiring 55 is configured by a through slit wiring arranged in the through slit 20 a provided so as to be located on both sides of the cavity portion 27 in the intermediate substrate 2. The through slit wiring electrically connects the first ground wiring 51 and the fourth ground wiring 54.
 これにより、構造体の平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ信号線13を囲む接地導体の形成が容易な配線構造を備えた構造体が得られる。 Thereby, it is possible to obtain a structure having a wiring structure that can reduce transmission loss while suppressing an increase in the planar size of the structure and can easily form a ground conductor surrounding the signal line 13.
 また、本実施形態では、中間基板2とベース基板1およびカバー基板3とが、互いの対向面に形成された金属層(中間基板2では、接続用金属層25,29、接合用金属層26それぞれが金属層を構成し、ベース基板1では、第1のグラウンド配線51、接合用金属層16それぞれが金属層を構成し、カバー基板3では第4のグラウンド配線54が金属層を構成している)同士を介して接合されているので、中間基板2の第5のグラウンド配線55,55と、ベース基板1の第1のグラウンド配線51,51およびカバー基板3の第4のグラウンド配線54とを容易に電気的に接続することが可能となる。 In the present embodiment, the intermediate substrate 2, the base substrate 1, and the cover substrate 3 are formed on the metal layers formed on the opposing surfaces (in the intermediate substrate 2, the connection metal layers 25 and 29, the bonding metal layer 26. Each of them constitutes a metal layer. In the base substrate 1, the first ground wiring 51 and the bonding metal layer 16 each constitute a metal layer, and in the cover substrate 3, the fourth ground wiring 54 constitutes a metal layer. The fifth ground wirings 55 and 55 of the intermediate substrate 2, the first ground wirings 51 and 51 of the base substrate 1, and the fourth ground wiring 54 of the cover substrate 3. Can be easily electrically connected.
 また、本実施形態では、中間基板2とベース基板1およびカバー基板3とは、金属層同士が互いの接合表面を活性化してから直接接合されている(つまり、表面活性化接合されている)ので、中間基板2とベース基板1およびカバー基板3とを常温で接合することが可能であり、接合時の熱膨張に起因した応力が、中間基板2とベース基板1およびカバー基板3との線膨張率差に起因して接合時に発生する応力を低減できる。 In the present embodiment, the intermediate substrate 2, the base substrate 1, and the cover substrate 3 are directly bonded after the metal layers activate each other's bonding surfaces (that is, surface activated bonding). Therefore, it is possible to bond the intermediate substrate 2 to the base substrate 1 and the cover substrate 3 at room temperature, and the stress caused by thermal expansion at the time of bonding is a line between the intermediate substrate 2, the base substrate 1 and the cover substrate 3. Stress generated at the time of joining due to the difference in expansion coefficient can be reduced.
 また、中間基板2と第5のグラウンド配線55との間には、電気的絶縁性を有する電気絶縁膜が設けられている。 In addition, an electrical insulating film having electrical insulation is provided between the intermediate substrate 2 and the fifth ground wiring 55.
 以下、MEMSリレーの具体的な構造について図6~図9を参照しながら説明するが、上述の接地導体5などの図示を省略してあり、MEMSリレーの基本的な構造のみ図示してある。 Hereinafter, the specific structure of the MEMS relay will be described with reference to FIGS. 6 to 9, but the above-described ground conductor 5 and the like are not illustrated, and only the basic structure of the MEMS relay is illustrated.
 ベース基板1は、矩形板状に形成されており、上記一表面側において長手方向の両端部それぞれに一対の信号線13,13が形成されている。ここで、各一対の信号線13,13は、長さ方向がベース基板1の短手方向と一致しており、一直線上に並んでいる。また、ベース基板1は、各一対の信号線13,13が一端部で、厚み方向において重なるビア15,15に電気的に接続されており、他端部に固定接点14,14が設けられている。また、ベース基板1は、各一対の信号線13,13が、ベース基板1の他表面側に形成された外部接続電極17,17と、ビア15,15を介して電気的に接続されている。 The base substrate 1 is formed in a rectangular plate shape, and a pair of signal lines 13 and 13 are formed at both ends in the longitudinal direction on the one surface side. Here, the pair of signal lines 13 and 13 have the length direction aligned with the short direction of the base substrate 1 and are aligned on a straight line. The base substrate 1 has a pair of signal lines 13 and 13 at one end and is electrically connected to vias 15 and 15 that overlap in the thickness direction, and fixed contacts 14 and 14 are provided at the other end. Yes. In addition, the base substrate 1 is electrically connected to a pair of signal lines 13 and 13 via external vias 15 and 15 and external connection electrodes 17 and 17 formed on the other surface side of the base substrate 1. .
 各固定接点14は、例えば、CuやAuなどの導電性が良好な金属材料からなる金属膜であって、スパッタ法や、電気めっき法、真空蒸着法などを利用して形成されている。なお、各固定接点14は、単層構造に限らず、多層構造でもよい。また、固定接点14の材料は、CuやAuに限らず、例えば、Cu、Au、Ag、Cr、Ti、Pt、Ru、Rh、Co、Niや、これらの合金などを採用してもよい。 Each fixed contact 14 is a metal film made of a metal material having good conductivity such as Cu or Au, and is formed using a sputtering method, an electroplating method, a vacuum deposition method, or the like. Each fixed contact 14 is not limited to a single layer structure, and may have a multilayer structure. Further, the material of the fixed contact 14 is not limited to Cu or Au, and for example, Cu, Au, Ag, Cr, Ti, Pt, Ru, Rh, Co, Ni, and alloys thereof may be employed.
 また、ベース基板1において上述のビア15が内側に設けられたビアホール12は、ベース基板1の上記一表面から上記他表面に近づくにつれて開口面積が徐々に大きくなるテーパ形状に形成されている。ここで、ビア15は、ビアホール12の内面に沿って形成されベース基板1の上記一表面側においてビアホール12を閉塞している。 In addition, the via hole 12 in which the above-described via 15 is provided inside the base substrate 1 is formed in a tapered shape in which the opening area gradually increases as it approaches the other surface from the one surface of the base substrate 1. Here, the via 15 is formed along the inner surface of the via hole 12 and closes the via hole 12 on the one surface side of the base substrate 1.
 また、中間基板2(以下、可動部形成基板2とも称する)は、半導体基板20の中央部に形成された開口部22および当該開口部22に並設され各一対の信号線13,13それぞれに対応する空洞部27,27および当該開口部22と各空洞部27,27とを連通させる連通部23,23が形成されベース基板1とカバー基板3との間に介在するフレーム部21と、フレーム部21の内側に配置されてフレーム部21に揺動自在に支持された可動部24と、可動部24のうち開口部22内に配置される矩形板状の可動部本体24aの長手方向の両端部から当該長手方向に沿って延設されて一対の信号線13,13それぞれに設けられた固定接点14,14に接離する可動接点214(図9(b)参照)を有する接点保持片24bとを備えている。ここにおいて、中間基板2は、フレーム部21が、ベース基板1およびカバー基板3と固着されており、可動接点214が、一対の固定接点14,14に対向し当該一対の固定接点14,14間を短絡する位置と開放する位置との間で変位可能となっている。なお、可動接点214は、固定接点14と同様に、CuやAuなどの導電性が良好な金属材料からなる金属膜であって、スパッタ法や、電気めっき法、真空蒸着法などを利用して形成されている。可動接点214は、単層構造に限らず、多層構造でもよく、例えば、Ti膜とAu膜との積層膜でもよい。また、可動接点214の材料は、CuやAuに限らず、例えば、Cu、Au、Ag、Cr、Ti、Pt、Ru、Rh、Co、Niや、これらの合金などを採用してもよい。 Further, the intermediate substrate 2 (hereinafter also referred to as the movable portion forming substrate 2) is provided with an opening 22 formed in the central portion of the semiconductor substrate 20 and a pair of signal lines 13 and 13 arranged in parallel to the opening 22 respectively. The corresponding cavity portions 27, 27 and the communication portions 23, 23 for communicating the openings 22 with the respective cavity portions 27, 27 are formed, and the frame portion 21 interposed between the base substrate 1 and the cover substrate 3, and the frame A movable portion 24 disposed inside the portion 21 and supported by the frame portion 21 in a swingable manner, and both ends in the longitudinal direction of a rectangular plate-shaped movable portion main body 24 a disposed in the opening 22 of the movable portion 24. A contact holding piece 24b having a movable contact 214 (see FIG. 9B) extending from the portion along the longitudinal direction and contacting and leaving the fixed contacts 14 and 14 provided on the pair of signal lines 13 and 13, respectively. And with That. Here, in the intermediate substrate 2, the frame portion 21 is fixed to the base substrate 1 and the cover substrate 3, and the movable contact 214 is opposed to the pair of fixed contacts 14, 14, and between the pair of fixed contacts 14, 14. Can be displaced between a position for short-circuiting and a position for opening. The movable contact 214 is a metal film made of a metal material having good conductivity such as Cu or Au, like the fixed contact 14, and uses a sputtering method, an electroplating method, a vacuum deposition method, or the like. Is formed. The movable contact 214 is not limited to a single layer structure, and may be a multilayer structure, for example, a laminated film of a Ti film and an Au film. The material of the movable contact 214 is not limited to Cu or Au, and for example, Cu, Au, Ag, Cr, Ti, Pt, Ru, Rh, Co, Ni, or an alloy thereof may be employed.
 また、可動部形成基板2は、可動部本体24aの短手方向の両端部それぞれの中央部に、支点用突片24cが突設され、各支点用突片24cにおけるカバー基板3との対向面に、支点突起24dが突設されており、支点突起24dが可動部24の揺動動作(シーソ動作)の支点として機能する。要するに、支点突起24dは、支点用突片24cとカバー基板3との間に介在しており、可動部24は、支点突起24dを介してカバー基板3に支持されることとなる。なお、可動部形成基板2は、フレーム21における開口部22と空洞部27,27との間の部位が、可動部形成基板2の長手方向に沿った方向への可動部24の移動を規制する移動規制部231を構成している。 Further, the movable part forming substrate 2 has a fulcrum projecting piece 24c projecting at the center of each of both ends in the short direction of the movable part main body 24a, and the fulcrum projecting piece 24c is opposed to the cover substrate 3. Further, a fulcrum protrusion 24d is provided so as to function as a fulcrum for the swinging operation (seesaw operation) of the movable portion 24. In short, the fulcrum protrusion 24d is interposed between the fulcrum protrusion 24c and the cover substrate 3, and the movable portion 24 is supported by the cover substrate 3 via the fulcrum protrusion 24d. In the movable portion forming substrate 2, the portion of the frame 21 between the opening 22 and the cavities 27 and 27 regulates the movement of the movable portion 24 in the direction along the longitudinal direction of the movable portion forming substrate 2. A movement restricting unit 231 is configured.
 上述の可動部形成基板2は、上述の可動部24が、4つの支持ばね部224を介してフレーム部21に揺動自在に支持されている。支持ばね224は、可動部本体24aの短手方向の両側面側で可動部本体24aの長手方向に離間した2箇所に形成されている。ここで、各支持ばね部224は、一端部が可動部本体24aに連続一体に連結され、他端部がフレーム部21の内周面に連続一体に連結されている。なお、支持ばね部224は、平面形状において上記一端部と上記他端部との間の部位を同一面内で蛇行した形状に形成することにより長さ寸法を長くしてある。しかして、可動部24が揺動する際に支持ばね部224に発生する応力を分散させることができ、各支持ばね部224が破損するのを防止することができる。 In the movable part forming substrate 2 described above, the movable part 24 is supported by the frame part 21 via four support spring parts 224 so as to be swingable. The support springs 224 are formed at two locations spaced apart in the longitudinal direction of the movable part main body 24a on both side surfaces in the short side direction of the movable part main body 24a. Here, one end of each support spring portion 224 is continuously and integrally connected to the movable portion main body 24 a, and the other end portion is continuously and integrally connected to the inner peripheral surface of the frame portion 21. In addition, the support spring part 224 is lengthened by forming the part between the said one end part and the said other end part in the planar shape in the meandering shape in the same plane. Thus, the stress generated in the support spring portion 224 when the movable portion 24 swings can be dispersed, and the support spring portions 224 can be prevented from being damaged.
 ところで、本実施形態におけるMEMSリレーは、可動部24を駆動する駆動手段として、可動部本体24aにおけるカバー基板3側に積層された磁性材料からなるアーマチュア6と、カバー基板3に設けられアーマチュア6を揺動自在に駆動する電磁石装置4とで構成される電磁駆動式の駆動手段を備えている。なお、駆動手段は、電磁力によって可動部24を駆動する電磁駆動式に限らず、静電力によって可動部24を駆動する静電駆動式でもよいし、圧電素子(電気機械要素)によって可動部24を駆動する圧電駆動式でもよい。 By the way, the MEMS relay according to the present embodiment includes an armature 6 made of a magnetic material laminated on the cover substrate 3 side of the movable portion main body 24a as a driving means for driving the movable portion 24, and an armature 6 provided on the cover substrate 3. An electromagnetic drive type driving means is provided which is composed of an electromagnet device 4 which is driven to swing. The drive means is not limited to the electromagnetic drive type that drives the movable part 24 by electromagnetic force, but may be an electrostatic drive type that drives the movable part 24 by electrostatic force, or the movable part 24 by a piezoelectric element (electromechanical element). It may be a piezoelectric drive type.
 アーマチュア6は、例えば、電磁軟鉄、電磁ステンレス、パーマロイなどの磁性材料を機械加工して矩形板状に形成され、接着、溶接、熱着、ろう付けなどの方法で、可動部本体部24aに固着されている。また、可動部本体24aにおけるベース基板1との対向面側には、レシジュアル(レシジャル)60が設けられている。 The armature 6 is formed into a rectangular plate by machining a magnetic material such as electromagnetic soft iron, electromagnetic stainless steel, and permalloy, and is fixed to the movable portion main body 24a by a method such as adhesion, welding, hot welding, or brazing. Has been. In addition, a reciprocal 60 is provided on the side of the movable portion main body 24a facing the base substrate 1.
 ここで、可動部本体24aはフレーム部21よりも薄肉であり、アーマチュア6の厚み寸法は、可動部形成基板2とカバー基板3とを固着した状態においてアーマチュア6とカバー基板3との間に適宜の空隙が形成されるように設定されている。また、レシジュアル60の厚み寸法は、可動部24とベース基板1との間に適宜の空隙が形成されるように設定されている。ここで、可動部形成基板2の基礎となる半導体基板20として、上述のダブルSOI基板を用いれば、可動部本体24aとベース基板1との距離をベース基板1側のシリコン層の厚みによって規定することが可能となって、固定接点14と可動接点214,214との間が開放された状態での固定接点14-可動接点214間の距離(絶縁距離)を高精度に設定することができる。また、可動部本体24aとカバー基板3との距離をカバー基板3側のシリコン層の厚みによって規定することが可能となり、アーマチュア6と電磁石装置4との距離(磁気ギャップ長)を高精度に設定することが可能となる。 Here, the movable part main body 24 a is thinner than the frame part 21, and the thickness dimension of the armature 6 is appropriately set between the armature 6 and the cover substrate 3 in a state where the movable part forming substrate 2 and the cover substrate 3 are fixed. It is set so that a void is formed. Further, the thickness dimension of the sequential 60 is set so that an appropriate gap is formed between the movable portion 24 and the base substrate 1. Here, if the above-described double SOI substrate is used as the semiconductor substrate 20 serving as the basis of the movable portion forming substrate 2, the distance between the movable portion main body 24a and the base substrate 1 is defined by the thickness of the silicon layer on the base substrate 1 side. Thus, the distance (insulating distance) between the fixed contact 14 and the movable contact 214 in a state where the fixed contact 14 and the movable contacts 214 and 214 are open can be set with high accuracy. In addition, the distance between the movable part main body 24a and the cover substrate 3 can be defined by the thickness of the silicon layer on the cover substrate 3 side, and the distance (magnetic gap length) between the armature 6 and the electromagnet device 4 can be set with high accuracy. It becomes possible to do.
 ところで、可動部形成基板2は、上記一表面側におけるフレーム部21の周部の全周に亘って、カバー基板3と接合するための接合用金属層238(図6および図9(a)参照)が形成され、上記他表面側におけるフレーム部21の周部の全周に亘って、ベース基板1と接合するための接合用金属層218(図9(b)参照)が形成されている。これに対して、カバー基板3における可動部形成基板2との対向面側の周部の全周に亘って、接合用金属層238に接合される接合用金属層(図示せず)が形成され、ベース基板1における可動部形成基板2との対向面側の周部の全周に亘って、接合用金属層218に接合される接合用金属層118(図6参照)が形成されている。なお、可動部形成基板2とベース基板1およびカバー基板3との接合方法は、上述の常温接合法に限らず、例えば、陽極接合法を採用してもよい。 By the way, the movable part formation board | substrate 2 is joining metal layer 238 (refer FIG. 6 and FIG. 9A) for joining to the cover board | substrate 3 over the perimeter of the frame part 21 in the said one surface side. ) And a bonding metal layer 218 (see FIG. 9B) for bonding to the base substrate 1 is formed over the entire circumference of the frame portion 21 on the other surface side. On the other hand, a bonding metal layer (not shown) to be bonded to the bonding metal layer 238 is formed over the entire circumference of the cover substrate 3 on the side facing the movable portion forming substrate 2. A joining metal layer 118 (see FIG. 6) to be joined to the joining metal layer 218 is formed over the entire circumference of the base substrate 1 on the side facing the movable portion forming substrate 2. In addition, the joining method of the movable part forming substrate 2, the base substrate 1, and the cover substrate 3 is not limited to the above-described room temperature joining method, and for example, an anodic joining method may be employed.
 カバー基板3は、中央部に、上述の電磁石装置4が収納する収納部36が形成されている。ここで、カバー基板3は、第2の基板30の中央部に、厚み方向に貫通し電磁石装置4が挿入される収納部用開口部34が形成されている。また、カバー基板3は、第2の基板2における可動部形成基板2側の一表面側に、収納部用開口部34を閉塞する閉塞板32が固着されている。要するに、カバー基板3は、収納部用開口部34の内周面と閉塞板32とで囲まれた空間が収納部36を構成している。しかして、ベース基板1と可動部形成基板2のフレーム部21とカバー基板3とで囲まれた空間は、気密空間となっている。 The cover substrate 3 is formed with a storage portion 36 for storing the above-described electromagnet device 4 in the center. Here, in the cover substrate 3, a storage portion opening 34 through which the electromagnet device 4 is inserted is formed in the central portion of the second substrate 30. In the cover substrate 3, a closing plate 32 that closes the storage portion opening 34 is fixed to one surface side of the second substrate 2 on the movable portion forming substrate 2 side. In short, in the cover substrate 3, a space surrounded by the inner peripheral surface of the storage portion opening 34 and the closing plate 32 forms a storage portion 36. Thus, the space surrounded by the base substrate 1, the frame portion 21 of the movable portion forming substrate 2, and the cover substrate 3 is an airtight space.
 上述の収納部用開口部34は、第2の基板30の上記一表面から他表面に近づくにつれて開口面積が徐々に大きくなるテーパ形状となっている。しかして、カバー基板3は、可動部形成基板2側とは反対側から電磁石装置4を挿入し易く、且つ、第2の基板30の上記一表面における収納部用開口部34の開口面積を比較的小さくすることができる。なお、上述の収納部用開口部34は、例えば、サンドブラスト法やエッチング法などによって形成すればよい。また、上述の閉塞板32は、例えば、厚みが5~50μm程度(好ましくは、20μm程度)に形成されたシリコン板やガラス板などの薄板からなる。このような閉塞板32は、例えば、シリコン基板やガラス基板を研磨やエッチングなどにより薄くすることにより形成されている。 The storage portion opening 34 has a tapered shape in which the opening area gradually increases as it approaches the other surface from the one surface of the second substrate 30. Thus, the cover substrate 3 is easy to insert the electromagnet device 4 from the side opposite to the movable portion forming substrate 2 side, and the opening area of the storage portion opening 34 on the one surface of the second substrate 30 is compared. Can be made smaller. Note that the storage portion opening 34 described above may be formed by, for example, a sandblasting method or an etching method. The closing plate 32 is made of a thin plate such as a silicon plate or a glass plate having a thickness of about 5 to 50 μm (preferably about 20 μm). Such a blocking plate 32 is formed, for example, by thinning a silicon substrate or a glass substrate by polishing or etching.
 電磁石装置4は、ヨーク40と、ヨーク40に巻回された2つのコイル42,42とを備えている。ヨーク40は、両コイル42,42が直接巻回される細長の矩形板状のコイル巻回部40aと、コイル巻回部40aの長手方向の両端部それぞれから閉塞板32に近づく向きに延設されコイル42,42への励磁電流に応じて互いの先端面が異極に励磁される一対の脚片40b,40bと、ヨーク40の両脚片40b,40bの間でコイル巻回部40aの長手方向の中央部に重ねて配置された矩形板状の永久磁石41とを備えている。しかして、各コイル42,42はそれぞれ、永久磁石41とヨーク40の脚片40b,40bとによってコイル巻回部40aの長手方向への移動が規制される。なお、ヨーク40は、電磁軟鉄などの鉄板を曲げ加工、鋳造加工、プレス加工などにより加工することによって形成されており、両脚片40b,40bの断面が矩形状に形成されている。 The electromagnet device 4 includes a yoke 40 and two coils 42 and 42 wound around the yoke 40. The yoke 40 extends in the direction of approaching the closing plate 32 from each of the elongated rectangular plate-shaped coil winding portion 40a around which both the coils 42 and 42 are directly wound, and both ends in the longitudinal direction of the coil winding portion 40a. The length of the coil winding portion 40a between the pair of leg pieces 40b and 40b whose tip surfaces are excited with different polarities in response to the excitation current to the coils 42 and 42 and the leg pieces 40b and 40b of the yoke 40 And a rectangular plate-like permanent magnet 41 disposed so as to overlap the central portion of the direction. Thus, the movement of the coil winding portion 40a in the longitudinal direction of each of the coils 42 and 42 is restricted by the permanent magnet 41 and the leg pieces 40b and 40b of the yoke 40, respectively. The yoke 40 is formed by processing an iron plate such as electromagnetic soft iron by bending, casting, pressing, or the like, and the cross sections of both leg pieces 40b, 40b are formed in a rectangular shape.
 上述の電磁石装置4は、2つのコイル42,42に励磁電流を通電したときに電磁力を発生するものであり、当該電磁力によって、可動部24に固着されているアーマチュア6を吸引することができる。 The above-described electromagnet device 4 generates an electromagnetic force when an excitation current is applied to the two coils 42 and 42, and the armature 6 fixed to the movable portion 24 can be attracted by the electromagnetic force. it can.
 永久磁石41は、コイル巻回部40aとの重ね方向(厚み方向)の両面それぞれの磁極面が異極に着磁されており、一方の磁極面がヨーク40のコイル巻回部40aに当接し、他方の磁極面がヨーク40の両脚片40b,40bの先端面と同一平面上に位置するように厚み寸法を設定してある。ここにおいて、上述の電磁石装置4は、後述のヨーク40の両脚片40b,40bの各先端面および永久磁石41の上記他方の磁極面が閉塞板32に当接する形で収納部36に収納されている。しかして、電磁石装置4における永久磁石41の上記他方の磁極面とヨーク40の両脚片40b,40bの先端面とを同一平面上に位置させることができるので、電磁石装置4とアーマチュア6との間のギャップ長の精度を高めることができる。 In the permanent magnet 41, the magnetic pole surfaces on both sides in the overlapping direction (thickness direction) with the coil winding portion 40a are magnetized with different polarities, and one magnetic pole surface abuts on the coil winding portion 40a of the yoke 40. The thickness dimension is set so that the other magnetic pole surface is located on the same plane as the tip surfaces of the leg pieces 40b, 40b of the yoke 40. Here, the above-described electromagnet device 4 is housed in the housing portion 36 in such a manner that the front end surfaces of both leg pieces 40b, 40b of the yoke 40 described later and the other magnetic pole surface of the permanent magnet 41 abut against the closing plate 32. Yes. Thus, the other magnetic pole surface of the permanent magnet 41 in the electromagnet device 4 and the tip surfaces of the leg pieces 40b, 40b of the yoke 40 can be positioned on the same plane, so that there is a gap between the electromagnet device 4 and the armature 6. The accuracy of the gap length can be increased.
 また、電磁石装置4は、絶縁性樹脂からなる断面コ字状の端子保持部44の両脚片44b,44bそれぞれから一対のコイル端子45,45が突出した端子ブロック46を備えており、平面視において端子保持部44の中央片44aがヨーク40のコイル巻回部40aと直交するようにコイル巻回部40aにおける永久磁石41側とは反対側に配設されている。ここにおいて、コイル端子45,45には、コイル42,42の端末が接続されており、一対のコイル端子45,45間に電圧を印加することで、両コイル42,42に電流が流れる。 In addition, the electromagnet device 4 includes a terminal block 46 in which a pair of coil terminals 45 and 45 protrude from both leg pieces 44b and 44b of a terminal holding portion 44 made of an insulating resin and having a U-shaped cross section. The central piece 44a of the terminal holding portion 44 is disposed on the opposite side of the coil winding portion 40a from the permanent magnet 41 side so as to be orthogonal to the coil winding portion 40a of the yoke 40. Here, the terminals of the coils 42, 42 are connected to the coil terminals 45, 45, and a current flows through both the coils 42, 42 by applying a voltage between the pair of coil terminals 45, 45.
 また、カバー基板3は、可動部形成基板2側とは反対側の表面にコイル端子45,45それぞれが電気的に接続される金属膜からなる配線パターン(導体パターン)37,37が形成されており、配線パターン37,37の一端部に、コイル端子45,45が半田付けなどによって接合され電気的に接続されている。一方、各配線パターン37,37の他端部は、ベース基板1の上記他表面側に設けられた駆動用の外部接続電極19,19(図7(a)参照)と電気的に接続されている。ここにおいて、各配線パターン37,37と駆動用の各外部接続電極19,19とは、カバー基板3、可動部形成基板2、ベース基板1それぞれに形成された通電用のビア315,215,115を介して電気的に接続されている。なお、カバー基板3のビア315と可動部形成基板2のビア215とは、カバー基板3と可動部形成基板2との互いの対向面側に形成されている接続用金属層(図示せず)同士を接合することにより電気的に接続されている。同様に、可動部形成基板2のビア215とベース基板1のビア115とは、可動部形成基板2とベース基板1との互いの対向面側に形成されている接続用金属層(図示せず)同士を接合することにより電気的に接続されている。 Further, the cover substrate 3 has wiring patterns (conductor patterns) 37, 37 made of a metal film to which the coil terminals 45, 45 are electrically connected on the surface opposite to the movable part forming substrate 2 side. In addition, coil terminals 45 and 45 are joined and electrically connected to one end portions of the wiring patterns 37 and 37 by soldering or the like. On the other hand, the other end portions of the wiring patterns 37 and 37 are electrically connected to driving external connection electrodes 19 and 19 (see FIG. 7A) provided on the other surface side of the base substrate 1. Yes. Here, the wiring patterns 37 and 37 and the driving external connection electrodes 19 and 19 are energized vias 315, 215 and 115 formed in the cover substrate 3, the movable portion forming substrate 2 and the base substrate 1, respectively. It is electrically connected via. Note that the via 315 of the cover substrate 3 and the via 215 of the movable part forming substrate 2 are connection metal layers (not shown) formed on the opposing surfaces of the cover substrate 3 and the movable part forming substrate 2. They are electrically connected by joining them together. Similarly, the via 215 of the movable part forming substrate 2 and the via 115 of the base substrate 1 are a connection metal layer (not shown) formed on the mutually facing surface side of the movable part forming substrate 2 and the base substrate 1. ) Are electrically connected by joining each other.
 次に、本実施形態のMEMSリレーの動作について説明する。 Next, the operation of the MEMS relay of this embodiment will be described.
 本実施形態のマイクロリレーでは、コイル42,42への通電が行われると、磁化の向きに応じてアーマチュア6の長手方向の一端部がヨーク40の一方の脚片40bに吸引され、可動部本体24aの一端側の接点保持片24bに固着されている可動接点214が、この可動接点214に対向する1対の固定接点14,14に所定の接圧で接触する(つまり、1対の固定接点14,14間が可動接点214を介して短絡される)。この状態でコイル42,42への通電を停止しても、永久磁石41の発生する磁束により、吸引力が維持され、そのままの状態が保持される。 In the microrelay of this embodiment, when the coils 42 are energized, one end in the longitudinal direction of the armature 6 is attracted to one leg piece 40b of the yoke 40 according to the direction of magnetization, and the movable part main body The movable contact 214 fixed to the contact holding piece 24b on one end side of the contact 24a contacts the pair of fixed contacts 14 and 14 facing the movable contact 214 with a predetermined contact pressure (that is, a pair of fixed contacts). 14 and 14 are short-circuited via the movable contact 214). Even if energization of the coils 42 and 42 is stopped in this state, the attractive force is maintained by the magnetic flux generated by the permanent magnet 41, and the state is maintained as it is.
 また、コイル42,42への通電方向を逆向きにすると、アーマチュア6の長手方向の他端部がヨーク40の他方の脚片40bに吸引され、可動部本体24aの他端側の接点保持片24bに固着されている可動接点214が、この可動接点214に対向する1対の固定接点14,14に所定の接点圧で接触する。この状態で通電を停止しても、永久磁石41の発生する磁束により、吸引力が維持され、そのままの状態が保持される。 When the energizing direction of the coils 42 is reversed, the other end portion of the armature 6 in the longitudinal direction is attracted to the other leg piece 40b of the yoke 40, and the contact holding piece on the other end side of the movable portion main body 24a. The movable contact 214 fixed to the contact 24b comes into contact with the pair of fixed contacts 14 and 14 facing the movable contact 214 with a predetermined contact pressure. Even if energization is stopped in this state, the attractive force is maintained by the magnetic flux generated by the permanent magnet 41, and the state is maintained as it is.
 なお、本実施形態のMEMSリレーは、アーマチュア6を駆動する電磁石装置4が永久磁石41を備えた有極型の電磁石装置であり、ラッチング型のリレーを構成しているが、これに限らず、電磁石装置4として永久磁石41を備えていない無極型の電磁石装置を用いてもよい。 Note that the MEMS relay of the present embodiment is a polar type electromagnet device in which the electromagnet device 4 that drives the armature 6 includes a permanent magnet 41, and constitutes a latching type relay. As the electromagnet device 4, a non-polar electromagnet device that does not include the permanent magnet 41 may be used.
 ところで、上述のビア15が内側に形成されるビアホール12は、第1の基板10の上記一表面から上記他表面に近づくにつれて開口面積が徐々に大きくなるテーパ状に形成されているので、開口面積が一様な場合な垂直孔状に形成する場合に比べて、容易に形成することができる。また、ビアホール12を垂直孔状に形成した場合には、ビアホール12の内側にビア15を形成できなくなる懸念がある。これに対して、ビアホール12がテーパ状に形成されていれば、めっき用のシード層をスパッタ法などにより形成してから、電気めっき法によりビア15を形成する製造プロセスにより、ビア15を形成することができる。なお、第1の基板10の厚さは特に限定するものではないが、例えば、200μm~1000μm程度の範囲で適宜設定すればよい。 By the way, the via hole 12 in which the via 15 described above is formed is formed in a tapered shape in which the opening area gradually increases from the one surface of the first substrate 10 toward the other surface. As compared with the case of forming a vertical hole in a uniform case, it can be easily formed. Further, when the via hole 12 is formed in a vertical hole shape, there is a concern that the via 15 cannot be formed inside the via hole 12. On the other hand, if the via hole 12 is formed in a tapered shape, the via 15 is formed by a manufacturing process in which the seed layer for plating is formed by sputtering or the like and then the via 15 is formed by electroplating. be able to. The thickness of the first substrate 10 is not particularly limited, but may be set as appropriate within a range of about 200 μm to 1000 μm, for example.
 ただし、第1の基板10にテーパ状のビアホール12が形成されている場合には、平面視におけるビアホール12の占有面積が大きくなり、MEMSリレーの小型化が制限されてしまう。 However, when the tapered via hole 12 is formed in the first substrate 10, the area occupied by the via hole 12 in a plan view becomes large, and the miniaturization of the MEMS relay is limited.
 これに対して、図10(a)~(d)のようにビアホール12を、第1の基板10の厚み方向の両側から規定の中間位置に近づくにつれて開口面積が徐々に小さくなる形状とすれば、ビアホール12の占有面積を小さくすることができ、MEMSリレーの小型化を図れる。なお、図10(a)と同図(b),(c),(d)とは、ビアホール12の形状が相違し、図10(b)と同図(c)と同図(d)とはビア15の形状が相違している。また、図10(a)~(d)のビアホール12は、開口形状が円形状であり、最小径を20μm~150μm程度の範囲、最大径を150μm~500μm程度の範囲で設定してあるが、これらの数値に特に限定するものではない。 On the other hand, as shown in FIGS. 10A to 10D, if the via hole 12 has a shape in which the opening area gradually decreases from the both sides in the thickness direction of the first substrate 10 toward the specified intermediate position. The area occupied by the via hole 12 can be reduced, and the MEMS relay can be reduced in size. 10 (a) and FIGS. 10 (b), (c), and (d) are different in the shape of the via hole 12, and FIG. 10 (b), FIG. 10 (c), and FIG. Are different in the shape of the via 15. In addition, the via hole 12 of FIGS. 10A to 10D has a circular opening shape, and the minimum diameter is set in a range of about 20 μm to 150 μm, and the maximum diameter is set in a range of about 150 μm to 500 μm. It does not specifically limit to these numerical values.
 上述の図10(a)のビアホール12は、最小径となる規定の中間位置が第1の基板10の厚み方向の一方に偏っているのに対して、図10(b),(c),(d)のビアホール12は、最小径となる規定の中間位置が第1の基板10の厚み方向の略中央となっているので、図10(a)の場合に比べて最大径を小さくすることができる。また、図10(c)では、ビアホール12がビア15により充実されているので、気密性を確保することができる。これに対して、図10(d)では、ビアホール12の最小径となる規定の中間位置付近のみでビアホール12を閉塞しているので、熱応力に起因してビアホール12の内周面とビア15との間に隙間が形成されるのを抑制することができ、耐熱応力性を高めることができる。 In the via hole 12 of FIG. 10A described above, the specified intermediate position having the minimum diameter is biased to one side in the thickness direction of the first substrate 10, whereas FIGS. In the via hole 12 of (d), the specified intermediate position that is the minimum diameter is substantially the center in the thickness direction of the first substrate 10, and therefore the maximum diameter is made smaller than in the case of FIG. Can do. Further, in FIG. 10C, since the via hole 12 is filled with the via 15, airtightness can be ensured. On the other hand, in FIG. 10D, since the via hole 12 is closed only in the vicinity of a prescribed intermediate position that is the minimum diameter of the via hole 12, the inner peripheral surface of the via hole 12 and the via 15 are caused by thermal stress. It is possible to suppress the formation of a gap between them, and to improve the heat stress resistance.
 上述の図10(b)のようなビア15を形成するには、まず、第1の基板10の上記一表面側および上記他表面側それぞれからサンドブラスト加工を行うことによって、第1の基板10にビアホール12を形成する(図11(a)参照)。その後、第1の基板10の上記一表面および上記他表面とビアホール12の内面とに、電気めっき用のシード層とする金属材料(例えば、Cu、Auなど)からなる金属層171をスパッタ法、蒸着法、無電解めっき法などにより形成する(図11(b)参照)。続いて、電気めっき法により金属層171をシード層としてビア15を形成すればよい(図11(c)参照)。なお、金属層171の厚みは、0.01μm~1μm程度の範囲で適宜設定すればよい。また、第1の基板10としてガラス基板ではなくシリコン基板を用いる場合には、ビアホール12をドライエッチングにより形成してから、熱酸化法などによって、シリコン基板の両面およびビアホール12の内面にシリコン酸化膜からなる絶縁膜を形成し、その後、金属層171を形成すればよい。 In order to form the via 15 as shown in FIG. 10 (b), first, sandblasting is performed on the first substrate 10 from the one surface side and the other surface side of the first substrate 10, respectively. A via hole 12 is formed (see FIG. 11A). Thereafter, a metal layer 171 made of a metal material (for example, Cu, Au, etc.) used as a seed layer for electroplating is sputtered on the one surface and the other surface of the first substrate 10 and the inner surface of the via hole 12. It forms by a vapor deposition method, an electroless plating method, etc. (refer FIG.11 (b)). Subsequently, the via 15 may be formed by electroplating using the metal layer 171 as a seed layer (see FIG. 11C). Note that the thickness of the metal layer 171 may be set as appropriate within a range of about 0.01 μm to 1 μm. When a silicon substrate is used as the first substrate 10 instead of a glass substrate, via holes 12 are formed by dry etching, and then a silicon oxide film is formed on both surfaces of the silicon substrate and the inner surfaces of the via holes 12 by a thermal oxidation method or the like. After that, an insulating film made of a metal layer 171 may be formed.
 また、図12(e)のようなビア15を形成するには、まず、第1の基板10の上記一表面側および上記他表面側それぞれからサンドブラスト加工を行うことによって、第1の基板10にビアホール12を形成する(図12(a)参照)。その後、第1の基板10の上記一表面および上記他表面とビアホール12の内面とに、電気めっき用のシード層とする金属層171をスパッタ法、蒸着法、無電解めっき法などにより形成するとともに、電気めっき用のシード層とする金属層172をスパッタ法、蒸着法、無電解めっき法などにより形成した第4の基板173を用意する(図12(b)参照)。続いて、第1の基板10に第4の基板173を貼り合わせる(図12(c)参照)。その後、電気めっき法により金属層171,172をシード層としてビア15を形成し(図12(d)参照)、その後、第4の基板173を第1の基板10から剥離すればよい(図12(e)参照)。なお、この例においても、第1の基板10としてガラス基板ではなくシリコン基板を用いる場合には、ビアホール12をドライエッチングにより形成してから、熱酸化法などによって、シリコン基板の両面およびビアホール12の内面にシリコン酸化膜からなる絶縁膜を形成し、その後、金属層171を形成すればよい。 In order to form the via 15 as shown in FIG. 12E, first, the first substrate 10 is subjected to sandblasting from the one surface side and the other surface side of the first substrate 10. A via hole 12 is formed (see FIG. 12A). Thereafter, a metal layer 171 serving as a seed layer for electroplating is formed on the one surface and other surface of the first substrate 10 and the inner surface of the via hole 12 by sputtering, vapor deposition, electroless plating, or the like. A fourth substrate 173 is prepared in which a metal layer 172 serving as a seed layer for electroplating is formed by sputtering, vapor deposition, electroless plating, or the like (see FIG. 12B). Subsequently, the fourth substrate 173 is bonded to the first substrate 10 (see FIG. 12C). Thereafter, the via 15 is formed by electroplating using the metal layers 171 and 172 as seed layers (see FIG. 12D), and then the fourth substrate 173 is peeled off from the first substrate 10 (FIG. 12). (See (e)). Also in this example, when a silicon substrate is used as the first substrate 10, a via hole 12 is formed by dry etching, and then both sides of the silicon substrate and the via hole 12 are formed by a thermal oxidation method or the like. An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
 次に、図10(d)のようなビア15を形成する方法の一例について図13を参照しながら説明する。 Next, an example of a method for forming the via 15 as shown in FIG. 10D will be described with reference to FIG.
 まず、第1の基板10の上記一表面側および上記他表面側それぞれからサンドブラスト加工を行うことによって、第1の基板10にビアホール12を形成する(図13(a)参照)。その後、第1の基板10の上記一表面と、ビアホール12のうち上記一表面側のテーパ状の部位の内面とに、電気めっき用のシード層とする金属層171をスパッタ法、蒸着法、無電解めっき法などにより形成する(図13(b)参照)。続いて、金属層171をシード層として電気めっきを行う第1の電気めっき工程により、ビア15の一部を構成する導体部15aを形成する(図13(c)参照)。その後、第1の基板10の上記他表面と、ビアホール12のうち上記他表面側のテーパ状の部位の内面とに、電気めっき用のシード層とする金属層181をスパッタ法、蒸着法、無電解めっき法などにより形成する(図13(d)参照)。続いて、金属層181をシード層として電気めっきを行う第2の電気めっき工程により、ビア15の一部を構成する導体部15bを形成する(図13(e)参照)。引き続いて、電気めっきを行う第3の電気めっき工程により、ビアホール12内面の導体部15a,15bとともにビア15を構成し且つビアホール12を閉塞する導体部15cを形成する(図13(f)参照)。なお、この例においても、第1の基板10としてガラス基板ではなくシリコン基板を用いる場合には、ビアホール12をドライエッチングにより形成してから、熱酸化法などによって、シリコン基板の両面およびビアホール12の内面にシリコン酸化膜からなる絶縁膜を形成し、その後、金属層171を形成すればよい。 First, via holes 12 are formed in the first substrate 10 by performing sandblasting from the one surface side and the other surface side of the first substrate 10 (see FIG. 13A). Thereafter, a metal layer 171 serving as a seed layer for electroplating is formed on the one surface of the first substrate 10 and the inner surface of the tapered portion on the one surface side of the via hole 12 by a sputtering method, a vapor deposition method, or the like. It is formed by an electrolytic plating method or the like (see FIG. 13B). Subsequently, a conductor portion 15a constituting a part of the via 15 is formed by a first electroplating step in which electroplating is performed using the metal layer 171 as a seed layer (see FIG. 13C). Thereafter, a metal layer 181 serving as a seed layer for electroplating is formed on the other surface of the first substrate 10 and the inner surface of the tapered portion on the other surface side of the via hole 12 by a sputtering method, a vapor deposition method, or the like. It is formed by an electrolytic plating method or the like (see FIG. 13D). Subsequently, a conductor portion 15b constituting a part of the via 15 is formed by a second electroplating process in which electroplating is performed using the metal layer 181 as a seed layer (see FIG. 13E). Subsequently, by a third electroplating step in which electroplating is performed, a conductor portion 15c that forms the via 15 together with the conductor portions 15a and 15b on the inner surface of the via hole 12 and closes the via hole 12 is formed (see FIG. 13F). . Also in this example, when a silicon substrate is used as the first substrate 10, a via hole 12 is formed by dry etching, and then both sides of the silicon substrate and the via hole 12 are formed by a thermal oxidation method or the like. An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
 上述の電気めっきを行う際には、硫酸銅めっき液にめっき促進剤およびめっき抑制剤が添加されたビアフィリング用の銅めっき液を用いている。ここにおいて、めっき促進剤は、ビアホール12の内側の金属層171,181の表面に多く付着してめっきを促進させる機能を有し、めっき抑制剤は、第1の基板10の上記一表面側、上記他表面側で金属層171,181の表面に多く付着してめっきを抑制する機能を有している。したがって、めっき液中にめっき促進剤およびめっき抑制剤を添加剤として添加しておくことにより、これらの添加剤の作用によりビアホール12の内側に形成される導体部15a,15b,15cの厚みを大きくすることができ、ビアホール12をビア15により閉塞しやすくなる。めっき促進剤としては、例えば、ビス(3-スルホプロピル)ジスルフィド(SPS)を用い、めっき促進剤として、分子量が3000~8000のポリエチレングリコール(PEG)を用いているが、これらの材料は特に限定するものではない。なお、ビアフィリング用の銅めっき液を攪拌する速度を速めることにより、めっき促進剤およびめっき抑制剤のよる効果を高めることができる。 When performing the above electroplating, a copper plating solution for via filling in which a plating accelerator and a plating inhibitor are added to a copper sulfate plating solution is used. Here, the plating accelerator has a function of adhering to the surfaces of the metal layers 171 and 181 inside the via hole 12 to promote plating, and the plating inhibitor is the one surface side of the first substrate 10. On the other surface side, it has a function of adhering to the surfaces of the metal layers 171 and 181 and suppressing plating. Therefore, by adding a plating accelerator and a plating inhibitor as additives in the plating solution, the thickness of the conductor portions 15a, 15b, 15c formed inside the via hole 12 by the action of these additives is increased. This makes it easier to close the via hole 12 with the via 15. For example, bis (3-sulfopropyl) disulfide (SPS) is used as the plating accelerator, and polyethylene glycol (PEG) having a molecular weight of 3000 to 8000 is used as the plating accelerator. However, these materials are particularly limited. Not what you want. In addition, the effect by a plating accelerator and a plating inhibitor can be heightened by speeding up the speed which stirs the copper plating solution for via filling.
 次に、図10(d)のようなビア15を形成する方法の他の一例について図14を参照しながら説明する。 Next, another example of a method for forming the via 15 as shown in FIG. 10D will be described with reference to FIG.
 まず、第1の基板10の上記一表面側および上記他表面側それぞれからサンドブラスト加工を行うことによって、第1の基板10にビアホール12を形成する(図14(a)参照)。その後、第1の基板10の上記一表面および上記他表面とビアホール12の内面とに、電気めっき用のシード層とする金属層171をスパッタ法、蒸着法、無電解めっき法などにより形成する(図14(b)参照)。続いて、ビアフィリング用の銅めっき液を用いて電気めっき工程を行うことでビア15の一部を構成する導体部15a,15bを形成し(図14(c)参照)、引き続いて、電気めっきを行うことにより、ビアホール12内面の導体部15a,15bとともにビア15を構成し且つビアホール12を閉塞する導体部15cを形成する(図14(d)参照)。なお、図13や図14に示した例では、電気めっきの時間を短くするとともに、より少量の銅めっき量でビアホール12の閉塞を実現するためには、ビアホール12の最小径を小さくすることが好ましい。また、この例においても、第1の基板10としてガラス基板ではなくシリコン基板を用いる場合には、ビアホール12をドライエッチングにより形成してから、熱酸化法などによって、シリコン基板の両面およびビアホール12の内面にシリコン酸化膜からなる絶縁膜を形成し、その後、金属層171を形成すればよい。 First, via holes 12 are formed in the first substrate 10 by performing sandblasting from the one surface side and the other surface side of the first substrate 10 (see FIG. 14A). Thereafter, a metal layer 171 serving as a seed layer for electroplating is formed on the one surface and other surface of the first substrate 10 and the inner surface of the via hole 12 by sputtering, vapor deposition, electroless plating, or the like ( (Refer FIG.14 (b)). Subsequently, by performing an electroplating process using a copper plating solution for via filling, conductor portions 15a and 15b constituting a part of the via 15 are formed (see FIG. 14C), and subsequently, electroplating is performed. As a result, the via 15 is formed together with the conductors 15a and 15b on the inner surface of the via hole 12, and the conductor 15c for closing the via hole 12 is formed (see FIG. 14D). In the examples shown in FIGS. 13 and 14, the minimum diameter of the via hole 12 can be reduced in order to shorten the electroplating time and to close the via hole 12 with a smaller amount of copper plating. preferable. Also in this example, when a silicon substrate is used as the first substrate 10, the via holes 12 are formed by dry etching, and then both sides of the silicon substrate and the via holes 12 are formed by a thermal oxidation method or the like. An insulating film made of a silicon oxide film is formed on the inner surface, and then the metal layer 171 is formed.
 次に、図10(d)のようなビア15を形成する方法の別の一例について図15を参照しながら説明する。 Next, another example of a method of forming the via 15 as shown in FIG. 10D will be described with reference to FIG.
 まず、第1の基板10の上記一表面側から上述の規定の中間位置に対応する所定深さまでサンドブラスト加工を行うことによって、第1の基板10に有底孔(凹部)12aを形成する(図15(a)参照)。その後、第1の基板10の上記一表面および有底孔12aの内面に電気めっき用のシード層とする金属層172をスパッタ法、蒸着法、無電解めっき法などにより形成する(図15(b)参照)。続いて、金属層172をシード層として電気めっきを行う第1の電気めっき工程により、ビア15の一部を構成する導体部15fを形成する(図15(c)参照)。続いて、第1の基板10の上記他表面において有底孔12aに重なる部位を上記他表面から導体部15fが露出するまでサンドブラスト加工を行うことによって、有底孔12aとともにビアホール12を構成する凹部12bを第1の基板10に形成する(図15(d)参照)。その後、第1の基板10の上記他表面と、ビアホール12のうち上記他表面側のテーパ状の部位の内面とに、電気めっき用のシード層とする金属層182をスパッタ法、蒸着法、無電解めっき法などにより形成する(図15(e)参照)。続いて、金属層182をシード層として電気めっきを行う第2の電気めっき工程により、上述の導体部15fとともにビア15を構成する導体部15gを形成する(図15(f)参照)。 First, a bottomed hole (concave portion) 12a is formed in the first substrate 10 by performing sandblasting from the one surface side of the first substrate 10 to a predetermined depth corresponding to the prescribed intermediate position (see FIG. 15 (a)). Thereafter, a metal layer 172 serving as a seed layer for electroplating is formed on the one surface of the first substrate 10 and the inner surface of the bottomed hole 12a by sputtering, vapor deposition, electroless plating, or the like (FIG. 15B). )reference). Subsequently, a conductor portion 15f constituting a part of the via 15 is formed by a first electroplating step in which electroplating is performed using the metal layer 172 as a seed layer (see FIG. 15C). Subsequently, a portion of the first substrate 10 that overlaps the bottomed hole 12a on the other surface is sandblasted until the conductor portion 15f is exposed from the other surface, thereby forming the via hole 12 together with the bottomed hole 12a. 12b is formed on the first substrate 10 (see FIG. 15D). Thereafter, a metal layer 182 serving as a seed layer for electroplating is formed on the other surface of the first substrate 10 and the inner surface of the tapered portion on the other surface side of the via hole 12 by sputtering, vapor deposition, It is formed by an electrolytic plating method or the like (see FIG. 15 (e)). Subsequently, a conductor portion 15g constituting the via 15 is formed together with the above-described conductor portion 15f by a second electroplating step in which electroplating is performed using the metal layer 182 as a seed layer (see FIG. 15F).
 以上説明した本実施形態のMEMSリレーによれば、ベース基板1の上記一表面側において長手方向の両端部それぞれに一対の信号線13,13を有し、中間基板(可動部形成基板)2が、開口部22および当該開口部22に並設され各一対の信号線13,13の対それぞれに対応する空洞部27,27および当該開口部22と各空洞部27,27とを連通させる連通部28,28が形成されベース基板1とカバー基板3との間に介在するフレーム部21と、フレーム部21の内側に配置されてフレーム部21に揺動自在に支持された可動部24と、可動部24のうち開口部22内に配置される可動部本体24aから延設されて一対の信号線13,13それぞれに設けられた固定接点14,14に接離する可動接点214を有する接点保持片24bとを備え、上述の構造体に、可動部24を揺動自在に駆動する駆動手段が設けられているので、平面サイズの大型化を抑制しつつ伝送損失の低減を図ることが可能で且つ信号線13を囲む接地導体5の形成が容易なMEMSリレーを提供することができる。 According to the MEMS relay of the present embodiment described above, a pair of signal lines 13 and 13 are provided at both ends in the longitudinal direction on the one surface side of the base substrate 1, and the intermediate substrate (movable portion forming substrate) 2 is provided. , The opening portion 22 and the cavity portions 27, 27 arranged in parallel to the opening portion 22 and corresponding to the pair of signal lines 13, 13, respectively, and the communication portion for communicating the opening portion 22 with the cavity portions 27, 27. A frame portion 21 formed between the base substrate 1 and the cover substrate 3; a movable portion 24 disposed inside the frame portion 21 and supported by the frame portion 21 so as to be swingable; Contact holding having a movable contact 214 extending from a movable portion main body 24 a disposed in the opening 22 of the portion 24 and contacting and separating from fixed contacts 14 and 14 provided on the pair of signal lines 13 and 13, respectively. 24b, and the above-described structure is provided with drive means for swingably driving the movable portion 24. Therefore, it is possible to reduce transmission loss while suppressing an increase in planar size and A MEMS relay in which the ground conductor 5 surrounding the signal line 13 can be easily formed can be provided.
 また、本実施形態のMEMSリレーでは、カバー基板3に電磁石装置4を収納する収納部36を形成してあるので、図16および図17に示した従来例のようにベース基板1’に電磁石装置4’を収納する収納部116’を設ける場合に比べて、電磁石装置4と信号線13,13との距離を長くすることができるから、電磁石装置4が発生する磁束の影響で伝送損失が生じるのを抑制することができる。 Further, in the MEMS relay of this embodiment, since the housing portion 36 for housing the electromagnet device 4 is formed on the cover substrate 3, the electromagnet device is mounted on the base substrate 1 'as in the conventional example shown in FIGS. Since the distance between the electromagnet device 4 and the signal lines 13 and 13 can be increased as compared with the case where the housing portion 116 ′ for housing 4 ′ is provided, transmission loss occurs due to the magnetic flux generated by the electromagnet device 4. Can be suppressed.
 また、本実施形態のMEMSリレーによれば、図16および図17に示した構成のようにベース基板1’に電磁石装置4’を収納する場合に比べて、ベース基板1の厚さ寸法を小さくすることができ、信号線13と外部接続電極17(図1(c)参照)とを電気的に接続するビア15の長さを短くすることができ、高周波特性を向上することができる。 Further, according to the MEMS relay of the present embodiment, the thickness dimension of the base substrate 1 is reduced as compared with the case where the electromagnet device 4 ′ is accommodated in the base substrate 1 ′ as in the configuration shown in FIGS. Therefore, the length of the via 15 that electrically connects the signal line 13 and the external connection electrode 17 (see FIG. 1C) can be shortened, and the high-frequency characteristics can be improved.
 また、第1の基板10として、ガラス基板に代えて高抵抗率のシリコン基板を用いれば、ガラス基板を用いた場合に比べてビアホール11,11,12を小型化することができ、上述の構造体およびMEMSリレーの平面サイズの小型化を図れるとともに、高周波特性の向上を図れる。また、第1の基板10としてLTCC基板を用いれば、LTCC基板の作製時に所望の配線(第1のグラウンド配線51,51、第2のグラウンド配線52,52、第3のグラウンド配線53,53、ビア15)を同時に形成することが可能であり、製造工程の簡略化を図れる。 Further, if a high resistivity silicon substrate is used as the first substrate 10 instead of the glass substrate, the via holes 11, 11, and 12 can be reduced in size as compared with the case where the glass substrate is used. The planar size of the body and the MEMS relay can be reduced, and the high frequency characteristics can be improved. Further, if an LTCC substrate is used as the first substrate 10, desired wirings ( first ground wirings 51 and 51, second ground wirings 52 and 52, third ground wirings 53 and 53, The vias 15) can be formed at the same time, and the manufacturing process can be simplified.
 1 ベース基板
 2 中間基板
 3 カバー基板
 4 電磁石装置
 5 接地導体
 6 アーマチュア
 13 信号線
 14 固定接点
 16 接合用金属層(金属層)
 21 フレーム部
 22 開口部
 23 連通部
 24 可動部
 24a 可動部本体
 24b 接点保持片
 25 接続用金属層(金属層)
 26 接合用金属層(金属層)
 27 空洞部
 28 壁面
 29 接続用金属層(金属層)
 51 第1のグラウンド配線(金属層)
 52 第2のグラウンド配線
 53 第3のグラウンド配線
 54 第4のグラウンド配線(金属層)
 55 第5のグラウンド配線
DESCRIPTION OF SYMBOLS 1 Base substrate 2 Intermediate substrate 3 Cover substrate 4 Electromagnet device 5 Ground conductor 6 Armature 13 Signal line 14 Fixed contact 16 Metal layer for joining (metal layer)
21 Frame part 22 Opening part 23 Communication part 24 Movable part 24a Movable part main body 24b Contact holding piece 25 Metal layer for connection (metal layer)
26 Metal layer for bonding (metal layer)
27 Cavity 28 Wall 29 Metal layer for connection (metal layer)
51 First ground wiring (metal layer)
52 Second ground wiring 53 Third ground wiring 54 Fourth ground wiring (metal layer)
55 Fifth ground wiring

Claims (6)

  1.  信号線が一表面側に形成されたベース基板と、ベース基板の一表面側に対向配置されたカバー基板と、ベース基板とカバー基板との間に介在し信号線を露出させる空洞部が厚み方向に貫設された中間基板と、ベース基板と中間基板とカバー基板とに亘って形成され信号線を囲む接地導体とを備え、当該接地導体は、ベース基板の前記一表面側において信号線の幅方向の両側で信号線に並行する第1のグラウンド配線と、ベース基板に形成されて各第1のグラウンド配線に電気的に接続され信号線に並行するビアからなる第2のグラウンド配線と、ベース基板の他表面側において第2のグラウンド配線同士を電気的に接続し信号線に並行する第3のグラウンド配線と、カバー基板におけるベース基板との対向面側で平面視において信号線と当該信号線の両側の第1のグラウンド配線とに跨る幅寸法を有する第4のグラウンド配線と、中間基板において空洞部の両側に形成され各第1のグラウンド配線と第4のグラウンド配線とを電気的に接続する貫通スリット配線からなる第5のグラウンド配線とで構成されてなることを特徴とする配線構造を備えた構造体。
    A base substrate with a signal line formed on one surface side, a cover substrate opposed to the one surface side of the base substrate, and a cavity that is interposed between the base substrate and the cover substrate to expose the signal line is in the thickness direction And a ground conductor that is formed across the base substrate, the intermediate substrate, and the cover substrate and surrounds the signal line, and the ground conductor has a width of the signal line on the one surface side of the base substrate. A first ground wiring parallel to the signal lines on both sides of the direction, a second ground wiring formed on the base substrate and electrically connected to each first ground wiring and made of vias parallel to the signal lines, and a base The second ground lines are electrically connected to each other on the other surface side of the substrate, and the third ground lines parallel to the signal lines and the signal lines and the relevant lines in plan view on the side of the cover substrate facing the base substrate A fourth ground wiring having a width across the first ground wiring on both sides of the signal line, and the first ground wiring and the fourth ground wiring formed on both sides of the cavity in the intermediate substrate A structure provided with a wiring structure, characterized by comprising a fifth ground wiring composed of through slit wiring to be connected.
  2.  前記中間基板と前記ベース基板および前記カバー基板とは、互いの対向面に形成された金属層同士を介して接合されてなることを特徴とする請求項1記載の配線構造を備えた構造体。
    2. The structure having a wiring structure according to claim 1, wherein the intermediate substrate, the base substrate, and the cover substrate are bonded to each other through metal layers formed on opposing surfaces.
  3.  前記中間基板と前記ベース基板および前記カバー基板とは、前記金属層同士が表面活性化接合されてなることを特徴とする請求項2記載の配線構造を備えた構造体。
    3. The structure having a wiring structure according to claim 2, wherein the intermediate substrate, the base substrate, and the cover substrate are formed by surface activation bonding of the metal layers.
  4.  前記中間基板と前記第5グラウンド配線との間には、絶縁膜が設けられていることを特徴とする請求項1~3のいずれかに記載の構造体。
    The structure according to any one of claims 1 to 3, wherein an insulating film is provided between the intermediate substrate and the fifth ground wiring.
  5.  請求項1ないし請求項4のいずれか1項に記載の配線構造を備えた構造体を有するMEMSリレーであって、前記ベース基板は、前記一表面側に、一対の前記信号線を有し、前記中間基板は、開口部および当該開口部に並設され前記各信号線それぞれに対応する前記空洞部および当該開口部と前記各空洞部とを連通させる連通部が形成され前記ベース基板と前記カバー基板との間に介在するフレーム部と、フレーム部の内側に配置されてフレーム部に揺動自在に支持された可動部と、可動部のうち開口部内に配置される可動部本体から延設されて一対の前記信号線それぞれに設けられた固定接点に接離する可動接点を有する接点保持片とを備え、前記構造体に、可動部を揺動自在に駆動する駆動手段が設けられてなることを特徴とするMEMSリレー。
    5. The MEMS relay having a structure including the wiring structure according to claim 1, wherein the base substrate includes a pair of the signal lines on the one surface side, The intermediate substrate is formed with an opening and a communication portion that is arranged in parallel with the opening and corresponds to each of the signal lines, and a communication portion that connects the opening and the cavity, and the base substrate and the cover. A frame portion interposed between the substrate, a movable portion disposed inside the frame portion and supported by the frame portion in a swingable manner, and a movable portion main body disposed in the opening portion of the movable portion. And a contact holding piece having a movable contact that contacts and separates from a fixed contact provided on each of the pair of signal lines, and the structure is provided with a driving means for driving the movable portion to be swingable. MEM characterized by Relay.
  6.  前記駆動手段は、前記可動部本体における前記カバー基板側に積層された磁性材料からなるアーマチュアと、前記カバー基板に設けられ前記アーマチュアを揺動自在に駆動する電磁石装置とで構成されてなることを特徴とする請求項5記載のMEMSリレー。 The driving means is composed of an armature made of a magnetic material laminated on the cover substrate side in the movable part main body and an electromagnet device provided on the cover substrate to drive the armature so as to be swingable. The MEMS relay according to claim 5, wherein:
PCT/JP2011/061159 2010-05-17 2011-05-16 Structure provided with wiring structure, and mems relay WO2011145549A1 (en)

Applications Claiming Priority (2)

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JP2010-113342 2010-05-17
JP2010113342A JP2011243363A (en) 2010-05-17 2010-05-17 Structure with wiring structure, and mems relay

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JP2014178409A (en) * 2013-03-14 2014-09-25 Seiko Epson Corp Interference filter, manufacturing method of interference filter, optical module, electronic apparatus and joint substrate

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US9153510B2 (en) 2013-05-28 2015-10-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9570783B1 (en) * 2015-08-28 2017-02-14 General Electric Company Radio frequency micro-electromechanical systems having inverted microstrip transmission lines and method of making the same

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JPH11266105A (en) * 1998-03-16 1999-09-28 Oki Electric Ind Co Ltd Signal transmission substrate
JP2005216541A (en) * 2004-01-27 2005-08-11 Matsushita Electric Works Ltd Micro relay and its manufacturing method
JP2006210010A (en) * 2005-01-25 2006-08-10 Matsushita Electric Works Ltd Micro relay
JP2010044964A (en) * 2008-08-13 2010-02-25 Toshiba Corp Micro movable device

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JPH11266105A (en) * 1998-03-16 1999-09-28 Oki Electric Ind Co Ltd Signal transmission substrate
JP2005216541A (en) * 2004-01-27 2005-08-11 Matsushita Electric Works Ltd Micro relay and its manufacturing method
JP2006210010A (en) * 2005-01-25 2006-08-10 Matsushita Electric Works Ltd Micro relay
JP2010044964A (en) * 2008-08-13 2010-02-25 Toshiba Corp Micro movable device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014178409A (en) * 2013-03-14 2014-09-25 Seiko Epson Corp Interference filter, manufacturing method of interference filter, optical module, electronic apparatus and joint substrate

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JP2011243363A (en) 2011-12-01

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