WO2011144144A1 - 一种数据解交织方法及装置 - Google Patents

一种数据解交织方法及装置 Download PDF

Info

Publication number
WO2011144144A1
WO2011144144A1 PCT/CN2011/075167 CN2011075167W WO2011144144A1 WO 2011144144 A1 WO2011144144 A1 WO 2011144144A1 CN 2011075167 W CN2011075167 W CN 2011075167W WO 2011144144 A1 WO2011144144 A1 WO 2011144144A1
Authority
WO
WIPO (PCT)
Prior art keywords
cache
code stream
idx
input code
stream
Prior art date
Application number
PCT/CN2011/075167
Other languages
English (en)
French (fr)
Inventor
周扬
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2011144144A1 publication Critical patent/WO2011144144A1/zh

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions

Definitions

  • the present invention mainly relates to the field of communications technologies, and in particular, to a data deinterleaving method and apparatus. Background technique
  • the Physical Uplink Share Channel (PUSCH) is used as a 1-3 code rate Turbo coding link.
  • PUSCH Physical Uplink Share Channel
  • three code streams can be generated on the PUSCH channel, which are an information stream, a first check stream, and a second check stream.
  • the input code stream is 1 line according to 32 bits.
  • Write the interleaving matrix (if the code stream length is not an integer multiple of 32 bits, add interleaving dummy at the front end of the code stream, so that each line in the interleaving matrix contains 32 bits); perform column permutation on the interleaving matrix, that is, according to the LTE protocol.
  • the column replacement rule adjusts the column order in the above interleaving matrix; all data in the interleaving matrix is read and transmitted in columns.
  • the column replacement rules specific to the information flow specified by the LTE protocol and the first check flow are as follows:
  • C ft 32, indicating the number of columns in the interleaving matrix
  • P (_/ ⁇ ) is the column number of the jth column before the column permutation after the column permutation.
  • the column replacement rule of the second check stream specified by the LTE protocol is the same as the above table 1 Differently, before interleaving the second check stream by using the column replacement rule shown in Table 1 above, it is necessary to add an interlace dummy at the front end of the second check stream, and shift the entire code stream to the left by one bit.
  • the interleaved information stream, the first check stream, and the second check stream need to be deinterleaved, respectively, to recover the 3-way code stream before interleaving.
  • the received code popularity number is R
  • the receiving end deinterleaves the code stream
  • the received data of each column is calculated in a serial manner before the interleaving, and is written into the RAM according to the address before the interleaving.
  • the addresses are sequentially read from the RAM. In this way, the throughput of the data at the time of deinterleaving is reduced; and the address calculation is performed before the code stream is written to the RAM, which also causes an unbalanced complexity of the deinterleaving.
  • a data deinterleaving method and apparatus are provided, which can improve the throughput of data during deinterleaving and balance the complexity of deinterleaving.
  • a data deinterleaving method is provided in the embodiment of the present invention, including:
  • the receiving end writes the received interleaved input code stream into at least two different buffers in a column, so that the amount of data stored in each buffer is equal, and the input code stream is interleaved.
  • the adjacent column data of the corresponding code stream is located in a storage unit corresponding to different buffers; the input code stream includes an information stream, a first check stream and a second check stream;
  • the stream includes an information stream, a code stream corresponding to the first check stream before performing the interleaving process, and a code stream of the second check stream that is cyclically shifted left by one bit before performing the interleaving process;
  • the corresponding code stream is rotated right by one bit before the interleaving process is performed on the second check stream.
  • a data deinterleaving method is provided in the embodiment of the present invention, including:
  • the receiving end writes the received interleaved input code stream into at least two different buffers in a column, so that the amount of data stored in each buffer is equal, and the input code stream corresponds to the code stream before performing the interleaving process.
  • the adjacent column data is located in a storage unit corresponding to different caches;
  • the adjacent column data is read from the corresponding storage units of different caches and reordered to obtain a code stream corresponding to the input code stream before the interleaving process.
  • An embodiment of the present invention provides a data deinterleaving apparatus, including:
  • a writing module configured to write the received interleaved input code stream into at least two different buffers in columns
  • the at least two different buffers are used to store the input code stream, wherein the amount of data stored in each buffer is equal, and the adjacent column data of the corresponding code stream before the interleaving process is located In a storage unit corresponding to different caches;
  • a reading module configured to read the adjacent column data from the storage unit corresponding to the different caches and reorder, to obtain a code stream corresponding to the input code stream before performing the interleaving process.
  • the embodiment of the invention has the following beneficial effects:
  • the input code stream is written into the at least two different buffers in columns, so that the adjacent column data of the corresponding code stream before the interleaving process can be located in the corresponding storage unit of different caches. .
  • the adjacent column data can be read from the corresponding storage units of different buffers and reordered to obtain the code stream of the input code stream before the interleaving process; further, if the input code stream is further included in the interleaving process
  • the second check that was previously shifted by one bit after the loop Flow the obtained second check stream may be rotated right by one bit before the interleaving process, so that the information flow, the first check stream, and the second check stream of the interleaving process may be completed.
  • the embodiment of the present invention can perform deinterleaving in parallel, thereby improving the throughput of data during deinterleaving.
  • the deinterleaving can be performed since the address is not calculated before the data is written. The complexity.
  • FIG. 1 is a flowchart of a data deinterleaving method according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of a data deinterleaving apparatus according to an embodiment of the present invention.
  • a data deinterleaving method and apparatus which can improve the throughput of data during deinterleaving and balance the complexity of deinterleaving.
  • the data deinterleaving method and apparatus provided in the embodiments of the present invention may perform deinterleaving on the information flow, the first check stream, and the second check stream of the PUSCH channel of the LTE protocol, and may also be used for other Turbo coding chains.
  • the code stream of the path is deinterleaved, which is not limited in the embodiment of the present invention.
  • FIG. 1 is a flowchart of a data deinterleaving method according to an embodiment of the present invention. As shown in FIG. 1, the method may include the following steps:
  • the receiving end writes the received interleaved input code stream into at least two different buffers in a column, so that the amount of data stored in each buffer is equal, and the corresponding code stream is corresponding to the code before the interleaving process.
  • the adjacent column data of the stream is located in a storage unit corresponding to different caches; the input code stream includes an information stream, a first check stream and a second check stream;
  • a BUF may be constructed by one or more storage units, such as RAM, to implement storage of the input code stream after the interleaving process.
  • the code corresponding to the input code stream before performing the interleaving process includes an information stream, a code stream corresponding to each of the first check stream before performing the interleaving process, and a code stream that is cyclically shifted left by one bit before the second check stream is subjected to the interleaving process;
  • the adjacent column data is read from the corresponding storage unit of the different caches and reordered, and the corresponding code stream obtained before the interleaving process is obtained may be:
  • the receiving end reads the adjacent column data from the same storage unit with the same cached address and reorders the data stream corresponding to the input code stream before the interleaving process.
  • the reading of the adjacent column data from the same storage unit with different cache addresses can reduce the frequent jitter read operation at the receiving end and improve the reading efficiency.
  • the number of the at least two different BUFs may be two, and the adjacent two columns of data may be read from the storage units with the same address of the two different BUFs; or, the at least two different The number of BUFs can be eight. In this case, eight columns of data can be read from the same storage unit with the addresses of eight different BUFs, etc.; the adjacent column data can be read and reordered to obtain the input code. The stream corresponding to the stream before the interleaving process is performed.
  • the number of BUFs is 2, 4, 8, 16 and 32 respectively, and the present invention is introduced separately.
  • the data deinterleaving method provided in the embodiment implements parallel deinterleaving processing.
  • the received input code stream subjected to the interleaving process is written into BUF0 and BUF1 in columns, wherein the amount of data stored in BUF0 and BUF1 is equal, and the adjacent column data of the corresponding code stream before the interleaving is performed on the input code stream.
  • the input code stream includes an information stream, a first check stream, and a second check stream that is cyclically shifted left by one bit before performing the interleaving process;
  • the adjacent column data is read from the same storage unit in BUF0 and BUF1 and reordered to obtain a code stream corresponding to the input code stream before the interleaving process. That is, the adjacent column data is read column by column from the same storage unit in BUF0 and BUF1, and after reading all the data of all the columns in each column, the data of all the rows of the next column is read until all adjacent columns are read. The data is read.
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25,
  • the input code stream of the receiving end (such as the base station) after the interleaving process is ⁇ 0, 16, 8, 24, 4 , 20, 12, 28, 2,
  • the received input code stream subjected to the interleaving process is written into BUF0 and BUF1 in columns, as shown in Table 2, wherein the memory cells in BUF0 store 1/2 Input stream
  • the memory location in BUF1 stores 1/2 of the input stream ⁇ 1 , 17, 9, 25, 5, 21, 13, 29, 3,
  • BUF0 and BUF1 store the same amount of data.
  • post_c_idx in Table 2 indicates the column number of the input code stream after the interleaving process
  • c_idx indicates the column number of the input code stream before the interleaving process
  • BUF0 and BUF1 indicate the buffer.
  • the data of each column may have several rows, and since the number of rows of each column before and after the column replacement is the same, and the row number of each row is unchanged, the addresses of the storage units with the same address in the above BUF0 and BUF1 may be Use the following formula to indicate:
  • pos denotes the address of the storage unit with the same address of BUFO and BUF1
  • * denotes the product
  • R denotes the number of lines of the input code stream after the interleaving process
  • r_idx denotes the line number of the input code stream after the interleaving process
  • Equation (1) can calculate the address pos of the memory cell with the same address of BUF0 and BUF1, and then read the adjacent column data from the same address pos of BUF0 and BUF1, and in the order of arrangement [BUFO, BUF1] rearranges the read adjacent column data, that is, the input code stream before the interleaving process can be obtained as ⁇ 0, 1 , 2, 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ⁇ .
  • the arrangement order [BUFO, BUFl] indicates that each time the adjacent column data is read from the same address pos of BUFO and BUF1, the column data is read from the BUF0 and the column data is read from the BUF1.
  • the input code stream before the interleaving process is obtained as ⁇ 0, 1, 2, 3, 4, 5 , 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 , 31 ⁇ .
  • the obtained code stream corresponding to the second check stream before the interleaving process can be rotated right by one bit, thereby completing the information flow and the first school.
  • the flow check and the deinterleaving process of the second check stream can be rotated right by one bit, thereby completing the information flow and the first school.
  • the received input code stream subjected to the interleaving process is written into the BUF0 to BUF3 in columns, wherein the amount of data stored in the BUF0 to BUF3 is equal, and the adjacent column data of the corresponding code stream before the interleaving is performed on the input code stream.
  • the input code stream includes an information stream, a first check stream, and a second check stream that is cyclically shifted left by one bit before performing the interleaving process;
  • the adjacent column data is read from the same storage unit in the BUF0 to the BUF3 and reordered to obtain a code stream corresponding to the input code stream before the interleaving process. That is, the adjacent column data is read column by column from the memory cells with the same address in BUF0 to BUF3, and after reading all the data of all the columns in each column, the data of all the rows of the next column is read until all adjacent columns are read. The data is read. Assume that the input stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8,
  • the input code stream of the receiving end (such as the base station) after the interleaving process is ⁇ 0, 16, 8, 24, 4 , 20, 12, 28, 2,
  • the memory cells in BUF2 store 1/4 of the input code stream ⁇ 1, 17, 9, 25, 5, 21, 13, 29 ⁇
  • the memory cells in BUF3 Stores 1/4 of the input stream ⁇ 3
  • post_c_idx in Table 3 indicates the column number of the input code stream after the interleaving process
  • c_idx indicates the column number of the input code stream before the interleaving process.
  • the data of each column may have several rows, and since the number of rows of each column before and after the column replacement is the same, and the row number of each row is unchanged, the addresses of the storage units having the same addresses in the above BUF0 to BUF3 are It can be expressed by the formula ( 1 ).
  • pos denotes the address of the storage unit with the same address of BUF0 to BUF3
  • R denotes the number of lines of the input code stream after the interleaving process
  • r_idx denotes the line number of the input code stream after the interleaving process
  • the above pos post_c_idx.
  • the address pos of the cell in turn, can read adjacent column data from the same address pos of BUF0 to BUF3, and rearrange the read adjacent column data according to the arrangement order [BUFO, BUF2, BUF1, BUF3], that is,
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ⁇ .
  • the obtained code stream corresponding to the second check stream before the interleaving process can be rotated right by one bit, thereby completing the information flow and the first school.
  • the flow check and the deinterleaving process of the second check stream can be rotated right by one bit, thereby completing the information flow and the first school.
  • the received input code stream subjected to the interleaving process is written into the BUF0 to BUF7 in columns, wherein the amount of data stored in the BUF0 to BUF7 is equal, and the adjacent column data of the corresponding code stream before the interleaving is performed on the input code stream.
  • the input code stream includes an information stream, a first check stream, and a second check stream that is cyclically shifted left by one bit before performing the interleaving process;
  • the adjacent column data is read from the same storage unit in BUF0 to BUF7 and reordered, and the code stream of the input code stream before the interleaving process is obtained. That is, the data of the adjacent column is read column by column from the storage unit with the same address in BUF0 to BUF7, and after the data of all the rows of each column is read, the data of all the rows of the next column is read until all the adjacent The column data is read.
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25,
  • the input code stream of the receiving end (such as the base station) after the interleaving process is ⁇ 0, 16, 8, 24, 4 , 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
  • the memory cells in BUF0 store 1/8 of the input.
  • post_c_idx in Table 4 indicates the column number of the input code stream after the interleaving process
  • c_idx indicates the column number of the input code stream before the interleaving process.
  • the adjacent column data of the same address pos of BUF0 to BUF7 is read, and the adjacent column data read is rearranged according to the arrangement order [BUF0, BUF4, BUF2, BUF6, BUF1, BUF5, BUF3, BUF7], that is,
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ⁇ .
  • the input code stream before the interleaving process is obtained is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18 , 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ⁇ .
  • the obtained code stream corresponding to the second check stream before the interleaving process can be rotated right by one bit, thereby completing the information flow and the first school.
  • the flow check and the deinterleaving process of the second check stream can be rotated right by one bit, thereby completing the information flow and the first school.
  • the received input code stream subjected to the interleaving process is written into the BUF0 to BUF15 in columns, wherein the amount of data stored in the BUF0 to BUF15 is equal, and the code corresponding to the interleaving is performed on the input code stream.
  • the adjacent column data of the stream is located in the same storage unit in the BUF0 to BUF15; wherein the input code stream includes the information stream, the first check stream, and the second processing that is cyclically shifted left by one bit before performing the interleaving process Check flow
  • the adjacent column data is read from the same storage unit in BUF0 to BUF15 and reordered to obtain a code stream corresponding to the input code stream before the interleaving process. That is, the data of the adjacent column is read column by column from the storage unit with the same address in BUF0 to BUF15, and after the data of all the rows of each column is read, the data of all the rows of the next column is read until all the adjacent The column data is read.
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25,
  • the input code stream of the receiving end (such as the base station) after the interleaving process is ⁇ 0, 16, 8, 24, 4 , 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
  • the memory location in BUF1 stores 1/16 of the input code stream ⁇ 8, 24 ⁇
  • the memory location in BUF2 stores 1/16 of the input code stream ⁇ 4, 20 ⁇ , ..., in BUF13
  • the storage unit stores 1/16 of the input code stream ⁇ 11, 27 ⁇
  • the storage unit in BUF 14 stores 1/16 of the input code stream ⁇ 7, 23 ⁇
  • the memory cells in BUF15 store 1/16 of the input stream ⁇ 15, 31 ⁇ , that is, the amount of data stored in BUF0 to BUF15 is equal.
  • post_c_idx in Table 5 indicates the column number of the input code stream after the interleaving process
  • c_idx indicates the column number of the input code stream before the interleaving process.
  • the input code stream is adjacent to the column 0, 8, 4, 12, 2, 10, 6, 14, before the interleaving process.
  • the data of each column may have several rows, and since the number of rows of each column before and after the column replacement is the same, and the row number of each row is unchanged, the above-mentioned BUFO to BUF 15 has the same address of the storage unit.
  • the address can be represented by the formula ( 1 ).
  • pos represents the address of the storage unit with the same address from BUFO to BUF15
  • R represents the number of lines of the input code stream after the interleaving process
  • r_idx represents the line number of the input code stream after the interleaving process
  • the above pos post_c_idx.
  • Rearranging the read adjacent column data that is, the input code stream before the interleaving process can be obtained as ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 , 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ⁇ .
  • the obtained code stream corresponding to the second check stream before the interleaving process can be rotated right by one bit, thereby completing the information flow and the first school.
  • the flow check and the deinterleaving process of the second check stream can be rotated right by one bit, thereby completing the information flow and the first school.
  • the received input code stream subjected to the interleaving process is written into the BUF0 to BUF31 in columns, wherein the amount of data stored in the BUF0 to BUF31 is equal, and the adjacent column data of the corresponding code stream before the interleaving is performed on the input code stream.
  • the distribution is stored in a storage unit having the same address in BUF0 to BUF31; wherein the input code stream includes an information stream, a first verification stream, and a second verification stream that is cyclically shifted left by one bit before performing the interleaving process;
  • the adjacent column data is read from the same storage unit in BUF0 to BUF31 and reordered, and the code stream of the input code stream before the interleaving process is obtained. That is, the data of the adjacent column is read column by column from the storage unit with the same address in BUF0 to BUF31, and after the data of all the rows of each column is read, the data of all the rows of the next column is read until all the adjacent The column data is read.
  • the input code stream before the interleaving process is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25,
  • the input code stream of the receiving end (such as the base station) after the interleaving process is ⁇ 0, 16, 8, 24, 4 , 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
  • the input code stream after the interleaving process is written in columns to BUF0 to BUF31 Thereafter, as shown in Table 6, the memory cells in BUFO store 1/32 of the input code stream ⁇ 0 ⁇ , the memory cells in BUF1 store 1/32 of the input code stream ⁇ 16 ⁇ , and the memory cells in BUF2 are stored. 1/32 of the input stream ⁇ 8 ⁇ , ..., the storage unit in BUF30 stores 1/32 of the input stream ⁇ 15 ⁇ ,
  • the memory location in BUF31 stores 1/32 of the input stream ⁇ 31 ⁇ , that is, the amount of data stored in BUF0 to BUF31 is equal.
  • post_c_idx in Table 6 indicates the column number of the input code stream after the interleaving process
  • c_idx indicates the column number of the input code stream before the interleaving process.
  • the input code stream is adjacent to the column 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10 before the interleaving process.
  • the data is located at the address of BUF0 to BUF16 In the same storage unit.
  • pos denotes the address of the storage unit with the same address of BUF0 to BUF31
  • R denotes the number of lines of the input code stream after the interleaving process
  • r_idx denotes the line number of the input code stream after the interleaving process
  • the above pos post_c_idx.
  • the obtained code stream corresponding to the second check stream before the interleaving process can be rotated right by one bit, thereby completing the information flow and the first school.
  • the flow check and the deinterleaving process of the second check stream can be rotated right by one bit, thereby completing the information flow and the first school.
  • the data deinterleaving method provided in the embodiment of the present invention is introduced.
  • the embodiment of the present invention can perform deinterleaving in parallel, thereby improving the throughput of data during deinterleaving.
  • the address is not calculated before the data is written, The complexity of deinterleaving can be balanced.
  • the data deinterleaving method provided by the embodiment of the present invention may include the foregoing steps 101 and 102, where The same as the above-mentioned example one to the fifth embodiment, and the embodiments of the present invention are not described herein.
  • the deinterleaving can be performed in parallel, so that the throughput of data at the time of deinterleaving can be improved; in addition, since the address is not calculated before the data is written, the complexity of deinterleaving can be balanced.
  • FIG. 2 is a structural diagram of a data deinterleaving apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus may include:
  • the writing module 201 is configured to write the received interleaved input code stream into at least two different caches 202 in columns;
  • the input code stream subjected to the interleaving process is an information stream or a first check stream.
  • At least two different buffers 202 are configured to store the input code stream written by the write module 201, wherein the amount of data stored in each buffer is equal, and the adjacent input code stream is adjacent to the corresponding code stream before the interleaving process is performed.
  • Column data is located in a storage unit corresponding to different caches;
  • the reading module 203 is configured to read adjacent column data from the storage units corresponding to different caches and reorder, to obtain a code stream corresponding to the input code stream before performing the interleaving process.
  • the adjacent column data of the corresponding code stream of the above input code stream before the interleaving process may be located in the same storage unit with the same cache address.
  • the reading module 203 can read the adjacent column data from the same storage unit from the different buffers and reorder the data stream to obtain the code stream corresponding to the input code stream before the interleaving process.
  • the device may further include:
  • the adjusting module 204 is configured to shift the loop of the corresponding code stream to the right by one bit before performing the interleaving process on the second check stream obtained by the reading module 203.
  • the writing module 201 may be specifically configured to write the received interleaved input code stream into columns BUF0 and BUF1 as shown in Table 2;
  • the reading module 203 can be specifically configured to read adjacent column data from the storage units of the BUF0 and BUF1 addresses post_c_idx*R+r_idx, where post_c_idx represents the interleaved input.
  • the writing module 201 can be specifically used to input the received interleaved input.
  • the code stream is written in columns as BUF0 to BUF3 as shown in Table 3;
  • the reading module 203 can be specifically configured to read adjacent column data from the storage unit of the BUF0 to BUF3 address post_c_idx*R+r_idx, where post_c_idx represents the column of the input code stream subjected to the interleaving process
  • post_c_idx represents the column of the input code stream subjected to the interleaving process
  • the serial number, * indicates the product
  • R indicates the number of lines of the input code stream subjected to the interleaving process
  • r_idx indicates the line number of the input code stream subjected to the interleaving process
  • post_c_idx takes values in order: 0, 4, 2, 6, 1 , 5 , 3 , 7; and in the order of arrangement [BUFO, BUF2, BUF1, BUF3] rearrange the adjacent column data read.
  • the writing module 201 may be specifically configured to write the received interleaved input code stream into the BUF0 to BUF7 as shown in Table 4;
  • the foregoing reading module 203 is specifically configured to read adjacent column data from the storage unit of the address BU_0 to BUF7 with the address of post_c_idx*R+r_idx, where post_c_idx represents the input code stream subjected to the interleaving process.
  • the column number, * indicates the product
  • R indicates the number of lines of the input code stream subjected to the interleaving process
  • r_idx indicates the line number of the input code stream subjected to the interleaving process
  • post_c_idx takes values in order: 0, 2, 1, 3; and in the order of arrangement [BUFO, BUF4, BUF2, BUF6, BUF1 , BUF5 , BUF3 , BUF7] rearrange the adjacent column data read.
  • the writing module 201 may be specifically configured to write the received interleaved input code stream into the BUF0 to BUF15 as shown in Table 5;
  • the foregoing reading module 203 is specifically configured to read adjacent column data from the storage unit of the address BU_0 to BUF15 with the address of post_c_idx*R+r_idx, where post_c_idx represents the input code stream subjected to the interleaving process.
  • the column number, * indicates the product
  • R indicates the number of rows of the input code stream subjected to the interleaving process
  • r - idx indicates the row number of the interleaved input code stream after the interleaving process
  • post_c_idx takes values in order: 0, 1; and in the order [BUFO, BUF8, BUF4, BUF12, BUF2, BUF10, BUF6, BUF14, BUF1, BUF9, BUF5, BUF13, BUF3, BUF11, BUF7, BUF 15] rearrange the adjacent column data read.
  • the writing module 201 can be specifically used to input the received interleaved input.
  • the code stream is written into the BUF0 to BUF31 as shown in Table 6 in columns;
  • the reading module 203 is specifically configured to read the data of the adjacent column from the address of the BUF0 to the BUF 31 as post_c_idx*R+r_idx, where post_c_idx represents the input processed by the interleaving process.
  • the column number of the code stream, * indicates the product
  • R indicates the number of lines of the input code stream subjected to the interleaving process
  • r_idx indicates the line number of the input code stream subjected to the interleaving process
  • the data deinterleaving device provided in the embodiment of the present invention is described above.
  • the embodiment of the present invention can perform deinterleaving in parallel, thereby improving the throughput of the deinterleaving.
  • the equalization can be performed. The complexity of deinterleaving.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes the steps of the above method embodiment; and the foregoing storage medium includes: a read only memory (ROM), a random access device (RAM) ), a variety of media such as a disk or an optical disk that can store program code.
  • ROM read only memory
  • RAM random access device

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

一种数据解交织方法及装置,该方法包括:接收端将接收到的经过交织处理的输入码流按列写入至少二个不同缓存,使得每个缓存中存储的数据量相等,且该输入码流在交织处理之前对应的码流的相邻列数据位于不同缓存相对应的存储单元中(101);该输入码流包括信息流,第一校验流及第二校验流;从不同缓存相对应的存储单元中读取相邻列数据并重新排序,获得该输入码流在交织处理之前对应的码流;该输入码流在交织处理之前对应的码流包括信息流、第一校验流在交织处理之前各自对应的码流,及第二校验流在交织处理之前经过循环左移一位处理的码流(102);将第二校验流在交织处理之前对应的码流循环右移一位(103)。本发明可以提高解交织时数据的吞吐率,并且均衡解交织的复杂度。

Description

一种数据解交织方法及装置 本申请要求于 2010 年 8 月 24 日提交中国专利局、 申请号为 201010264163.2、 发明名称为 "一种数据解交织方法及装置" 的中国专利申 请的优先权, 其全部内容通过引用结合在本申请中。 技术领域
本发明主要涉及通信技术领域, 特别涉及一种数据解交织方法及装置。 背景技术
在长期演进 ( Long Term Evolution, LTE )协议中, 物理上行共享信道 ( Physical Uplink Share Channel, PUSCH )作为一种 1/3码率的 Turbo编码链 路。 经过 Turbo编码后, PUSCH信道上可以产生 3路码流, 分别为信息流、 第一校验流、 第二校验流。
为了避免在 PUSCH信道上传输时受到突发性噪声干扰而导致一连串的 数据错误, 通常需要在发送端 (如用户终端 )分别对 3路码流进行如下交织: 即将输入码流按照 32bits为 1行写入交织矩阵 (如果码流长度不是 32bits的 整数倍,则在码流前端添加交织哑元,使得交织矩阵中每 1行都包含 32bits ); 对交织矩阵进行列置换, 即按照 LTE协议规定的列置换规则对上述交织矩阵 中的列顺序进行调整; 按列将交织矩阵中所有数据读取并传输。 其中, LTE 协议规定的信息流、 第一校验流专用的列置换规则如下表 1所示:
表 1
Figure imgf000003_0001
其中, C ft=32, 表示交织矩阵中的列数; P (_/· )表示为列置换后第 j 列在列置换前的列序号。 例如, (())=0表示列置换后的第 0列在列置换前 的列序号为 0; Ρ ( 1 ) =16表示列置换后的第 1列在列置换前的列序号为 16, 以此类推。 其中, 由于 LTE协议规定的第二校验流的列置换规则与上述表 1 不同, 在使用上述表 1所示的列置换规则对第二校验流进行交织前, 需要在 第二校验流前端添加交织哑元, 并将整个码流循环左移一位。
在接收端(如基站), 需要分别对上述已交织的信息流、 第一校验流以及 第二校验流进行解交织, 从而恢复出交织前的 3路码流。 例如, 假定接收码 流行数为 R, 当接收端接收到第 0列 (每一列数据为 R个)数据时, 根据表 1所示的列置换规则可知, 该列数据在交织前的列号为 P ( 0 ) =0, 则按照地 址 =0, 1 , ... ... , R-1将第 0列数据写入存储器例如随机存储器( Random Access
Memory, RAM ) 中; 当接收端接收到第 1列数据时, 根据表 1所示的列置 换规则可知, 该列数据在交织前的列号为 P ( l ) =16, 则按照地址 =16R, 16R+1 , ... ... , 16R+ ( R-1 )将第 1列数据写入 RAM中; 当接收端接收到第
2列数据时,根据表 1所示的列置换规则可知,该列数据在交织前的列号为 P ( 2 ) =8, 则按照地址 =8R, 8R+1 , ... ... , 8R+ ( R-1 )将第 2列数据写入 RAM 中; ... ...; 依次类推, 直到 RAM存储了完整的码流之后, 再按地址顺序读 取出来。 由于第二校验位与信息位、 第一校验流在交织处理上的细微差别, 在读取第二校验流之后, 还需要将第二校验流循环右移一位, 即将第二校验 流最后一位移至第二校验流首端。 至此, 完成对已交织的信息流、 第一校验 流以及第二校验流进行解交织。
上述的接收端在对码流进行解交织时, 对每一路码流来说, 以串行方式 将接收的每一列数据在交织前的地址计算出来, 并按照该交织前的地址写入 RAM中 , 在码流全部写入 RAM后 , 再按地址从 RAM中顺序读取出来。 这 样, 会降低解交织时数据的吞吐率; 而且在将码流写入 RAM之前进行地址 计算, 还会导致解交织的复杂度的不均衡。
发明内容
本发明实施例中提供了一种数据解交织方法及装置, 能够提高解交织时 数据的吞吐率, 并且均衡解交织的复杂度。
本发明实施例中提供了一种数据解交织方法, 包括:
接收端将接收到的经过交织处理的输入码流按列写入至少二个不同緩 存, 以使得每个緩存中存储的数据量相等, 而且所述输入码流在进行交织处 理之前对应的码流的相邻列数据位于不同緩存相对应的存储单元中; 所述输 入码流包括信息流, 第一校验流以及第二校验流;
从不同緩存相对应的存储单元中读取所述相邻列数据并重新排序, 获得 所述输入码流在进行交织处理之前对应的码流; 所述输入码流在进行交织处 理之前对应的码流包括信息流、 第一校验流在进行交织处理之前各自对应的 码流, 以及所述第二校验流在进行交织处理之前经过循环左移一位处理的码 流;
将第二校验流在进行交织处理之前对应的码流循环右移一位。
本发明实施例中提供了一种数据解交织方法, 包括:
接收端将接收到的经过交织处理的输入码流按列写入至少二个不同緩 存, 以使得每个緩存中存储的数据量相等, 而且所述输入码流在进行交织处 理之前对应的码流的相邻列数据位于不同緩存相对应的存储单元中;
从不同緩存相对应的存储单元中读取所述相邻列数据并重新排序, 获得 所述输入码流在进行交织处理之前对应的码流。
本发明实施例中提供了一种数据解交织装置, 包括:
写入模块, 用于将接收到的经过交织处理的输入码流按列写入至少二个 不同緩存;
所述至少二个不同緩存, 用于存储所述输入码流, 其中, 每个緩存中存 储的数据量相等, 而且所述输入码流在进行交织处理之前对应的码流的相邻 列数据位于不同緩存相对应的存储单元中;
读取模块, 用于从所述从不同緩存相对应的存储单元中读取所述相邻列 数据并重新排序, 获得所述输入码流在进行交织处理之前对应的码流。
与现有的技术相比, 本发明实施例具有以下有益效果:
本发明实施例中, 将输入码流按列写入至少二个不同緩存, 使得该输入 码流在进行交织处理之前对应的码流的相邻列数据可以位于不同緩存的相对 应的存储单元中。 这样, 可以从不同緩存相对应的存储单元中读取上述相邻 列数据并重新排序, 获得该输入码流在进行交织处理之前的码流; 进一步地, 若输入码流还包括在进行交织处理之前经过循环左移一位处理的第二校验 流, 则可以将获得的第二校验流在进行交织处理之前对应的码流循环右移一 位, 从而可以完成对进行交织处理的信息流、 第一校验流以及第二校验流的 解交织处理。 与釆用串行方式进行解交织相比, 本发明实施例可以并行地进 行解交织, 从而能够提高解交织时数据的吞吐率; 另外, 由于在写入数据之 前无需计算地址, 可以均衡解交织的复杂度。
附图说明
为了更清楚地说明本发明实施例中的技术方案, 下面将对实施例中所需 要使用的附图作简单地介绍, 显而易见地, 下面描述中的附图仅仅是本发明 的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动的前提 下, 还可以根据这些附图获得其他的附图。
图 1 为本发明实施例中提供的一种数据解交织方法的流程图;
图 2 为本发明实施例中提供的一种数据解交织装置的结构图。
具体实施方式
下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行 清楚、 完整地描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而 不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例, 都属于本发明保护的范围。
本发明实施例中提供了一种数据解交织方法及装置, 能够提高解交织时 数据的吞吐率, 并且均衡解交织的复杂度。 其中, 本发明实施例中所提供的 数据解交织方法及装置可以对 LTE协议的 PUSCH信道的信息流、 第一校验 流以及第二校验流进行解交织处理, 也可以对其他 Turbo编码链路的码流进 行解交织, 本发明实施例不作限定。
请参阅图 1,图 1为本发明实施例中提供的一种数据解交织方法的流程图, 如图 1所示, 该方法可以包括以下步骤:
101、接收端将接收到的经过交织处理的输入码流按列写入至少二个不同 緩存, 以使得每个緩存中存储的数据量相等, 而且该输入码流在进行交织处 理之前对应的码流的相邻列数据位于不同緩存相对应的存储单元中; 该输入 码流包括信息流, 第一校验流以及第二校验流; 本实施例中, 上述至少二个不同緩存 ( BUF ) 的数量具体可以是 2n个, 其中, K=n<=5。 即上述至少二个不同 BUF的具体可以是 2个、 4个、 8个、 16个或 32个。
本实施例中,一个 BUF可以由一个或多个存储单元例如 RAM搭建构成 , 实现对进行交织处理后的输入码流的存储。
102、从不同緩存相对应的存储单元中读取相邻列数据并重新排序,获得 上述输入码流在进行交织处理之前对应的码流; 其中, 上述输入码流在进行 交织处理之前对应的码流包括信息流、 第一校验流在进行交织处理之前各自 对应的码流, 以及第二校验流在进行交织处理之前经过循环左移一位处理的 码流;
本实施例中, 从不同緩存相对应的存储单元中读取相邻列数据并重新排 序, 获得上述输入码流在进行交织处理之前对应的码流具体可以为:
接收端从不同緩存的地址相同的存储单元中读取上述相邻列数据并重新 排序, 获得所述输入码流在进行交织处理之前对应的码流。 其中, 从不同緩 存的地址相同的存储单元中读取上述相邻列数据可以减少接收端频繁的跳动 读取操作, 提高读取效率。
本实施例中, 上述至少二个不同 BUF的数量可以是 2个, 此时可以从 2 个不同 BUF的地址相同的存储单元中读取相邻的 2列数据; 又或者,上述至 少二个不同 BUF的数量可以是 8个, 此时可以从 8个不同 BUF的地址相同 的存储单元中读取相邻的 8列数据等等; 读取相邻列数据后可以重新排序, 从而获得该输入码流在进行交织处理之前对应的码流。
103、 将第二校验流在进行交织处理之前对应的码流循环右移一位。 由于在进行交织处理之前, 第二校验流经过循环左移一位处理, 所以第 二校验流在进行交织处理之前对应的码流的首位必定是交织哑元, 所以第二 校验在进行交织处理之前对应的码流循环右移一位可以直接通过如下方式实 现: 即在第二校验流对应的码流的首端添加一个交织哑元, 然后去掉其最后 一位。
下面分别以 BUF的数量为 2, 4, 8, 16和 32为例, 分别介绍本发明实 施例中提供的数据解交织方法, 实现并行解交织处理。
举例一:
先将接收到的进行交织处理的输入码流按列写入 BUF0和 BUF1, 其中, BUF0和 BUF1 中存储的数据量相等, 而且该输入码流在进行交织之前对应 的码流的相邻列数据位于 BUF0和 BUF1中的地址相同的存储单元中;其中, 该输入码流包括信息流, 第一校验流以及在进行交织处理之前经过循环左移 一位处理的第二校验流;
从 BUF0和 BUF1中的地址相同的存储单元中读取上述的相邻列数据并 重新排序, 获得该输入码流在进行交织处理之前对应的码流。 即, 从 BUF0 和 BUF1中的地址相同的存储单元中逐列地读取相邻列数据, 每一列所有行 的数据全部读完后, 再读下一列的所有行的数据, 直至所有相邻列数据读取 完毕为止。
假设在进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31}, 则根据表 1所述的列置换规则可知, 进行交织处 理之后接收端(如基站)的输入码流为 {0, 16, 8, 24, 4, 20, 12, 28, 2,
18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
27, 7, 23, 15, 31}, 则将接收到的进行交织处理的输入码流按列写入 BUF0 和 BUF1后, 如表 2所示, 其中, BUF0中的存储单元存储了 1/2的输入码流
{0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30}, BUF1 中的存储单元存储了 1/2的输入码流 {1, 17, 9, 25, 5, 21, 13, 29, 3,
19, 11, 27, 7, 23, 15, 31}, 即 BUF0和 BUF1存储的数据量相等。
表 2
Figure imgf000009_0001
其中 , 表 2中的 post— c— idx表示进行交织处理之后的输入码流的列序号, c_idx表示进行交织处理之前的输入码流的列序号, BUF0和 BUF 1表示緩存。 如表 2所示, 当 post— c— idx=0时, 该输入码流在进行交织之前的相邻列 0和 1的数据位于 BUF0和 BUF1的地址相同的存储单元中; 当 post— c— idx=l时, 该输入码流在进行交织之前的相邻列 16和 17的数据位于 BUF0和 BUF1的 地址相同的存储单元中; ... ...; 当 post— c— idx=15时, 该输入码流在进行交织 之前的相邻列 30和 31的数据位于 BUF0和 BUF1的地址相同的存储单元中。
本实施例中, 每一列的数据可能存在若干行, 并且由于列置换前后每一 列的行数相同, 而且每一行的行序号不变, 所以上述 BUF0和 BUF1中的地 址相同的存储单元的地址可以釆用以下公式表示:
pos=post_c_idx*R+r_idx ( 1 )
其中, pos表示 BUFO和 BUF1的地址相同的存储单元的地址, *表示作 乘积, R表示进行交织处理之后的输入码流的行数, r— idx表示进行交织处理 之后的输入码流的行序号, r_idx从 0开始,直至最后一行 r— idx=R-l。当 r— idx 每取一个值时, post— c— idx按顺序依次取值 =0, 8, 4, 12, 2, 10, 6, 14, 1 , 9, 5 , 13 , 3 , 11 , 7, 15 , 16。 在每一列的数据仅存在一行的情况下, 上述 的 pos=post— c— idx。
当 r— idx每取一个值时, 依次将 post— c—idx=0, 8, 4, 12, 2, 10, 6, 14, 1 , 9, 5 , 13 , 3 , 11 , 7, 15代入公式( 1 ) 即可计算出 BUF0和 BUF1的地 址相同的存储单元的地址 pos, 进而可以从 BUF0和 BUF1 的相同地址 pos 中读取紧挨着的相邻列数据, 并按照排列顺序 [BUFO, BUF1]将读取的相邻 列数据重新排列, 即可以获得进行交织处理之前的输入码流为 { 0, 1 , 2, 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。 其中, 排列顺序 [BUFO, BUFl] 表示每一次从 BUFO和 BUFl的相同地址 pos读取紧挨着的相邻列数据之后, 将从 BUF0读取列数据排在前面, 将从 BUF1读取列数据排在后面。 例如, 从 BUF0和 BUF1的相同地址 pos ( ost_c_idx=0 ) 中读取相邻列数据为 0和 1, 将读取的相邻列数据 0和 1按照排列顺序 [BUFO, BUFl]进行排序为 {0, 1}; 其中, post— c— idx依次取值 =0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15, 将每一次从 BUF0和 BUF1的相同地址 pos读取紧挨着的相 邻列数据进行重新排列并连接后, 即可获得进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。
本实施例中, 可以设置 elk— cnt[3:0] 为时钟计数器, 记录读取操作的时 钟数, 取值范围为 [0, 15], 贝' J post_c_idx={clk_cnt[0], clk_cnt[l], clk_cnt[2], elk— cnt[3]}。
在获得该输入码流在进行交织处理之前对应的码流之后, 可以将获得的 在进行交织处理之前的第二校验流对应的码流循环右移一位, 从而完成信息 流、 第一校验流以及第二校验流的解交织处理。
举例二:
先将接收到的进行交织处理的输入码流按列写入 BUF0至 BUF3, 其中, BUF0至 BUF3 中存储的数据量相等, 而且该输入码流在进行交织之前对应 的码流的相邻列数据位于 BUF0至 BUF3中的地址相同的存储单元中;其中, 该输入码流包括信息流, 第一校验流以及在进行交织处理之前经过循环左移 一位处理的第二校验流;
从 BUF0至 BUF3中的地址相同的存储单元中同读取上述的相邻列数据 并重新排序,获得该输入码流在进行交织处理之前对应的码流。 即,从 BUF0 至 BUF3中的地址相同的存储单元中逐列地读取相邻列数据, 每一列所有行 的数据全部读完后, 再读下一列的所有行的数据, 直至所有相邻列数据读取 完毕为止。 假设在进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31}, 则根据表 1所述的列置换规则可知, 进行交织处 理之后接收端(如基站)的输入码流为 {0, 16, 8, 24, 4, 20, 12, 28, 2,
18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
27, 7, 23, 15, 31 }, 则将进行交织处理的输入码流按列写入 BUF0至 BUF3 后, 如表 3所示, 其中, BUF0中的存储单元存储了 1/4的输入码流 {0, 16, 8, 24, 4, 20, 12, 28}, BUF1中的存储单元存储了 1/4的输入码流 {2, 18,
10, 26, 6, 22, 14, 30}, BUF2中的存储单元存储了 1/4的输入码流 {1, 17, 9, 25, 5, 21, 13, 29}, BUF3中的存储单元存储了 1/4的输入码流 {3,
19, 11, 27, 7, 23, 15, 31}, 即 BUF0至 BUF3存储的数据量相等。
其中, 表 3中的 post— c— idx表示进行交织处理之后的输入码流的列序号, c_idx 表示进行交织处理之前的输入码流的列序号。 如表 3 所示, 当 post_c_idx=0时, 该输入码流在进行交织处理之前的相邻列 0, 2, 1和 3的 数据位于 BUF0至 BUF3的地址相同的存储单元中; 当 post— c— idx=l时, 该 输入码流在进行交织处理之前的相邻列 16, 18, 17和 15的数据位于 BUF0 至 BUF3的地址相同的存储单元中; ......; 当 post— c— idx=7时, 该输入码流 在进行交织处理之前的相邻列 28, 30, 29和 31的数据位于 BUF0至 BUF3 的地址相同的存储单元中。
表 3
Figure imgf000012_0001
本实施例中, 每一列的数据可能存在若干行, 并且由于列置换前后每一 列的行数相同, 而且每一行的行序号不变, 所以上述的 BUF0至 BUF3中的 地址相同的存储单元的地址可以釆用公式( 1 )来表示。其中, pos表示 BUF0 至 BUF3的地址相同的存储单元的地址, R表示进行交织处理后的输入码流 的行数, r— idx表示进行交织处理后的输入码流的行序号, r— idx从 0开始, 直至最后一行 r— idx=R-l。 当 r— idx每取一个值时, post— c— idx按顺序依次取 值 =0, 4, 2, 6, 1, 5, 3, 7。 在每一列的数据仅存在一行的情况下, 上述 的 pos=post— c— idx。
当 r— idx每取一个值时, 依次将 post— c—idx=0, 4, 2, 6, 1, 5, 3, 7代 入公式( 1 ) 即可计算出 BUF0至 BUF3的地址相同的存储单元的地址 pos, 进而可以从 BUF0至 BUF3的相同地址 pos中读取相邻列数据, 并按照排列 顺序 [BUFO, BUF2, BUFl, BUF3]将读取的相邻列数据重新排列, 即可以获 得进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }。 例如, 从 BUF0至 BUF3的相同地址 pos ( post— c— idx=0 ) 中读取相邻列数据为 0, 2, 1和 3, 将读取的相邻列数据 0, 2, 1和 3按照 排列顺序 [BUFO, BUF2, BUFl, BUF3]进行排序为 {0, 1, 2, 3 }; 其中, post— c— idx依次取值 =0, 4, 2, 6, 1, 5, 3, 7, 将每一次从 BUF0至 BUF3 的相同地址 pos读取紧挨着的相邻列数据进行重新排列并连接后, 即可获得 进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。
本实施例中, 可以设置 elk— cnt[2:0] 为时钟计数器, 记录读取操作的时 钟数, 取值范围为 [0 , 7], 则 post_c_idx= {clk_cnt[0], clk_cnt[ 1 ], clk_cnt[2] }。
在获得该输入码流在进行交织处理之前对应的码流之后, 可以将获得的 在进行交织处理之前的第二校验流对应的码流循环右移一位, 从而完成信息 流、 第一校验流以及第二校验流的解交织处理。
举例三:
先将接收到的进行交织处理的输入码流按列写入 BUF0至 BUF7, 其中, BUF0至 BUF7 中存储的数据量相等, 而且该输入码流在进行交织之前对应 的码流的相邻列数据位于 BUF0至 BUF7中的地址相同的存储单元中;其中, 该输入码流包括信息流, 第一校验流以及在进行交织处理之前经过循环左移 一位处理的第二校验流;
从 BUF0至 BUF7中的地址相同的存储单元中读取上述相邻列数据并重 新排序,获得该输入码流在进行交织处理之前的码流。 即,从 BUF0至 BUF7 中的地址相同的存储单元中逐列地读取相邻列的数据, 每一列所有行的数据 全部读完后, 再读下一列的所有行的数据, 直至所有相邻列数据读取完毕为 止。
假设在进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31}, 则根据表 1所述的列置换规则可知, 进行交织处 理之后接收端(如基站)的输入码流为 {0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
27, 7, 23, 15, 31},则将进行交织处理后的输入码流按列写入 BUF0至 BUF7 后, 如表 4所示, 其中, BUF0中的存储单元存储了 1/8的输入码流 {0, 16, 8, 24}, BUF1中的存储单元存储了 1/8的输入码流 {4, 20, 12, 28}, BUF2 中存储了 1/8的输入码流 {2, 18, 10, 26}, BUF3中的存储单元存储了 1/8 的输入码流 {6, 22, 14, 30}, BUF4的存储单元中存储了 1/8的输入码流 {1, 17, 9, 25}, BUF5的存储单元中存储了 1/8的输入码流 {5, 21, 13, 29}, BUF6中的存储单元存储了 1/8的输入码流 {3, 19, 11, 27}, BUF7中的存 储单元存储了 1/8的输入码流 {7, 23, 15, 31}, 即 BUF0〜BUF7存储的数 据量相等。
其中, 表 4 中的 post— c— idx表示进行交织处理后的输入码流的列序号, c_idx 表示进行交织处理之前的输入码流的列序号。 如表 4 所示, 当 post— c— idx=0时, 该输入码流在进行交织处理之前的相邻列 0, 4, 2, 6, 1, 5 , 3和 7的数据位于 BUF0至 BUF7的地址相同的存储单元中;当 post— c— idx=l 时, 该输入码流在进行交织处理之前的相邻列 16, 20, 18, 22, 17, 21, 15 和 23 的数据位于 BUF0 至 BUF7 的地址相同的存储单元中; ......; 当 post_c_idx=3时, 该输入码流在进行交织处理之前的相邻列 24, 28, 26, 30, 25, 29, 27和 31的数据位于 BUF0至 BUF7的地址相同的存储单元中。
表 4
Figure imgf000014_0001
本实施例中, 每一列的数据可能存在若干行, 并且由于列置换前后每一 列的行数相同, 而且每一行的行序号不变, 所以上述的 BUF0至 BUF7中的 地址相同的存储单元的地址可以釆用公式( 1 )来表示。其中, pos表示 BUF0 至 BUF7的地址相同的存储单元的地址, R表示进行交织处理后的输入码流 的行数, r—idx表示进行交织处理后的输入码流的行序号, r— idx从 0开始, 直至最后一行 r— idx=R-l。 当 r—idx每取一个值时, post— c— idx按顺序依次取 值 ==0, 2, 1,3。在每一列的数据仅存在一行的情况下,上述的 pos=post— c— idx。
当 r—idx每取一个值时, 依次将 post— c—idx=0, 2, 1, 3代入公式( 1 ) 即可计算出 BUF0至 BUF7的地址相同的存储单元的地址 pos, 进而可以从 BUF0至 BUF7的相同地址 pos中读取相邻列数据, 并按照排列顺序 [BUF0 , BUF4, BUF2, BUF6, BUF1, BUF5, BUF3, BUF7]将读取的相邻列数据重 新排列, 即可以获得进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。 例如, 从 BUF0至 BUF7 的相同地址 pos ( ost_c_idx=0 ) 中读取相邻列数据为 0, 4, 2, 6, 1, 5, 3和 7, 将读取的 相邻列数据 0, 4, 2, 6, 1, 5, 3和 7按照排列顺序 [BUFO, BUF4, BUF2, BUF6, BUF1, BUF5, BUF3, BUF7]进行排序为 {0, 1, 2, 3, 4, 5, 6, 7}; 其中, post— c— idx依次取值 =0, 2, 1, 3, 将每一次从 BUF0至 BUF7的 相同地址 pos读取紧挨着的相邻列数据进行重新排列并连接后, 即可获得进 行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。
本实施例中, 可以设置 elk— cnt[l:0] 为时钟计数器, 记录读取操作的时 钟数, 取值范围为 [0 , 3], 则 post_c_idx= {clk_cnt[0], clk_cnt[ 1 ] }。
在获得该输入码流在进行交织处理之前对应的码流之后, 可以将获得的 在进行交织处理之前的第二校验流对应的码流循环右移一位, 从而完成信息 流、 第一校验流以及第二校验流的解交织处理。
举例四:
先将接收到的进行交织处理的输入码流按列写入 BUF0至 BUF15,其中, BUF0至 BUF15中存储的数据量相等, 而且该输入码流在进行交织对应的码 流的相邻列数据位于 BUF0至 BUF15中的地址相同的存储单元中; 其中, 该 输入码流包括信息流, 第一校验流以及在进行交织处理之前经过循环左移一 位处理的第二校验流;
从 BUF0至 BUF15中的地址相同的存储单元中读取上述相邻列数据并重 新排序, 获得该输入码流在进行交织处理之前对应的码流。 即, 从 BUF0至 BUF15中的地址相同的存储单元中逐列地读取相邻列的数据,每一列所有行 的数据全部读完后, 再读下一列的所有行的数据, 直至所有相邻列数据读取 完毕为止。
假设在进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31}, 则根据表 1所述的列置换规则可知, 进行交织处 理之后接收端(如基站)的输入码流为 {0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
27, 7, 23, 15, 31 },则将进行交织处理后的输入码流按列写入 BUF0至 BUF15 后,如表 5所示,其中, BUF0中的存储单元存储了 1/16的输入码流 {0, 16},
BUF1 中的存储单元存储了 1/16的输入码流 {8, 24}, BUF2中的存储单元 存储了 1/16的输入码流 {4, 20}, ...... , BUF13 中的存储单元存储了 1/16 的输入码流 {11, 27}, BUF14中的存储单元存储了 1/16的输入码流 {7, 23},
BUF15中的存储单元存储了 1/16的输入码流 {15, 31}, 即 BUF0至 BUF15 存储的数据量相等。
其中, 表 5 中的 post— c— idx表示进行交织处理后的输入码流的列序号, c— idx表示进行交织处理前的输入码流的列序号。如表 5所示,当 post— c— idx=0 时, 该输入码流在进行交织处理之前的相邻列 0, 8, 4, 12, 2, 10, 6, 14,
1, 9, 5, 13, 3, 11, 7和 15的数据位于 BUF0至 BUF15的地址相同的存 储单元中; 当 post— c— idx=l时, 该输入码流在进行交织处理前的相邻列 16,
24, 20, 28, 18, 26, 22, 30, 17, 25, 21, 29, 19, 27, 23和 31的数据 位于 BUF0至 BUF15的地址相同的存储单元中。 表 5
Figure imgf000017_0001
本实施例中, 每一列的数据可能存在若干行, 并且由于列置换前后每一 列的行数相同, 而且每一行的行序号不变, 所以上述的 BUFO至 BUF 15中的 地址相同的存储单元的地址可以釆用公式( 1 )来表示。其中, pos表示 BUFO 至 BUF15的地址相同的存储单元的地址, R表示进行交织处理后的输入码流 的行数, r— idx表示进行交织处理后的输入码流的行序号, r— idx从 0开始, 直至最后一行 r— idx=R-l。 当 r— idx每取一个值时, post— c— idx按顺序依次取 值 =0, 1。 在每一列的数据仅存在一行的情况下, 上述的 pos=post— c— idx。
当 r— idx每取一个值时, 依次将 post— c— idx=0, 1代入公式( 1 ) 即可计 算出 BUFO至 BUF15的地址相同的存储单元的地址 pos, 进而可以从 BUFO 至 BUF15的相同地址 pos中读取相邻列数据,并按照排列顺序 [BUF0,BUF8, BUF4, BUF12, BUF2, BUF10, BUF6, BUF14, BUF1, BUF9, BUF5, BUF13, BUF3, BUFll, BUF7, BUF15]将读取的相邻列数据重新排列, 即 可以获得进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}。
本实施例中, 可以设置 elk— cnt[0] 为时钟计数器, 记录读取操作的时钟 数, 取值范围为 [0 , 1 ] , 则 post_c_idx= {clk_cnt[0] }。
在获得该输入码流在进行交织处理之前对应的码流之后, 可以将获得的 在进行交织处理之前的第二校验流对应的码流循环右移一位, 从而完成信息 流、 第一校验流以及第二校验流的解交织处理。
举例五:
先将接收到的进行交织处理的输入码流按列写入 BUF0至 BUF31 ,其中, BUF0至 BUF31中存储的数据量相等, 而且该输入码流在进行交织之前对应 的码流的相邻列数据分布存储在 BUF0至 BUF31 中的地址相同的存储单元 中; 其中, 该输入码流包括信息流, 第一校验流以及在进行交织处理之前经 过循环左移一位处理的第二校验流;
从 BUF0至 BUF31中的地址相同的存储单元中读取上述相邻列数据并重 新排序,获得该输入码流在进行交织处理之前的码流。即,从 BUF0至 BUF31 中的地址相同的存储单元中逐列地读取相邻列的数据, 每一列所有行的数据 全部读完后, 再读下一列的所有行的数据, 直至所有相邻列数据读取完毕为 止。
假设在进行交织处理之前的输入码流为 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31}, 则根据表 1所述的列置换规则可知, 进行交织处 理之后接收端(如基站)的输入码流为 {0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11,
27, 7, 23, 15, 31 },则将进行交织处理后的输入码流按列写入 BUF0至 BUF31 后, 如表 6所示, BUFO中的存储单元存储了 1/32的输入码流 {0}, BUF1 中的存储单元存储了 1/32的输入码流 {16 }, BUF2中的存储单元存储了 1/32 的输入码流 { 8 }, ...... , BUF30中的存储单元存储了 1/32的输入码流 { 15 },
BUF31中的存储单元存储了 1/32的输入码流 {31 }, 即 BUF0至 BUF31存储 的数据量相等。
其中, 表 6 中的 post— c— idx表示进行交织处理后的输入码流的列序号, c— idx表示进行交织处理前的输入码流的列序号。如表 6所示,当 post— c— idx=0 时, 该输入码流在进行交织处理前的相邻列 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31的数据位于 BUF0至 BUF16的地址相同的存储单元 中。
表 6
Figure imgf000020_0001
本实施例中, 每一列的数据可能存在若干行, 并且由于列置换前后每一 列的行数相同, 而且每一行的行序号不变, 所以上述的 BUF0至 BUF31中的 地址相同的存储单元的地址可以釆用公式( 1 )来表示。其中, pos表示 BUF0 至 BUF31的地址相同的存储单元的地址, R表示进行交织处理后的输入码流 的行数, r—idx表示进行交织处理后的输入码流的行序号, r— idx从 0开始, 直至最后一行 r— idx=R-l。 当 r—idx每取一个值时, post— c— idx均取值 =0。 在 每一列的数据仅存在一行的情况下, 上述的 pos=post— c— idx。
当 r—idx每取一个值时, 依次将 post— c— idx=0代入公式( 1 ) 即可计算出 BUF0至 BUF31 的地址相同的存储单元的地址 pos, 进而可以从 BUF0至 BUF31的相同地址 pos中读取相邻列数据, 并按照排列顺序 [BUFO, BUF16, BUF8, BUF24, BUF4, BUF20, BUF12, BUF28, BUF2, BUF18, BUF10, BUF26, BUF6, BUF22, BUF14, BUF30, BUF1 , BUF17, BUF9, BUF25, BUF5, BUF21 , BUF13 , BUF29, BUF3 , BUF19, BUF11 , BUF27, BUF7, BUF23 , BUF15, BUF31]将读取的相邻列数据重新排列, 即可以获得进行交 织处理前的输入码流为 { 0, 1 , 2, 3 , 4, 5, 6, 7, 8, 9, 10, 11 , 12, 13 , 14, 15, 16, 17, 18, 19, 20, 21 , 22, 23 , 24, 25, 26, 27, 28, 29, 30, 31 }。
在获得该输入码流在进行交织处理之前对应的码流之后, 可以将获得的 在进行交织处理之前的第二校验流对应的码流循环右移一位, 从而完成信息 流、 第一校验流以及第二校验流的解交织处理。
上述对本发明实施例中提供的数据解交织方法进行了介绍, 本发明实施 例可以并行地进行解交织, 从而能够提高解交织时数据的吞吐率; 另外, 由 于在写入数据之前无需计算地址, 可以均衡解交织的复杂度。
本发明实施例中, 若输入码流仅仅包括信息流和第一校验流, 则本发明 实施例提供的另一种数据解交织方法包括上述的步骤 101和步骤 102即可, 其中, 举例说明与上述举例一至举例五相同, 本发明实施例不作赘述。 可以 并行地进行解交织, 从而能够提高解交织时数据的吞吐率; 另外, 由于在写 入数据之前无需计算地址, 可以均衡解交织的复杂度。
请参阅图 2,图 2为本发明实施例中提供的一种数据解交织装置的结构图 , 如图 2所示, 该装置可以包括:
写入模块 201 , 用于将接收到的经过交织处理的输入码流按列写入至少 二个不同緩存 202;
本实施例中, 经过交织处理的输入码流为信息流或第一校验流。
至少二个不同緩存 202, 用于存储写入模块 201写入的输入码流, 其中, 每个緩存中存储的数据量相等, 而且上述输入码流在进行交织处理之前对应 的码流的相邻列数据位于不同緩存相对应的存储单元中;
本实施例中, 不同緩存的个数为 2n个, 其中, K=n<=5。
读取模块 203 , 用于从从不同緩存相对应的存储单元中读取相邻列数据 并重新排序, 获得上述输入码流在进行交织处理之前对应的码流。
举例来说, 上述输入码流在进行交织处理之前对应的码流的相邻列数据 可以位于不同緩存的地址相同的存储单元中。 相应地, 读取模块 203可以从 从不同緩存的地址相同的存储单元中读取相邻列数据并重新排序, 获得上述 输入码流在进行交织处理之前对应的码流。
可选地, 若上述输入码流为在进行交织处理之前经过循环左移一位处理 的第二校验流, 则装置还可以包括:
调整模块 204, 用于将读取模块 203获得的第二校验流在进行交织处理 之前对应的码流的循环右移一位。
举例来说, 写入模块 201具体可以用于将接收到的经过交织处理的输入 码流按列写入如表 2所示的 BUF0和 BUF1;
相应地, 读取模块 203 具体可以用于从 BUF0 和 BUF1 的地址为 post— c— idx*R+ r_idx的存储单元中读取相邻列数据, 其中, post— c— idx表示 经过交织处理的输入码流的列序号, *表示作乘积, R表示经过交织处理的输 入码流的行数, r_idx表示经过交织处理的输入码流的行序号, 并且 r— idx依 次取值 =0, 1 , 2, ……, R-1 ; 每当 r— idx取一个值时, post— c— idx按顺序依 次取值 =0, 8, 4, 12, 2, 10, 6, 14, 1 , 9, 5 , 13 , 3 , 11 , 7, 15 , 16; 并按照排列顺序 [BUFO, BUF1]将读取的相邻列数据重新排列。
举例来说, 写入模块 201具体可以用于将接收到的经过交织处理的输入 码流按列写入如表 3所示 BUF0至 BUF3 ;
相应地, 读取模块 203 具体可以用于从 BUF0 至 BUF3 的地址为 post_c_idx*R+ r_idx的存储单元中读取相邻列数据, 其中, post— c— idx表示经 过交织处理的输入码流的列序号, *表示作乘积, R表示经过交织处理的输入 码流的行数, r— idx表示经过交织处理的输入码流的行序号, 并且 r— idx依次 取值 =0, 1 , 2, ……, R-1 ; 每当 r— idx取一个值时, post— c— idx按顺序依次 取值 = 0, 4, 2, 6, 1 , 5 , 3 , 7; 并按照排列顺序 [BUFO, BUF2, BUF1 , BUF3]将读取的相邻列数据重新排列。
举例来说, 写入模块 201具体可以用于将接收到的经过交织处理的输入 码流按列写入如表 4所示的 BUF0至 BUF7;
相应地, 上述读取模块 203 具体可以用于从 BUF0至 BUF7 的地址为 post_c_idx*R+ r_idx的存储单元中读取相邻列数据, 其中, post— c— idx表示经 过交织处理的输入码流的列序号, *表示作乘积, R表示经过交织处理的输入 码流的行数, r— idx表示经过交织处理的输入码流的行序号, 并且 r— idx依次 取值 =0, 1 , 2, ……, R-1 ; 每当 r— idx取一个值时, post— c— idx按顺序依次 取值 = 0, 2, 1 , 3; 并按照排列顺序 [BUFO, BUF4, BUF2, BUF6, BUF1 , BUF5 , BUF3 , BUF7]将读取的相邻列数据重新排列。
举例来说, 写入模块 201具体可以用于将接收到的经过交织处理的输入 码流按列写入如表 5所示的 BUF0至 BUF15;
相应地, 上述读取模块 203具体可以用于从 BUF0至 BUF15的地址为 post_c_idx*R+ r_idx的存储单元中读取相邻列数据, 其中, post— c— idx表示经 过交织处理的输入码流的列序号, *表示作乘积, R表示经过交织处理的输入 码流的行数, r— idx表示经过交织处理的交织后的输入码流的行序号, 并且 r— idx依次取值 =0, 1 , 2, …… , R-1 ; 每当 r— idx取一个值时, post— c— idx按 顺序依次取值 = 0, 1 ;并按照排列顺序 [BUFO, BUF8, BUF4, BUF12, BUF2, BUF10, BUF6, BUF14, BUF1 , BUF9, BUF5 , BUF13 , BUF3 , BUF11 , BUF7, BUF 15]将读取的相邻列数据重新排列。
举例来说, 写入模块 201具体可以用于将接收到的经过交织处理的输入 码流按列写入如表 6所示的 BUF0至 BUF31;
相应地, 上述读取模块 203 具体用于从 BUF0 至 BUF31 的地址为 post— c— idx*R+ r— idx中读取相邻列的数据, 其中, post— c— idx表示经过交织处 理的输入码流的列序号, *表示作乘积, R表示经过交织处理的输入码流的行 数, r— idx表示经过交织处理的输入码流的行序号, 并且 r— idx依次取值 =0, 1 , 2, ... ... , R-1 ; 每当 r— idx取一个值时, post— c— idx= 0; 并按照排列顺序
[BUFO, BUF16, BUF8, BUF24, BUF4, BUF20, BUF12, BUF28, BUF2, BUF18, BUF10, BUF26, BUF6, BUF22, BUF14, BUF30, BUF1 , BUF17, BUF9, BUF25 , BUF5, BUF21 , BUF13 , BUF29, BUF3 , BUF19, BUF11 , BUF27, BUF7, BUF23 , BUF15, BUF31]将读取的相邻列数据重新排列。
上述对本发明实施例中提供的数据解交织装置进行了介绍, 本发明实施 例可以并行地进行解交织, 从而能够提高解交织的吞吐率; 另外, 由于在写 入数据之前无需计算地址, 可以均衡解交织的复杂度。
本领域普通技术人员可以理解: 实现上述方法实施例的全部或部分步骤 可以通过纯硬件来完成, 或者通过程序指令相关硬件来完成。 前述的程序可 以存储于一计算机可读取存储介质中, 该程序在执行时, 执行包括上述方法 实施例的步骤; 而前述的存储介质包括: 只读存储器(R0M )、 随机存取器 ( RAM ), 磁碟或者光盘等各种可以存储程序代码的介质。
以上对本发明实施例中提供的一种数据解交织方法及装置进行了详细 实施例的说明只是用于帮助理解本发明的方法及其核心思想; 同时, 对于本 领域的一般技术人员, 依据本发明的思想, 在具体实施方式及应用范围上均 会有改变之处, 综上, 本说明书内容不应理解为对本发明的限制。

Claims

权利 要 求
1、 一种数据解交织方法, 其特征在于, 包括:
接收端将接收到的经过交织处理的输入码流按列写入至少二个不同緩 存, 以使得每个緩存中存储的数据量相等, 而且所述输入码流在进行交织处 理之前对应的码流的相邻列数据位于不同緩存相对应的存储单元中; 所述输 入码流包括信息流, 第一校验流以及第二校验流;
从不同緩存相对应的存储单元中读取所述相邻列数据并重新排序, 获得 所述输入码流在进行交织处理之前对应的码流; 所述输入码流在进行交织处 理之前对应的码流包括信息流、 第一校验流在进行交织处理之前各自对应的 码流, 以及所述第二校验流在进行交织处理之前经过循环左移一位处理的码 流;
将第二校验流在进行交织处理之前对应的码流循环右移一位。
2、根据权利要求 1所述的方法, 其特征在于, 所述接收端将接收到的经 过交织处理的输入码流按列写入至少二个不同緩存包括:
接收端将接收到的经过交织处理的输入码流按列写入 2n个緩存, 其中, K=n<=5„
3、根据权利要求 2所述的方法, 其特征在于, 所述从不同緩存相对应的 存储单元中读取所述相邻列数据并重新排序, 获得所述输入码流在进行交织 处理之前对应的码流包括:
从不同緩存的地址相同的存储单元中读取所述相邻列数据并重新排序, 获得所述输入码流在进行交织处理之前对应的码流。
4、根据权利要求 3所述的方法, 其特征在于, 若所述至少二个緩存为緩 存 0和緩存 1 , 则从不同緩存的地址相同的存储单元中读取所述相邻列数据 并重新排序, 获得所述输入码流在进行交织处理之前对应的码流包括:
从所述緩存 0和緩存 1的地址为 post— c—idx*R+ r— idx的存储单元中读取 所述相邻列数据, 其中, 所述 post— c— idx表示所述输入码流的列序号, *表示 作乘积, R表示所述输入码流的行数, r idx表示所述输入码流的行序号, 并 且 r— idx依次取值 =0, 1,2,……, R-l;每当 r— idx取一个值时,所述 post— c— idx 按顺序依次取值 =0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15, 16;
按照排列顺序 [緩存 0, 緩存 1]将读取的所述相邻列数据重新排列。
5、根据权利要求 3所述的方法, 其特征在于, 若所述至少二个緩存为緩 存 0至緩存 3, 则从不同緩存的地址相同的存储单元中读取所述相邻列数据 并重新排序, 获得所述输入码流在进行交织处理之前对应的码流包括:
从緩存 0至緩存 3的地址为 post— c— idx*R+ r— idx的存储单元中读取所述 相邻列数据, 其中, 所述 post— c— idx表示所述输入码流的列序号, *表示作乘 积, R表示所述输入码流的行数, r— idx表示所述输入码流的行序号,并且 r— idx 依次取值 =0, 1, 2, ……, R-1; 每当 r— idx取一个值时, 所述 post— c— idx按 顺序依次取值 =0, 4, 2, 6, 1, 5, 3, 7;
按照排列顺序 [緩存 0, 緩存 2, 緩存 1, 緩存 3]将读取的所述相邻列数 据重新排列。
6、根据权利要求 3所述的方法, 其特征在于, 若接收端将经过交织处理 的输入码流按列写入緩存 0至緩存 7, 则从不同緩存的地址相同的存储单元 中读取所述相邻列数据并重新排序, 获得所述输入码流在进行交织处理之前 对应的码流包括:
从緩存 0至緩存 7的地址为 post— c— idx*R+ r— idx的存储单元中读取所述 相邻列数据, 其中, 所述 post— c— idx表示所述输入码流的列序号, *表示作乘 积, R表示所述输入码流的行数, r— idx表示所述输入码流的行序号,并且 r— idx 依次取值 =0, 1, 2, ……, R-1; 每当 r— idx取一个值时, 所述 post— c— idx按 顺序依次取值 =0, 2, 1, 3;
按照排列顺序 [緩存 0, 緩存 4, 緩存 2, 緩存 6, 緩存 1, 緩存 5, 緩存 3, 緩存 7]将读取的所述相邻列数据重新排列。
7、根据权利要求 3所述的方法, 其特征在于, 若接收端将经过交织处理 的输入码流按列写入緩存 0至緩存 15,则从不同緩存的地址相同的存储单元 中读取所述相邻列数据并重新排序, 获得所述输入码流在进行交织处理之前 对应的码流包括:
从緩存 0至緩存 15的地址为 post— c— idx*R+ r— idx的存储单元中读取所述 相邻列数据, 其中, 所述 post— c— idx表示所述输入码流的列序号, *表示作乘 积, R表示所述输入码流的行数, r— idx表示所述交织后的输入码流的行序号, 并且 r— idx依次取值 =0 , 1 , 2,……, R- 1;每当 r— idx取一个值时,所述 post— c— idx 按顺序依次取值 = 0, 1 ;
按照排列顺序 [緩存 0, 緩存 8, 緩存 4, 緩存 12, 緩存 2, 緩存 10, 緩 存 6, 緩存 14, 緩存 1 , 緩存 9, 緩存 5 , 緩存 13 , 緩存 3 , 緩存 11 , 緩存 7, 緩存 15]将读取的所述相邻列数据重新排列。
8、根据权利要求 3所述的方法, 其特征在于, 若接收端将经过交织处理 的输入码流按列写入緩存 0至緩存 31 ,则从不同緩存的地址相同的存储单元 中读取所述相邻列数据并重新排序, 获得所述输入码流在进行交织处理之前 对应的码流包括:
从緩存 0至緩存 31的地址为 post— c— idx*R+ r_idx中读取所述相邻列数 据, 其中, 所述 post— c— idx表示所述交织后的输入码流的列序号, *表示作乘 积, R表示所述输入码流的行数, r— idx表示所述输入码流的行序号,并且 r— idx 依次取值 =0, 1 , 2, ……, R-1 ; 每当 r— idx取一个值时, 所述 post— c— idx= 0; 按照排列顺序 [緩存 0, 緩存 16, 緩存 8, 緩存 24, 緩存 4, 緩存 20, 緩 存 12, 緩存 28, 緩存 2, 緩存 18, 緩存 10, 緩存 26, 緩存 6, 緩存 22, 緩 存 14, 緩存 30, 緩存 1 , 緩存 17, 緩存 9, 緩存 25 , 緩存 5 , 緩存 21 , 緩存 13 , 緩存 29, 緩存 3 , 緩存 19, 緩存 11 , 緩存 27 , 緩存 7, 緩存 23 , 緩存 15 , 緩存 31 ]将读取的所述相邻列数据重新排列。
9、 一种数据解交织方法, 其特征在于, 包括:
接收端将接收到的经过交织处理的输入码流按列写入至少二个不同緩 存, 以使得每个緩存中存储的数据量相等, 而且所述输入码流在进行交织处 理之前对应的码流的相邻列数据位于不同緩存相对应的存储单元中;
从不同緩存相对应的存储单元中读取所述相邻列数据并重新排序, 获得 所述输入码流在进行交织处理之前对应的码流。
10、 根据权利要求 9所述的方法, 其特征在于, 所述输入码流为信息流 或者第一校验流。
11、 根据权利要求 9所述的方法, 其特征在于, 所述输入码流为在进行 交织处理之前经过循环左移一位处理的第二校验流, 则在获得所述第二校验 流在进行交织处理之前对应的码流之后, 所述方法还包括:
将第二校验流在进行交织处理之前对应的码流循环右移一位。
12、 根据权利要求 9〜11 任一项所述的方法, 其特征在于, 所述接收端 将接收到的经过交织处理的输入码流按列写入至少二个不同緩存包括:
接收端将接收到的经过交织处理的输入码流按列写入 2n个緩存, 其中, K=n<=5„
13、 一种数据解交织装置, 其特征在于, 包括:
写入模块, 用于将接收到的经过交织处理的输入码流按列写入至少二个 不同緩存;
所述至少二个不同緩存, 用于存储所述输入码流, 其中, 每个緩存中存 储的数据量相等, 而且所述输入码流在进行交织处理之前对应的码流的相邻 列数据位于不同緩存相对应的存储单元中;
读取模块, 用于从所述从不同緩存相对应的存储单元中读取所述相邻列 数据并重新排序, 获得所述输入码流在进行交织处理之前对应的码流。
14、根据权利要求 13所述的装置, 其特征在于, 所述输入码流为信息流 或者第一校验流。
15、根据权利要求 13所述的装置, 其特征在于, 若所述输入码流为在进 行交织处理之前经过循环左移一位处理的第二校验流, 则所述装置还包括: 调整模块, 用于将所述读取模块获得的所述第二校验流在进行交织处理 之前对应的码流的循环右移一位。
16、 根据权利要求 13〜15任一项所述的装置, 其特征在于, 所述緩存的 个数为 2η个, 其中, 1 <=η<=5。
17、 根据权利要求 16所述的装置, 其特征在于,
所述写入模块, 具体用于将接收到的经过交织处理的输入码流按列写入 緩存。和緩存 1;
所述读取模块,具体用于从所述緩存 0和緩存 1的地址为 post— c— idx*R+ r— idx的存储单元中读取所述相邻列数据, 其中, 所述 post— c— idx表示所述输 入码流的列序号, *表示作乘积, R表示所述输入码流的行数, r— idx表示所 述输入码流的行序号, 并且 r— idx依次取值 =0, 1, 2, ...... , R-1; 每当 r— idx 取一个值时, 所述 post— c— idx按顺序依次取值 =0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15, 16; 并按照排列顺序 [緩存 0, 緩存 1]将读取 的所述相邻列数据重新排列。
18、 根据权利要求 16所述的装置, 其特征在于,
所述写入模块, 具体用于将接收到的经过交织处理的输入码流按列写入 緩存。至緩存 3;
所述读取模块,具体用于从所述緩存 0至緩存 3的地址为 post— c— idx*R+ r— idx的存储单元中读取所述相邻列数据, 其中, 所述 post— c— idx表示所述输 入码流的列序号, *表示作乘积, R表示所述输入码流的行数, r— idx表示所 述输入码流的行序号, 并且 r— idx依次取值 =0, 1, 2, ...... , R-1; 每当 r— idx 取一个值时, 所述 post— c— idx按顺序依次取值= 0, 4, 2, 6, 1, 5, 3, 7; 并按照排列顺序 [緩存 0, 緩存 2, 緩存 1, 緩存 3]将读取的所述相邻列数据 重新排列。
19、 根据权利要求 16所述的装置, 其特征在于,
所述写入模块, 具体用于将接收到的经过交织处理的输入码流按列写入 緩存 0至緩存 7;
所述读取模块,具体用于从所述緩存 0至緩存 7的地址为 post— c— idx*R+ r— idx的存储单元中读取所述相邻列数据, 其中, 所述 post— c— idx表示所述输 入码流的列序号, *表示作乘积, R表示所述输入码流的行数, r— idx表示所 述输入码流的行序号, 并且 r— idx依次取值 =0, 1, 2, ...... , R-1; 每当 r— idx 取一个值时, 所述 post— c— idx按顺序依次取值= 0, 2, 1, 3; 并按照排列顺 序 [緩存 0, 緩存 4, 緩存 2, 緩存 6, 緩存 1, 緩存 5, 緩存 3, 緩存 7]将读 取的所述相邻列数据重新排列。
20、 根据权利要求 16所述的装置, 其特征在于,
所述写入模块, 具体用于将接收到的经过交织处理的输入码流按列写入 緩存。至緩存 15;
所述读取模块,具体用于从所述緩存 0至緩存 15的地址为 post— c— idx*R+ r— idx的存储单元中读取所述相邻列数据, 其中, 所述 post— c— idx表示所述输 入码流的列序号, *表示作乘积, R表示所述输入码流的行数, r— idx表示所 述交织后的输入码流的行序号, 并且 r— idx依次取值 =0, 1, 2, ...... , R-1; 每当 r— idx取一个值时, 所述 post— c— idx按顺序依次取值= 0, 1; 并按照排列 顺序 [緩存 0, 緩存 8, 緩存 4, 緩存 12, 緩存 2, 緩存 10, 緩存 6, 緩存 14, 緩存 1, 緩存 9, 緩存 5, 緩存 13, 緩存 3, 緩存 11, 緩存 7, 緩存 15]将读 取的所述相邻列数据重新排列。
21、 根据权利要求 16所述的装置, 其特征在于,
所述写入模块, 具体用于将接收到的经过交织处理的输入码流按列写入 緩存。至緩存 31;
所述读取模块,具体用于从所述緩存 0至緩存 31的地址为 post— c— idx*R+ r— idx中读取所述相邻列数据, 其中, 所述 post— c— idx表示所述交织后的输入 码流的列序号, *表示作乘积, R表示所述输入码流的行数, r— idx表示所述 输入码流的行序号, 并且 r— idx依次取值 =0, 1, 2, ...... , R-1; 每当 r— idx 取一个值时, 所述 post— c— idx=0; 并按照排列顺序 [緩存 0, 緩存 16, 緩存 8, 緩存 24, 緩存 4, 緩存 20, 緩存 12, 緩存 28, 緩存 2, 緩存 18, 緩存 10, 緩存 26, 緩存 6, 緩存 22, 緩存 14, 緩存 30, 緩存 1, 緩存 17, 緩存 9, 緩 存 25, 緩存 5, 緩存 21, 緩存 13, 緩存 29, 緩存 3, 緩存 19, 緩存 11, 緩 存 27, 緩存 7, 緩存 23, 緩存 15, 緩存 31]将读取的所述相邻列数据重新排 列。
PCT/CN2011/075167 2010-08-24 2011-06-02 一种数据解交织方法及装置 WO2011144144A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010264163.2 2010-08-24
CN 201010264163 CN102136879B (zh) 2010-08-24 2010-08-24 一种数据解交织方法及装置

Publications (1)

Publication Number Publication Date
WO2011144144A1 true WO2011144144A1 (zh) 2011-11-24

Family

ID=44296542

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/075167 WO2011144144A1 (zh) 2010-08-24 2011-06-02 一种数据解交织方法及装置

Country Status (2)

Country Link
CN (1) CN102136879B (zh)
WO (1) WO2011144144A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420674B (zh) * 2011-11-01 2014-03-26 上海华为技术有限公司 子块交织方法及并行子块交织器
WO2017193396A1 (zh) * 2016-05-13 2017-11-16 华为技术有限公司 信息处理方法、终端及基站

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101388745A (zh) * 2008-03-05 2009-03-18 中科院嘉兴中心微系统所分中心 一种应用于无线多媒体传感网的并行信道解码装置
CN101499875A (zh) * 2008-02-02 2009-08-05 三星电子株式会社 支持可变处理速率的lte解速率匹配与解交织的装置
CN101674161A (zh) * 2009-10-15 2010-03-17 华为技术有限公司 解速率匹配方法及装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499875A (zh) * 2008-02-02 2009-08-05 三星电子株式会社 支持可变处理速率的lte解速率匹配与解交织的装置
CN101388745A (zh) * 2008-03-05 2009-03-18 中科院嘉兴中心微系统所分中心 一种应用于无线多媒体传感网的并行信道解码装置
CN101674161A (zh) * 2009-10-15 2010-03-17 华为技术有限公司 解速率匹配方法及装置

Also Published As

Publication number Publication date
CN102136879A (zh) 2011-07-27
CN102136879B (zh) 2013-04-24

Similar Documents

Publication Publication Date Title
US8090896B2 (en) Address generation for multiple access of memory
US8132076B1 (en) Method and apparatus for interleaving portions of a data block in a communication system
US8638244B2 (en) Encoding module, apparatus and method for determining a position of a data bit within an interleaved data stream
KR19990033431A (ko) 병렬 길쌈 부호화기를 사용한 채널 부호기 설계방법
WO2018090629A1 (zh) 一种解交织解速率匹配的方法、装置及计算机存储介质
TW200947933A (en) Method and apparatus for contention-free interleaving using a single memory
WO2012034398A1 (zh) 维特比解码实现方法及装置
JP3891568B2 (ja) 誤り訂正符号を復号化する方法及び装置
US8201030B2 (en) Method and apparatus for parallel structured Latin square interleaving in communication system
WO2011144144A1 (zh) 一种数据解交织方法及装置
EP1022859A1 (en) Efficient memory addressing for convolutional interleaving
TWI313813B (en) Integrated circuit for data processing
US7272769B1 (en) System and method for interleaving data in a wireless transmitter
US8103944B2 (en) Memory architecture for high throughput RS decoding for MediaFLO receivers
TWI239728B (en) Third generation FDD modem interleaver and the method thereof
US20090313522A1 (en) Method and apparatus for low latency turbo code encoding
JP2001217815A (ja) 既知長のデータパケットに対するインターリーバブロックの最適サイズ計算方法およびデータパケットに対するインターリーバ
CN114629507B (zh) 一种Turbo和LDPC码速率匹配和交织器共享存储设计方法
WO2008028419A1 (fr) Procédé et système d&#39;entrelacement/désentrelacement dans un système de communication
Yang et al. Network-on-chip for turbo decoders
TW201332316A (zh) 增壓碼
WO2011140909A1 (zh) 速率匹配方法及装置
US6988234B2 (en) Apparatus and method for memory sharing between interleaver and deinterleaver in a turbo decoder
WO2012109851A1 (zh) 一种交织和解交织的方法、交织器和解交织器
WO2011091672A1 (zh) 一种速率匹配实现方法和系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11783061

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11783061

Country of ref document: EP

Kind code of ref document: A1