WO2011127728A1 - 一种子帧粗同步的方法及装置 - Google Patents

一种子帧粗同步的方法及装置 Download PDF

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Publication number
WO2011127728A1
WO2011127728A1 PCT/CN2010/078741 CN2010078741W WO2011127728A1 WO 2011127728 A1 WO2011127728 A1 WO 2011127728A1 CN 2010078741 W CN2010078741 W CN 2010078741W WO 2011127728 A1 WO2011127728 A1 WO 2011127728A1
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Prior art keywords
virtual sub
data
frame
signal
differential
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PCT/CN2010/078741
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English (en)
French (fr)
Inventor
邱宁
李强
曾文琪
于天昆
刘中伟
邢艳楠
梁立宏
李立文
林峰
褚金涛
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中兴通讯股份有限公司
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Publication of WO2011127728A1 publication Critical patent/WO2011127728A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2673—Details of algorithms characterised by synchronisation parameters
    • H04L27/2676—Blind, i.e. without using known symbols

Definitions

  • the present invention relates to a Time Division-Synchronized Code Division Multiple Access (TD-SCDMA) system, and more particularly to a method and apparatus for coarse synchronization of a subframe.
  • TD-SCDMA Time Division-Synchronized Code Division Multiple Access
  • TD-SCDMA is one of the three mainstream standards of 3G (third-generation mobile communication technology) and has broad application prospects.
  • the user equipment In the TD-SCDMA system, the user equipment (UE) needs to search for a possible cell after the initial power-on, and select a suitable cell to log in. Only after the UE logs in to the cell, can the UE obtain more detailed information of the cell. The information about the neighboring cell is obtained, and only after logging in to the cell, the paging or initiating call can be monitored. Generally, the process from the power-on search to the login to the appropriate cell is defined as the initial cell search process, referred to as ICS.
  • the initial search process of the TD-SCDMA cell includes a rough location of the Downlink Pilot Time Slot (DwPTS), that is, a step of subframe synchronization.
  • the base station signal of TD-SCDMA is transmitted in a period of 5ms (milliseconds), each 5ms signal is called 1 subframe, and the downlink synchronization code (Sync-DL) appears in the same position period on each subframe, and the subframe coarse synchronization is
  • the terminal finds the downlink synchronization code in the subframe, and roughly completes the process of synchronizing with the base station signal subframe, and the initial position of the subframe is substantially aligned.
  • the correlation method lacks practical value because of the huge amount of computation and the significant degradation of performance in the environment of multipath and co-frequency cell interference.
  • Sync-DL On the left side there is a 32-chip Guard Period (GP).
  • the base station does not transmit signals during this time.
  • the power of the GP is very high. Small, so from the time distribution of the received power, the power of the Sync-DL segment is larger than that of the GP, when the sum of the Sync-DL segment power is divided by the 64 chips on both sides (32 chips on each side). In this case, a larger estimation factor can be obtained, and the approximate position of the DwPTS is determined by this method. Therefore, the power position of the received signal can be used to establish the power "feature window" to search for the approximate position of the DwPTS.
  • GP Guard Period
  • the AGC Automatic Gain Control
  • the power between the uplink and downlink time slots may vary greatly, in order to To obtain a reasonably quantized downlink synchronization code signal and its nearby GP on a digital baseband, existing methods have to try a variety of possible AGC gains, and in each AGC gain scenario, feature window search is performed with all AGC gains.
  • the feature window optimal value obtained in the scene is used as the estimated position of the subframe synchronization code position.
  • the feature window synchronization method based on AGC attempts has the following problems:
  • the interval and range of AGC attempts depend on various factors such as the RF device, ADC bit width, and dynamic range of the downstream signal, increasing the cross-linking coupling between multiple module designs.
  • the invention provides a cell search rough synchronization method and device, which solves the problem of using AGC outliers, increasing the probability of false positives, increasing the correlation between modules, etc., and realizing a rough frame of the subframe avoiding the AGC attempt. Step method and device.
  • a method for coarse synchronization of a subframe includes: a terminal digital baseband signal, and a hard decision on the sample signal to obtain a symbol bit of the sample signal;
  • the terminal intercepts the virtual sub-frame from the sign bit of the sample signal, and performs differential operation on the adjacent samples in each of the intercepted virtual sub-frames to obtain differential hard-decision virtual sub-frame data;
  • the terminal accumulates the plurality of differential hard decision virtual sub-frame data, and removes the sign bit for each sample of the accumulated result;
  • the terminal looks up the location with the downlink synchronization code feature in the accumulated result.
  • the step of accumulating the plurality of differential hard-decision virtual sub-frame data by the terminal may include: the terminal taking the imaginary part of the plurality of differential hard-decision virtual sub-frame data as the estimated data; and performing, by using the estimated data of the plurality of differential hard-decision virtual sub-frame data Accumulate.
  • the method may further include: after accumulating the plurality of differential hard decision virtual sub-frame data, the terminal further extracts data of the m chips from the start position of the accumulated result at the end position of the accumulated result, where m > 0.
  • the method may further include: the terminal turning on the low noise amplifier in the RF device during the cell search process, and configuring the programmable gain amplifier in the RF device to a maximum gain; and, the low noise amplifier and the programmable gain amplifier outputting the antenna
  • the signal is amplified and the amplified signal is sent to an analog to digital converter that converts the amplified signal into a digital baseband signal.
  • the location with the downlink synchronization code feature can be: The amplitude of the accumulation result is higher than the position of the adjacent signal.
  • the feature window can be used.
  • the data of every 6400 chips can be used as a virtual sub-frame in units of 6400 chips.
  • the present invention further provides an apparatus for coarse synchronization of a subframe, comprising: a hard decision module, a difference module, an accumulation operation module, a de-sign bit module, and a downlink synchronization code position determining module, which are sequentially connected;
  • the hard decision module is set to a digital baseband signal, and the hard signal is subjected to a hard decision to obtain a sign bit of the sample signal, and the sign bit of the sample signal is sent to the difference module;
  • the difference module is configured to intercept the virtual sub-frame from the received sign bit of the sample signal, perform differential operation on the adjacent sample points in each of the intercepted virtual sub-frames, obtain differential hard-decision virtual sub-frame data, and send the data to the accumulation operation.
  • the accumulating operation module is configured to accumulate the received plurality of differential hard decision virtual sub-frame data, and send the accumulated result to the de-symbol bit module;
  • the de-sign bit module is arranged to remove the sign bit for each sample of the received accumulated result and send it to the line downlink synchronization code position determining module;
  • the downlink synchronization code position determining module is arranged to find a position having a downlink synchronization code feature among the received accumulation results.
  • the accumulating operation module may be configured to accumulate the plurality of differential hard decision virtual sub-frame data by: taking the imaginary part of the plurality of differential hard-decision virtual sub-frame data as the estimated data; and, the hard-decision virtual sub-frame data of the plurality of differential Estimate the data to be accumulated.
  • the de-sign bit module can also be arranged to extract data of m chips from the start position of the accumulated result at the end of the accumulated result, where m > 0.
  • the present invention is based on hard decision data accumulation to avoid the design of the AGC attempt, and introduces a differential operation to eliminate the influence of phase and channel, thereby eliminating the dynamic range of the cell search coarse synchronization to the RF device, the ADC bit width, and the downlink signal.
  • the dependence of many factors has significantly improved the stability of the cell search coarse synchronization process.
  • Figure 1 is a schematic diagram of a downlink synchronization code
  • FIG. 2 is a flowchart of a method for coarse synchronization of a subframe according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of coarse synchronization performance of a subframe under an AWGN channel
  • Figure 4 is a schematic diagram showing the effect of the positional deviation of the sample value on the coarse synchronization performance of the subframe
  • 5 is a schematic diagram of the effect of a 3 ppm crystal frequency offset on the coarse synchronization performance of a subframe
  • 6 is a schematic diagram of a coarse synchronization performance of a subframe under an easel channel
  • FIG. 7 is a schematic diagram of the coarse synchronization performance of a subframe under the case2 channel
  • FIG. 8 is a schematic diagram of a coarse synchronization performance of a subframe under a case 3 channel
  • FIG. 9 is a schematic diagram of the effect of co-frequency neighbor interference on the coarse synchronization performance of a subframe
  • FIG. 10 is a structural diagram of an apparatus for coarse synchronization of a subframe according to an embodiment of the present invention.
  • the existing feature window method is based on the principle that the power of the synchronization code is higher than the power of the surrounding Gp segment.
  • the input of the soft decision must be used.
  • the baseband signal of the RF output itself is an analog signal, which is converted by A/D (analog/digital) conversion.
  • the quantization here is a soft decision, meaning that in addition to the symbols, there is also data amplitude information, for example, 107.152 is quantized to become 107, -13.87 is quantized and becomes -14.
  • the design method of the AGC attempt has to be introduced, but the introduction of the AGC attempt leads to a series of abnormal values, increased false positive probability, and increased correlation between modules.
  • the new problem makes the system sensitive to the work scene and not robust enough.
  • the present embodiment is based on the principle that the downlink synchronization code appears every sub-frame period, because the downlink synchronization code appears in a subframe period, and other data is randomly transmitted in each subframe, and the signal amplitude at the downlink synchronization code position is increased after the multiple subframes are accumulated. Based on other data, the location of the downlink synchronization code is judged based on this principle, and the above problems caused by the soft decision are avoided.
  • FIG. 2 is a schematic diagram of a method for coarse synchronization of a subframe according to the embodiment, including:
  • the terminal always turns on the LNA (Low Noise Amplifier) in the RF device during the cell search process, and fixedly configures the VGA (Programmable Gain Amplifier) in the RF device to the maximum gain;
  • LNA and VGA are cascaded amplifiers, LNA has both on and off states, VGA gain is configurable, and VGA is configured for maximum gain, ensuring ADC (analog to digital conversion) conversion regardless of the actual power of the input signal.
  • a digital signal can be obtained for hard decision to generate the sign bit of the digital signal.
  • the sign bit refers to the sign of the signal, for example, the sign bit of 107.152 is +1, and the sign bit of -13.87 is -1.
  • the amplifier gain itself does not affect the change of the sign bit, but in order to ensure that the output signal has sufficient amplitude, the amplifier noise and the minimum quantization interval are reduced.
  • the influence of data, configured as the maximum gain is the most convenient and effective way, can also be configured to a specific gain of non-maximum gain, but at least the specific gain, the minimum sensitivity input signal, the amplitude of the amplifier output signal is higher than the ADC conversion The minimum quantization interval of the device.
  • the LNA and the VGA amplify the signal output by the antenna, send the amplified signal to the ADC (analog-to-digital converter), perform analog-to-digital conversion on the ADC, and convert the amplified signal into a digital baseband signal output;
  • ADC analog-to-digital converter
  • the terminal performs a digital baseband signal, and performs a hard decision on the digital baseband signal (sampling signal) to obtain a sign bit of the sample signal;
  • the hard decision strategy avoids the process of performing AGC attempts in the existing methods with different possible range of received power, ADC bit width and signal dynamic range, which is related to parameters; for example, existing The possible range of signal power received in the terminal is -110dBm ⁇ +10dBm. In the case of an ADC bit width of 6 bits, it is typical to try many gain values such as 90dB, 80dB, 70dB, ... OdB to obtain proper synchronization. Code, quantify the power difference.
  • the process of the present embodiment and the corresponding parameter values are not directly related to the parameters of the ADC bit width, the input signal sensitivity requirement, and the gain range of the AGC, and therefore, the coupling between the modules is reduced.
  • the sampling rate can use a single chip rate, or multiple times the chip rate, the single chip rate needs to store less data, and the calculation amount is the lowest. Therefore, the single chip rate can be used with priority.
  • Signal is a signal
  • real is the real part of the signal
  • imag is the imaginary part of the signal
  • the meaning of the whole formula is, the input complex number only retains the sign bit of the real part and the imaginary part as the output, and is reassigned to the signal, for example 107.152-13.87 j , after the formula is +lj.
  • the terminal intercepts data from the symbol bit of the sample signal as a virtual subframe
  • the terminal intercepts data in units of 6,400 chips, and each 6400 chips of data is used as an imaginary sub-frame.
  • the length of each sub-frame is 6400 chips. Since the start position of the sub-frame is not determined here, it is arbitrarily assumed here that a chip takes data for the start position of the sub-frame, and every 6400 chips are taken. Defined as a virtual sub-frame.
  • the terminal performs a difference operation on adjacent samples in each virtual sub-frame to obtain a length L.
  • the signal of one chip is defined as adjacent.
  • the channel can be approximated as no change in the time interval, and the frequency offset does not cause sufficient phase rotation.
  • the result of the difference is the phase influence caused by the channel and the frequency offset. Eliminate, so that the data of each sub-frame can be accumulated.
  • Signal conj(Signal).*[Signal(2:end);Signal(l)]; where Signal is a virtual sub-frame and conj is a conjugate operation. This equation completes the differential correlation operation of adjacent chips.
  • the signal of the difference between the synchronization codes of two adjacent chips should only have an imaginary part, and the real part can be saved to reduce the influence of noise and interference. Only half of the imaginary part is taken as the estimated data, because the amplitude of the result after the difference is 2 in the case of no noise, and the amplitude is 1 after dividing by 2, which is more convenient to describe, and whether or not half takes no influence on the implementation.
  • Signal imag(Signal)/2;
  • Signal is the differential hard-decision virtual sub-frame data, and imag is the imaginary part of the complex number.
  • the method of removing the sign bit includes: obtaining the amplitude (taking the absolute value), taking the power, and the like.
  • the loop complements the tail sequence to prevent the actual sync code position from appearing at the beginning or end of the virtual sub-frame, beyond the virtual sub-frame range.
  • SignalR abs(SignalR); abs is an absolute value operation.
  • SignalRC [SignalR; SignalR(l: 144-1)]; This formula is a loop complementing the tail sequence, taking the data of the m chips at the beginning of the accumulation result at the end of the accumulated result, m can be based on the feature window The parameter is determined, m > 0. If 144 is used, it can also be determined empirically to prevent the actual sync code position from appearing at the beginning or end of the virtual sub-frame beyond the virtual sub-frame range.
  • the terminal searches for the location with the downlink synchronization code feature in the accumulated result by using the feature window.
  • the feature window parameters can be selected as: P1 and P3 width 32, P2 width 64, and P2 on both sides of P2.
  • the signal amplitude of 64 chips at the sync code position is higher than that of the adjacent signal.
  • the following is a way to find 64 chip amplitudes higher than the 32 chips on the left and 32 chip amplitudes on the right, because the feature window method and the prior art are basically The same, the following description is more simplified.
  • the following is a process of finding a position having a downlink synchronization code feature in the magnitude of the accumulated result by using a feature window, including:
  • each chip may be the starting position of the actual downlink synchronization code, so there are 6400 possible sync code start positions, which are described as the virtual sync code start position.
  • DfPow P2Pow - 2*PlPow; P2Pow is the amplitude sum of P2 segment, and DfPow is the amplitude difference. This step is to calculate the amplitude of P2 segment and the amplitude of P1 segment which is 2 times larger.
  • [Deffisti, PosEsti] max(DfPow); where DfPow is the eigenvalue corresponding to the starting position of each virtual sync code, max is the maximum eigenvalue, Deffisti is the maximum eigenvalue, and PosEsti is the maximum eigenvalue. Location index.
  • PosEsti PosEsti+P2Pos-l;
  • the previous step finds the position where the length of the P1 is advanced in the downlink synchronization code in the subframe. This step deducts the length of the P1 advance.
  • PosEsti PosEsti - 6400; Since the data of the tail is rotated by the position data, the synchronization position beyond 6400 is actually obtained by the data before 6400 chips, so it should be before 6400chip In order to synchronize the position and because the sub-frame appears in the 6400 chip cycle, whether or not the 6400chip is deducted has no direct effect on the actual synchronization result, the deduction here is only more reasonable for the result range.
  • the performance of the cell search coarse synchronization method in various scenarios is simulated and compared in the case where the number of virtual sub-frames N of the typical parameter is 32, to verify that the present embodiment can be relatively robust in various adverse scenarios. jobs.
  • the performance of coarse synchronization based on hard-decision cell search in AWGN (additive white Gaussian noise) channel is analyzed.
  • the abscissa is the signal-to-noise ratio of the downlink synchronization code
  • the ordinate is the probability that the coarse synchronization position result is wrong (and The ideal position offset is more than 16 chips) and the number of simulations per sample is 32,000 sub-frames. It can be seen that the method can obtain better performance under the AWGN channel.
  • the error probability is about 10%.
  • the SNR is higher than -3dB, the error probability is reduced to less than 1%. .
  • a single chip sample is used in the method.
  • the downlink synchronization code position has not been obtained at this time, and AFC (Automatic Frequency Control) cannot be performed.
  • AFC Automatic Frequency Control
  • the local crystal frequency is not exactly the same as the expected frequency, it will cause two aspects of the baseband data. The influence of: (1) the frequency offset of the baseband signal caused by the local frequency offset; (2) The position of the sample value caused by the frequency deviation of the ADC moves with time.
  • Figure 5 simulates the effects of the above two factors on the performance of the method when the crystal frequency shift reaches 3 ppm. Since the differential operation is introduced, the baseband signal frequency offset itself has almost no visible influence on the coarse synchronization performance, but the 3 ppm crystal frequency offset will cause the movement of the sample position of 0.0192 chips in each subframe, in the interval of 32 subframes. Inside, the position of the sample value has been shifted by 0.6144 chips. The performance of the initial sub-frame sample value deviation is 1/2chip and the crystal frequency is 3ppm. The performance has been degraded to l/2chip ⁇ . The sample position deviation is close.
  • Figures 6 to 8 simulate the performance of the cell search coarse timing in the Casel ⁇ Case3 channel environment defined by the minimum performance standard.
  • the Casel and Case2 channels are a low-speed fading channel environment.
  • the 3km/h vehicle speed will result in a maximum Doppler frequency of only 5.6Hz at a carrier frequency of 2GHz, that is, the fading period will be as long as about 180ms or 36 subframes, based on
  • the hard-synchronized coarse synchronization method provides a sufficient span in time because it does not require an AGC attempt, which greatly guarantees the low-speed environment, especially in the case of Casel's single-path low-vehicle environment. Since the differential operation basically eliminates the influence of channel characteristics, the coarse synchronization performance is also ideal in the high-speed environment of Case3.
  • Figure 8 simulates the scenario where the same-frequency neighbor cell interference exists at the same time.
  • the power ratio of the neighboring cell seen by the mobile station relative to the cell is OdB, and the arrival time lags. 1 chip.
  • the same-frequency neighbor cell interference with little delay can not only lead to performance degradation, but also a certain degree of performance improvement.
  • the hard decision feature window method itself only utilizes the same downlink synchronization.
  • the code has this characteristic every sub-frame period, and the synchronization code of the area and the neighboring area are the same.
  • the step code satisfies this feature and can be reflected in the estimation factor.
  • a device for coarse synchronization of a subframe comprising: a hard decision module, a difference module, an accumulation operation module, a de-sign bit module, and a downlink synchronization code position determining module, which are sequentially connected, wherein: the hard decision module is set to The digital baseband signal is subjected to a hard decision on the digital baseband signal (sampling signal), and the sign bit of the sample signal is obtained and sent to the differential module;
  • the accumulating operation module is configured to take the imaginary part of the differential hard decision virtual sub-frame data as the estimated data, accumulate the estimated data of the consecutive N ( N > 2 ) differential hard decision virtual sub-frame data, and send the accumulated result to the de-sign bit module;
  • the de-sign bit module is set to remove the sign bit for each sample of the accumulated result, and cyclically complement the tail sequence, that is: the data of the m chips at the start position of the accumulation result is added to the end position of the accumulated result, m > 0 And sent to the downlink synchronization code position determining module;
  • the downlink synchronization code position determining module is arranged to find a position having the downlink synchronization code feature in the accumulation result by means of the feature window.
  • the invention introduces a differential operation to eliminate the influence of phase and channel, thereby eliminating the dependence of the cell search coarse synchronization on many factors such as the radio frequency device, the ADC bit width and the dynamic range of the downlink signal, and obviously improves the cell. Search for the stability of the coarse synchronization process.

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Description

一种子帧粗同步的方法及装置
技术领域
本发明涉及时分同步码分多址接入 ( Time Division-Synchronized Code Division Multiple Access, TD-SCDMA ) 系统， 尤其涉及一种子帧粗同步的方 法及装置。
背景技术
TD-SCDMA是 3G (第三代移动通讯技术） 的三大主流标准之一， 具有 广泛的应用前景。
在 TD-SCDMA系统中， 终端（User Equipment, UE )在初始上电后需要 搜寻可能存在的小区， 并选择合适的小区登录， 只有在 UE登录到小区后， 才能获取本小区更详细的信息并获取邻近小区的信息， 也只有在登录到小区 后， 才可以监听寻呼或发起呼叫， 通常将从开机搜索到登录到合适小区的过 程定义为小区初始搜索过程， 简称 ICS。
TD-SCDMA小区初始搜索过程中包括获知同步码（ Downlink Pilot Time Slot, DwPTS ) 的粗略位置， 也就是子帧同步的步骤。 TD-SCDMA的基站信 号以 5ms (毫秒）为周期发送， 每个 5ms的信号称为 1个子帧， 下行同步码 ( Sync-DL )在每个子帧上的同一位置周期出现，子帧粗同步是指终端找到子 帧中的下行同步码， 粗略地完成与基站信号子帧同步， 子帧起始位置大致对 齐的过程。
目前有两种子帧粗同步的方法， 一种是根据 TD-SCDMA子帧的功率分 布特性搜索的能量窗法；另一种是在整个子帧范围内与 32个 Sync-DL码作相 关的相关法。
相关法由于运算量巨大且在多径和同频小区干扰的环境中性能明显退 化， 因此， 缺乏实用价值。
对于能量窗法，考虑到在 TD-SCDMA的帧结构中，请参考图 1 , Sync-DL 的左边有 32码片 （chips ) 的保护间隔 （Guard Period, GP ) , 基站在这段时 间不发射信号， 右边有 96码片的 GP, Sync-DL本身为 64码片， 由于 GP的 功率很小， 故从接收功率的时间分布上看， 与 GP相比 Sync-DL段的功率较 大， 当用 Sync-DL段功率之和除以两边的 64码片（两边各 32码片）功率之和 时， 可以得到较大的估计因子， 用此方法判断出 DwPTS的大致位置， 因此可 以利用接收信号的功率形状建立功率 "特征窗"的方法来搜索 DwPTS的大致 位置。
由于在进行小区初始搜索的过程时， 子帧同步尚未建立， AGC (自动增 益控制）无法进入同步模式， 且受到邻近 UE的影响， 上下行时隙之间的功 率可能存在着巨大的差异， 为了在数字基带上获取合理量化的下行同步码信 号及其附近的 GP,现有方法不得不尝试多种可能的 AGC增益，并在每种 AGC 增益场景下，都进行特征窗搜索， 以所有 AGC增益场景下获取的特征窗最优 值作为子帧同步码位置的估计位置。
基于 AGC尝试的特征窗同步方法存在以下问题：
1 ) 当 AGC增益较低且实际信号功率较小时， 大部分数据都未获得有效 多的量化比特， 与过小数据相除导致异常特征值的频繁出现， 该无效结果影 响正常的特征值估计。
2 )过多的 AGC尝试种类增加了定时位置误判的概率， 降低了小区搜索 的整体性能。
3 ) AGC尝试的间隔和范围取决于射频器件、 ADC位宽以及下行信号的 动态范围等多种因素， 增加多个模块设计之间的交联耦合。
4 ) 为了保障粗定时的性能， 尤其是低车速环境下的可靠性， 往往单次 AGC增益就必须经历足够多的子帧， 多次 AGC尝试将大幅增加小区搜索的 处理时间。
发明内容
本发明提供一种小区搜索粗同步方法及装置， 以解决釆用 AGC异常值、 误判概率上升、模块间关联增加等问题， 实现一种规避 AGC尝试的子帧粗同 步的方法及装置。
为解决上述技术问题， 本发明的一种子帧粗同步的方法， 包括： 终端釆样数字基带信号， 对釆样信号进行硬判决， 得到釆样信号的符号 位；
终端从釆样信号的符号位中截取虚子帧， 对所截取的每个虚子帧中相邻 的样点进行差分运算， 得到差分硬判决虚子帧数据；
终端对多个差分硬判决虚子帧数据进行累加， 并对累加结果的每个样点 去除符号位； 以及
终端在累加结果中查找具有下行同步码特征的位置。
终端对多个差分硬判决虚子帧数据进行累加的步骤可包括： 该终端取多 个差分硬判决虚子帧数据的虚部作为估计数据； 以及， 该多个差分硬判决虚 子帧数据的估计数据进行累加。
该方法还可包括： 终端对多个差分硬判决虚子帧数据进行累加后， 还从 累加结果的起始位置起取 m个码片的数据补充在累加结果的末尾位置，其中， m > 0。
该方法还可包括： 终端在小区搜索过程中打开射频器件中的低噪声放大 器， 并将射频器件中的可编程增益放大器配置为最大增益； 以及， 低噪声放 大器和可编程增益放大器对天线输出的信号进行放大， 并将放大后的信号发 送给模拟数字转换器， 该模拟数字转换器将放大后的信号转换为数字基带信 号。 具有下行同步码特征的位置可以为： 累加结果中幅度高于邻近信号的位 置。
终端在累加结果中查找具有下行同步码特征的位置时， 可以釆用特征窗 的方式。
终端从釆样信号的符号位中截取虚子帧时， 可以以 6400个码片为单位， 将每 6400个码片的数据作为一个虚子帧。
本发明还提供一种子帧粗同步的装置， 包括： 依次相连的硬判决模块、 差分模块、 累加运算模块、 去符号位模块和下行同步码位置确定模块； 其中， 硬判决模块设置成釆样数字基带信号， 对釆样信号进行硬判决， 得到釆 样信号的符号位， 将该釆样信号的符号位发送给差分模块；
差分模块设置成从所接收到的釆样信号的符号位中截取虚子帧， 对所截 取的每个虚子帧中相邻的样点进行差分运算， 得到差分硬判决虚子帧数据， 发送给累加运算模块；
累加运算模块设置成对所接收到的多个差分硬判决虚子帧数据进行累 加， 将累加结果发送给去符号位模块；
去符号位模块设置成对所接收到的累加结果的每个样点去除符号位， 并 发送给行下行同步码位置确定模块；
下行同步码位置确定模块设置成在所接收到的累加结果中查找具有下行 同步码特征的位置。
累加运算模块可设置成通过如下方式对多个差分硬判决虚子帧数据进行 累加： 取多个差分硬判决虚子帧数据的虚部作为估计数据； 以及， 对该多个 差分硬判决虚子帧数据的估计数据进行累加。
去符号位模块还可设置成从累加结果的起始位置起取 m个码片的数据补 充在累加结果的末尾位置， 其中， m > 0。
综上所述，本发明基于硬判决数据累加以避免 AGC尝试的设计， 引入了 差分运算消除相位和信道的影响， 从而消除了小区搜索粗同步对射频器件、 ADC位宽以及下行信号的动态范围等诸多因素的依赖， 明显提高了小区搜索 粗同步过程的稳定性。
附图概述
图 1为下行同步码的示意图；
图 2为本发明实施方式子帧粗同步的方法的流程图；
图 3为 AWGN信道下子帧粗同步性能的示意图；
图 4为釆样值位置偏差对子帧粗同步性能影响的示意图；
图 5为 3ppm晶振频偏对子帧粗同步性能影响的示意图； 图 6为 easel信道下子帧粗同步性能的示意图；
图 7为 case2信道下子帧粗同步性能的示意图；
图 8为 case3信道下子帧粗同步性能的示意图；
图 9为同频邻区干扰对子帧粗同步性能影响的示意图；
图 10为本发明实施方式的子帧粗同步的装置的结构图。
本发明的较佳实施方式
现有的特征窗方法基于判断同步码功率高于周围 Gp段功率的原理， 必 须要使用软判决的输入， 射频输出的基带信号本身是模拟信号， A/D (模拟 / 数字）转换将其转化为多比特量化的数字信号， 这里的量化就是软判决， 意 思是除了符号外， 还有数据幅度的信息， 例如 107.152被量化后变为 107, -13.87被量化后变为 -14。
为了在数字基带上获取合理量化的下行同步码信号及其附近的 GP,不得 不引入 AGC尝试的设计方法， 但 AGC尝试的引入导致了异常值、 误判概率 上升、模块间关联增加等一系列新的问题， 致使系统对于工作场景颇为敏感， 不够稳健。
鉴于釆用 AGC存在上述诸多固有缺陷， 为此，有必要考虑一种更为稳健 的方法， 回避 AGC尝试， 以避免其引发的一系列问题， 减少与周边模块的交 联耦合， 在可接受的搜索时间内， 降低低车速场景下的漏检概率。
本实施方式基于下行同步码每子帧周期出现的原理， 由于下行同步码以 子帧为单位周期出现， 而其他数据每个子帧随机发送， 多个子帧累加后下行 同步码位置处的信号幅度高于其他数据， 基于此原理判断下行同步码所在位 置， 避免了软判决所带来的上述问题。
下面结合附图对本实施方式进行详细说明。
图 2为本实施方式的子帧粗同步的方法， 包括：
201 : 终端在小区搜索过程中始终打开射频器件中的 LNA (低噪声放大 器） ， 并将射频器件中的 VGA (可编程增益放大器） 固定配置为最大增益； LNA与 VGA为级联的放大器， LNA有打开和关闭两种状态， VGA的增 益可配置，将 VGA配置为最大增益，确保了无论输入信号的实际功率是多少， 经 ADC (模拟数字转换）转换均可以得到数字信号， 以进行硬判决， 产生数 字信号的符号位。 符号位是指信号的正负符号， 例如 107.152的符号位为 +1 , -13.87的符号位为 -1。
由于本实施方式釆用硬判决数据的方法， 也即只保留数据的符号位， 放 大器增益本身并不影响符号位的变化， 但为了确保输出信号有足够的幅度， 降低放大器噪声和最小量化间隔对数据的影响， 配置为最大增益是最便捷有 效的方式， 也可以配置成非最大增益的特定增益， 但至少需要在该特定增益 下， 最低灵敏度输入信号时，放大器输出信号的幅度高于 ADC转换器的最小 量化间隔。
202: LNA和 VGA对天线输出的信号进行放大， 将放大后的信号发送给 ADC (模拟数字转换器） , ADC进行模数转换， 将放大后的信号转换为数字 基带信号输出；
203: 终端釆样数字基带信号， 对所釆样的数字基带信号（釆样信号）进 行硬判决， 得到釆样信号的符号位；
硬判决是指仅仅取数据的符号位作为输出， 除了符号外， 没有其他信息， 例如 107.152被量化后变为 1 , -13.87被量化后变为 -1。 对信号只保留正负符 号位， 不保留幅度信息定义为硬判决过程。
釆用硬判决的策略 ,避免了现有方法中在不同接收功率可能的区间、 ADC 位宽和信号动态范围等存在差异的情况下进行 AGC尝试的过程，该过程与参 数相关； 例如， 现有方法在终端中接收到信号功率的可能范围为 -110dBm ~ +10dBm,在 ADC位宽为 6比特情况下，典型需要尝试 90dB、 80dB、 70dB、 ... OdB 等众多增益值以获得合适的同步码， 量化判断功率差异。 本实施方式的 过程和相应参数取值与 ADC位宽、 输入信号灵敏度需求和 AGC的增益范围 等其他模块的参数均没有直接关系， 因此， 减少了模块之间的耦合。 由于本实施方式只关注同步码周期出现的特征， 因此， 釆样率可以釆用 单倍 chip速率， 也可以釆用多倍 chip速率， 单倍 chip速率需要存储的数据较 少， 运算量也最低， 因此可优先釆用单倍 chip速率釆样。 Signal = (real(Signal)>=0)*2-l + ((imag(Signal)>=0)*2- 1 )* sqrt (- 1 )；该式为硬 判决过程， Signal是釆样信号， real是取信号的实部， imag是取信号的虚部， 整个公式的意义为， 将输入的复数只保留实部和虚部的符号位作为输出， 重 新赋值给该信号， 例如 107.152-13.87j , 经过该式计算后为 +l-j。
204: 终端从釆样信号的符号位中截取数据作为虚子帧；
终端以 6400个 chip为单位截取数据， 每 6400个 chip的数据作为一个虚 子帧。每个子帧的长度为 6400个 chip,由于此处还没有确定子帧的起始位置， 因此在该处任意假定某个 chip为子帧的起始位置取数据， 每取 6400个 chip, 将其定义为一个虚子帧。
205 : 终端对每个虚子帧中相邻的样点进行差分的运算， 得到长度为 L
( L=6400chip ) 的差分硬判决虚子帧数据；
以时间为单位， 时间关系相差 1个 chip的信号定义为相邻。
由于相邻 chip之间的时间间隔只有 0.78125us,在该时间区间上可以近似 认为信道没有变化， 频偏也未引起足够的相位旋转， 差分后的结果将信道和 频偏等引起的相位影响基本消除， 使各子帧的数据可以累加。
Signal = conj(Signal).*[Signal(2:end);Signal(l)]; 其中， Signal是虚子帧， conj是共轭运算， 本式完成了相邻 chip的差分相关运算。
206: 取差分硬判决虚子帧数据的虚部作为估计数据；
由于本地同步码的产生方式是一个实数序列乘以（) , 因此， 相邻两个 chip 的同步码差分后的信号应当只存在虚部， 不保留实部可以减少噪声和干 扰的影响， 还可以仅取虚部的一半作为估计数据， 因为无噪声情况下差分后 的结果幅度为 2, 除以 2后幅度为 1 , 更加便于描述， 是否取一半对实施并无 影响。
Signal = imag(Signal)/2; Signal是差分硬判决虚子帧数据， imag是取复数 的虚部运算。
207: 对连续 N ( N > 2 )个差分硬判决虚子帧数据的估计数据进行累加； 由于下行同步码以子帧为单位周期出现，而其他数据每个子帧随机发送， 多个子帧累加后下行同步码位置处都是一样的数据， 例如 N个子帧累加后同 步码处幅度为 N, 但是其他位置数据每个子帧各不相同相互抵消， 累加后幅 度小于 N, 因此累加后同步码位置处信号幅度高于其他数据， 基于此原理判 断下行同步码所在位置， 此步骤实现将同步码与其他数据区分开。
208: 在完成 N个差分硬判决虚子帧数据的估计数据的累加之后， 对累 加结果的每个样点去除符号位， 并循环补足尾部序列；
去除符号位方法包括： 求幅度（取绝对值）和取功率等。
循环补足尾部序列是为了防止实际同步码位置出现在虚子帧起始位置或 末尾位置， 超出虚子帧范围。
SignalR = abs(SignalR); abs为取绝对值运算。
SignalRC = [SignalR;SignalR(l : 144-1)]; 该式为循环补足尾部序列， 取累 加结果起始位置处的 m个 chip的数据补在累加结果的末尾位置， m可以根据 特征窗的参数确定， m > 0, 如取 144, 也可以根据经验确定， 以防止实际同 步码位置出现在虚子帧起始位置或末尾位置， 超出虚子帧范围。
209:终端釆用特征窗的方式在累加结果中查找具有下行同步码特征的位 置。
可以选择特征窗参数为： P1和 P3的宽度 32, P2宽度 64, P2两侧各保 留宽度 8的 chip。
同步码位置处有 64个 chip的信号幅度高于邻近信号的特征，下面是寻找 64个 chip幅度高于左边 32个 chip和右边 32个 chip幅度的方式， 由于该特 征窗方法和现有技术基本相同， 下面的描述较为简略。
下面是釆用特征窗的方式在累加结果的幅度中寻找具有下行同步码特征 的位置的过程， 包括：
2091 : 对累加结果的幅度求取特征值；
由于虚子帧中有 6400个 chip,每个 chip均可能是实际的下行同步码的起 始位置， 因此有 6400个可能的同步码起始位置， 这里描述为虚拟同步码起始 位置。
起始位置的特征值的计算方法为： PlPow = max(PlPow,P3Pow); PlPow是 PI段的幅度和， P3Pow是 P3段 的幅度和， max是求取最大值运算， 本步骤是求取 P1段幅度和与 P3段幅度 和的较大者作为 P1段的幅度和。
DfPow = P2Pow - 2*PlPow; P2Pow是 P2段的幅度和， DfPow是幅度差， 本步骤是计算 P2段幅度和比 2倍的 P1段幅度和要大多少。
考虑到硬判决数据的幅度均相同， 不存在定标问题， 因此， 釆用 P2Pow 与 2*PlPow的减法取代了传统的除法以降低实现复杂度。
2092:查找最大的 DfPow,保留虚子帧中最大的 DfPow的值和所在位置；
[Deffisti, PosEsti] = max(DfPow); 其中， DfPow为每个虚拟同步码起始位 置对应的特征值， max为寻找最大特征值， Deffisti 为最大特征值的大小， PosEsti为最大特征值对应的位置索引。
2093: 根据最大 DfPow所在位置推算出下行同步码所在位置；
PosEsti = PosEsti+P2Pos-l； 上一步骤找到的是子帧中下行同步码提前了 P1长度所在的位置， 此步骤扣除了 P1提前的长度。
if PosEsti > 6400, 则 PosEsti = PosEsti - 6400; 由于尾部的数据^^始位 置数据循环移位得到， 超出 6400的同步位置， 实际是由 6400个 chip之前的 数据获得的，因此，应当以 6400chip之前为同步位置，又由于子帧以 6400chip 周期出现， 是否扣除 6400chip对实际同步结果并无直接影响， 此处扣除仅是 为了结果范围表示更加合理。
本实施方式釆用典型参数虚子帧数量 N为 32的情况下对小区搜索粗同 步方法在各种场景下的性能进行了仿真比较， 以证实本实施方式在多种恶劣 场景下均可以较为稳健的工作。
首先， 分析 AWGN (加性白高斯噪声）信道下基于硬判决小区搜索粗同 步的性能， 图 3中横坐标为下行同步码的信噪比， 纵坐标是粗同步位置结果 发生错误的概率（与理想位置偏移超过 16chip ) ,每个样点的仿真数量为 32000 个子帧。 可见， 该方法在 AWGN信道下可以获得较好的性能， 信噪比为 -5dB 时， 错误概率大致为百分之十， 信噪比高于 -3dB时， 错误概率降低至百分之 一以下。 为了降低存储空间， 在方法中使用了单倍 chip釆样， 因此， 釆样值位置 偏差会对粗同步性能构成一定影响， 图 4中三条曲线分别对应理想定时， 1/4 釆样值位置偏差和 l/2chip釆样值位置偏差， 由图可见， l/4chip釆样值位置偏 差对性能影响并不明显， l/2chip釆样值位置偏差这种最恶劣的情况导致的性 能退化在 2dB左右， 在该情况下的实际性能也能满足系统要求。
由于本方法工作在小区搜索第一步，此时尚未获得下行同步码位置， AFC (自动频率控制）无法进行， 考虑到当本地晶振频率与期望频率不完全相同 时， 会对基带数据造成两方面的影响： ( 1 )本振频偏引起的基带信号频率偏 移； （2 ) ADC釆样频偏引起的釆样值位置随时间累计而移动。
图 5仿真了当晶振频偏达到 3ppm时， 上述两种因素对本方法性能的影 响。 由于引入了差分运算， 因此， 基带信号频偏本身对粗同步性能几乎无可 见影响， 但 3ppm的晶振频偏每个子帧会导致 0.0192个 chip的釆样值位置的 移动， 在 32个子帧的区间内， 釆样值位置累计移动了 0.6144个 chip, 图中仿 真了起始子帧釆样值位置偏差 l/2chip且晶振频偏 3ppm情况下的性能， 可见 其性能已退化到与 l/2chip釆样值位置偏差接近。
下面评估多径衰落信道对小区搜索粗定时性能的影响， 图 6〜图 8仿真了 最小性能标准定义的 Casel~Case3信道环境下小区搜索粗定时的性能。
Casel和 Case2信道是一种低速衰落信道环境， 3km/h的车速在 2GHz的 载波频率上将导致最大多普勒频率只有 5.6Hz, 也就是说衰落周期将长达约 180ms或 36个子帧， 基于硬判决的粗同步方法由于不需要进行 AGC尝试， 因此在时间上提供了充足的跨度， 较大程度上保障了低车速环境， 尤其是 Casel 的类单径低车速环境下的性能。 由于差分运算基本消除了信道特性的 影响， 在 Case3这种高速环境下， 粗同步性能也较为理想。
考虑到可能存在的同频邻小区干扰， 图 8仿真了同时存在同频邻小区干 扰的场景，其中在移动台看到的邻小区相对于本小区的功率配比分别为 OdB, 到达时间滞后了 1个 chip。
在图 9中可见，时延相差不大的同频邻小区干扰不仅不会导致性能退化， 还对性能有一定程度的提升作用， 这是因为硬判决特征窗方法本身只是利用 了同样的下行同步码每个子帧周期出现这一特性， 本区的同步码和邻区的同 步码都满足这一特征， 能够在估计因子中得以体现。
图 10为本实施方式的子帧粗同步的装置，包括：依次相连的硬判决模块、 差分模块、 累加运算模块、 去符号位模块和下行同步码位置确定模块， 其中： 硬判决模块设置成釆样数字基带信号， 对所釆样的数字基带信号 （釆样 信号）进行硬判决， 得到釆样信号的符号位， 发送给差分模块；
差分模块设置成从接收到的釆样信号的符号位中截取数据作为虚子帧， 对每个虚子帧中相邻的样点进行差分运算，得到长度为 L ( L=6400chip )的差 分硬判决虚子帧数据， 将差分硬判决虚子帧数据发送给累加运算模块；
累加运算模块设置成取差分硬判决虚子帧数据的虚部作为估计数据， 对 连续 N ( N > 2 )个差分硬判决虚子帧数据的估计数据进行累加， 将累加结果 发送给去符号位模块；
去符号位模块设置成对累加结果的每个样点去除符号位， 并循环补足尾 部序列， 即： 取累加结果起始位置处的 m个 chip的数据补在累加结果的末尾 位置， m > 0, 并发送给下行同步码位置确定模块；
下行同步码位置确定模块设置成釆用特征窗的方式在累加结果中查找具 有下行同步码特征的位置。
工业实用性
与现有技术相比， 本发明引入了差分运算消除相位和信道的影响， 从而 消除了小区搜索粗同步对射频器件、 ADC位宽以及下行信号的动态范围等诸 多因素的依赖， 明显提高了小区搜索粗同步过程的稳定性。

Claims

权 利 要 求 书
1、 一种子帧粗同步的方法， 包括：
终端釆样数字基带信号， 对釆样信号进行硬判决， 得到所述釆样信号的 符号位；
所述终端从所述釆样信号的符号位中截取虚子帧， 对所截取的每个虚子 帧中相邻的样点进行差分运算， 得到差分硬判决虚子帧数据；
所述终端对多个所述差分硬判决虚子帧数据进行累加， 并对累加结果的 每个样点去除符号位； 以及
所述终端在所述累加结果中查找具有下行同步码特征的位置。
2、 如权利要求 1所述的方法， 其中， 所述终端对多个所述差分硬判决虚 子帧数据进行累加的步骤包括：
所述终端取多个差分硬判决虚子帧数据的虚部作为估计数据； 以及， 对所述多个差分硬判决虚子帧数据的估计数据进行累加。
3、 如权利要求 1或 2所述的方法， 还包括： 所述终端对多个所述差分硬 判决虚子帧数据进行累加后， 从累加结果的起始位置起取 m个码片的数据补 充在累加结果的末尾位置， 其中， m > 0。
4、 如权利要求 1所述的方法， 还包括：
所述终端在小区搜索过程中打开射频器件中的低噪声放大器， 并将所述 射频器件中的可编程增益放大器配置为最大增益；
所述低噪声放大器和可编程增益放大器对天线输出的信号进行放大， 并 将放大后的信号发送给模拟数字转换器 , 所述模拟数字转换器将所述放大后 的信号转换为所述数字基带信号。
5、 如权利要求 1所述的方法， 其中，
所述具有下行同步码特征的位置为： 所述累加结果中幅度高于邻近信号 的位置。
6、 如权利要求 5所述的方法， 其中， 所述终端在所述累加结果中查找具 有下行同步码特征的位置时， 釆用特征窗的方式。
7、 如权利要求 1所述的方法， 其中， 所述终端从所述釆样信号的符号位 中截取虚子帧时， 以 6400个码片为单位， 将每 6400个码片的数据作为一个 虚子帧。
8、 一种子帧粗同步的装置， 包括： 依次相连的硬判决模块、 差分模块、 累加运算模块、 去符号位模块和下行同步码位置确定模块； 其中，
所述硬判决模块设置成釆样数字基带信号， 对釆样信号进行硬判决， 得 到所述釆样信号的符号位， 将该釆样信号的符号位发送给所述差分模块； 所述差分模块设置成从所接收到的所述釆样信号的符号位中截取虚子 帧， 对所截取的每个虚子帧中相邻的样点进行差分运算， 得到差分硬判决虚 子帧数据， 发送给所述累加运算模块；
所述累加运算模块设置成对所接收到的多个所述差分硬判决虚子帧数据 进行累加， 将累加结果发送给所述去符号位模块；
所述去符号位模块设置成对所接收到的累加结果的每个样点去除符号 位， 并发送给所述行下行同步码位置确定模块；
所述下行同步码位置确定模块设置成在所接收到的累加结果中查找具有 下行同步码特征的位置。
9、 如权利要求 8所述的装置， 其中，
所述累加运算模块是设置成通过如下方式对多个所述差分硬判决虚子帧 数据进行累加： 取多个差分硬判决虚子帧数据的虚部作为估计数据； 对所述 多个差分硬判决虚子帧数据的估计数据进行累加。
10、 如权利要求 8所述的装置， 其中，
所述去符号位模块还设置成从所述累加结果的起始位置起取 m个码片的 数据补充在该累加结果的末尾位置， 其中， m > 0。
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