WO2011127682A1 - Alimentation à découpage et son procédé de régulation de courant de sortie - Google Patents

Alimentation à découpage et son procédé de régulation de courant de sortie Download PDF

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Publication number
WO2011127682A1
WO2011127682A1 PCT/CN2010/073771 CN2010073771W WO2011127682A1 WO 2011127682 A1 WO2011127682 A1 WO 2011127682A1 CN 2010073771 W CN2010073771 W CN 2010073771W WO 2011127682 A1 WO2011127682 A1 WO 2011127682A1
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Prior art keywords
current
voltage
control signal
power supply
output
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PCT/CN2010/073771
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English (en)
Chinese (zh)
Inventor
陈忠
Original Assignee
上海明石光电科技有限公司
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Publication of WO2011127682A1 publication Critical patent/WO2011127682A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop

Definitions

  • the present invention relates to the field of power supplies, and in particular, to a switching power supply and a method for adjusting the output current thereof.
  • the switching power supply is mainly composed of a pulse frequency modulation (PFM) controller and a power transistor, and generates a stable output voltage by controlling the turn-on and turn-off of the power transistor.
  • PFM pulse frequency modulation
  • FIG. 1 a typical constant current output flyback switching power supply in the prior art is shown.
  • the switching power supply 100 mainly includes a PFM controller 101, a power transistor 102, a sampling resistor 103, secondary side ⁇ current zero-crossing detecting resistors 109 and 110, and a transformer 115.
  • the transformer 115 includes a primary side line ⁇ 104, a secondary side line ⁇ 105 and an auxiliary line ⁇ 106.
  • the AC input voltage Vac is rectified by the rectifier bridge 108 and input to the first filter capacitor 114.
  • the first DC voltage Vin on the first filter capacitor 114 supplies power to the entire circuit.
  • the first DC voltage Vin on the first filter capacitor 114 is input to the power supply terminal VCC of the PFM controller 101 via the startup resistor 112, and the capacitor 116 is a filter capacitor between the power supply terminal VCC and the ground terminal GND.
  • the PFM controller 101 starts operating. Additionally, the voltage on the auxiliary line ⁇ 106 charges the capacitor 116 via the rectifier diode 113 to maintain the voltage required for operation of the PFM controller 101.
  • the voltage on the secondary side line 105 is rectified by the diode 107 to charge the second filter capacitor 117, and the second DC voltage Vout on the second filter capacitor 117 is required to provide an external load.
  • the driving end OUT of the PFM controller 101 is connected to the control terminal of the power transistor 102 to cause the power transistor 102 to perform a high frequency switching operation.
  • the sampling resistor 103 is connected in series with the power transistor 102 and grounded for sampling the primary current flowing through the primary edge ⁇ 104, and transmits the sampled voltage obtained after the sampling conversion to the peak current detecting terminal Vcs of the PFM controller 101.
  • the voltage across the secondary side line ⁇ 105 is reflected on the auxiliary line ⁇ 106 by the turns ratio.
  • the voltage on the auxiliary line ⁇ 106 is divided by the zero-crossing detecting resistors 109 and 110 to obtain a feedback voltage, which is transmitted to the secondary-side current zero-cross detecting terminal Vfb of the PFM controller 101.
  • Vfb represents a feedback voltage received by the secondary current zero-crossing detecting terminal Vfb
  • Ip represents the primary edge
  • Is represents the secondary current passing through the secondary line ⁇ 105
  • Vcs represents the sampling voltage received by the peak current detecting terminal Vcs
  • OUT represents the driving voltage outputted by the driving terminal OUT.
  • the voltage waveform of the feedback voltage received by the current zero-crossing detecting terminal Vfb is similar to the voltage waveform across the secondary side line ,105, and the voltage amplitude is determined by the auxiliary line ⁇ 106 and the secondary line ⁇ The 105 turns ratio and the resistance ratio of the zero-crossing detecting resistors 109 and 110 are determined.
  • the secondary line ⁇ 105 is turned on, the secondary current Is flows through the secondary line ⁇ 105, and the feedback voltage is a positive voltage.
  • the PFM controller 101 records that the feedback voltage is positive for the duration of the on time Ton, representing the secondary line. ⁇ 105 The length of the conduction time.
  • the secondary current Is decreases with a certain slope.
  • the feedback voltage drops in a free-running manner and crosses the zero point, as shown by time point A in FIG.
  • the PFM controller 101 detects that the feedback voltage input to the current zero-cross detecting terminal Vfb is zero-crossing, the PFM controller 101 terminates the recording process of the on-time Ton, and simultaneously turns on the recording of the off-time Toff, and the off-time Toff represents the sub-deputy.
  • the duration of the edge ⁇ 105 is turned off.
  • the conduction of the secondary line ⁇ 105 means that there is a current passing therethrough (ie, the secondary current Is is not 0), and the turning off means that no current flows therethrough (ie, the secondary current Is is 0).
  • the driving voltage generated by the driving terminal OUT of the PFM controller 101 is at a high level, turning on the power transistor 102.
  • the primary current Ip flowing through the primary side turn 104 rises with a certain slope.
  • the primary current Ip flows through the sampling resistor 103, thereby generating a corresponding sampling voltage on the sampling resistor 103, which is transmitted to the peak current detecting terminal Vcs of the PFM controller 101.
  • the driving voltage generated by the driving terminal OUT of the PFM controller 101 is turned to a low level, the power transistor 102 is turned off, and the time Toff is turned off.
  • the recording process is terminated, and the recording process of the on-time Ton is turned back on. Thereby, the energy stored in the primary side line 104 during the off time Toff is released to the secondary line ⁇ 105 during the on time Ton of the next switching period, and the switching power supply is Enter the next switching cycle.
  • the switching period of the switching power supply 100 is the above-mentioned on-time
  • the sum of Ton and the off time Toff, the average current Iavg outputted by the switching power supply 100 to the load is the average value of the secondary current I105 conduction current Is in the switching cycle of the switching power supply 100; the average value and the conduction of the secondary current Is
  • the peak current Isk at the start time of the on-time Ton is related to, and the peak current Isk of the secondary line ⁇ 105 is determined by the peak current Ipk of the primary side line ⁇ 104 and the turns ratio of the primary side line ⁇ 104 and the secondary side line ⁇ 105 at the end time of the off time Toff.
  • the peak current Ipk of the primary side line 104 is determined by the threshold voltage Vth and the sampling resistor 103 inside the PFM controller 101.
  • the average current Iavg outputted by the switching power supply 100 can be expressed by the formula (1). For:
  • the internal control circuit of the PFM controller 101 makes the ratio of the on-time Ton to the off-time Toff a fixed value, so according to the formula (1), the value of the average current Iavg is also a fixed value, thereby making the switch
  • the current output by the power supply 100 remains constant.
  • the control of the constant current output of the switching power supply 100 in the above technical solution is realized by detecting the electrical signal of the primary side line ⁇ 104 without sampling the output current of the switching power supply 100, and is therefore called a primary side control technique.
  • the advantage of this technique is that there is no need to sample the output current of the switching power supply 100 (i.e., the current in the secondary line ⁇ 105), thereby eliminating the optocoupler-based isolated feedback circuit.
  • the disadvantage of this technique is that after the internal circuit of the PFM controller 101 is determined, the ratio of the fixed on-time Ton to the off-time Toff is such that the generated output current is constant and cannot be adjusted according to actual needs.
  • the prior art also includes another switching power supply, which inputs a current and outputs a feedback signal to the PFM controller via the optocoupler isolation feedback, and the PFM controller changes the duty ratio of the driving voltage signal according to the external control signal and the feedback signal.
  • the disadvantages of this technique are: The output current must be sampled and the feedback is isolated by the optocoupler, which results in a complicated circuit and increased cost; the sampling resistance of the output current causes the efficiency of the power supply system to decrease; the signal-to-noise ratio of the output current sampled signal is at a small current. Deterioration, resulting in poor control accuracy when the output current is small.
  • the problem to be solved by the present invention is to provide a switching power supply and a method for adjusting the output current thereof, which improves the adjustment flexibility of the output current of the switching power supply.
  • Embodiments of the present invention provide a power off, including a transformer, a pulse frequency modulation controller, and a switching transistor, where
  • the transformer includes a primary side turn ⁇ , a secondary side line ⁇ and an auxiliary line ⁇ , the secondary side line ⁇ is coupled to the original edge line , and the auxiliary line ⁇ is coupled to the secondary side line ;;
  • the switching transistor includes a control end, a first end and a second end, the control end inputs a driving voltage, and the first end is connected to the output end of the primary side line ;
  • the pulse frequency modulation controller inputs a feedback voltage and a sampling voltage, the feedback voltage being associated with a voltage output by the auxiliary winding, the sampling voltage being associated with a voltage of a second end of the switching transistor, the pulse frequency modulation
  • the controller further inputs a control signal, and the pulse frequency modulation controller generates the driving voltage according to the feedback voltage, the sampling voltage and the control signal, and is used for controlling the switching transistor to switch the turning on or off of the primary edge ,, Adjusting the on-time and off-time of the secondary side line ⁇ .
  • the embodiment of the invention further provides a switching power supply, further comprising a rectifier diode and a filter capacitor, wherein an input end of the rectifier diode is connected to one end of the secondary side line ,, an output end of the rectifier diode and another side of the secondary side line One end is respectively connected to both ends of the filter capacitor for rectifying the current in the sub-edge line ⁇ .
  • the embodiment of the invention further provides a switching power supply, the pulse frequency modulation controller comprising a timing capacitor and a control unit, configured to generate the driving voltage according to the feedback voltage, the sampling voltage and the control signal, wherein the timing a capacitor is used to time the on-time and the off-time of the sub-edge ⁇ , and a timing voltage at both ends thereof is used to generate the driving voltage; the control unit generates the control signal, the feedback voltage, and the sampling voltage according to the control signal a charging current for charging the timing capacitor and a discharging current for discharging, wherein a duration of the charging current is an off time of the secondary line ⁇ , and a duration of the discharging current is an on time of the secondary line ⁇ .
  • the pulse frequency modulation controller comprising a timing capacitor and a control unit, configured to generate the driving voltage according to the feedback voltage, the sampling voltage and the control signal, wherein the timing a capacitor is used to time the on-time and the off-time of the sub-edge ⁇ , and a timing voltage at
  • the embodiment of the invention further provides a switching power supply, and the control unit comprises:
  • a charge and discharge control unit that generates a charge and discharge control signal and the drive voltage according to the feedback voltage, the sampling voltage, and the timing voltage, the charge and discharge control signal including an alternating first voltage and a second voltage, the first voltage
  • the duration is the duration of the charging current
  • the second voltage is held
  • the continuation time is the duration of the discharge current
  • the current generating unit generates the charging current and the discharging current according to the control signal and the charge and discharge control signal.
  • An embodiment of the present invention further provides a switching power supply, where the current generating unit includes:
  • a charging current generating unit generating a first charging current according to the control signal, and outputting the first charging current as a charging current when the charging/discharging control signal is a first voltage
  • the discharge current generating unit generates a first discharge current based on the control signal, and outputs the first discharge current as a discharge current when the charge and discharge control signal is the second voltage.
  • the embodiment of the invention further provides a switching power supply, further comprising a first resistance setting end, the current generating unit further comprising:
  • a first current generator generating a first reference current according to a signal input to the first resistance setting end
  • a second current generator generating a second reference current according to the control signal
  • the charging current generating unit includes:
  • a first current mirror generating a first current after mirroring the first reference current
  • a second current mirror mirroring the second reference current to generate a second current
  • the first current and the second current are subtracted to generate the first charging current;
  • the discharging current generating unit includes:
  • a third current mirror generating a third current after mirroring the first reference current
  • a fourth current mirror mirroring the second reference current to generate a fourth current
  • the third current and the fourth current are added to generate the first discharge current.
  • the embodiment of the invention further provides a switching power supply, and the charging and discharging control unit comprises:
  • a first comparator comparing the feedback voltage with a second reference voltage to generate a feedback comparison signal
  • a second comparator comparing the sampled voltage with a third reference voltage to generate a sample comparison signal
  • the secondary current on/off timer receives the timing voltage, the feedback comparison signal, and the sampling comparison signal to generate the driving voltage and the charging and discharging control signal.
  • the embodiment of the invention further provides a switching power supply, further comprising a bias current source, according to the control signal The number generates a bias current, and the bias current is input to the bias resistor and the sampling resistor to adjust the sampling voltage.
  • An embodiment of the present invention further provides a method for adjusting an output current of a switching power supply, where the switching power supply includes a transformer having a primary side line ⁇ , a secondary side line ⁇ , and an auxiliary line ,, and the secondary side line ⁇ is coupled to the primary side line , The auxiliary line ⁇ is coupled to the secondary side line , and the output current of the secondary side line ⁇ is an output current of the switching power supply, including: switching the conduction of the primary side line ⁇ according to a feedback voltage, a sampling voltage, and a control signal Turning off to adjust an on-time and an off-time of the secondary side line , wherein the feedback voltage is associated with a voltage output by the auxiliary line ,, and the sampling voltage is associated with a current output by the primary side line ⁇ .
  • the embodiment of the invention further provides a method for adjusting the output current of the switching power supply, and switching the turning on or off of the primary side line according to the feedback voltage, the sampling voltage and the control signal comprises: using the charging and discharging process of the timing capacitor to the pair The on-time and the off-time of the edge line are timed; the charging time and the discharging time of the timing capacitor are controlled by adjusting a charging current and a discharging current of the timing capacitor, wherein the duration of the charging current is the secondary line ⁇ The turn-off time, the duration of the discharge current is the on-time of the secondary side line ⁇ .
  • the embodiment of the invention further provides a method for adjusting the output current of the switching power supply, and further comprising: adjusting a voltage value of the sampling voltage to adjust a peak value of the current output by the primary side line ⁇ .
  • the embodiment of the present invention further provides a method for adjusting a output current of a switching power supply, and adjusting a voltage value of the sampling voltage includes: generating a bias current according to the control signal; converting the bias current into a bias voltage; The bias voltage is superimposed with the sampling voltage.
  • the on-time and the off-time of the secondary side line ⁇ are adjusted by the control signal, thereby changing the ratio between the on-time and the off-time, thereby improving the adjustment of the output current of the switching power supply. flexibility.
  • the technical solution also adjusts the peak current of the primary side line ⁇ by adjusting the voltage value of the sampling voltage, thereby adjusting the peak current of the secondary side line ,, thereby improving the adjustment flexibility of the output current of the switching power supply.
  • FIG. 1 is a schematic structural view of a prior art switching power supply
  • FIG. 2 is a schematic diagram of signal waveforms of the switching power supply shown in FIG. 1; 3 is a schematic structural diagram of a switching power supply according to an embodiment of the present invention;
  • FIG. 4 is a schematic structural view of a PFM controller in the structure shown in FIG. 3;
  • FIG. 5 is a circuit configuration diagram of the module 301 in the structure shown in Figure 4;
  • FIG. 6 is a circuit configuration diagram of the module 302 in the structure shown in Figure 4;
  • FIG. 7 is a schematic diagram of signal waveforms of a switching power supply according to an embodiment of the present invention.
  • FIG. 8 is a control signal-output current characteristic diagram of a switching power supply according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural view of another embodiment of the PFM controller in the configuration shown in FIG.
  • the average value of the output current is also a fixed value according to the formula (1). Adjusted according to the needs of the actual application, the flexibility is low.
  • the optocoupler isolation feedback structure can regulate the output current, but its circuit is complicated and difficult to integrate, and the control accuracy is poor when the output current is small.
  • the switching power supply of the embodiment of the present invention includes: a transformer, a pulse frequency modulation controller, and a switching transistor, wherein
  • the transformer includes a primary side turn ⁇ , a secondary side line ⁇ and an auxiliary line ⁇ , the secondary side line ⁇ is coupled to the original edge line , and the auxiliary line ⁇ is coupled to the secondary side line ;;
  • the switching transistor includes a control end, a first end and a second end, the control end inputs a driving voltage, and the first end is connected to the output end of the primary side line ;
  • the pulse frequency modulation controller inputs a feedback voltage, a sampling voltage, and a control signal, the feedback voltage being associated with a voltage output by the auxiliary line, the sampling voltage being associated with a voltage of a second end of the switching transistor,
  • the pulse frequency modulation controller generates the driving voltage according to the feedback voltage, the sampling voltage and the control signal, and is used for controlling the switching transistor to switch the turning on or off of the primary side line , to adjust the conduction of the auxiliary side line ⁇ Time and turn-off time.
  • the conduction of the secondary side line ⁇ means that there is current output on the secondary side line ,
  • the turning off of the secondary side line ⁇ means that there is no current output on the secondary side line ,
  • the output current of the secondary side line ⁇ (which may be referred to as a secondary side current)
  • the average value is the output current of the switching power supply.
  • a driving voltage is generated by an external control signal in combination with a feedback voltage and a sampling voltage, and the driving voltage is used to control the turning on or off of the primary side line , to adjust the conduction time of the secondary side line ⁇ And the turn-off time, thereby changing the ratio of the on-time and the off-time of the sub-edge ⁇ , thereby improving the adjustment flexibility of the output current of the switching power supply (ie, the output current of the secondary line ⁇ ), and the structure of the package is easy integrated.
  • FIG. 3 the figure is a schematic structural diagram of a switching power supply according to an embodiment of the present invention.
  • the switching power supply 200 of the present embodiment mainly includes an input rectifying unit 200a, an output rectifying unit 200b, a transformer 215, a switching transistor 202, and a PFM controller 201.
  • the input rectifying unit 200a includes a rectifier bridge 208 composed of four diodes and an input filter capacitor 214 for rectifying the input AC voltage Vac to generate an input voltage Vin, which is a DC voltage.
  • the transformer 215 is a flyback transformer, and includes a primary side line 204, a secondary side line 205, and an auxiliary line 206.
  • the input end of the primary side line 204 receives the input voltage Vin, and the secondary side line 205
  • the primary edge ⁇ 204 is coupled, and the auxiliary winding 206 is coupled to the secondary winding 205.
  • the switching transistor 202 includes a control terminal, a first terminal and a second terminal, and the switching transistor may be a field effect transistor, and a first end thereof (in this embodiment, a drain of the field effect transistor) is connected to the primary edge ⁇ 204 At the output end, its control terminal (the gate of the field effect transistor in this embodiment) is input to the driving voltage generated by the PFM controller 201.
  • the switching transistor 202 may also be a bipolar transistor, the base of which is the control end, the collector is the first end, and the second end of the second end is emitted. .
  • the PFM controller 201 inputs a feedback voltage, a sampling voltage, and a control signal, the feedback voltage being associated with a voltage output by the auxiliary line 206, wherein the sampling voltage is associated with a voltage of the second end of the switching transistor 202,
  • the PFM controller 201 generates the driving voltage according to the feedback voltage, the sampling voltage, and the control signal, and is used to control the switching transistor 202 to switch the turning on or off of the primary side line 204 to adjust the secondary side line.
  • the on-time Ton of the 205 and the off-time Toff thereby adjusting the ratio of the on-time Ton to the off-time Toff.
  • the output rectifying unit 200b rectifies the secondary current flowing in the secondary side line 205, and specifically includes: a rectifier diode 207, a filter capacitor 217, and a resistor 211, and the rectifier diode 207
  • the input end is connected to one end of the sub-edge ⁇ 205, and the output end of the rectifying diode 207 and the other end of the sub-side ⁇ 205 are respectively connected to two ends of the filter capacitor 217 for arranging the sub-side line
  • the current in 205 is rectified.
  • the resistor 211 is connected in parallel across the filter capacitor 217 to serve as a bleeder resistor.
  • the secondary side line 205 is connected to one end of the rectifier diode 217 and the primary side line ⁇ 204 is connected to one end of the switching transistor 202, and the voltage output end of the auxiliary line ⁇ 206 is the same name end.
  • the sampling voltage is coupled to the voltage of the second terminal of the switching transistor 202 through a sampling resistor 203.
  • One end of the sampling resistor 203 is connected to the second end of the switching transistor 202 (in the present embodiment, the source of the field effect transistor is a source), and the other end is grounded, and the primary current Ip flowing through the primary side line 204 is performed. Sampling, generating the sampled voltage.
  • the input voltage Vin is input to the power terminal VCC and the ground terminal GND of the PFM controller 201 via the resistor 212 and the capacitor 216.
  • the electrical signal generated by the voltage output terminal of the auxiliary line ⁇ 206 is rectified by the rectifier diode 213 and also input to the power supply terminal VCC for providing a stable supply voltage.
  • the driving terminal OUT of the PFM controller 201 is connected to the control terminal of the switching transistor 202, and outputs the driving voltage to perform a high-frequency switching operation.
  • the sampling resistor 203 is connected in series with the switching transistor 202 for detecting the primary current Ip in the primary side line 204, and generates a sampling voltage and input it to the peak current detecting terminal Vcs of the PFM controller 201.
  • the sampling voltage in this embodiment is also associated with the voltage of the second terminal of the switching transistor 202 through the bias resistor 220. The specific correlation process will be described in detail below.
  • the feedback voltage is associated with a voltage of a voltage output terminal of the auxiliary line ⁇ 206 through a voltage dividing unit (including zero-crossing detecting voltage dividing resistors 209 and 210 in this embodiment), and a voltage on the auxiliary line ⁇ 206 passes the The zero-crossing detection voltage dividing resistors 209 and 210 are divided and fed back to the secondary current zero-crossing detecting terminal Vfb of the PFM controller 201.
  • the PFM controller 201 also includes a control signal input terminal DIM for receiving a control signal (as provided by the adjustable voltage source 221 in FIG. 3).
  • the PFM controller 201 in this embodiment further includes a first resistance setting terminal RS1 and a second resistance setting terminal RS2, wherein the first resistance setting terminal RS1 is connected to the first power One end of the resistor 218, the other end of the first resistor 218 is grounded, the second resistor setting end RS2 is connected to one end of the second resistor 219, and the other end of the second resistor 219 is grounded.
  • a bias current source (not shown) is further integrated, and a bias current is generated according to the control signal received by the control signal input terminal DIM.
  • the bias current is input to the bias resistor 220 and the sampling resistor 203 to adjust the sampling voltage received by the peak current detecting terminal Vcs. The specific adjustment process will be described in further detail below.
  • the PFM controller 201 adjusts the on-time Ton and the off-time Toff of the secondary side line 205 of the switching power supply 200 according to the control signal, thereby adjusting the ratio of the on-time Ton to the off-time Toff. And adjusting the peak value of the primary current Ip flowing in the primary side line ⁇ 204 by adjusting the voltage value of the sampling voltage of the peak current detecting terminal Vcs, thereby adjusting the peak value of the secondary side current Is flowing in the secondary side line 205 .
  • the specific adjustment gain is determined by the internal resistance of the first resistor 218, the second resistor 219, the bias resistor 220, the sampling resistor 203, and the PFM controller 201.
  • the average value lavg of the output current of the switching power supply 200 can be adjusted to a fixed value corresponding to the control signal, which is independent of the output voltage Vout of the load terminal and the input voltage Vin.
  • FIG. 4 is a schematic diagram of the internal circuit structure of the PFM controller 201 shown in FIG. 3
  • FIG. 5 is a schematic diagram of the internal circuit structure of the module 301 shown in FIG. 4
  • FIG. 6 is a schematic diagram of the internal circuit structure of the module 302 shown in FIG. 3 to 6 are explained in detail.
  • the PFM controller 201 includes a timing capacitor and a control unit, and the timing capacitor is used to time the on-time Ton and the off-time Toff of the sub-edge ⁇ 205, and the timing voltages at both ends thereof are used to generate the driving voltage;
  • the control unit generates a charging current for charging the timing capacitor and a discharging current according to the control signal, the feedback voltage, and the sampling voltage, and the duration of the charging current is the off time Toff of the secondary line ⁇ 205
  • the duration of the discharge current is the on-time Ton of the secondary side line 205.
  • the control unit in the PFM controller 201 includes: a charge and discharge control unit (including the modules 520b, 321 and 322 shown in FIG. 6), and generates a charge and discharge control signal Tons and a gate according to the feedback voltage, the sampling voltage and the timing voltage. a driving voltage, the charge and discharge control signal Tons comprising alternating first voltages and second voltages, the duration of the first voltage being equal to the duration of the charging current, the duration of the second voltage being equal to the Duration of discharge current; current generation unit (package)
  • the module 301 shown in FIG. 4 and the module 520a shown in FIG. 6 generate the charging current and the discharging current according to the control signal and the charge and discharge control signal Tons.
  • the current generating unit includes: a charging current generating unit (including 313, 314, 318 shown in FIG. 4 and 505, 503 shown in FIG. 6), and generating a first charging current Ich according to the control signal, in the charging When the discharge control signal Tons is the first voltage, the first charging current Ich is output as a charging current; the discharging current generating unit (including 315, 316, 319 shown in FIG. 4 and 506 shown in FIG. 6), according to the The control signal generates a first discharge current Idis, and outputs the first discharge current Idis as a discharge current when the charge and discharge control signal Tons is the second voltage.
  • the driving voltage is transmitted from the output terminal PFM to a driver 304 for amplification and output to the output terminal OUT of the PFM controller 201.
  • the PFM controller 201 further includes a power supply biasing unit 303 for processing a power supply signal between the power supply terminal VCC and the ground terminal GND to generate a required power signal and a reference voltage (see FIG. 4). In VI, V2, V3) and so on.
  • the current generating unit described in this embodiment will be further described in detail below with reference to FIG.
  • the module 301 in FIG. 4 includes four signal inputs (a first input, a second input, a third input, and a fourth input) and three signal outputs (a first output, a second output, and Third output).
  • the first input terminal receives the first reference voltage VI; the second input terminal is connected to the first resistance setting terminal RS1; the third input terminal is connected to the control signal input terminal DIM; and the fourth input terminal is connected to the second input terminal.
  • the first output terminal is connected to the input terminal Ch of the module 302; the second output terminal is connected to the input terminal Dis of the module 302; and the third output terminal is connected to the peak current detecting terminal Vcs.
  • the current generating unit includes: a first current generator 310 in the module 301, generating a first reference according to a signal input to the first resistance setting terminal RS1 (through the first resistor 218) and a first reference voltage VI a second current generator 312, generating a second reference current lb according to a control signal Vdim input to the control signal input terminal DIM and a signal input to the second resistance terminal RS2 (through the second resistor 219) And a charging current generating unit that generates a charging current of the timing capacitor according to the charging and discharging control signal Tons; and a discharging current generating unit that generates a discharging current of the timing capacitor according to the charging and discharging control signal Toons.
  • the charging current generating unit includes: a first current mirror 313 that generates a first current ml*Ia after mirroring the first reference current la; a second current mirror 314, for the second reference
  • the current mirror lb image generates a second current m2*Ib, wherein the first current ml*Ia and the second current m2*Ib are subtracted by the current subtractor 318 to generate the first charging current Ich.
  • the discharge current generating unit includes: a third current mirror 315 that generates a third current m3*Ia after mirroring the first reference current la; and a fourth current mirror 316 mirroring the second reference current lb A fourth current m4*Ib is generated; wherein the third current m3*Ia and the fourth current m4*Ib are added by the current adder 319 to generate the first discharge current Idis.
  • the current generating unit further includes an inverting amplifier 311 in the module 301 for inverting and amplifying the control signal Vdim to generate an inverted control signal. Therefore, the input signal of the second current generator 312 in this embodiment is the inverted control signal instead of the control signal Vdim itself.
  • the current generating unit in this embodiment further includes a fifth current mirror 317 serving as the bias current source, and mirroring the second reference current lb to generate a fifth current m5*Ib (ie, a bias current) Ives ) is transmitted to the peak current detecting terminal Vcs and then input to the bias resistor 220 and the sampling resistor 203, and a bias voltage is generated on the bias resistor 220 to be superimposed with the sampling voltage on the sampling resistor 203 Thereafter, the voltage input to the peak current detecting terminal Vcs is adjusted.
  • a fifth current mirror 317 serving as the bias current source, and mirroring the second reference current lb to generate a fifth current m5*Ib (ie, a bias current) Ives ) is transmitted to the peak current detecting terminal Vcs and then input to the bias resistor 220 and the sampling resistor 203, and a bias voltage is generated on the bias resistor 220 to be superimposed with the sampling voltage on the sampling resistor 203 Thereafter, the voltage
  • the bias current Ives also flows into the sampling resistor 203 at the same time, so that the current passing through the sampling resistor 203 is the sum of the bias current Ives and the primary current Ip in the primary side line 204, but
  • the resistance value of the bias resistor 220 (generally hundreds of ohms to thousands of ohms) is much larger than the resistance value of the sampling resistor 203 (generally several ohms), so the bias current Ives flows through the sampling. The voltage generated by resistor 203 is ignored here.
  • the current generating unit further includes a first switch 505 and a second switch 506.
  • the input end of the first switch 505 receives the first charging current Ich, and the control terminal receives an inverted signal of the charge and discharge control signal Tons (via the NOT gate 503), where the charge and discharge control signal Tons is first When the voltage (specifically low level), the first charging current Ich is output as a charging current, and the timing capacitor Ct is charged; the output end of the second switch 506 receives the first discharging current Idis, and the control end
  • the charge/discharge control signal Tons is received, and when the charge and discharge control signal Tons is at a second voltage (specifically, a high level), the first discharge current Idis is output as a discharge current, and the timing capacitor Ct is discharged.
  • the first end of the timing capacitor Ct is connected to the output end of the first switch 505 and the input end of the second switch 506, the second end of the timing capacitor Ct is grounded, and the charging process is performed by the charging current. a discharge process of the discharge current, such that the first end of the timing capacitor Ct is generated The timing voltage.
  • the first current generator 310 generates a first reference current la according to the first reference voltage VI and the first resistor 218 connected to the first resistance setting terminal RS1.
  • the first reference current la The current value is determined by the ratio of the voltage value of the first reference voltage VI to the resistance value of the first resistor 218.
  • the first reference current current la is simultaneously input to the first current mirror 313 and the third current mirror 315, and the current gains of the first current mirror 313 and the third current mirror 315 are respectively ml and m3, thereby
  • the first current at the output of the first current mirror 313 is ml*Ia
  • the third current at the output of the third current mirror 315 is m3*Ia.
  • the inverting amplifier 311 inverts and controls the control signal Vdim input to the control signal input terminal DIM to be transmitted to the second current generator 312.
  • the gain of the inverting amplifier 311 is a negative slope characteristic, that is, when the control signal Vdim is increased, the inverted control signal generated by the inverting amplifier 311 is decreased; when the control signal Vdim is decreased, the inverse The inverted control signal generated by the phase amplifier 311 is increased accordingly.
  • the second current generator 312 generates a second reference current lb according to the inverted control signal output by the inverting amplifier 311 and the second resistor 219 connected to the second resistance setting terminal RS2, the second reference current
  • the current value of lb is determined by the ratio between the voltage value of the inverted control signal output from the inverting amplifier 311 and the resistance value of the second resistor 219 to which the second resistance setting terminal RS2 is connected.
  • the current value of the second reference current lb is determined by the control signal Vdim, the gain of the inverting amplifier 311, and the resistance value of the second resistor 219.
  • the second reference current lb acts as an input to the second current mirror 314, the fourth current mirror 316, and the fifth current mirror 317.
  • the current gains of the second current mirror 314, the fourth current mirror 316, and the fifth current mirror 317 are m2, m4, and m5, respectively, thereby, the current value of the second current at the output of the second current mirror 314
  • the current value of the fourth current at the output of the fourth current mirror 316 is m4*Ib
  • the current value of the fifth current at the output of the fifth current mirror 317 is m5*Ib.
  • the current gains ml, m2, m3 of the first current mirror 313, the second current mirror 314, the third current mirror 315, the fourth current mirror 316, and the fifth current mirror 317 are M4 and m5 are determined by the internal device parameters of each current mirror.
  • the first current generated by the current subtractor 318 to the first current mirror 313 is ml*Ia
  • the first charging current Ich is generated after the second current m2*Ib generated by the second current mirror 314 is subtracted.
  • the current adder 319 adds the third current m3*Ia generated by the third current mirror 315 and the fourth current m4*Ib generated by the fourth current mirror 316 to generate the first discharge current Idis.
  • the first charging current Ich is input to the input end of the first switch 505 via the input terminal Ch of the module 302, and the first discharging current Idis is input to the second switch 506 via the other input terminal Dis of the module 302. The output.
  • the current generating unit adjusts the first charging current Ich, the first discharging current Idis, and the bias current Ives according to the control signal Vdim applied on the control signal input terminal DIM.
  • the adjustment coefficient is determined by the resistance value of the first resistor 218 of the first resistance setting terminal RS1, the resistance value of the second resistor 219 at the second resistor setting terminal RS2, the gain of the inverting amplifier 311, and the gain of each current mirror. Determined by m2, m3, m4, m5.
  • the first charging current Ich is expressed as:
  • the first charging current Ich and the first discharging current Idis are charged and discharged as the charging current and the discharging current, respectively, under the control of the charging and discharging control signal Tons, to
  • the off time Toff and the on time Ton of the secondary side line 205 are adjusted, thereby adjusting the ratio of the on time Ton and the off time Toff.
  • the module 302 in Fig. 4 will be further described in detail below.
  • the module 302 includes four signal inputs and a signal output;
  • the first input terminal Ch of the module 302 is connected to the output end of the current subtractor 318; the second input terminal Dis is connected to the output end of the current adder 319; and the third input terminal is connected to the secondary side current zero crossing detection.
  • the fourth input terminal is connected to the peak current detecting terminal Vcs.
  • the output signal of the output terminal PFM of the module 302 is amplified by the driver 304 and output by the output terminal OUT.
  • the fourth input end of the module 302 is connected to one end of the bias resistor 220 through the peak current detecting terminal Vcs, and the other end of the bias resistor 220 is connected to one end of the sampling resistor 203 connected to the switching transistor 202, and the sampling resistor The other end of 203 is grounded.
  • the module 302 includes: a first comparator 321, a second comparator 322, and a module 320.
  • the first input end of the module 320 is connected to the input end Ch of the module 302, the second input end of the module 320 is connected to the input end Dis of the module 302, and the third input end Demag of the module 320 is connected to the output end of the first comparator 321 .
  • the fourth input Peak of the module 320 is connected to the output of the second comparator 322, and the output signal of the module 320 is output by the output PFM of the module 302.
  • the positive input terminal of the first comparator 321 is connected to the second reference voltage V2, the negative input terminal is connected to the secondary current zero-crossing detecting terminal Vfb, and the output terminal is connected to the third input terminal Demag of the module 320.
  • the negative input terminal of the second comparator 322 is connected to the third reference voltage V3, the positive input terminal is connected to the peak current detecting terminal Vcs, and the output terminal is connected to the fourth input terminal Peak of the module 320.
  • the charging and discharging control unit includes the first comparator 321, the second comparator 322, and the secondary current on/off timer (FIG. 6). 520b, integrated in module 320). It should be noted that, referring to FIG. 6, the module 320 includes the timing capacitor Ct, the first switch 505, the second switch 506, the NOT gate 503, and the secondary current on/off timer 520b in the charge and discharge control unit. .
  • the secondary current on/off timer 520b generates the charge and discharge control signal Tons, and charges the first charging current Ich as a charging current to the timing capacitor Ct when the charge and discharge control signal Tons is the first voltage.
  • the charging time of the timing capacitor Ct corresponds to the off time Toff of the secondary side line 205; when the charging and discharging control signal Tons is the second voltage, the first discharging current Idis is used as the discharging current to the timing capacitor Ct
  • the discharge is performed, and the discharge time of the timing capacitor Ct corresponds to the on-time Ton of the sub-edge ⁇ 205.
  • the output terminal PFM of the module 320 When the charge and discharge control signal Tons is the first voltage (specifically, the low level), at a certain time point during the off time Toff, the output terminal PFM of the module 320 outputs a high level, which is caused by the driver 304.
  • the switching transistor 202 is turned on to generate a primary current Ip flowing through the primary side turn 204 and the switching transistor 202.
  • the primary current Ip flows through the sampling resistor 203, and the sampling voltage Vrcs is generated on the sampling resistor 203.
  • the bias current Ives generated by the fifth current mirror 317 flows through the bias current.
  • a resistor 220 (having a resistance value of Rpk) and a sampling resistor 203 (having a resistance value of Res) generate a bias voltage Vrpk on the bias resistor 220.
  • the sampling voltage Vrcs is superimposed with the bias voltage Vrpk and then transmitted to the second comparator 322 via the peak current detecting terminal Vcs, compared with the third reference voltage V3, and when the third reference voltage V3 is exceeded, the second comparator 322 outputs a high level, so that the signal of the fourth input end Peak is at a high level, and the fourth input end Peak is high, so that the charge and discharge control signal Tons generated by the secondary side current on/off timer 520b is a second voltage (specific It is high level) to stop charging the timing capacitor Ct, the off time Toff of the secondary side line 205 is ended, and the output end of the secondary side current on/off timer 520b (ie, the output terminal PFM of the module 320) outputs a low level.
  • the driving voltage is generated after the driver 304, so that the switching transistor 202 is turned off, and the secondary side line 205 starts to generate the secondary current Is, which is output via the output rectifying unit 200b.
  • the charge-discharge control signal Tons generated by the secondary-side current on-off timer 520b is a second voltage (specifically, a high level), and the first discharge current Idis is used.
  • the timing capacitor Ct is discharged as a discharge current, and the on-time Ton timing of the secondary side line 205 is started thereby, and the timing capacitance Ct discharge time corresponds to the on-time Ton of the secondary side line 205.
  • the voltage on the auxiliary line ⁇ 206 also crosses zero, and the voltage is divided by the zero-crossing detecting voltage dividing resistors 209 and 210, and then transmitted to the secondary
  • the side current cross-zero detection terminal Vfb is transmitted to the first comparator 321 for comparison with the second reference voltage V2.
  • the feedback voltage of the secondary current zero-crossing detection terminal Vfb is lower than the second reference voltage V2, and the output of the first comparator 321 is at a high level, and the signal is transmitted to the input terminal of the module 320. Demag.
  • the secondary current on/off timer 520b detects that the Demag signal is at a high level, the charge and discharge control signal Tons generated thereof is changed, so that the discharge process of the timing capacitor Ct is stopped, and correspondingly, the secondary line ⁇ The on-time Ton timing of 205 ends, and at the same time, the timing capacitor Ct is restarted to be charged, and the off-time Toff of the next cycle is thereby started.
  • the secondary current on/off timer 520b performs the timing capacitance Ct by using the charging current (specifically, the first charging current Ich in this embodiment) and the discharging current (specifically, the first discharging current Idis in this embodiment).
  • Charging, discharging, and timing, the duration of the charging process is equal to the off time Toff of the secondary side line 205, and the duration of the discharging process is equal to the on time Ton of the secondary side line 205.
  • the duration of the off time Toff ie, the charging time of the timing capacitor Ct
  • the duration of the Ton ie, the discharge time of the timing capacitor Ct
  • the ratio of the on-time Ton to the off-time Toff is only The ratio of a charging current Ich to the first discharging current Idis is determined independently of the magnitude of the capacitance of the timing capacitor Ct.
  • Iavg can be expressed as:
  • the technical solution can adjust the output current of the switching power supply 200 by adjusting the control signal Vdim.
  • the control signal Vdim can adjust the average value Iavg of the output current of the switching power supply 200, and the adjustment process is related to the following factors: the first resistor 218 connected to the first resistor setting terminal RS1 and the second resistor setting terminal RS2 connected The second resistor 219, the bias resistor 220, the sampling resistor 203, the turns ratio of the primary side line 204 and the secondary side line 205, and the first current generator, the second current generator, and the current mirrors inside the PFM controller 201 Circuit parameters of the device.
  • the inverting amplifier 311 in the current generating unit includes: a third operational amplifier 408 whose positive input terminal receives the control signal Vdim and whose negative input terminal is connected to its output terminal, the connection structure
  • the third operational amplifier 408 constitutes a unity gain amplifier, and the signal at the output thereof follows the control signal Vdim;
  • the fourth operational amplifier 409 has a negative input terminal through the third
  • the resistor 412 is coupled to the output of the third operational amplifier 408 and is coupled to the output of the fourth operational amplifier 409 via a fourth resistor 413, the positive input of which is coupled to a reference voltage Vref (generated by the power supply bias unit 303) .
  • the gain of the inverting amplifier 311 is a negative slope, that is, when the control signal Vdim is increased, the generated inverted control signal is decreased; conversely, when the control signal Vdim is decreased, the generated inverse is generated.
  • the phase control signal is increased.
  • the first current generator 310 in the current generating unit includes a first operational amplifier 401 and a first transistor 402.
  • the positive input terminal of the first operational amplifier 401 receives the first reference voltage VI (generated by the power supply bias unit 303), and the negative input terminal of the first operational amplifier 401 is connected through the first resistance setting terminal RS1.
  • One end of the first resistor 218 is, and the other end of the first resistor 218 is grounded.
  • the first transistor 402 is connected in a source follower structure, the gate thereof is connected to the output end of the first operational amplifier 401, the source thereof is grounded via the first resistor 218, and the drain thereof is the first
  • the current signal output terminal of the current generator 310 generates the first reference current Ia.
  • the first reference current la at the output of the first current generator 310 is expressed as:
  • VI represents the voltage value of the first reference voltage
  • R218 represents the resistance value of the first resistor 218.
  • the second current generator 312 in the current generating unit includes a second operational amplifier 410 and a second transistor 411.
  • a positive input terminal of the second operational amplifier 410 is coupled to an output of the fourth operational amplifier 409, and a negative input terminal of the second operational amplifier 410 is coupled to ground via the second resistor 219.
  • the second transistor 411 is connected in a source follower structure, the gate thereof is connected to the output end of the second operational amplifier 410, the source is grounded via the second resistor 219, and the drain is the second current generator.
  • the current signal output terminal of 312 generates the second reference current Ib.
  • the second reference current lb is a ratio of a voltage value of the inverted control signal generated by the inverting amplifier 311 to a resistance value of the second resistor 219.
  • the input signal of the second current generator 312 is an inverted control signal generated by the inverting amplifier 311, and in other embodiments of the present invention, the inverse may be further
  • the phase amplifier 311 is omitted and the control signal Vdim is used directly as an input to the second current generator 312.
  • the second reference current lb at the output of the second current generator 312 is expressed as:
  • R219 (7) represent resistance values of the fourth resistor 413, the third resistor 412, and the second resistor 219, respectively, and Vref represents a voltage value of the reference voltage Vref, Vdim A voltage value indicating the control signal Vdim.
  • the first current mirror 313 in the current generating unit includes a first P-type transistor 403 and a second P-type transistor 405, the source of the first P-type transistor 403 is connected to the positive pole of the power source, and the drain is connected to the first
  • the gate of the P-type transistor 403 receives the first reference current la
  • the source of the second P-type transistor 405 is connected to the anode of the power source
  • the gate is connected to the gate of the first P-type transistor 403.
  • the current gain ml of the first current mirror 313 is determined by the aspect ratio of the two P-type transistors described above, and the generated first current ml *Ia is output from the drain of the second P-type transistor 405.
  • the second current mirror 314 in the current generating unit includes a third P-type transistor 414, a fourth P-type transistor 416, a first N-type transistor 417, and a second N-type transistor 418, the third P-type transistor 414.
  • the source is connected to the positive pole of the power source, the drain is connected to the gate of the third P-type transistor 414 and receives the second reference current lb, and the source of the fourth P-type transistor 416 is connected to the positive pole of the power supply, and the gate is connected a gate of the third P-type transistor 414, a source of the first N-type transistor 417 is grounded, and a drain is connected to a drain of the fourth P-type transistor 416 and a gate of the first N-type transistor 417 The source of the second N-type transistor 418 is grounded, the gate is connected to the gate of the first N-type transistor 417, and the drain generates the second current m2*Ib.
  • the current gain m2 of the second current mirror 314
  • the third current mirror 315 in the current generating unit includes a fifth P-type transistor 404, a third N-type transistor 406, a fourth N-type transistor 407, and the first P-type transistor 403, the fifth p-type
  • the source of the transistor 404 is connected to the anode of the power source, the gate is connected to the gate of the first P-type transistor 403, the source of the third N-type transistor 406 is grounded, and the drain is connected to the drain of the fifth P-type transistor 404.
  • a gate of the third N-type transistor 406 a source of the fourth N-type transistor 407 is grounded, a gate is connected to a gate of the third N-type transistor 406, and a drain generates the third current M3*Ia, whose current gain m3 is determined by the aspect ratio of the above four transistors included.
  • the fourth current mirror 316 in the current generating unit includes a fifth N-type transistor 419 and the third P-type transistor 414, a fourth P-type transistor 416, and a first N-type transistor 417, the fifth N-type
  • the source of the transistor 419 is grounded, the gate is connected to the gate of the first N-type transistor 417, and the drain generates the fourth current m4*Ib, the current gain m4 of which includes the width-to-length ratio of the above four transistors. determine.
  • the fifth current mirror 317 in the current generating unit includes a sixth P-type transistor 415 and a third P-type transistor 414, the source of the sixth P-type transistor 415 is connected to the positive pole of the power source, and the gate is connected to the The gate of the third P-type transistor 414 generates a fifth current m5*Ib (ie, the bias current Ives) and is grounded via the bias resistor 220 and the sampling resistor 203.
  • m5*Ib ie, the bias current Ives
  • the current subtractor 318 in the current generating unit includes the second P-type transistor 405 and the second N-type transistor 418, and is connected by the drains of the two transistors to perform current subtraction.
  • the current at the output of the current subtractor 318 is the first charging current Ich, and its value is (ml*Ia - m2*Ib).
  • the current adder 319 in the current generating unit includes the fourth N-type transistor 407 and the fifth N-type transistor 419, and is connected by the drains of the two transistors to effect addition of current.
  • the current at the output of the current adder 319 is the first discharge current Idis, which is ( m3 * Ia + m4 * Ib ).
  • the current generating unit adjusts the first charging current Ich and the first discharging current Idis according to the input control signal Vdim, and the bias current Ives is also simultaneously adjusted by the control signal Vdim, and the specific adjustment thereof
  • the procedures and parameters can be referred to the formulas (2), (3), (4), (6), (7).
  • the charge and discharge control unit will be described in detail below with reference to Figs. 3, 4 and 6.
  • FIG. 6 is a schematic structural diagram of the module 302 in FIG. 4 according to an embodiment of the present invention, wherein the charge and discharge control unit includes: a first comparator 321 , and a feedback voltage received by the secondary current zero-crossing detecting terminal Vfb Comparing with the second reference voltage V2 (generated by the power supply biasing unit 303) to generate a feedback comparison signal; the second comparator 322, the sampling voltage received by the peak current detecting terminal Vcs and the third reference voltage V3 Comparing (generated by the power supply biasing unit 303) to generate a sampling comparison signal; the secondary current on/off timer 520b, receiving the feedback comparison signal, the sampling comparison signal, and the timing voltage generated by the timing capacitor Ct, generating The driving voltage and the charge and discharge control signal Tons.
  • the module 520a is a part of the current generating unit, and the description thereof is as described above. I won't go into details here.
  • the secondary current on/off timer 520b includes: a D flip-flop 501 having a D input receiving a logic high level ("1"), a clock input receiving the feedback comparison signal, and an RS flip-flop 502 having a reset terminal a positive output terminal of the D flip-flop 501 is connected, the set terminal receives the sampling comparison signal, and a positive output terminal generates the charge and discharge control signal Tons; and a third comparator 507 whose positive input terminal inputs the timing voltage The negative input terminal inputs a fourth reference voltage V4 (generated by the power supply bias unit 303); the NAND gate 509 has an input terminal connected to the output end of the third comparator 507, and the other input terminal receives the The inverted signal of the charge and discharge control signal Tons (passing through the gate 508) is connected to the reset terminal of the D flip-flop 501, and the output terminal thereof generates the driving voltage via the inverter 510.
  • a D flip-flop 501 having a D input receiving a logic high level ("1")
  • the timing capacitor Ct in Fig. 6 regulates the on and off times of the secondary side line 205, and its charge and discharge process is controlled by the charge and discharge control signal Tons.
  • the charge and discharge control unit outputs a driving voltage (via the output terminal PFM) to a low level, and the charge and discharge control signal Tons signal is at a high level, so that the current generating unit
  • the second switch 506 is turned on, the first switch 505 is turned off, and the discharge current (ie, the first discharge current Idis) input by the input terminal Dis is discharged through the second switch 506;
  • the voltage signal is coupled via the auxiliary line ⁇ 206, it is transmitted to the secondary current zero-crossing detecting terminal Vfb via the divided voltage (via the zero-crossing detecting voltage dividing resistors 209 and 210 in FIG. 3), and the secondary side line 205 is turned on.
  • the feedback voltage received by the secondary current zero-crossing detecting terminal Vfb is lower than the second reference voltage V2, thereby causing the level of the output of the first comparator 321 (ie, the The feedback comparison signal) goes high and is input to the input terminal Demag; the rising edge of the input terminal Demag causes the positive output terminal of the D flip-flop 501 to output a high level, and the positive output terminal of the RS flip-flop 502 is cleared, so that Charge and discharge control signal
  • the Tons signal is low, that is, the on-time Ton timing ends, and the off-time Toff is turned on; the charge-discharge control signal Tons is at a level such that the first switch 505 is turned on, the second switch 506 is turned off, and the timing capacitor is turned off.
  • the Ct is charged by the charging current (ie, the first charging current Ich) through the first switch 505 to generate the timing voltage; when the timing capacitor Ct is connected to the positive input terminal of the third comparator 507, the timing voltage exceeds the first When the four reference voltages V4, the third comparator 507 outputs a high level, and the driving voltage generated by the corresponding output terminal PFM is at a high level, and the D flip-flop 501 is reset; after that, the driving signal of the high level is driven.
  • the charging current ie, the first charging current Ich
  • the output of the actuator 304 is such that the switching transistor 202 is turned on, and the primary current Ip is generated; the sampling voltage generated by the primary current Ip on the sampling resistor 203 is superimposed and adjusted by the bias voltage generated on the bias resistor 220, and then transmitted to the peak.
  • the current detecting terminal Vcs when the voltage received by the peak current detecting terminal Vcs exceeds the third reference voltage V3, the output voltage of the second comparator 322 becomes high and is transmitted to the input terminal Peak, so that the output of the RS flip-flop 502 is
  • the charge and discharge control signal Tons is again set to a high level, the off time Toff timing ends, the on time Ton timing process is turned back on, and the drive voltage of the output terminal PFM is reset to a low level so that the switching transistor 202 is turned off;
  • the timing capacitor Ct is again discharged through the second switch 506, and the secondary side line 205 is again turned on to generate the secondary current Is to release the stored therein.
  • the on-time Ton and the off-time Toff of the sub-edge ⁇ 205 correspond to the high-level and low-level durations of the charge-discharge control signal Tons, that is, the discharge time and the charging time of the timing capacitor Ct, respectively.
  • the discharge time and the charging time of the timing capacitor Ct are respectively determined by the magnitudes of the capacitances of the first discharge current Idis and the first charging current Ich and the timing capacitor Ct; therefore, the ratio of the on-time Ton to the off-time Toff is determined by the first charging
  • the ratio of the current Ich to the first discharge current Idis is determined independently of the magnitude of the capacitance of the timing capacitor Ct.
  • the ratio of the first charging current Ich to the first discharging current Idis is also fixed, whereby the output current of the switching power supply 200
  • the average value Iavg is also fixed accordingly, so that the average value Iavg of the corresponding output current can be obtained by adjusting the voltage value of the control signal Vdim.
  • Vfb represents a feedback voltage received by the secondary current zero-crossing detecting terminal Vfb
  • Vcs represents a voltage signal received by the peak current detecting terminal Vcs
  • Vrcs represents a sampling resistor.
  • Vrpk represents the voltage signal on the bias resistor 220
  • Ipk represents the peak value of the primary current Ip
  • Isk represents the peak value of the secondary current Is
  • Iavg represents the average value of the secondary current Is
  • Vet represents the timing capacitance Ct Timing voltage on
  • state 1 indicates a waveform corresponding to a higher voltage value of the control signal Vdim
  • state 2 indicates a waveform corresponding to a voltage value of the control signal Vdim
  • state 3 indicates a voltage value at the control signal Vdim Corresponding waveform at lower time.
  • the bias voltage Vrpk across the bias resistor 220 also increases correspondingly, so that the peak current detecting terminal Vcs receives
  • the voltage signal Vcs rises faster to the third reference voltage V3, so that the primary side line ⁇ is turned off faster, resulting in a corresponding decrease in the primary side current peak Ipk and the secondary side current peak Isk, and thus the output current ( That is, the average value Iavg of the secondary current Is) is also correspondingly reduced.
  • FIG. 8 is a graph showing a correspondence relationship between a control signal Vdim of a switching power supply and an average value Iavg of an output current according to an embodiment of the present invention. It is to be noted that the curve of FIG. 8 is other than the control signal Vdim in the switching power supply. The other device parameters have been determined under the premise of getting. As can be seen from Fig. 8, when the control signal Vdim is increased, the average value Iavg of the output current is also increased accordingly. In actual applications, the voltage value of the control signal Vdim can be adjusted according to the required output current. In addition, in other embodiments of the present invention, if the inverting amplifier 311 shown in FIG. 4 is not included in the current generating unit, the average value Iavg of the output current corresponding to the increase of the control signal Vdim Reduced.
  • the fifth current mirror 317 and the bias resistor 220 in this embodiment are used to adjust the sampling voltage.
  • the bias current Ives generated by the fifth current mirror 317 flows through the bias resistor 220 and the sampling resistor 203, and generates a bias voltage to adjust the sampling voltage received by the peak current detecting terminal Vcs.
  • the magnitude of the bias current Ives is controlled by the control signal Vdim.
  • a bias current source independent of the control signal Vdim may be used to generate the bias current Ives to adjust the sampling voltage to adjust the primary edge ⁇ The peak current of 204, in turn, enables adjustment of the peak current of the secondary side line 205.
  • the PFM controller 201 in the above embodiment is integrated in a single chip, and the first resistor 218 and the second resistor 219 are connected to the PFM controller 201 through chip pins.
  • the first resistor 218 and second resistor 219 may also be integrated inside the chip.
  • the difference is that, due to the limitation of the semiconductor process level, the resistance value of the resistor integrated in the chip may have a certain deviation. Therefore, the scheme of using the external resistor in this embodiment makes the resistance value more accurate, and the corresponding input and output changes. Relationships are also easier to control.
  • FIG. 9 shows a schematic circuit diagram of another embodiment of the PFM controller 201 shown in FIG. Figure.
  • the overall structure is similar to the previously described embodiment, including a timing capacitor 612 and a control unit, wherein the control unit includes a current generating unit (including 601 to 608, 610, 611, 613 to 617 in FIG. 9) and a charge and discharge control unit ( Including 640 and 623, 625) in FIG.
  • the current generating unit includes: a timing current generating unit (including 601 to 608, 610, 611 in FIG. 9) that receives the control signal Vdim, generates a timing current let, and the timing current The current value is adjusted by the voltage value of the control signal Vdim; the first reference current source 613 outputs a first reference current Id, and the first reference current Id and the timing current let are subtracted to generate a second charging current.
  • a timing current generating unit including 601 to 608, 610, 611 in FIG. 9
  • the second charging current is output as a charging current when the charging and discharging control signal Tons is a first voltage (specifically, a low level); the second reference current source 616 outputs a second reference current k*Id, The second reference current k*Id is added to the timing current let to generate a second discharge current, and the second discharge current is when the charge and discharge control signal Tons is a second voltage (specifically, a high level) Output as a discharge current.
  • the first reference current source 613 is a reference current source commonly used in the prior art
  • the second reference current source 616 may be a current mirror (gain is k).
  • the second reference current k*Id is generated after the first reference current is mirrored, and may also be an independent current source.
  • the timing current generating unit includes a third current generator that generates a third reference current Ic according to the control signal Vdim, and a timing current mirror that generates the timing current Ict after mirroring the third reference current Ic.
  • the control signal Vdim is inverted by the inverting amplifier and input to the third current generator.
  • the inverting amplifier includes: a sixth operational amplifier 601, a positive input terminal receiving the control signal Vdim, a negative input terminal connected to an output terminal thereof; a seventh operational amplifier 602, a negative input terminal connected through the fifth resistor 604
  • the output terminal of the sixth operational amplifier 601 is connected to the output terminal of the seventh operational amplifier 602 through a sixth resistor 605.
  • the positive input terminal is connected to the reference voltage, and the output terminal generates an inverted control signal.
  • the third current generator includes: a fifth operational amplifier 603, the positive input terminal receives the inverted control signal, the negative input terminal is coupled to the second resistance set terminal RS2; and the third transistor 606 is coupled to the gate An output terminal of the fifth operational amplifier 603 is connected to the second resistance setting terminal RS2, and a drain generates the third reference current Ic.
  • the timing current mirror includes P-type transistors 607, 608 and N-type transistors 610, 611 that generate the timing current Ict after mirroring the third reference current Ic.
  • another current mirror is further included, which is composed of P-type transistors 607 and 609 for mirroring the third reference current Ic to generate a bias current Ives for the sampling voltage. Make adjustments, the adjustment process is referred to the previous article, and will not be repeated here.
  • the charge and discharge control unit receives the feedback voltage, the sampling voltage, and the timing voltage to generate the driving voltage and the charge and discharge control signal Tons.
  • the structure of the charge and discharge control unit is similar to that of the foregoing embodiment, and includes: a fourth comparator 625, comparing the feedback voltage with the second reference voltage V2 to generate a feedback comparison signal; and a fifth comparator 623, Comparing the sampling voltage with the third reference voltage V3 to generate a sampling comparison signal; the secondary current on/off timer 640, receiving the timing voltage, the feedback comparison signal, and the sampling comparison signal to generate the driving voltage and charging Discharge control signal Tons.
  • the secondary current on/off timer 640 is similar to the previous embodiment, and includes: a D flip-flop 622 having a D input receiving a logic high level, a clock input receiving the feedback comparison signal; and an RS flip 621 resetting The terminal is connected to the positive output terminal of the D flip-flop 622, the set terminal receives the sampling comparison signal, and the positive output terminal generates the charge and discharge control signal Tons; the sixth comparator 618, the positive input terminal receives the timing a voltage, the negative input terminal thereof receives the fourth reference voltage V4; the NAND gate 620 has an input terminal connected to the output end of the comparator 618, and the other input terminal receives the inverted signal of the charge and discharge control signal Tons (via The non-gate 619 is generated, and its output terminal is connected to the reset terminal of the D flip-flop 622, and the output terminal thereof generates the driving voltage via the inverter 624.
  • the charge and discharge control signal Tons controls the charge and discharge process of the timing capacitor 612 through the third switch 614 and the fourth switch 615.
  • the input end of the third switch 614 inputs the first reference current Id
  • the control end receives an inverted signal of the charge and discharge control signal Tons (generated via the NOT gate 617), and the output end thereof receives the timing current Ict .
  • the input end of the fourth switch 615 receives the timing current let, the control end receives the charge and discharge control signal Tons, and the output end thereof receives the second reference current k*Id; the first end of the timing capacitor 612 is connected
  • An output end of the third switch 614 and an input end of the fourth switch 615 are grounded at a second end thereof, and the first end thereof generates the timing voltage.
  • the embodiment of the present invention further provides a method for adjusting an output current of a switching power supply.
  • the timing capacitor Ct is adjusted by adjusting a voltage value of the control signal Vdim.
  • the current values of the charging current and the discharging current change the on-time Ton and the off-time Toff of the secondary line ⁇ 205, thereby adjusting the ratio of the on-time Ton to the off-time Toff, thereby changing The average value of the switching power supply output current.
  • the bias current is input to the bias resistor 220 and the sampling resistor 203 to be converted into a bias voltage, and the bias is The voltage is superimposed on the sampling voltage to adjust the magnitude of the voltage received by the peak current detecting terminal Vcs, thereby adjusting the peak current of the primary side line ⁇ 204, thereby realizing the adjustment of the peak current of the secondary side line 205. Therefore, the average value of the output current of the switching power supply 200 is changed.
  • the switching power supply and the method for adjusting the output current thereof provided by the above technical solution adjust the on-time and the off-time of the secondary side line by the control signal, thereby changing the ratio between the on-time and the off-time. Therefore, the adjustment flexibility of the output current is improved.
  • control signal is used to adjust the sampling voltage obtained by the primary current passing through the sampling resistor, and then the peak current of the primary side line ⁇ is adjusted, thereby changing the peak current of the secondary side line ,, and further flexibly adjusting the output current.

Abstract

La présente invention a trait à une alimentation à découpage et à son procédé de régulation de courant de sortie. L'alimentation à découpage inclut un transformateur (215), un organe de commande de modulation d'impulsions en fréquence (201) et un transistor de commutation (202). L'organe de commande de modulation d'impulsions en fréquence (201) génère une tension d'attaque en fonction d'une tension de rétroaction, d'une tension d'échantillonnage et d'un signal de commande fourni en entrée afin de commander le transistor de commutation (202) afin qu'il active ou qu'il désactive un enroulement primaire (204) du transformateur de manière à ajuster le temps d'allumage et le temps de coupure d'un enroulement secondaire (205) du transformateur. La tension de rétroaction correspond à la tension fournie en sortie par l'enroulement auxiliaire (206) du transformateur, et la tension d'échantillonnage correspond à la tension existant au niveau de la seconde extrémité du transistor de commutation (202). L'alimentation à découpage et son procédé de régulation de courant de sortie permettent d'améliorer la flexibilité de régulation du courant de sortie de l'alimentation à découpage.
PCT/CN2010/073771 2010-04-14 2010-06-10 Alimentation à découpage et son procédé de régulation de courant de sortie WO2011127682A1 (fr)

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