WO2011114416A1 - Procédé de détermination de la tension d'alimentation d'un circuit intégré à semi-conducteur et système de régulation de la tension d'alimentation d'un circuit intégré à semi-conducteur - Google Patents

Procédé de détermination de la tension d'alimentation d'un circuit intégré à semi-conducteur et système de régulation de la tension d'alimentation d'un circuit intégré à semi-conducteur Download PDF

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WO2011114416A1
WO2011114416A1 PCT/JP2010/054302 JP2010054302W WO2011114416A1 WO 2011114416 A1 WO2011114416 A1 WO 2011114416A1 JP 2010054302 W JP2010054302 W JP 2010054302W WO 2011114416 A1 WO2011114416 A1 WO 2011114416A1
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delay
circuit
semiconductor integrated
integrated circuit
power supply
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PCT/JP2010/054302
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English (en)
Japanese (ja)
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宣夫 札抜
喜幸 平井
陽子 藤田
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ケイレックス・テクノロジー株式会社
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Priority to JP2010510590A priority Critical patent/JPWO2011114416A1/ja
Priority to PCT/JP2010/054302 priority patent/WO2011114416A1/fr
Publication of WO2011114416A1 publication Critical patent/WO2011114416A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Definitions

  • the present invention relates to a power supply voltage determination method for a semiconductor integrated circuit that determines an optimum power supply voltage for the semiconductor integrated circuit, and a power supply voltage control system for the semiconductor integrated circuit.
  • the power supply voltage has been controlled for the purpose of reducing the power consumption of semiconductor integrated circuits or guaranteeing the operation performance.
  • DVFS Dynamic Voltage and Frequency Scaling
  • processor commercialized by ARM provides a function called IEM (Intelligent Energy Management), and the output of the performance monitor circuit mounted on the chip is processed by embedded software to obtain the optimum operating power supply voltage. ing.
  • IEM Intelligent Energy Management
  • the optimum operating power supply voltage is determined based on the evaluation of the prototype. Therefore, it is difficult to accumulate reliable data unless the chip is produced in large quantities such as a microprocessor. Or, like IEM, it is necessary to perform processing by software using an internal processor in order to calculate the optimum operating power supply voltage. For this reason, the products to be applied are extremely limited.
  • Patent Document 1 As a method for calculating the performance dispersion system of a semiconductor integrated circuit for accurately calculating the influence of process variations and the like on the performance of the semiconductor integrated circuit, for example, there is a method described in Patent Document 1.
  • process fluctuations, power supply voltage fluctuations, and temperature fluctuations are not directly calculated as variations in characteristics of large-scale semiconductor integrated circuits, but are mapped to variations in gate levels.
  • a method for calculating variation in circuit characteristics has been proposed.
  • the variation in characteristics of the semiconductor integrated circuit is calculated by mapping the variation in the gate level to the variation in the gate level. It takes time to create In addition, the device parameter dependency is not taken into account in the variation in characteristics of the semiconductor integrated circuit indicated by the created performance distribution.
  • the variation in characteristics of a semiconductor integrated circuit is preferably calculated in consideration of the dependence of device parameters that cause characteristics variation for each signal transmission path based on the connection relationship of various circuits included in the semiconductor integrated circuit. Was not realized.
  • the conventional performance distribution system calculation method for a semiconductor integrated circuit only calculates the power consumption of the semiconductor integrated circuit using the performance distribution.
  • An optimum power supply voltage for shortening the time for creating a performance distribution of a semiconductor integrated circuit and reducing the power consumption of the semiconductor integrated circuit using the performance distribution is provided.
  • An object of the present invention is to provide a power supply voltage determination method for a semiconductor integrated circuit to be determined and a power supply voltage control system for the semiconductor integrated circuit.
  • a method of determining a power supply voltage of a semiconductor integrated circuit includes: a cell library of a plurality of cells constituting a semiconductor integrated circuit; and at least a gate as a parameter that causes variation in characteristics of delay times of the plurality of cells.
  • process variation information given as a variation range of device parameters including parameters equivalent to the above parameters on a long or threshold voltage or a device model (for example, SPICE model), and at least a power supply voltage or an operating temperature given as an operating condition.
  • the plurality of cells having a high sensitivity of the plurality of parameters and different dependencies between the plurality of parameters are selected from the cell library, and the selected plurality of cells are selected.
  • Forming a characteristic monitor circuit including a plurality of delay circuits in which a plurality of cells are connected in series, and the delay time of all signal transmission paths in the semiconductor integrated circuit is a plurality of parameters that cause the characteristic variation of each cell.
  • a database expressed and stored as a response curved surface for the above is prepared, and the optimum power supply voltage that satisfies the required performance of the delay characteristics of the semiconductor integrated circuit when a plurality of parameters that cause the characteristic variation is given to the database
  • a plurality of parameters serving as the characteristic variation factor are estimated from the output of the characteristic monitor circuit, and the estimated characteristic variation factor
  • the optimum power supply voltage of the semiconductor integrated circuit is determined using a plurality of parameters and the map.
  • a substrate bias voltage determination method for a semiconductor integrated circuit includes: a cell library of a plurality of cells constituting a semiconductor integrated circuit; and at least a parameter that causes a characteristic variation factor of a delay time of the plurality of cells.
  • process variation information given as a variation range of a device parameter including a parameter equivalent to the parameter on the gate length or threshold voltage or a device model (for example, SPICE model), and at least a power supply voltage or an operating temperature given as an operating condition .
  • Statistically analyzing the characteristic variation of each cell included in the cell library expressing the delay time of each cell as a response surface with respect to a plurality of parameters serving as a characteristic variation factor, and a plurality of parameters serving as the characteristic variation factor.
  • the sensitivity and mutual dependence of Based on the calculation results for the sensitivity of the plurality of parameters and the dependence between the plurality of parameters, a plurality of cells having high sensitivity of the plurality of parameters and different dependencies between the plurality of parameters are selected from the cell library, and the selected cells are selected.
  • Forming a characteristic monitor circuit including a delay circuit in which a plurality of cells are connected in series, and the delay time of all signal transmission paths in the semiconductor integrated circuit is a plurality of parameters that cause the characteristic variation of each cell.
  • An optimum substrate bias voltage satisfying the required performance of a delay characteristic of the semiconductor integrated circuit when a database expressed and stored as a response curved surface is created and a plurality of parameters that cause the characteristic variation is given to the database
  • a map showing the relationship between the determined optimum substrate bias voltage and the multiple parameters that cause the characteristic variation is created.
  • the optimum substrate bias voltage of the semiconductor integrated circuit is determined using a plurality of parameters that cause the characteristic variation and the map.
  • a power supply voltage control system for a semiconductor integrated circuit includes a semiconductor integrated circuit and a plurality of delay circuits, and each of the delay signals is different from an input signal using the plurality of delay circuits.
  • a characteristic monitor circuit that outputs a signal
  • an encoder circuit that encodes each of a plurality of delay signals output from the characteristic monitor circuit and outputs data of a predetermined number of bits, and the data that is output from the encoder circuit according to the data
  • a power supply voltage control circuit for outputting a power supply voltage value corresponding to the data to the semiconductor integrated circuit based on a table in which the power supply voltage value of the semiconductor integrated circuit is set.
  • a substrate bias voltage control system for a semiconductor integrated circuit includes a semiconductor integrated circuit and a plurality of delay circuits, and each of the plurality of delay circuits is used to provide different delays with respect to an input signal.
  • a characteristic monitor circuit that outputs a signal
  • an encoder circuit that encodes each of a plurality of delay signals output from the characteristic monitor circuit and outputs data of a predetermined number of bits, and a response to the data output from the encoder circuit
  • a substrate bias voltage control circuit for outputting a substrate bias voltage value corresponding to the data to the semiconductor integrated circuit based on a table in which the substrate bias voltage value of the semiconductor integrated circuit is set.
  • the present invention by using the design data and process variation information of the semiconductor integrated circuit, the dependency between the device parameters that cause the characteristic variation is obtained for all the signal transmission paths in the semiconductor integrated circuit.
  • FIG. 2 is a flowchart for explaining the outline of the power supply voltage determination method for the semiconductor integrated circuit according to the embodiment of the present invention following FIG. 1; It is a figure which shows an example of the optimal operation
  • FIG. 5 is a diagram illustrating a circuit configuration example of a characteristic monitor circuit and an encoder circuit of the power supply voltage control system for the semiconductor integrated circuit shown in FIG. 4.
  • FIGS. 2A and 2B show an embodiment of a response surface for a plurality of device parameters that cause the delay time of each cell stored in the cell library characteristic variation model shown in step ST104 in FIG.
  • FIG. It is a figure which shows one Example of the semiconductor chip carrying the characteristic monitor circuit containing the delay circuit comprised using the cell extracted from the cell library. It is a figure which shows one Example of the chip level timing model shown to step ST110 in FIG.
  • DESCRIPTION OF SYMBOLS 100 Power supply voltage control system of a semiconductor integrated circuit, 200 ... Semiconductor chip, 300 ... Target semiconductor integrated circuit, 400 ... Characteristic monitoring circuit, 500 ... Encoding circuit, 600 ... DC / DC converter
  • FIG. 1 is a flowchart for explaining an outline of a power supply voltage determination method for a semiconductor integrated circuit according to an embodiment of the present invention.
  • FIG. 2 is a flowchart for explaining the outline of the power supply voltage determination method for the semiconductor integrated circuit according to the embodiment of the present invention subsequent to FIG. 1 and 2, the characteristic monitor circuit design data and the encoder circuit design data used when determining the power supply voltage of the semiconductor integrated circuit according to the present embodiment are created.
  • the cell library includes a plurality of macro cells (functional blocks (basic circuits)), SPICE models, logic functions, and electrical characteristics necessary for designing a semiconductor integrated circuit provided by a semiconductor manufacturer.
  • the process variation information includes information on random variation and information on systematic variation when the semiconductor integrated circuit is manufactured.
  • the systematic variation refers to a reproducible variation that correlates with the position and layout pattern of the transistor, or the characteristics and manufacturing conditions of the manufacturing apparatus.
  • the exposure pattern variation due to the exposure apparatus CMP (Chemical Mechanical)
  • Random variation refers to variation that occurs regardless of systematic variation, and includes, for example, variation in threshold voltage due to variation in impurity concentration.
  • the characterization process uses a SAP (Stochastic Analysis Process) technique to analyze the dependency on the characteristic variation factor of the macro cell included in the cell library, and to calculate the characteristic variation model of the cell library. It is a process to generate.
  • SAP Stochastic Analysis Process
  • the dependence of the delay time of the cell and the power consumption on the device parameters is calculated by executing a delay simulation process based on a transistor constituting the cell.
  • the characteristic variation factor is, for example, the transistor gate length, threshold voltage, gate width, gate oxide film thickness, diffusion resistance, wiring resistance, wiring capacitance, or device model (SPICE model, etc.) that varies due to systematic variation.
  • device parameters such as parameters equivalent to them, and parameters such as power supply voltage, operating temperature or substrate bias voltage given as operating conditions.
  • the characteristic variation factor fluctuates circuit operation characteristics such as delay time and power consumption.
  • step ST104 the cell library characteristic variation model generated in step ST103 is made into a database.
  • This cell library characteristic variation model is a database that stores analysis results (response surface) of dependence on each device parameter and operating conditions obtained by characterization processing for cells included in the cell library of step ST101. is there.
  • step ST105 principal component analysis (PCA) analyzes the cell library characteristic variation using a statistical method, and for each characteristic change of each cell, the device parameter that becomes the characteristic change factor is changed. Extract sensitivity and correlation.
  • the sensitivity is an index that represents the degree of influence of device parameters that are characteristics variation factors on the characteristics variation of each cell in the cell library. This sensitivity is determined based on, for example, the magnitude of the influence of device parameters on the cell delay characteristics.
  • the correlation is an index that represents the degree of contribution between device parameters that is a characteristic variation factor with respect to cell characteristic variation. For example, the correlation is large when the variation for the same device parameter shows the same tendency, and the correlation is small when the tendency is different.
  • step ST106 in the cell selection of the delay circuit, based on the result of the principal component analysis, a cell group in which the sensitivity of each device parameter is high and the correlation with other device parameters is small is included in the cell library. Select from.
  • step ST107 the delay circuit design is performed by configuring different delay circuits in which each of the selected cell groups is connected in a plurality of stages in series so that the influence of random variations can be ignored.
  • the design data of each delay circuit is created by setting the number of cell stages of each delay circuit so that the delay time difference between the delay circuits is within a measurable range.
  • the characteristic monitor circuit design data is a database for storing design data including connection information and the like of the cells constituting the delay circuit designed in step ST107.
  • step ST109 chip level timing model generation is performed for each of the target semiconductor integrated circuit and the characteristic monitor circuit (delay circuit) using the characteristic monitor circuit design data and the SAP technology.
  • characteristic variation factors such as device parameters, power supply voltage, operating temperature, etc.
  • the response surface is an approximate function of the output variable represented by the input variable created based on the sampled input variable (here, each parameter of the characteristic variation factor) and output variable (here, the delay time of the signal transmission path). It is. That is, the variation of the delay time characteristic of the circuit is expressed as a function of each parameter of the characteristic variation factor.
  • step ST110 the chip level timing model created in step ST109 is made into a database.
  • the dependence of the delay characteristics of all signal transmission paths included in each of the target semiconductor integrated circuit and the characteristic monitor circuit (delay circuit) with respect to the characteristic variation factor, that is, a response surface is stored.
  • the optimum power supply voltage map generation processing is a device parameter (for example, a delay time to be measured) of the characteristic monitor circuit (delay circuit) from the inverse function of the chip level timing model, that is, the response surface. , Gate length, threshold voltage, etc.). Then, an optimum power supply voltage that satisfies the required performance (step ST111) is obtained from the delay characteristics of the target semiconductor integrated circuit corresponding to the obtained device parameters.
  • the required performance in step ST111 is, for example, a delay characteristic to be satisfied as the specification of the target semiconductor integrated circuit.
  • step ST113 the optimum power supply voltage obtained in step ST112 is made into a database as a map.
  • the database of the optimum power supply voltage map when the output (measured delay time) of the characteristic monitor circuit (delay circuit) is changed, the delay characteristic of the target semiconductor integrated circuit satisfies the required performance (step ST111).
  • the obtained power supply voltage is stored as an optimum power supply voltage map.
  • FIG. 3 shows an example in which the optimum power supply voltage Vdd (V) obtained for the threshold voltage LVt ( ⁇ ) and the threshold voltage HVt ( ⁇ ) as device parameters is displayed as a map.
  • step ST114 polynomial conversion and logic synthesis are performed by converting the optimum power supply voltage map created in step ST113 into a polynomial using each output of the characteristic monitor circuit (delay circuit) as a variable, and performing logic synthesis on this polynomial.
  • the encoder circuit design data forms an encoder circuit that inputs each delay time output from the characteristic monitor circuit (delay circuit) as data having a predetermined number of bits and outputs an optimum power supply voltage as data having a predetermined number of bits.
  • Logic synthesis is to form a logic circuit (gate level netlist) expressed by gate connections from circuit operation specifications written in an abstract description (in this case polynomial) like a hardware description language. . That is, the synthesized logic circuit has a function of inputting a binary code group corresponding to the delay time of each delay circuit of the characteristic monitor circuit and outputting a binary code representing a differential power supply voltage.
  • step ST115 the encoder circuit design data created in step ST112 is stored in the database, and this process is terminated.
  • the characteristic monitor circuit design data and the encoder circuit design data are created using statistical analysis processing and delay simulation processing.
  • the characteristic monitor circuit delay circuit
  • An encoder circuit for calculating an optimum power supply voltage that is calculated from the output and that satisfies the required performance of the semiconductor integrated circuit can be formed.
  • FIG. 4 is a block diagram showing a schematic configuration of the power supply voltage control system 100 of the semiconductor integrated circuit.
  • FIG. 5 is a diagram showing circuit configurations of the characteristic monitor circuit 400 and the encoder circuit 500 shown in FIG.
  • FIG. 6 is a diagram showing a circuit configuration of DC / DC converter 600 shown in FIG.
  • the power supply voltage control system 100 of the semiconductor integrated circuit shown in FIG. 4 is measured by a plurality of delay circuits included in the characteristic monitor circuit 400 using the semiconductor chip 200 on which both the target semiconductor integrated circuit 300 and the characteristic monitor circuit 400 are mounted.
  • the delay characteristic is output as data of a predetermined number of bits.
  • the encoder circuit 500 receives the output of the characteristic monitor circuit 400 as an input, and outputs, as data of a predetermined number of bits, an optimum power supply voltage that satisfies the required performance of the delay characteristics of all signal transmission paths included in the target semiconductor integrated circuit 300. .
  • the DC / DC converter (power supply voltage control circuit) 600 adjusts the power supply voltage value according to the output of the encoder circuit 500 and determines the power supply voltage to be applied to the semiconductor chip 200.
  • the target semiconductor integrated circuit 300 and the characteristic monitor circuit 400 are mounted on the same chip. Since the target semiconductor integrated circuit 300 and the characteristic monitor circuit 400 are formed by the same manufacturing method, it is assumed that the circuit design data and the process variation information are the same.
  • the target semiconductor integrated circuit 300 includes, for example, an IC and an LSI such as a microprocessor and a gate array configured by various logic circuits, but the target semiconductor integrated circuit 300 is not particularly limited.
  • the characteristic monitor circuit 400 includes a plurality of delay circuits configured based on the characteristic monitor circuit design data stored in step ST108 with respect to the target semiconductor integrated circuit 300, and each delay signal based on the delay characteristic of each delay circuit. And a delay error between the standard delay signal and the delay error are output to the encoder circuit 500.
  • the encoder circuit 500 encodes the delay error input from the characteristic monitor circuit 400 into data having a predetermined number of bits, and outputs the encoded signal to the DC / DC converter 600.
  • the DC / DC converter 600 adjusts the power supply voltage value according to the encode signal input from the encoder circuit 500, and outputs the adjusted power supply voltage value to the semiconductor chip 200.
  • the characteristic monitor circuit 400 includes a clock generator 401, a standard delay circuit 402, a delay monitor path circuit 403, a path selector circuit 404, a delay time detector 405, a frequency divider 407, a selector circuit 408, and an address decoder 409.
  • the encoder circuit 500 is connected to the delay time detector 405 and outputs the difference between the delay values of the standard delay circuit 402 and the delay monitor path circuit 403 in numerical values.
  • the clock generator 401 When the MODE signal is “L” level, the clock generator 401 is in a delay operation mode in which a clock signal is output to the standard delay circuit 402 and the delay monitor path circuit 403. When the MODE signal is “H” level, A clock oscillation operation mode in which a clock signal is output to the frequency divider 407 is set. Further, when the R / B signal is “H” level, the clock generator 401 is in a state of stopping operation (sleep mode), and when the R / B signal is “L” level, the clock generator 401 is in operation state (active mode). It becomes.
  • the clock generator 401 When the clock generator 401 enters the delay operation mode by the MODE signal and enters the active mode by the R / B signal, the clock generator 401 generates a predetermined clock signal according to the reference clock signal CLK, and the clock signal is delayed by the standard delay circuit 402 and the delay. Output to the monitor path circuit 403. In addition, when the clock generator 401 enters the clock oscillation operation mode by the MODE signal and enters the active mode by the R / B signal, the clock generator 401 oscillates a predetermined clock signal according to the reference clock signal CLK and supplies it to the frequency divider 407. Output.
  • the standard delay circuit 402 is a delay circuit designed including the standard delay element of the target semiconductor integrated circuit 300 based on, for example, a delay margin designed according to the specifications of the target semiconductor integrated circuit 300.
  • the standard delay circuit 402 delays the clock signal input from the clock generator 401 and outputs it to the path selector circuit 404.
  • the delay monitor path circuit 403 includes a plurality of delay circuits designed based on the design data designed in the chip level timing model processing.
  • the delay monitor path circuit 403 delays the clock signal input from the clock generator 401 by the delay circuit selected by the path selector circuit 404 and outputs the delayed signal to the path selector circuit 404.
  • the address decoder 409 is, for example, a predetermined delay circuit among a plurality of delay circuits included in the standard delay circuit 402 and the delay monitor path circuit 403 connected to the path selector circuit 404 by an SEL [3: 0] address signal input from the outside.
  • a select signal for selecting the delay circuit is output to the path selector circuit 404.
  • the path selector circuit 404 selects a predetermined delay circuit among a plurality of delay circuits included in the standard delay circuit 402 and the delay monitor path circuit 403 in accordance with the select signal input from the address decoder 409.
  • the path selector circuit 404 outputs a delay signal output from the selected predetermined delay circuit to the delay time detector 405.
  • the path selector circuit 404 corresponds to the 4-bit select signal input from the address decoder 409, and includes, for example, one delay circuit of 16 different delay circuits included in the delay monitor path circuit 403. select.
  • the delay time detector 405 detects an error between delay signals output from a predetermined delay circuit in the standard delay circuit 402 and the delay monitor path circuit 403 selected by the path selector circuit 404, and encodes the detected error into an encoding circuit. Output to 500.
  • the frequency divider 407 divides the clock signal input from the clock generator 401 by a predetermined frequency dividing ratio and outputs the frequency divided signal to the selector circuit 408.
  • Encoder circuit 500 encodes an error between each delay signal input from delay time detector 405 into data having a predetermined number of bits.
  • the encoded signal is output to the outside as, for example, CDOUT [3: 0] and also output to the selector circuit 408.
  • the selector circuit 408 outputs the encode signal input from the encoder circuit 500 to the external DC / DC converter 600 as, for example, CDOUT [4] when the MODE signal is in the delay operation mode when the “L” level. To do. Further, when the MODE signal is in the clock oscillation operation mode when the MODE signal is “H” level, the selector circuit 408 uses, for example, the frequency-divided signal input from the frequency divider 407 as the frequency-divided signal Clock (f / n). Output to an external DC / DC converter 600.
  • FIG. 6 is a diagram illustrating a configuration example of the DC / DC converter 600.
  • the power supply voltage control circuit 600 shown in FIG. 6 adjusts the power supply voltage value in accordance with the combination of 4-bit data indicated by CDOUT [3: 0] input from the encoding circuit 500 and applies it to the target semiconductor integrated circuit 300. Output.
  • a DC / DC converter 600 shown in FIG. 6 includes a PWM control circuit 601 and a switching circuit 602.
  • the PWM control circuit 601 adjusts the duty ratio of the pulse signal that controls the power supply voltage Vcc according to the 4-bit data indicated by CDOUT [3: 0] input from the encode circuit 500 and outputs the adjusted signal to the switching circuit 602. .
  • the switching circuit 602 switches the power supply according to the pulse width of the pulse signal input from the PWM control circuit 601, adjusts the voltage value, and outputs the voltage value to the target semiconductor integrated circuit 300 in the semiconductor chip 200.
  • the power supply voltage value is adjusted between 1.08 V and 1.32 V in accordance with the setting of CDOUT [3: 0].
  • the target in the semiconductor chip 200 is obtained.
  • the power supply voltage applied to the semiconductor integrated circuit 300 can be optimally controlled using the delay outputs of the plurality of delay circuits included in the characteristic monitor circuit 400.
  • step ST109 specific examples of each process in step ST109, step ST111, step ST112, and step ST114 will be described below.
  • step ST109 the dependence on the characteristic variation factors such as device parameters, power supply voltage, and operating temperature included in the delay characteristics of the target semiconductor integrated circuit on which the characteristic monitor circuit is mounted and the characteristic monitor circuit (delay circuit) is obtained.
  • a standard delay model (delay matrix) in which device parameters for delay elements are set with different correlations is created.
  • An example of the created standard delay model (delay matrix) is shown below.
  • Lg, V tp , V tn ,..., Vdd are device parameters of the target semiconductor integrated circuit
  • Lg is a gate length
  • V tp is a p-channel threshold voltage
  • V tn is an n-channel threshold voltage
  • Vdd is a power supply voltage.
  • the device parameters of the target semiconductor integrated circuit are merely examples, and in addition to Lg, V tp , V tn ,..., Vdd, the gate width W, operating temperature temp, substrate bias voltage Vsubp, Vsubn, etc. may be used as device parameters. .
  • step ST111 when the variation in delay characteristics of the target semiconductor integrated circuit is the maximum value tmax , the standard delay model (delay matrix) t chip has a delay characteristic smaller than that of the target semiconductor integrated circuit.
  • This relational expression is shown below.
  • Vdd f v (Lg, V tp , V tn ,%)
  • step ST114 polynomial conversion and logic synthesis convert the optimum power supply voltage map created in step ST112 into a polynomial with each output of the characteristic monitor circuit (delay circuit) as a variable.
  • Lg, V tp , V tn ,..., Vdd are device parameters of the target semiconductor integrated circuit
  • Lg is a gate length
  • V tp is a p-channel threshold voltage
  • V tn is an n-channel threshold voltage
  • Vdd is a power supply voltage.
  • the device parameters of this semiconductor integrated circuit are an example, and in addition to Lg, V tp , V tn ,..., Gate width W, operating temperature temp, substrate bias voltage Vsubp, Vsubn, etc. may be used as device parameters.
  • Mathematical formulas (4), (5), and (6) are delay matrices that estimate the dependence between device parameters that are delay elements of the target semiconductor integrated circuit.
  • V tp f p (t m1 , t m2, ⁇ , t mn) ⁇ (8)
  • V tn f n (t m1 , t m2 ,..., T mn ) (9)
  • the device parameters that are delay elements can be converted into functions that correlate with the delay time of the delay circuit by the equations (7), (8), and (9).
  • V dd F (t m1 , t m2 ,..., T mn ) (10)
  • the power supply voltage of the target semiconductor integrated circuit can be obtained by a function correlated with the delay time of the delay circuit included in the characteristic monitor circuit 400.
  • FIG. 7 is a diagram showing an example of the cell library shown in step ST101 in FIG. 8A and 8B are diagrams showing an example of a response surface for a plurality of device parameters that cause the delay time of each cell stored in the cell library shown in step ST101 in FIG. .
  • FIG. 9 is a diagram illustrating an example of a circuit configuration of a semiconductor chip on which a characteristic monitor circuit including a delay circuit configured using cells extracted from a cell library is mounted.
  • FIG. 10 is a diagram showing an example of the chip level timing model shown in step ST110 in FIG.
  • the cell library 700 shown in FIG. 7 shows an example in which an inverter circuit INV, a NAND circuit ND2, and a NOR circuit NR2 are stored as elements constituting a semiconductor integrated circuit.
  • the gate length Lg, the threshold voltage Vtp, the threshold voltage Vtn, the power supply voltage Vdd, etc. are provided as device parameters for the delay element among the characteristic variation factors of the respective circuits. Is stored.
  • mathematical expressions representing delay characteristics using device parameters of the inverter circuit INV, NAND circuit ND2, and NOR circuit NR2 are shown below. Equation (11) represents the delay characteristic of the inverter circuit INV, Equation (12) represents the delay characteristic of the NAND circuit ND2, and Equation (13) represents the delay characteristic of the NOR circuit NR2.
  • FIG. 8A is a diagram showing, as a three-dimensional map, a response curved surface of power consumption with respect to the threshold voltage Vtp and the gate length Lg as device parameters that cause characteristic variation.
  • FIG. 8A is a diagram showing, as a three-dimensional map, a response curved surface of power consumption with respect to the threshold voltage Vtp and the gate length Lg as device parameters that cause characteristic variation.
  • FIG. 8B is a diagram showing a response surface of a delay time with respect to the power supply voltage Vdd and the temperature temp as a device parameter as a characteristic variation factor as a three-dimensional map.
  • the cell library 700 shown in FIG. 7 is an example expressing only response surfaces of delay times of the inverter circuit INV, NAND circuit ND2, and NOR circuit NR2, and illustrates response surfaces of delay times and power consumption of other cells. Is omitted.
  • the sensitivities and mutual dependencies of a plurality of device parameters that are characteristic variation factors are calculated. From the calculated sensitivity of the plurality of device parameters and the dependencies between them, a plurality of cell groups having a high sensitivity of the plurality of device parameters and having different dependencies are selected from all the cells in the cell library 700. To do.
  • a plurality of delay circuits having different delay characteristics are configured by connecting each of the selected cell groups in a plurality of stages so that the influence of random variations can be ignored.
  • the plurality of delay circuits sets the number of cell stages of each delay circuit so that the delay time or the delay time difference between the delay circuits falls within a measurable range.
  • An example of the set delay circuit is shown as a characteristic monitor circuit 1000 in FIG.
  • the characteristic monitor circuit 1000 shown in FIG. 9 is a configuration example of one delay circuit, and illustration of other delay circuits having different delay characteristics is omitted.
  • the target semiconductor integrated circuit 900 is included in the semiconductor chip 800 on which the characteristic monitor circuit 1000 shown in FIG. 9 is mounted.
  • the target semiconductor integrated circuit 900 is an example of a logic circuit including a flip-flop circuit, an inverter circuit, a NAND circuit, a NOR circuit, a wiring load (wiring resistance and wiring capacitance), and the like.
  • the target semiconductor integrated circuit 900 includes a signal transmission path (A ⁇ C) from the terminal A to the terminal C, a signal transmission path (B ⁇ C) from the terminal B to the terminal C, and a signal transmission path (from the terminal B to the terminal D) ( B ⁇ D) has three signal transmission paths.
  • the circuit configuration of the signal transmission path (A ⁇ C) is from the input stage to terminal A, wiring load R1, NAND circuit 901, wiring load R2, NOR circuit 902, wiring load R3, inverter circuit 903, wiring load R4, NAND circuit 904.
  • the wiring load R5, the NAND circuit 905, the wiring load R6, and the terminal C are connected in series.
  • the circuit configuration of the signal transmission path (B ⁇ C) is from the input stage to terminal B, wiring load R7, NOR circuit 906, wiring load R8, NOR circuit 907, wiring load R9, wiring load R10, NAND circuit 904, wiring load R5.
  • the NAND circuit 905, the wiring load R6, and the terminal C are connected in series.
  • the circuit configuration of the signal transmission path (B ⁇ D) is from the input stage to terminal B, resistor R7, NOR circuit 906, wiring load R8, NOR circuit 907, wiring load R9, NAND circuit 908, wiring load R11, NOR circuit 909.
  • the wiring load R12, the NOR circuit 910, the wiring load R13, and the terminal D are connected in series.
  • the delay circuit shown as the characteristic monitor circuit 1000 is an example of a cell selected from the cell library 700, and shows a case where the delay circuit is constituted by five stages of NAND circuits.
  • This cell is not limited to the NAND circuit, and may be replaced with another cell selected as described above.
  • the number of stages is not limited to five, and the number of stages is sufficiently large (for example, 20 stages or more) so that the influence of random variations can be eliminated, so that the delay time or the delay time difference between the delay circuits falls within a measurable range.
  • the number of cell stages may be set in.
  • wiring loads R15 to R19 are arranged between NAND circuits 1001 to 1005, respectively, and a plurality of circuits 1001 to 1005 and wiring loads R15 to R19 are alternately connected in series. .
  • step ST109 to step ST113 shown in FIG. 2 Characteristics variation factors such as device parameters, threshold voltage Vtp, threshold voltage Vtn, gate length Lg, and power supply voltage Vdd included in the delay characteristics of each signal transmission path (A ⁇ C, B ⁇ C, B ⁇ D) shown in FIG.
  • a response surface (not shown) is calculated as a dependency on.
  • the calculation result is stored as a chip level timing model 1100 shown in FIG.
  • the chip level timing model 1100 is expressed as the following formula (14), formula (15), and formula (16).
  • These formulas (14), (15), and (16) include the gate length Lg, threshold voltage Vtp, threshold voltage Vtn, power supply voltage Vdd, and the like as device parameters.
  • Expression (14) represents the delay characteristic of the signal transmission path A ⁇ C in the target semiconductor integrated circuit 900
  • Expression (15) represents the delay characteristic of the signal transmission path B ⁇ C in the target semiconductor integrated circuit 900
  • Equation (16) represents the delay characteristic of the signal transmission path B ⁇ D in the target semiconductor integrated circuit 900.
  • the optimum power supply voltage Vdd (V) represented by the above equation (17) is set to the threshold voltage LVt ( ⁇ ) and the threshold voltage HVt ( ⁇ ) which are device parameters included as characteristic variation factors. Is expressed in three dimensions.
  • the characteristic monitor circuit 1000 shown in FIG. 9 shows a configuration example of the first delay circuit.
  • a second delay circuit (not shown) having a delay characteristic different from the configuration example of the delay circuit is shown here.
  • a third delay circuit (not shown).
  • the delay elements of the first, second, and third delay circuits include threshold voltage Vtp, threshold voltage Vtn, gate length Lg, power supply voltage Vdd, and the like as device parameters as shown in the chip level timing model 1100. It is. Accordingly, the delay characteristics of the first, second, and third delay circuits are expressed as the following formula (18), formula (19), and formula (20). Equation (18) represents the delay characteristic of the first delay circuit, Equation (19) represents the delay characteristic of the second delay circuit, and Equation (20) represents the delay characteristic of the third delay circuit. .
  • Equation (21) represents an inverse function with respect to the p-channel threshold voltage Vtp
  • Equation (22) represents an inverse function with respect to the n-channel threshold voltage Vtn
  • Equation (23) represents an inverse function with respect to the gate length Lg.
  • Vdd MIN (Delay 1 , Delay 2 , Delay 3 , etc.
  • the optimum power supply voltage Vdd MIN is converted into a polynomial with the output of each delay circuit in the characteristic monitor circuit 1000 as a variable. That is, the optimum power supply voltage Vdd MIN can be obtained using the output of each delay circuit in the characteristic monitor circuit 1000 as a variable.
  • Equation (19), Equation (19), and Equation (20) physically (circuitically) as data of a predetermined number of bits will be described.
  • Equation (24) representing the optimum power supply voltage Vdd MIN is as follows. It can represent with numerical formula (25) shown to.
  • Vdd MIN (Code (Delay 1), Code (Delay 2), Code (Delay 3), 7)
  • the optimum power supply voltage Vdd MIN can be obtained by using Code (Delay 1 ), Code (Delay 2 ), and Code (Delay 3 ) represented by binary values as variables.
  • the encoder circuit is designed by logic synthesis using the above equation (25)
  • the delay time of each delay circuit output from the characteristic monitor circuit 1000 is input as data of a predetermined number of bits, and the optimum power supply voltage Vdd MIN is set to a predetermined bit.
  • the encoder circuit 500 shown in FIG. 5 for outputting as numerical data is formed.
  • the variation characteristics of the delay characteristics of the target semiconductor integrated circuit 900 are analyzed using statistical analysis processing and principal component analysis processing on the cell library of the target semiconductor integrated circuit 900. It is possible to design a characteristic monitor circuit 1000 that includes a plurality of delay circuits including device parameters and having delay characteristics in consideration of all signal transmission paths of the target semiconductor integrated circuit 900. Further, by inversely converting the mathematical expression representing the delay characteristic of each delay circuit, it is possible to convert the mathematical expression representing the delay time of the device parameter included in the delay element of each delay circuit into a mathematical expression.
  • the optimum supply voltage Vdd MIN is it possible to determine the output of the delay circuit as a variable. Furthermore, by designing the optimum supply voltage Vdd MIN is determined encoder circuit to encode the output of each delay circuit, to be capable of obtaining the delayed output of the delay circuits coded optimum supply voltage Vdd MIN as a variable Become. As a result, the circuit for obtaining the optimum power supply voltage Vdd MIN becomes a binary processing circuit, which facilitates design and processing.
  • the second embodiment is characterized in that the substrate bias voltage Vsub of the semiconductor integrated circuit is determined.
  • the second embodiment is an example in which the device parameters and the power supply voltage Vdd of the semiconductor integrated circuit described in the first embodiment are replaced with the substrate bias voltage Vsub.
  • a specific example of the cell library of the semiconductor integrated circuit shown in the above embodiment will be described, and more specific processing of the processing shown in FIGS. 1 and 2 will be described.
  • the same processing as that in the first embodiment is performed, and thus a duplicate description is omitted.
  • the cell library stores an inverter circuit INV, a NAND circuit ND2, and a NOR circuit NR2 as elements constituting a semiconductor integrated circuit.
  • the inverter circuit INV, NAND circuit ND2, and NOR circuit NR2 of this cell library the gate length Lg, the threshold voltage Vtp, the threshold voltage Vtn, the substrate bias voltage Vsub, etc. as device parameters for the delay element among the characteristic variation factors of the respective circuits. Is stored.
  • Equation (26) represents the delay characteristic of the inverter circuit INV
  • Equation (27) represents the delay characteristic of the NAND circuit ND2
  • Equation (28) represents the delay characteristic of the NOR circuit NR2.
  • each inverter circuit INV, NAND circuit ND2, and NOR circuit NR2 are analyzed statistically on a transistor basis for the inverter circuit INV, NAND circuit ND2, and NOR circuit NR2 of the cell library. Is determined as a response surface (not shown).
  • the sensitivity of a plurality of device parameters that are characteristic variation factors and the dependency between them are calculated. From the calculated sensitivity of multiple device parameters and their dependencies, select multiple cell groups with high sensitivity of multiple device parameters and different dependencies from all cells in the cell library. .
  • a plurality of delay circuits having different delay characteristics are configured by connecting each of the selected cell groups in a plurality of stages so that the influence of random variations can be ignored.
  • the plurality of delay circuits sets the number of cell stages of each delay circuit so that the delay time or the delay time difference between the delay circuits falls within a measurable range.
  • An example of the set delay circuit is shown as a characteristic monitor circuit 1000 in FIG.
  • the characteristic monitor circuit 1000 shown in FIG. 9 is a configuration example of one delay circuit, and illustration of other delay circuits having different delay characteristics is omitted.
  • the target semiconductor integrated circuit 900 is included in the semiconductor chip 800 on which the characteristic monitor circuit 1000 shown in FIG. 9 is mounted.
  • the target semiconductor integrated circuit 900 is an example of a logic circuit including a flip-flop circuit, an inverter circuit, a NAND circuit, a NOR circuit, a wiring load (wiring resistance and wiring capacitance), and the like.
  • the target semiconductor integrated circuit 900 includes a signal transmission path (A ⁇ C) from the terminal A to the terminal C, a signal transmission path (B ⁇ C) from the terminal B to the terminal C, and a signal transmission path (from the terminal B to the terminal D) ( B ⁇ D) has three signal transmission paths.
  • the circuit configuration of the signal transmission path (A ⁇ C) is from the input stage to terminal A, wiring load R1, NAND circuit 901, wiring load R2, NOR circuit 902, wiring load R3, inverter circuit 903, wiring load R4, NAND circuit 904.
  • the wiring load R5, the NAND circuit 905, the wiring load R6, and the terminal C are connected in series.
  • the circuit configuration of the signal transmission path (B ⁇ C) is from the input stage to terminal B, wiring load R7, NOR circuit 906, wiring load R8, NOR circuit 907, wiring load R9, wiring load R10, NAND circuit 904, wiring load R5.
  • the NAND circuit 905, the wiring load R6, and the terminal C are connected in series.
  • the circuit configuration of the signal transmission path (B ⁇ D) is from the input stage to terminal B, wiring load R7, NOR circuit 906, wiring load R8, NOR circuit 907, wiring load R9, NAND circuit 908, wiring load R11, NOR circuit 909.
  • the wiring load R12, the NOR circuit 910, the wiring load R13, and the terminal D are connected in series.
  • the delay circuit shown as the characteristic monitor circuit 1000 is an example of a cell selected from the cell library 700, and shows a case where the delay circuit is constituted by five stages of NAND circuits.
  • This cell is not limited to the NAND circuit, and may be replaced with another cell selected as described above.
  • the number of stages is not limited to five, and the number of stages is sufficiently large (for example, 20 stages or more) so that the influence of random variations can be eliminated, so that the delay time or the delay time difference between the delay circuits falls within a measurable range.
  • the number of cell stages may be set in.
  • wiring loads R15 to R19 are arranged between NAND circuits 1001 to 1005, respectively, and a plurality of NAND circuits 1001 to 1005 and wiring loads R15 to R19 are alternately connected in series. Yes.
  • step ST109 to step ST113 shown in FIG. 2 Variations in characteristics such as device parameters, threshold voltage Vtp, threshold voltage Vtn, gate length Lg, and substrate bias voltage Vsub included in the delay characteristics of each signal transmission path (A ⁇ C, B ⁇ C, B ⁇ D) shown in FIG.
  • a response surface (not shown) is calculated as a dependency on the factor.
  • the calculation result is stored as a chip level timing model (not shown).
  • This chip level timing model is expressed as the following formula (29), formula (30), and formula (31).
  • These mathematical formulas (29), (30), and (31) include the gate length Lg, threshold voltage Vtp, threshold voltage Vtn, substrate bias voltage Vsub, and the like as device parameters.
  • Expression (29) represents the delay characteristic of the signal transmission path A ⁇ C in the target semiconductor integrated circuit 900
  • Expression (30) represents the delay characteristic of the signal transmission path B ⁇ C in the target semiconductor integrated circuit 900
  • Equation (31) represents the delay characteristic of the signal transmission path B ⁇ D in the target semiconductor integrated circuit 900.
  • the delay characteristic which is the specification of the target semiconductor integrated circuit 900 is Delay MAX , and when this Delay MAX is given to the above formula (29), formula (30) and formula (31) as the required performance, the inverse function thereof is obtained.
  • the substrate bias voltage is expressed by the following equation (32).
  • Vsub MIN Vtp, Vtn, Lg, etc
  • the characteristic monitor circuit 1000 shown in FIG. 9 shows a configuration example of the first delay circuit.
  • a second delay circuit (not shown) having a delay characteristic different from the configuration example of the delay circuit is shown here.
  • a third delay circuit (not shown).
  • the delay elements of the first, second, and third delay circuits include device parameters such as threshold voltage Vtp, threshold voltage Vtn, gate length Lg, and substrate bias voltage Vsub as shown in the chip level timing model. It is. Therefore, the delay characteristics of the first, second, and third delay circuits are expressed as the following formula (33), formula (34), and formula (35). Equation (33) represents the delay characteristic of the first delay circuit, Equation (34) represents the delay characteristic of the second delay circuit, and Equation (35) represents the delay characteristic of the third delay circuit. .
  • Equation (36) represents an inverse function with respect to the p-channel threshold voltage Vtp
  • Equation (37) represents an inverse function with respect to the n-channel threshold voltage Vtn
  • Equation (38) represents an inverse function with respect to the gate length Lg.
  • Vtp (Delay 1 , Delay 2 , Delay 3 ,%)
  • the substrate bias voltage Vsub is converted into a polynomial with the output of each delay circuit in the characteristic monitor circuit 1000 as a variable. That is, the substrate bias voltage Vsub can be obtained using the output of each delay circuit in the characteristic monitor circuit 1000 as a variable.
  • Equation (33) representing the delay characteristics of these delay circuits.
  • An encoder circuit that outputs each delay time Delay 1 , Delay 2, and Delay 3 obtained by (34) and Equation (35) physically as a data of a predetermined number of bits will be described.
  • Equation (39) representing the substrate bias voltage Vsub is as follows: It can represent with the numerical formula (40) shown.
  • the substrate bias voltage Vsub can be obtained by using Code (Delay 1 ), Code (Delay 2 ), and Code (Delay 3 ) represented by binary values as variables.
  • the encoder circuit is designed by logic synthesis using the above equation (40)
  • the delay time of each delay circuit output from the characteristic monitor circuit 1000 is input as data of a predetermined number of bits, and the substrate bias voltage Vsub is set to the predetermined number of bits.
  • the variation characteristics of the delay characteristics of the target semiconductor integrated circuit 900 are analyzed using statistical analysis processing and principal component analysis processing on the cell library of the target semiconductor integrated circuit 900. It is possible to design a characteristic monitor circuit 1000 that includes a plurality of delay circuits including device parameters and having delay characteristics in consideration of all signal transmission paths of the target semiconductor integrated circuit 900. Further, by inversely converting the mathematical expression representing the delay characteristic of each delay circuit, it is possible to convert the mathematical expression representing the delay time of the device parameter included in the delay element of each delay circuit into a mathematical expression.
  • the substrate bias voltage Vsub can be obtained using the output of each delay circuit as a variable by performing a polynomial transformation on the mathematical formula for obtaining the substrate bias voltage Vsub using the converted device parameters. Furthermore, by designing an encoder circuit that codes the output of each delay circuit and obtains the substrate bias voltage Vsub, the delay output of each delay circuit coded with the substrate bias voltage Vsub can be obtained as a variable. As a result, the circuit for obtaining the substrate bias voltage Vsub becomes a binary processing circuit, which facilitates design and processing.

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Abstract

La présente invention se rapporte à un procédé de détermination de la tension d'alimentation d'un circuit intégré à semi-conducteur. Elle se rapporte également à un système de régulation de la tension d'alimentation d'un circuit intégré à semi-conducteur. Dans le procédé de détermination de tension d'alimentation d'un circuit intégré à semi-conducteur selon l'invention, une tension d'alimentation du circuit intégré est déterminée de la manière suivante : sur la base d'une pluralité de bibliothèques de cellules constituant le circuit intégré à semi-conducteur et d'informations d'écart de traitement, l'écart caractéristique de chaque cellule incluse dans les bibliothèques de cellules est analysé d'un point de vue statistique ; les sensibilités et la dépendance mutuelle d'une pluralité de paramètres qui provoquent l'écart caractéristique du temps de retard de chacune des cellules sont calculées ; un circuit de surveillance de caractéristique est monté et une base de données est créée, les temps de retard de tous les trajets de transmission de signaux dans le circuit intégré à semi-conducteur étant stockés dans la base de données ; une carte est créée qui indique une relation entre la pluralité de paramètres qui provoquent l'écart caractéristique et la tension d'alimentation optimale du circuit intégré à semi-conducteur ; au moyen de la fonction inverse de la surface de réponse d'une cellule constituant une pluralité de circuits à retard, la pluralité de paramètres qui provoquent l'écart caractéristique est estimée sur la base du signal de sortie du circuit de surveillance de caractéristique ; et la tension d'alimentation du circuit intégré à semi-conducteur est déterminée au moyen de la carte et de la pluralité estimée de paramètres qui provoquent l'écart caractéristique.
PCT/JP2010/054302 2010-03-15 2010-03-15 Procédé de détermination de la tension d'alimentation d'un circuit intégré à semi-conducteur et système de régulation de la tension d'alimentation d'un circuit intégré à semi-conducteur WO2011114416A1 (fr)

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JP2010510590A JPWO2011114416A1 (ja) 2010-03-15 2010-03-15 半導体集積回路の電源電圧決定方法及び半導体集積回路の電源電圧制御システム
PCT/JP2010/054302 WO2011114416A1 (fr) 2010-03-15 2010-03-15 Procédé de détermination de la tension d'alimentation d'un circuit intégré à semi-conducteur et système de régulation de la tension d'alimentation d'un circuit intégré à semi-conducteur

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216338A (ja) * 1999-01-20 2000-08-04 Sony Corp 電源電圧制御装置
JP2004246988A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置
JP2005073494A (ja) * 2003-08-26 2005-03-17 Hewlett-Packard Development Co Lp 電圧を調整するためのシステム及び方法
WO2008114416A1 (fr) * 2007-03-20 2008-09-25 Fujitsu Limited Régulateur de tension d'alimentation, support d'enregistrement et procédé de régulation de tension d'alimentation
JP2008258185A (ja) * 2007-03-30 2008-10-23 Matsushita Electric Ind Co Ltd 半導体集積回路装置、半導体集積回路の設計方法及び半導体集積回路設計装置
JP2009010344A (ja) * 2007-05-30 2009-01-15 Oki Electric Ind Co Ltd 半導体集積回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216338A (ja) * 1999-01-20 2000-08-04 Sony Corp 電源電圧制御装置
JP2004246988A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置
JP2005073494A (ja) * 2003-08-26 2005-03-17 Hewlett-Packard Development Co Lp 電圧を調整するためのシステム及び方法
WO2008114416A1 (fr) * 2007-03-20 2008-09-25 Fujitsu Limited Régulateur de tension d'alimentation, support d'enregistrement et procédé de régulation de tension d'alimentation
JP2008258185A (ja) * 2007-03-30 2008-10-23 Matsushita Electric Ind Co Ltd 半導体集積回路装置、半導体集積回路の設計方法及び半導体集積回路設計装置
JP2009010344A (ja) * 2007-05-30 2009-01-15 Oki Electric Ind Co Ltd 半導体集積回路

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