WO2011109056A1 - Amplifier offset and noise reduction in a multistage system - Google Patents

Amplifier offset and noise reduction in a multistage system Download PDF

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Publication number
WO2011109056A1
WO2011109056A1 PCT/US2010/061514 US2010061514W WO2011109056A1 WO 2011109056 A1 WO2011109056 A1 WO 2011109056A1 US 2010061514 W US2010061514 W US 2010061514W WO 2011109056 A1 WO2011109056 A1 WO 2011109056A1
Authority
WO
WIPO (PCT)
Prior art keywords
input terminal
amplifier
operational amplifier
coupled
offset voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/061514
Other languages
English (en)
French (fr)
Other versions
WO2011109056A8 (en
Inventor
Adam L. Shook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to JP2012557031A priority Critical patent/JP2013521742A/ja
Priority to CN201080064868.8A priority patent/CN102783016B/zh
Publication of WO2011109056A1 publication Critical patent/WO2011109056A1/en
Publication of WO2011109056A8 publication Critical patent/WO2011109056A8/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45586—Indexing scheme relating to differential amplifiers the IC comprising offset generating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45588—Indexing scheme relating to differential amplifiers the IC comprising offset compensating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45622—Indexing scheme relating to differential amplifiers the IC comprising a voltage generating circuit

Definitions

  • the invention relates generally to multistage amplifier system and, more particularly, to multistage amplifier system having reduced noise and offset.
  • FIG. 1 shows a conventional two-stage amplifier system 100 can be seen.
  • first stage 102 and a second stage 104 which are each generally inverting amplifiers.
  • resistor networks resistor networks (resistors Rl/Rl and resistors R3/R4) are coupled between the negative input terminals and output terminals of operational amplifiers 106 and 108, respectively, so that stage 102 can receive the input signal VIN and that stage 104 can receive output signal VOUT1.
  • offset voltage source 110 and 112 provide offset voltages VOSl and VOS2 to operational amplifiers 106 and 108, respectively.
  • Each of the voltage sources 110 and 112 (which include the internal offsets of amplifiers 106 and 108) are also coupled to supply rail 114 (which is generally at ground).
  • output signal VOUT1 can be represented as follows:
  • VOUT1 (V/N - VOSl) + VOSl
  • output signal V0UT2 can be represented as follows:
  • VOUT2 (VOUTl -VOS2)+ VOS2
  • Equation (3) can also be expressed as a function of offset voltage VOS1 (where offset voltage VOS2 is about 0):
  • VOUT2 ⁇ 3 ⁇ 4/N +— ⁇ — + l oSl
  • VOUT2 (VOSl - VOS2) + VOS2
  • VOS 1 can be significant.
  • system 100 may require the use of trim circuit or better device matching to reduce the noise and offset contributions from offset voltage VOS1.
  • An example embodiment of the invention provides an comprising a first amplifier stage having an input terminal and an output terminal, wherein the first amplifier receives an input signal at its input terminal, and wherein the first amplifier stage includes a first offset voltage source that provide a first offset voltage to the first amplifier stage and that is coupled to a supply rail; and a second amplifier stage having an input terminal and an output terminal, wherein the input terminal of the second amplifier stage is coupled to the output terminal of the first amplifier stage, and wherein the second amplifier offset includes a second offset voltage source that provides a second offset voltage to the second amplifier stage, and wherein the second offset voltage source is coupled to the first amplifier stage so as to substantially reduce noise contribution from the first offset voltage.
  • the first and second amplifiers stages further comprise a first inverting amplifier and a second inverting amplifier, respectively.
  • the first inverting amplifier further comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the second offset voltage source is coupled to the first input terminal of the operational amplifier, and wherein the first voltage offset source is coupled to the second input terminal of the operational amplifier; and a resistor network coupled to the input terminal of the first inverting amplifier, the first input terminal of the operational amplifier, and the output terminal of the operational amplifier.
  • the resistor network further comprises a plurality of resistors coupled in series with one another.
  • the first input terminal of the operational amplifier is a negative input terminal, and wherein the second input terminal of the operational amplifier is a positive input terminal.
  • the second inverting amplifier further comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the second voltage offset source is coupled to the second input terminal of the operational amplifier; and a resistor network coupled to the output terminal of the first inverting amplifier, the first input terminal of the operational amplifier, and the output terminal of the operational amplifier.
  • the first input terminal of the operational amplifier is a negative input terminal, and wherein the second input terminal of the operational amplifier is a positive input terminal.
  • an apparatus comprising a first inverting amplifier having: a first resistor that receives an input signal; a first operational amplifier having a positive input terminal, an negative input terminal, and an output terminal, wherein the negative input terminal is coupled to the first resistor; a second resistor that is coupled between the output terminal of the first operational amplifier and the negative input terminal of the first operational amplifier; and a first offset voltage source that is coupled between the positive input terminal of the first operational amplifier and ground; and a second inverting amplifier having: a third resistor that is coupled to the output terminal of the first operational amplifier; a second operational amplifier having a negative input terminal, a positive input terminal, and an output terminal, wherein the negative input terminal of the second operational amplifier is coupled to the third resistor; a fourth resistor that is coupled between the output terminal of the second operational amplifier and the negative input terminal of second operational amplifier; and a second offset voltage source that is coupled between the positive input terminal of the second operational amplifier and the negative input terminal of the negative input terminal of the
  • FIG. 1 is an example of a conventional multistage system
  • FIG. 2 is an example of a multistage system in accordance with an example embodiment of the invention.
  • FIG. 2 illustrates a multistage system 200 in accordance with an example embodiment of the invention.
  • System 200 generally comprises amplifiers stages 202 and 204 (which are generally inverting amplifiers). When compared to system 100, system 200 has the same general components. One difference, however, is the coupled to voltage source 112 and the negative input terminal of operational amplifier 106 instead of supply rail 114. By making this change, the output voltage VOUT1 is represented as follows:
  • VOUT2 (VOUTI - (VOSl + VOS2))+ (VOSl + VOS2)
  • equation (1) is substituted into equation (6), it becomes:
  • Equation (7) can also be expressed as a function of offset voltage VOSl (where offset voltage VOS2 is about 0):
  • VOUT2 VIN + - — VOSl + VOS1
  • VOUTl - VOUT2 VOUTl +— (VOUTI - (VOSl + VOS2))- (VOSl + VOS2)
  • Equations (11) and (12) can be rewritten as follows (where the input signal VIN and offset voltage VOS2 contributions have been dropped):
  • system 200 has superior performance over system 100.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
PCT/US2010/061514 2010-03-05 2010-12-21 Amplifier offset and noise reduction in a multistage system Ceased WO2011109056A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012557031A JP2013521742A (ja) 2010-03-05 2010-12-21 マルチステージシステムにおける増幅器オフセット及びノイズ低減
CN201080064868.8A CN102783016B (zh) 2010-03-05 2010-12-21 多级系统中的放大器偏移及噪声减少

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/718,134 US7965139B1 (en) 2010-03-05 2010-03-05 Amplifier offset and noise reduction in a multistage system
US12/718,134 2010-03-05

Publications (2)

Publication Number Publication Date
WO2011109056A1 true WO2011109056A1 (en) 2011-09-09
WO2011109056A8 WO2011109056A8 (en) 2012-02-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/061514 Ceased WO2011109056A1 (en) 2010-03-05 2010-12-21 Amplifier offset and noise reduction in a multistage system

Country Status (4)

Country Link
US (1) US7965139B1 (enExample)
JP (1) JP2013521742A (enExample)
CN (1) CN102783016B (enExample)
WO (1) WO2011109056A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011130569A1 (en) * 2010-04-14 2011-10-20 Aerovironment, Inc. Ground fault interrupt circuit for electric vehicle
US9054660B1 (en) * 2014-01-10 2015-06-09 Analog Devices Global Amplifying system
US9954496B2 (en) * 2015-12-21 2018-04-24 Texas Instruments Incorporated Mitigating amplifier pop noise
CN108964616A (zh) * 2018-06-08 2018-12-07 北方电子研究院安徽有限公司 一种电容检测信号处理电路降低噪声方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663680A (en) * 1996-04-04 1997-09-02 Nordeng; Arnold E. Chopper stabilized amplifier having an additional differential amplifier stage for improved noise reduction
US20020140506A1 (en) * 2000-11-14 2002-10-03 Kobayashi Kevin Wesley Wide dynamic range transimpedance amplifier
US6507241B1 (en) * 2000-10-03 2003-01-14 International Business Machines Corporation Method and circuit for automatically correcting offset voltage

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US3899743A (en) 1974-01-07 1975-08-12 Gen Electric Biasing circuit for multistage transistor amplifiers
GB8728853D0 (en) 1987-12-10 1988-01-27 Bt & D Technologies Ltd Transimpedance pre-amplifier & receiver including pre-amplifier
EP0913926B1 (en) * 1997-10-31 2004-03-03 STMicroelectronics S.r.l. Integrated power amplifier which allows parallel connections
DE69732487D1 (de) * 1997-12-16 2005-03-17 St Microelectronics Nv Operationsverstärkeranordnung
US6329876B1 (en) * 1999-01-04 2001-12-11 Tripath Technology, Inc. Noise reduction scheme for operational amplifiers
FR2814008A1 (fr) 2000-09-12 2002-03-15 Koninkl Philips Electronics Nv Dispositif d'amplification a linearite optimisee
JP4319413B2 (ja) * 2001-04-11 2009-08-26 エヌエックスピー ビー ヴィ 演算増幅器の高デューティサイクルオフセット補償
EP1258981A1 (en) * 2001-05-18 2002-11-20 Alcatel Operational amplifier arrangement including a quiescent current control circuit
US7132882B2 (en) 2002-07-19 2006-11-07 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Amplifier having multiple offset-compensation paths and related systems and methods
JP4752509B2 (ja) * 2004-01-05 2011-08-17 日本電気株式会社 増幅器
KR100698332B1 (ko) * 2005-02-04 2007-03-23 삼성전자주식회사 이득제어 증폭기
JP4246177B2 (ja) * 2005-04-28 2009-04-02 シャープ株式会社 オフセット補正回路およびオペアンプ回路
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663680A (en) * 1996-04-04 1997-09-02 Nordeng; Arnold E. Chopper stabilized amplifier having an additional differential amplifier stage for improved noise reduction
US6507241B1 (en) * 2000-10-03 2003-01-14 International Business Machines Corporation Method and circuit for automatically correcting offset voltage
US20020140506A1 (en) * 2000-11-14 2002-10-03 Kobayashi Kevin Wesley Wide dynamic range transimpedance amplifier

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Also Published As

Publication number Publication date
CN102783016B (zh) 2015-11-25
CN102783016A (zh) 2012-11-14
JP2013521742A (ja) 2013-06-10
US7965139B1 (en) 2011-06-21
WO2011109056A8 (en) 2012-02-02

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