WO2011100906A2

WO2011100906A2 - Method and apparatus for simulating packet delay variation in current network

Info

Publication number: WO2011100906A2
Application number: PCT/CN2011/072611
Authority: WO
Inventors: 吴国强; 唐纯勇
Original assignee: 华为技术有限公司
Priority date: 2011-04-11
Filing date: 2011-04-11
Publication date: 2011-08-25
Also published as: CN102171966A; WO2011100906A3; CN102171966B

Abstract

Embodiments of the invention provide a method and an apparatus for simulating Packet Delay Variation (PDV) in a current network. The method includes: a first clock packet including a first time is transmitted, with the period of t, to a slave clock device, so that the slave clock device returns a second clock packet after receiving the first clock packet, wherein the first time is a difference value between the time for transmitting the first clock packet and a first network delay in the current network, the time when the slave clock device receives the first clock packet is a second time, and the time when the slave clock device transmits the second clock packet is a third time; after the second clock packet is received, a fourth time is transmitted to the slave clock device, so that the slave clock device adjusts, according to the first time, the second time, the third time and the fourth time, the slave clock to synchronize with a master clock, wherein the fourth time is a sum of the time when the second clock packet is received and a second network delay in the current network. The embodiments of the invention achieve simulating the PDV procedure in the current network, can perform a PDV test for the current network in a simulation environment, and achieve the feasibility validation for clock algorithms in the current network.

Description

Method and device for simulating current network packet delay jitter

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to a method and apparatus for simulating a current network packet delay jitter. Background technique

With the development of IP networks, most communication networks now implement IP transmission. Since the IP network is an asynchronous network, it is impossible to obtain a clock through the physical link of the IP network. At present, the clock synchronization of the IP clock is relatively mature. However, in the case where the intermediate network device does not support IEEE (Institute of Electrical and Electronics Engineers) 1588, it is necessary to know the IP packet delay jitter of the transmission network (Packet). Delay Variation, hereinafter referred to as: PDV), can achieve IP clock synchronization well. The PDV indicates the delay jitter of the packet leaving the transmitting end to the receiving end. The PDV reflects the network characteristics of the intermediate transmission process.

With the development of modern transmission technologies, the form of transmission network networking is becoming more and more complex. Commonly used transmission Network networking scenarios include microwave transmission networks, satellite transmission networks, WIFI, ADSL, XDSL, MCWill (Multi-Carrier Wireless Information Local Loo), and switches. The PDV characteristics of the transport network in these networking scenarios are different and complex. For example, in a microwave transmission network, a master clock on a ground base station controller communicates clock information with a base station (BTS) in other places through microwave transmission, and implements clock synchronization between the base station's slave clock and the base station controller's master clock through a clock algorithm. In the satellite transmission network, the master clock on the ground base station controller communicates the clock information with the base station in other places through satellite transmission, and realizes the clock synchronization between the slave clock of the base station and the master clock of the base station controller by the clock algorithm.

The existing technology can set up various transmission network networking in the laboratory to simulate the environment of the live network, thereby implementing PDV testing on various transmission networks to verify whether the clock algorithm adapts to the transmission characteristics of the existing network. However, due to the increasingly complex transmission network of the existing network, the cost of constructing various transmission networks in the laboratory is relatively high, and for complex transmission networks, the environment built by the laboratory may not be able to simulate the environment of the existing network, so that the test data is not accurate. Summary of the invention

Embodiments of the present invention provide a method and apparatus for simulating a current network packet delay jitter to achieve reduction

The cost of PDV testing increases the accuracy of PDV testing.

The embodiment of the invention provides a method for simulating the delay of the current network packet delay, which includes:

Transmitting, by the clock device, a first clock packet including the first time to the slave clock device, so that the slave clock device receives the first clock packet and returns a second clock packet; The difference between the time of the first clock packet and the time of the first network packet of the current network; the time when the slave clock device receives the first clock packet is the second time; the time when the slave clock device sends the second clock packet For the third moment;

After receiving the second clock packet, sending a fourth time to the slave clock device, so that the slave clock device adjusts the slave clock and the master according to the first time, the second time, the third time, and the fourth time Clock synchronization; the fourth time is a sum of a time when the second clock packet is received and a second network delay of the live network;

The first network delay of the live network and the second network delay of the live network in each period are sequentially acquired from the live network in a period of t.

The embodiment of the invention provides a device for simulating the current network packet delay jitter, which comprises:

a first sending module, configured to send a first clock packet including a first time to the slave clock device in a period of t, so that the slave clock device receives the first clock packet and returns a second clock packet; The moment is the difference between the time when the first clock packet is sent and the time delay of the first network in the live network; the time when the slave clock device receives the first clock packet is the second time; the slave clock device sends the The moment of the second clock packet is the third moment;

a second sending module, configured to send a fourth time to the slave clock device after receiving the second clock packet, so that the slave clock device is configured according to the first time, the second time, the third time, and the first The fourth time adjustment slave clock is synchronized with the master clock; the fourth time is the sum of the time when the second clock packet is received and the second network delay of the live network;

The method and device for simulating the current network packet delay jitter in the embodiment of the present invention, inserting the network delay of the existing network The main clock device and the slave clock device used in the simulation enable the PDV data of the live network to be inserted and played back in the simulated environment, thereby realizing the process of simulating the PDV of the live network, thereby enabling the existing network to be performed in the simulated environment. PDV test to verify the feasibility of the existing network clock algorithm. DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief description of the drawings to be used in the description of the embodiments will be briefly made. It is obvious that the drawings in the following description are some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in view of the drawings.

1 is a flowchart of Embodiment 1 of a method for simulating a packet delay of an existing network packet according to the present invention;

2 is a flowchart of Embodiment 2 of a method for simulating a packet delay of an existing network packet according to the present invention;

Figure 3 is a schematic diagram of network delay of the live network;

4 is a schematic diagram of Embodiment 1 of an analog network packet delay jitter device according to the present invention;

FIG. 5 is a schematic diagram of Embodiment 2 of a device for simulating a current network packet delay jitter according to the present invention. detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

FIG. 1 is a flowchart of Embodiment 1 of a method for simulating a packet delay of an existing network packet according to the present invention. As shown in FIG. 1, the method includes:

Step 101: Send a first clock packet including the first time to the slave clock device in a period of t, so that the slave clock device returns the second clock packet after receiving the first clock packet.

In order to implement the IP clock synchronization of the existing network, the embodiment of the present invention provides a method for simulating the live network PDV, that is, the embodiment of the present invention can simulate the appearance network PDV by using a simple method, and then perform PDV test according to the same to implement clock synchronization. Therefore, PDV testing can be performed on the live network without performing PDV testing on the live network or in the same scenario as the existing network in the lab. PDV test The purpose is to adapt the PDV characteristics of the transmission network through various clock algorithms, and finally ensure that the slave clock in the transmission network is synchronized with the master clock.

In this embodiment, the master clock device is used as the execution body.

The primary clock device periodically sends a first clock packet to the slave clock device, where the first clock packet includes the first time; the first time is the time when the first clock packet is sent by the master clock device. The difference between the first network delay of the live network;

After receiving the first clock packet, the clock device returns a second clock packet to the master clock device. The time when the clock device receives the first clock packet is the second time, and the time when the slave clock device sends the second clock packet is The third moment.

After receiving the first clock packet from the clock device, the difference between the second time and the first time is used as the current network delay. In this embodiment, since the master clock device directly sends the first clock packet to the slave clock device, for example, in the laboratory, the master clock device can send the first clock packet to the slave clock device through a network cable (for example, 20 cm in length). Therefore, there is almost no delay between the master clock device and the slave clock device. Therefore, the difference between the second time and the first time is equal to the first network time delay of the live network.

The first network delay of the current network is the network delay of the packet sent by the active device to the current network slave device, and the network delay obtained from the clock device is equivalent to the received packet from the device in the current network. Network latency. The active network master device may be, for example, a BSC or a BSC master control unit, and the current network slave device may be, for example, a BTS or a BTS master control unit.

The first network delay of the live network in each period and the second network delay of the live network are obtained from the existing network in order of t. The first network delay of the existing network and the second network delay of the live network can be obtained from the existing network in the period of t. The t can be a value according to an actual situation, and the embodiment of the present invention does not limit the value of t.

Step 102: After receiving the second clock packet, send a fourth time to the slave clock device, so that the slave clock device adjusts the slave clock to synchronize with the master clock according to the first time, the second time, the third time, and the fourth time.

After receiving the second clock packet, the master clock device sends a fourth time to the slave clock device. The fourth time is the sum of the time when the master clock device receives the second clock packet and the second network delay of the current network.

After receiving the fourth time packet from the clock device, the difference between the fourth time and the third time is used as the current network delay; wherein the third time is the time when the second clock packet is sent from the clock device. Real In the embodiment, since the second clock packet is directly sent from the clock device to the master clock device, for example, in the laboratory, the slave clock device can send the second clock packet to the master clock device through the network cable (for example, 20 cm in length). Therefore, there is almost no delay between the slave clock device and the master clock device, and thus, the difference between the fourth time and the third time is equal to the second network delay of the live network.

The network delay of the current network is the network delay of the packets sent from the device to the active device on the live network. The network delay obtained from the clock device is equivalent to the packet sent by the slave device in the current network. The network delay to the active network master device.

After receiving the fourth time from the clock device, the slave clock can be adjusted according to the first time, the second time, the third time, and the fourth time, so that the slave clock is synchronized with the master clock.

Specifically, the process of adjusting the slave clock to synchronize with the master clock according to the first time, the second time, the third time, and the fourth time is, for example, the following:

The slave circuit obtains the line delay D according to Equation 1, and then obtains the time deviation P between the slave clock and the master clock according to Equation 2, and then adjusts to synchronize with the master clock according to the time offset P, for example: if the time deviation P is 0.2S, then The slave clock is clocked down by 0.2 s to synchronize the slave clock with the master clock.

Where Equation 1 is: D = [ ( t2-tl ) + ( t4-t3 ) ]/2;

Equation 2 is: P = t2-tl-D; tl represents the first time, t2 represents the second time, t3 represents the third time, t4 represents the fourth time, D represents the line delay, and P represents the time deviation.

In this embodiment, the network delay of the live network is inserted into the master clock device and the slave clock device for the simulation, so that the PDV data of the live network can be inserted and played back in the simulated environment, and the process of simulating the PDV of the live network is implemented. This allows PDV testing of the live network in a simulated environment.

2 is a flowchart of Embodiment 2 of a method for simulating a packet delay of an existing network packet according to the present invention. As shown in FIG. 2, the method includes:

Step 201: Obtain PDV data of the current network, that is, obtain the first network delay of the live network and the second network delay of the live network.

For the network delay of the current network, see Figure 3, Figure 3 is a schematic diagram of the network delay of the live network. As shown in Figure 3, the BSC in the current network transmits the packet to the BTS through a complex transmission network, where the BSC is present. On the network master device, the clock in the BSC is the master clock, the BTS is the slave device on the live network, and the clock in the BTS is the slave clock.

As shown in Figure 3, the master clock sends the tl information to the slave clock through the Sync file. After the Sync message is obtained, t2 is sent, and the slave clock sends a Delay-req message to the master clock, and the master clock sends t4 to the slave clock through the Delay-resp message. Thus, the time information of tl, t2, t3, t4 is obtained from the clock. The Delay-req packet sent from the clock to the primary clock may carry t3 or not.

Where tl is the time when the Sync message leaves the BSC; t2 is the time when the Sync message arrives at the BTS; t3 is the time when the Delay-req message leaves the BTS; t4 is the time when the Delay-req message arrives at the BSC; tl, t2, Both t3 and t4 can be accurate to nanoseconds. T2-tl is the first network delay of the existing network, and t4-t3 is the second network delay of the existing network.

Il sets the master clock and the slave clock to complete the synchronization, then the network delay Delay=[(t2-tl)+(t4-t3)]/2=[(t4-tl)-(t3-t2)]/2. It can be concluded that the network delay Delay has not been related to whether the master clock and the slave clock are completely synchronized, but only related to the accuracy of the master clock and the slave clock itself. Therefore, as long as the nanosecond precision clock and the nanosecond delay time delay value can be measured by using a counter with a nanosecond accuracy, FPGA can be used to achieve nanosecond accuracy.

Obtain the PDV data of the live network, that is, periodically obtain the Atl=t2-tl and At2=t4-t3 of the live network. Specifically, the first network delay (Atl) of the live network and the second network delay (At2) of the live network can be obtained by: parsing the BSC received by the BTS on the remote or near-end BTS maintenance station The received packet receives the first network delay of the current network and the second network delay of the current network in a period of t; wherein each network acquires a first network delay of the existing network and a second network delay of the existing network.

On the remote or near-end BTS maintenance station, the packets sent by the BSC received by the BTS are parsed, and tl, t2, t3, and t4 are obtained. For example, if the Sync packet is parsed, the tl can be learned and the Delay-resp message can be parsed. It can be known that t4, and t2 and t3 are known from the BTS, so that the first network delay of the live network and the second network delay of the live network can be obtained.

In a period, the current network may send multiple packets. According to these packets, multiple network network first network delays and multiple live network second network delays may be obtained. Then, multiple live networks may be used. The network delay and the second network delay of the plurality of existing networks respectively select one live network first network delay and one live network second network delay as the adopted values. For example: Set the Sync packet sending frequency to 128*n packets/second, where n is an integer greater than or equal to 1, with a period of 1 second; then 128*n points per 1 second, you can get 128* n the first network delay of the existing network and the second network delay of the 128*n live network, and then select the first network delay of the live network and the second network delay of the live network in the current period. There may be multiple methods for selecting one of the plurality of existing network first network delays (or the current network second network delay), for example:

The first type selects the smallest one from the plurality of existing network first network delays; the second type uses the average value of the first network delay values of all the live networks in each period as the selected current period. The first network delay of the live network; the third type, when the value of the first network delay of all the live networks in each period is removed from the maximum value and the minimum value as the first network in the current network Fourth, the 1/2 of the sum of the minimum value of the first network delay in each period and the minimum value of the first network delay is taken as the first network in the current network in the current period. The delay and the second network delay of the live network, that is, the delay in the uplink direction and the downlink direction can be considered symmetric in this method.

The method of selecting from a plurality of current network and a second network delay in the current network selection method for a first network delay ^{^:} the same mesh.

Step 202: Insert the PDV data of the live network obtained in step 201 into the simulation environment to simulate the PDV of the live network.

In a simulated environment, such as in a lab environment, insert playback of PDV data from the live network. The master clock device and the slave clock device in this embodiment may be devices in a lab environment. The insertion of the upstream and downstream directions will be specifically described below.

Upstream direction (that is, the direction in which the master clock device sends packets to the slave clock device): When the master clock device issues the sync clock packet, it times the time stamp tl ' ', tl "=tl '-Atl ; when the sync clock packet reaches the slave clock The device obtains a t2 from the clock device; at this time, the uplink delay obtained from the clock device is t2'-tl "=t2'-tl '+Atl;

Downstream direction (that is, the direction in which packets are sent from the clock device to the master clock device): When the slave clock device issues the Delay-req clock packet, it times the time stamp t3 ', where the delay-req clock packet can also be time stamped. T3,; When the Delay-req clock packet arrives at the master clock device, the master clock device obtains a t4, and then the master clock device returns a Delay- resp clock packet to the slave clock device, and times the time stamp _t 4", t4"=t4 , +At2; At this time, the downlink delay obtained from the clock device is t4,, - t3'=t4'+At2-t3'„ where tl is the time at which the Sync clock packet is transmitted for the master clock device; t2 is slave The time at which the clock device receives the Sync clock packet; t3, the time at which the Delay-req clock packet is sent from the clock device; t4, the time at which the master clock device receives the Delay-req clock packet.

Since the master clock device and the slave clock device in this embodiment can be in a laboratory environment, The network delay between the master clock device and the slave clock device is almost 0, that is, t2, -tl, 0, t4'-t3'~0, whereby the uplink delay obtained from the clock device is Atl, downlink. The delay is At2; that is, the network delay obtained from the clock device is the same as that in the live network.

When the PDV data of the live network is inserted into the playback environment in the simulation environment, the period of the clock packet sent by the master clock device and the slave clock device is the same as the period of the PDV data of the live network. That is to say, the PDV data of the live network is obtained by the period t, and the clock packet is sent in the simulation environment in the period of t, and the corresponding network delay data is inserted.

The method provided by the embodiment of the present invention can simulate the PDV characteristics of the live network in a laboratory environment, and then perform PDV testing on the master clock device and the slave clock device in the embodiment, that is, adapt to the transmission network through various clock algorithms. The PDV feature ultimately guarantees that the slave clock is synchronized with the master clock.

The method provided by the embodiment of the invention has the following effects:

It can solve the difficulties encountered in constructing various complex networks in the laboratory environment, and can also reduce the huge material cost and testing cost of constructing various complex networks;

The PDV data can be collected at the remote or near-end BTS maintenance station, and then the PDV jitter test of the clock algorithm under the complex transmission network can be realized in the laboratory environment, thereby verifying the delay of the IP clock algorithm in advance. Whether the time jitter capability meets the requirements of the live network, and does not need to wait until the clock algorithm is online to find the problem.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments. The foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

FIG. 4 is a schematic diagram of Embodiment 1 of the present invention for simulating a packet delay jitter device. As shown in FIG. 4, the device includes: a first sending module 41 and a second sending module 43.

The first sending module 41 is configured to send the first clock packet including the first time to the slave clock device in a period of t, so that the slave clock device receives the first clock packet and returns a second clock packet; The moment is the difference between the time when the first clock packet is sent and the time delay of the first network in the live network; the time when the slave clock device receives the first clock packet is the second time; the slave clock device sends the The time at which the second clock packet is described is the third time.

The second sending module 43 is configured to send the second clock packet to the slave clock device. Four times, so that the slave clock device synchronizes the slave clock with the master clock according to the first time, the second time, the third time, and the fourth time; the fourth time is the second clock packet received The sum of the time and the second network delay of the live network.

The first network delay of the live network and the second network delay of the current network in each period are sequentially obtained from the current network by using t. The first network delay of the current network is the network delay of the packet sent by the active device to the current network to receive the packet from the device. The second network delay of the current network is sent by the slave device on the live network to the current network. The network delay at which the master device receives packets.

For the working process and working principle of each module in this embodiment, refer to the description in the foregoing method embodiments, and details are not described herein again. The analog network packet delay jitter device provided in this embodiment may be included in the master clock device in the foregoing method embodiment. The simulated current network packet delay jitter device provided in this embodiment is used to implement the method shown in FIG. 1 or FIG. Method embodiment.

In this embodiment, the first sending module and the second sending module insert the network delay of the existing network into the master clock device and the slave clock device for the simulation, so that the PDV data of the live network can be inserted and played back in the simulated environment. The process of simulating the live network PDV is implemented, so that the PDV test can be performed on the live network in the simulated environment.

FIG. 5 is a schematic diagram of a second embodiment of a device for simulating a packet delay jitter in the present invention. On the basis of the embodiment shown in FIG. 4, the device may further include: The second network delay is obtained by the block 45.

The obtaining module 45 may include: a parsing unit 451 and a selecting unit 453.

The parsing unit 451 is configured to obtain at least one existing network first network delay and at least one existing network second network delay in each period by parsing the packet sent by the active network master device received by the current network.

The selecting unit 453 is configured to select the first network delay and the live network of the live network in the current period according to the at least one live network first network delay and the at least one live network second network delay in each period. The second network delay.

Further, the selecting unit 453 may include any one or more of the following subunits: a first subunit 4531, a second subunit 4533, a third subunit 4535, a fourth subunit 4537, and a fifth subunit 4539.

The first subunit 4531 is configured to delay from the at least one live network first network in each period The one with the smallest value is selected as the first network delay of the live network in the current period, and the smallest one of the at least one existing network second network delay in each period is selected as the live network in the current period. Two network delays.

The second sub-unit 4533 is configured to use the average value of the values of the first network delays of all the live networks in each period as the first network delay of the live network in the current period, and the second network of all the live networks in each period. The average value of the network delay is used as the second network delay of the live network in this period.

The third sub-unit 4535 is configured to use the average value of the values of the first network delays of all the live networks in each period as the first network delay of the live network in the current period, and the second network of all the live networks in each period. The average value of the network delay is used as the second network delay of the live network in this period.

The fourth sub-unit 4537 is configured to use the average value after removing the maximum value and the minimum value of the values of all the first network delays in the current network in each period as the first network delay of the live network in the current period, and each period is The value of the second network delay of all existing networks in the current network is the average value after the maximum value and the minimum value are removed as the second network delay of the live network in the current period.

The fifth subunit 4539 is configured to use 1/2 of the sum of the values of all the first network delays of the existing network in each period and the minimum value of the values of all the second network delays as the current period. The first network delay of the current network and the second network delay of the existing network.

Further, the second sending module 43 is specifically configured to: obtain a line delay according to Equation 1, obtain a time deviation between the slave clock and the master clock according to Equation 2, and then adjust the slave clock to synchronize with the master clock according to the time offset.

Equation 1 is: D = [ ( t2-tl ) + ( t4-t3 ) ]/2; Equation 2 is: P = t2-tl-D; where tl represents the first moment, t2 represents the second moment, t3 represents At the third moment, t4 represents the fourth moment, D represents the line delay, and P represents the time offset.

For the working process and working principle of each module and unit in this embodiment, refer to the description in the foregoing method embodiments, and details are not described herein again. The analog network packet delay jitter device provided in this embodiment is used to implement the foregoing method embodiments.

In this embodiment, the first sending module and the second sending module insert the network delay of the existing network into the master clock device and the slave clock device for the simulation, so that the PDV data of the live network can be inserted and played back in the simulated environment. The process of simulating the live network PDV is implemented, so that the PDV test can be performed on the live network in the simulated environment. The embodiment of the present invention further provides an analog network packet delay jitter system, where the system includes a slave clock device and a master clock device, where the master clock device includes any of the simulated live networks provided by the embodiment shown in FIG. 4 or FIG. Packet delay jitter device.

The simulated live network packet delay jitter system provided in this embodiment is used to implement the foregoing method embodiments. In this embodiment, the master clock device inserts the network delay of the existing network into the master clock device and the slave clock device for the simulation, so that the PDV data of the live network can be inserted and played back in the simulated environment, and the simulated live network PDV is realized. The process, which allows PDV testing of the live network in a simulated environment.

It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Rights request

A method for simulating a current network packet delay jitter, which is characterized by comprising:

The method for simulating the current network packet delay jitter according to claim 1, wherein: the first network delay of the live network is when the active network master sends a packet to the network that receives the packet from the device. Delay

The second network delay of the live network is the network delay of the packet sent by the current network slave device to the current network master device.

The method for simulating the current network packet delay jitter according to claim 2, wherein the first network delay of the live network and the second network delay of the live network are obtained by:

Acquiring at least one existing network first network delay and at least one existing network second network delay in each period by parsing the packet sent by the current network master device received by the current network from the device;

Selecting the first network delay of the live network and the second network delay of the live network in the current period according to the at least one live network first network delay and the at least one live network second network delay in each period .

The method for simulating the current network packet delay jitter according to claim 3, wherein the at least one live network first network delay and the at least one live network second according to each period Network delay, the process of selecting the first network delay of the live network and the delay of the second network of the live network in the current period, including:

Selecting the smallest one from the first network delay of the at least one live network in each period As the first network delay of the live network in the current period, the smallest one of the at least one live network second network delay in each period is selected as the second network delay of the live network in the current period; or The average value of the first network delay of all live networks in each period is taken as the first network delay of the live network in the current period, and the average value of the second network delay of all the live networks in each period is averaged. The value is used as the second network delay of the live network in this period; or

The average value of the first network delay of all live networks in each period is taken as the first network delay of the live network in the current period, and the average value of the second network delay of all the live networks in each period is averaged. The value is used as the second network delay of the live network in this period; or

The average value of all the first network delays in the current network is removed from the maximum and minimum values as the first network delay in the current network, and all the live networks in each period are second. The value of the network delay is the average value after the maximum value and the minimum value are removed as the second network delay of the live network in the current period; or

The 1/2 of the sum of the minimum value of the first network delay of all the live networks in each period and the minimum value of the values of all the second network delays is taken as the first network delay of the live network in the current period. And the second network delay of the existing network.

The method for simulating the current network packet delay jitter according to any one of claims 2-4, wherein: the active network master device is a base station controller or a base controller of a base station controller; The device is the main control unit of the base transceiver station or the base transceiver station.

The method for simulating the current network packet delay jitter according to any one of claims 1-4, wherein the slave clock device adjusts according to the first time, the second time, the third time, and the fourth time The process of synchronizing the clock from the master clock includes:

Obtaining a line delay according to Equation 1 according to Equation 1, obtaining a time deviation of the slave clock from the master clock according to Equation 2, and then adjusting synchronization with the master clock according to the time offset;

7. A device for simulating a current network packet delay jitter, characterized in that:

a first sending module, configured to send a first clock packet including a first time to the slave clock device in a period of t, so that the slave clock device receives the first clock packet and returns a second clock packet; The first time is the difference between the time when the first clock packet is sent and the first network delay of the current network; the time when the slave clock device receives the first clock packet is the second time; the slave clock device sends The moment of the second clock packet is a third moment;

The device for simulating the current network packet delay jitter according to claim 7, wherein: the first network delay of the live network is when the active network master sends a packet to the network that receives the packet from the device. Delay

The device for simulating the current network packet delay jitter according to claim 8, further comprising: obtaining the first network delay of the live network and the delay of the second network of the live network Block, the obtaining module includes:

a parsing unit, configured to: when parsing the packet sent by the current network master device received by the current network slave device, acquiring at least one existing network first network delay and at least one existing network second network in each period Delay

a selecting unit, configured to select, according to the at least one existing network first network delay and the at least one existing network second network delay in each period, the first network delay and the current network in the current period The second network delay.

The device for simulating the current network packet delay jitter according to claim 9, wherein the selecting unit comprises:

a first subunit, configured to select, from the at least one live network first network delay in each period, a value of the lowest network as the first network delay in the current network, from each period in the period Determining, in the current network, the second network delay, the one having the smallest value as the second network delay in the current network; and/or a second subunit, configured to use an average value of the values of the first network delays of all the live networks in each period as the first network delay in the current network, and all the second networks in each period. The average value of the network delay is used as the second network delay of the live network in the current period; and/or

a third sub-unit, configured to use an average value of the values of the first network delays of all the live networks in each period as the first network delay of the live network in the current period, and the second network of all the live networks in each period The average value of the network delay is used as the second network delay of the live network in the current period; and/or

The fourth sub-unit is configured to use the average value of the first network delay of all the live networks in each period after removing the maximum value and the minimum value as the first network delay of the live network in the current period, and each period is The value of the second network delay of all existing networks in the current network is the average value after the maximum value and the minimum value are removed as the second network delay in the live network in the current period; and/or

a fifth sub-unit, configured to use 1/2 of a sum of a minimum value of all the first network delays of each live network in each period and a minimum value of values of all second network delays as the current period The first network delay of the current network and the second network delay of the existing network.

The analog network packet delay jitter device according to any one of claims 7 to 10, wherein the second sending module is specifically configured to: obtain a line delay according to Equation 1, and obtain the slave according to Equation 2. a time deviation of the clock from the master clock, and then adjusting to synchronize with the master clock according to the time offset;