CN102171966B - Method and apparatus for simulating packet delay jitter in current network - Google Patents
Method and apparatus for simulating packet delay jitter in current network Download PDFInfo
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Abstract
Embodiments of the invention provide a method and an apparatus for simulating Packet Delay Variation (PDV) in a current network. The method includes: a first clock packet including a first time is transmitted, with the period of t, to a slave clock device, so that the slave clock device returns a second clock packet after receiving the first clock packet, wherein the first time is a difference value between the time for transmitting the first clock packet and a first network delay in the current network, the time when the slave clock device receives the first clock packet is a second time, and the time when the slave clock device transmits the second clock packet is a third time; after the second clock packet is received, a fourth time is transmitted to the slave clock device, so that the slave clock device adjusts, according to the first time, the second time, the third time and the fourth time, the slave clock to synchronize with a master clock, wherein the fourth time is a sum of the time when the second clock packet is received and a second network delay in the current network. The embodiments of the invention achieve simulating the PDV procedure in the current network, can perform a PDV test for the current network in a simulation environment, and achieve the feasibility validation for clock algorithms in the current network.
Description
Technical field
The embodiment of the invention relates to communication technical field, relates in particular to a kind of simulation existing network packet delay dither method and device.
Background technology
Along with the development of IP network, present most of communication network has all been realized the IP transmission.Because IP network is an asynchronous network, therefore can't obtain clock by the physical link of IP network.At present, the IP clock realizes that clock synchronous is relatively ripe, but do not support IEEE (Institute of Electrical and Electronics Engineers in intermediary network device, IEEE-USA) in 1588 the situation, need to know that (Packet DelayVariation is designated hereinafter simply as: PDV) characteristic could well realize the IP clock synchronous for the IP packet delay shake of transmission network.Wherein, PDV represents to be carved into when message leaves transmitting terminal the receiving terminal delay variation situation of the time of reception, and PDV has reacted the network characteristic of intermediate conveyor process.
Along with the development of modern transmission technology, the transmission network network construction form becomes increasingly complex.Transmission network networking scene commonly used includes microwave transmission network, satellite transmission network, WIFI, ADSL, XDSL, MCWill (Multi-Carrier Wireless Information Local Loop, multi-carrier-wave wireless information local loop), switch etc.The PDV characteristic of transmission network is different in these networking scene, and is very complicated.For example: in microwave transmission network, master clock on the ground base station controller is communicated by letter clock information by the local base station of microwave transmission and other (BTS), realize the clock synchronous from the master clock of clock and base station controller of base station by the clock algorithm; In satellite transmission network, the master clock on the ground base station controller transmits the base station communication local with other via satellite with clock information, realizes the clock synchronous from the master clock of clock and base station controller of base station by the clock algorithm.
Existing technology can be built the environment that existing network is simulated in various transmission network networkings in the laboratory, thereby realizes various transmission networks are carried out the PDV test, whether adapts to the transmission characteristic of existing network with checking clock algorithm.Yet because the existing network transmission network becomes increasingly complex, so that build the cost of various transmission networks in the laboratory higher, and for the transmission network of complexity, the environment that build in the laboratory possibly can't be simulated the environment of existing network, causes test data inaccurate.
Summary of the invention
The embodiment of the invention provides a kind of simulation existing network packet delay dither method and device, to realize reducing the cost of PDV test, improves the accuracy of PDV test.
The embodiment of the invention provides a kind of simulation existing network packet delay dither method, comprising:
Comprise first constantly the first clock bag take t as the cycle to sending from clockwork, so that describedly after clockwork receives described the first clock bag, return the second clock bag; Described first is the moment of described the first clock bag of transmission and the difference of existing network first network time delay constantly; The described moment that receives described the first clock bag from clockwork is second constantly; The described moment that sends described second clock bag from clockwork is the 3rd constantly;
After receiving described second clock bag, sent for the 4th moment to described from clockwork, so that described synchronous from clock and master clock according to described first moment, second moment, the 3rd moment and the adjustment of the 4th moment from clockwork; The described the 4th constantly for receiving the moment and existing network second network time delay sum of described second clock bag;
Described existing network first network time delay in each cycle and described existing network second network time delay are what get access to from existing network successively take t as the cycle.
The embodiment of the invention provides a kind of simulation existing network packet delay jittering device, comprising:
The first sending module is used for take t as the cycle comprising first constantly the first clock bag to sending from clockwork, so that describedly return the second clock bag after clockwork receives described the first clock bag; Described first is the moment of described the first clock bag of transmission and the difference of existing network first network time delay constantly; The described moment that receives described the first clock bag from clockwork is second constantly; The described moment that sends described second clock bag from clockwork is the 3rd constantly;
The second sending module for after receiving described second clock bag, sent for the 4th moment to described from clockwork, so that described synchronous from clock and master clock according to described first moment, second moment, the 3rd moment and the adjustment of the 4th moment from clockwork; The described the 4th constantly for receiving the moment and existing network second network time delay sum of described second clock bag;
Described existing network first network time delay in each cycle and described existing network second network time delay are what get access to from existing network successively take t as the cycle.
Simulation existing network packet delay dither method and the device of the embodiment of the invention, the network delay of existing network is inserted for the clock equipment of simulation with from clockwork, so that the PDV data of existing network can be inserted playback in the environment of simulation, realized the process of simulation existing network PDV, can in the environment of simulation, carry out the PDV test to existing network thus, to realize the feasibility checking of existing network clock algorithm.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use was done a simply introduction during the below will describe embodiment, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flow chart that the present invention simulates existing network packet delay dither method embodiment one;
Fig. 2 is the flow chart that the present invention simulates existing network packet delay dither method embodiment two;
Fig. 3 is the schematic diagram of the network delay of existing network;
Fig. 4 is the schematic diagram that the present invention simulates existing network packet delay jittering device embodiment one;
Fig. 5 is the schematic diagram that the present invention simulates existing network packet delay jittering device embodiment two.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Fig. 1 is the flow chart that the present invention simulates existing network packet delay dither method embodiment one, and as shown in Figure 1, the method comprises:
In order to realize the IP clock synchronous of existing network, the embodiment of the invention provides the method for simulation existing network PDV, and namely the embodiment of the invention can adopt simple method to simulate existing network PDV, then carries out accordingly the PDV test, to realize clock synchronous.Carry out the PDV test so that need not the scene of existing network thus, also need not to build the scene the same with existing network in the laboratory, just can carry out the PDV test to existing network.The purpose of PDV test is the PDV characteristic that adapts to transmission network by various clock algorithms, finally guarantees in the transmission network synchronous from clock and master clock.
Present embodiment is take clock equipment as executive agent.
Clock equipment periodically to send the first clock bag from clockwork, wherein comprises first constantly take t as the cycle in this first clock bag; This first moment sends the moment of this first clock bag and the difference of existing network first network time delay for clock equipment;
After receiving the first clock bag from clockwork, return the second clock bag to clock equipment; Wherein, the moment that receives the first clock bag from clockwork was second moment, and the moment that sends the second clock bag from clockwork was the 3rd moment.
After receiving the first clock bag from clockwork, with second constantly and the difference in first moment as this network delay.In the present embodiment, because clock equipment directly sends to the first clock bag from clockwork, for example in the laboratory, clock equipment can send to the first clock bag from clockwork by netting twine (for example length is 20 centimetres), so clock equipment and from almost there not being time delay between the clockwork, thus, the difference in second moment and first moment equals existing network first network time delay.
Wherein, existing network first network time delay is that the existing network main equipment sends message receives message to existing network from equipment network delay, and the network delay that obtains from clockwork thus is equivalent to receive from equipment the existing network network delay of message.The existing network main equipment for example can be the main control unit of BSC or BSC, and existing network for example can be the main control unit of BTS or BTS from equipment.
Existing network first network time delay in each cycle and existing network second network time delay are what get access to from existing network successively take t as the cycle.Can take t as the cycle, from existing network, get access to a plurality of existing network first network time delays and existing network second network time delay.Wherein, described t can be according to the actual conditions value, and the embodiment of the invention does not limit the value of t.
Behind step 102, the reception second clock bag, to sending the 4th from clockwork constantly, so that adjust synchronous from clock and master clock from clockwork according to first moment, second moment, the 3rd moment and the 4th moment.
After clock equipment receives the second clock bag, to sending the 4th from clockwork constantly; Wherein the 4th moment received the moment and existing network second network time delay sum of second clock bag for clock equipment.
Receive the 4th constantly behind the bag from clockwork, with the 4th constantly and the difference in the 3rd moment as this network delay; Wherein, the 3rd constantly is the moment that sends the second clock bag from clockwork.In the present embodiment, owing to directly the second clock bag is sent to clock equipment from clockwork, for example in the laboratory, can the second clock bag be sent to clock equipment by netting twine (for example length is 20 centimetres) from clockwork, so almost do not have time delay between clockwork and the clock equipment, thus, the difference in the 4th moment and the 3rd moment equals existing network second network time delay.
Wherein, existing network second network time delay is that existing network sends message to the network delay of existing network main equipment reception message from equipment, and the network delay that obtains from clockwork thus is equivalent to send message to the network delay of existing network main equipment from equipment the existing network.
From clockwork receive the 4th constantly after, can be according to first constantly, second constantly, the 3rd constantly and the 4th constantly, use the clock algorithm to adjust from clock, so that synchronous from clock and master clock.
Concrete, from clockwork according to first constantly, second constantly, the 3rd constantly and the 4th constantly adjust from the synchronous process of clock and master clock for example can for:
Obtain the circuit time delay D from clock according to formula 1, obtain from the time deviation P of clock and master clock according to formula 2 afterwards, and then adjust with master clock according to time deviation P synchronous, for example: be 0.2S if obtain time deviation P, then will slow down 0.2S from clock, so that synchronous from clock and master clock.
Wherein, formula 1 is: D=[(t2-t1)+(t4-t3)]/2;
Formula 2 is: P=t2-t1-D; T1 represents first constantly, and t2 represents second constantly, and t3 represents the 3rd constantly, and t4 represents the 4th constantly, and D represents the circuit time delay, and P represents time deviation.
In the present embodiment, the network delay of existing network is inserted for the clock equipment of simulation with from clockwork, so that the PDV data of existing network can be inserted playback in the environment of simulation, realized the process of simulation existing network PDV, can in the environment of simulation, carry out the PDV test to existing network thus.
Fig. 2 is the flow chart that the present invention simulates existing network packet delay dither method embodiment two, and as shown in Figure 2, the method comprises:
The network delay of existing network can be referring to Fig. 3, and Fig. 3 is the schematic diagram of the network delay of existing network; As shown in Figure 3, the BSC in the existing network by complicated transmission network with message transmissions to BTS, wherein BSC is the existing network main equipment, the clock among the BSC is master clock, BTS be existing network from equipment, the clock among the BTS is from clock.
As shown in Figure 3, master clock sends to t1 information from clock by the Sync message, obtains t2 after clock is received the Sync message, from the time clockwise master clock send the Delay_req message, master clock is issued t4 from clock by the Delay_resp message again.Thus, just obtained t1 from clock, t2, t3, the temporal information of t4.Wherein, from the time clockwise master clock Delay_req message that sends, can carry t3, also can not carry t3.
Wherein, t1 is the moment that the Sync message leaves BSC; T2 is the moment that the Sync message arrives BTS; T3 is the moment that the Delay_req message leaves BTS; T4 is the moment that the Delay_req message arrives BSC; T1, t2, t3, t4 all can be as accurate as nanosecond.T2-t1 is described existing network first network time delay, and t4-t3 is described existing network second network time delay.
Suppose master clock and from the clock Complete Synchronization, so network delay Delay=[(t2-t1)+(t4-t3)]/2=[(t4-t1)-(t3-t2)]/2.Can draw thus, network delay Delay with master clock and from clock whether Complete Synchronization it doesn't matter, and only with master clock and relevant from the precision of clock own.So can realize the measurement of the time delay time D elay value of the precision clock of nanosecond and nanosecond can realizing the nanosecond precision with FPGA as long as service precision is the counter of nanosecond.
Obtain the PDV data of existing network, be the Δ t1=t2-t1 that periodically obtains existing network, Δ t2=t4-t3.
Concrete, can obtain in the following manner existing network first network time delay (Δ t1) and described existing network second network time delay (Δ t2): on the BTS of far-end or near-end maintenance console, message by the BSC that resolves the BTS reception sends obtains existing network first network time delay and existing network second network time delay take t as the cycle; Wherein obtain an existing network first network time delay and an existing network second network time delay in each cycle.
On the BTS of far-end or near-end maintenance console, resolve the message of the BSC transmission of BTS reception, can know t1, t2, t3 and t4; For example, resolve the Sync message, namely can know t1, resolve the Delay_resp message and can know t4, and t2 and t3 can be known from BTS, just can obtain thus existing network first network time delay and existing network second network time delay.
In one-period, existing network may send a plurality of messages, according to these messages, can obtain a plurality of existing network first network time delays and a plurality of existing network second network time delay; Then an existing network first network time delay is chosen respectively and an existing network second network time delay is used as adopted value in the Yanzhong in the time of can be from a plurality of existing network first network time delays and a plurality of existing network second network.For example: with the Sync message give out a contract for a project set of frequency be 128*n bag/second, wherein n is the integer more than or equal to 1, take 1 second as one-period; 128*n point arranged in so per 1 second, namely can obtain 128*n existing network first network time delay and 128*n existing network second network time delay, then therefrom choose existing network first network time delay and existing network second network time delay in this cycle.
From a plurality of existing network first network time delays (or existing network second network time delay), choose one method can have multiple, for example:
The first, of numerical value minimum is chosen in the Yanzhong during from a plurality of existing network first network; The second, with the mean value of the numerical value of all the existing network first network time delays in each cycle as the existing network first network time delay in this cycle of choosing; The third removes mean value after maximum and the minimum value as the existing network first network time delay in this cycle with the numerical value of all the existing network first network time delays in each cycle; The 4th kind, with the minimum value sum of the numerical value of the minimum value of the numerical value of the first network time delay in each cycle and first network time delay 1/2 simultaneously as the existing network first network time delay in this cycle and existing network second network time delay, can think in this kind method that namely the time delay of up direction and down direction is symmetrical.
To choose one method identical with the method for choosing existing network first network time delay in the Yanzhong during from a plurality of existing network second network.
In simulated environment, for example in laboratory environment, insert the PDV data of playback existing network.Clock equipment in the present embodiment and can be the equipment the laboratory environment from clockwork.The below specifically describes the insertion of uplink and downlink direction.
Up direction (being that clock equipment is to the direction that sends message from clockwork): clock equipment is stamped timestamp t1 when sending sync clock bag ", t1 "=t1 '-Δ t1; When sync clock bag arrives from clockwork, obtain a t2 ' from clockwork; At this moment, the uplink time delay that obtains from clockwork is t2 '-t1 "=t2 '-t1 '+Δ t1;
Down direction (namely sending the direction of message from clockwork to clock equipment): when sending Delay_req clock bag, stamp timestamp t3 ' from clockwork, wherein, also can not beat timestamp t3 ' in the Delay_req clock bag; When Delay_req clock bag arrived clock equipment, clock equipment obtained a t4 ', and then clock equipment is to returning Delay_resp clock bag from clockwork, and stamps timestamp t4 ", t4 "=t4 '+Δ t2; At this moment, the descending time delay that obtains from clockwork is t4 "-t3 '=t4 '+Δ t2-t3 '.
Wherein, t1 ' sends the moment of Sync clock bag for clock equipment; T2 ' is for receiving the moment of Sync clock bag from clockwork; T3 ' is the moment that sends Delay_req clock bag from clockwork; T4 ' receives the moment of Delay_req clock bag for clock equipment.
Because the clock equipment in the present embodiment and can be the laboratory environment from clockwork, so be almost 0 in clock equipment with from the network delay between the clockwork, be t2 '-t1 ' ≈ 0, t4 '-t3 ' ≈ 0, thus, the uplink time delay that obtains from clockwork is Δ t1, and descending time delay is Δ t2; Identical the network delay that namely obtains from clockwork and the existing network.
When the PDV data of existing network were inserted playback in simulated environment, clock equipment was identical with the cycle of the PDV data of existing network with the cycle from clockwork tranmitting data register bag.That is to say that the PDV data of existing network get access to take t as the cycle, then in simulated environment take t as cycle tranmitting data register bag, and insert corresponding network delay data.
The method that the embodiment of the invention provides, can in the environment in laboratory, simulate the PDV characteristic of existing network, then carry out the PDV test to the clock equipment in the present embodiment with from clockwork, the PDV characteristic that namely adapts to transmission network by various clock algorithms, final assurance is synchronous from clock and master clock.
The method that the embodiment of the invention provides has following effect:
Can solve to have now and under laboratory environment, build the difficulty that various complicated networkings run into, can also reduce huge Material Cost and the testing cost of building various complicated networkings;
Can realize the PDV data acquisition at the BTS of far-end or near-end maintenance console, then under laboratory environment, just can realize the clock algorithm PDV jitter test under the complicated transmission group net, whether the anti-delay jitter ability that can verify in advance thus IP clock algorithm satisfies the existing network requirement, and need not by the time just to pinpoint the problems after this clock algorithm online.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; Aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
Fig. 4 is the schematic diagram that the present invention simulates existing network packet delay jittering device embodiment one, and as shown in Figure 4, this device comprises: the first sending module 41 and the second sending module 43.
The first sending module 41 is used for take t as the cycle comprising first constantly the first clock bag to sending from clockwork, so that describedly return the second clock bag after clockwork receives described the first clock bag; Described first is the moment of described the first clock bag of transmission and the difference of existing network first network time delay constantly; The described moment that receives described the first clock bag from clockwork is second constantly; The described moment that sends described second clock bag from clockwork is the 3rd constantly.
The second sending module 43 sends four moment to described from clockwork for after receiving described second clock bag, so that described synchronous from clock and master clock according to described first moment, second moment, the 3rd moment and the adjustment of the 4th moment from clockwork; The described the 4th constantly for receiving the moment and existing network second network time delay sum of described second clock bag.
Wherein, the described existing network first network time delay in each cycle and described existing network second network time delay are what get access to from existing network successively take t as the cycle.Existing network first network time delay is that the existing network main equipment sends message receives message to existing network from equipment network delay; Existing network second network time delay is that described existing network sends message receives message to described existing network main equipment network delay from equipment.
The workflow of modules and operation principle do not repeat them here referring to the description in above-mentioned each embodiment of the method in the present embodiment.The simulation existing network packet delay jittering device that present embodiment provides can be included in the clock equipment among the said method embodiment, and the simulation existing network packet delay jittering device that present embodiment provides is used for realizing Fig. 1 or embodiment of the method shown in Figure 2.
In the present embodiment, the first sending module and the second sending module insert the network delay of existing network for the clock equipment of simulation with from clockwork, so that the PDV data of existing network can be inserted playback in the environment of simulation, realize the process of simulation existing network PDV, can in the environment of simulation, carry out the PDV test to existing network thus.
Fig. 5 is the schematic diagram that the present invention simulates existing network packet delay jittering device embodiment two, and on basis embodiment illustrated in fig. 4, this device can also comprise: the acquisition module 45 that is used for obtaining existing network first network time delay and existing network second network time delay.
Choose unit 453 and be used for according to described at least one the existing network first network time delay in each cycle and described at least one existing network second network time delay, choose existing network first network time delay and existing network second network time delay in this cycle.
Further, choose unit 453 can comprise in the following subelement any one or a plurality of: the first subelement 4531, the second subelement 4533, the 3rd subelement 4535, the 4th subelement 4537 and the 5th subelement 4539.
The Yanzhong selected of numerical value minimum as the existing network first network time delay in this cycle when the first subelement 4531 was used for described at least one existing network first network within each cycle, and the Yanzhong selects of numerical value minimum as the existing network second network time delay in this cycle during described at least one existing network second network within each cycle.
The second subelement 4533 is used for mean value with the numerical value of all the existing network first network time delays in each cycle as the existing network first network time delay in this cycle, with the mean value of the numerical value of all the existing network second network time delays in each cycle as the existing network second network time delay in this cycle.
The 3rd subelement 4535 is used for mean value with the numerical value of all the existing network first network time delays in each cycle as the existing network first network time delay in this cycle, with the mean value of the numerical value of all the existing network second network time delays in each cycle as the existing network second network time delay in this cycle.
The 4th subelement 4537 is used for numerical value with all the existing network first network time delays in each cycle and removes mean value after maximum and the minimum value as the existing network first network time delay in this cycle, and the numerical value of all the existing network second network time delays in each cycle is removed mean value after maximum and the minimum value as the existing network second network time delay in this cycle.
The 5th subelement 4539 is used for 1/2 while with the minimum value of the numerical value of all the existing network first network time delays in each cycle and the minimum value sum of the numerical value of all second network time delays as the existing network first network time delay in this cycle and existing network second network time delay.
Further, the second sending module 43 specifically is used for: obtain the circuit time delay according to formula 1, obtain from the time deviation of clock and master clock according to formula 2, and then synchronous from clock and master clock according to the time deviation adjustment.
Formula 1 is: D=[(t2-t1)+(t4-t3)]/2; Formula 2 is: P=t2-t1-D; Wherein, t1 represents first constantly, and t2 represents second constantly, and t3 represents the 3rd constantly, and t4 represents the 4th constantly, and D represents the circuit time delay, and P represents time deviation.
The workflow of modules and unit and operation principle do not repeat them here referring to the description in above-mentioned each embodiment of the method in the present embodiment.The simulation existing network packet delay jittering device that present embodiment provides is used for realizing above-mentioned each embodiment of the method.
In the present embodiment, the first sending module and the second sending module insert the network delay of existing network for the clock equipment of simulation with from clockwork, so that the PDV data of existing network can be inserted playback in the environment of simulation, realize the process of simulation existing network PDV, can in the environment of simulation, carry out the PDV test to existing network thus.
The embodiment of the invention also provides a kind of simulation existing network packet delay dithering system, and this system comprises that from clockwork and clock equipment wherein Fig. 4 or the arbitrary simulation existing network packet delay jittering device that provides embodiment illustrated in fig. 5 are provided this clock equipment.
The simulation existing network packet delay dithering system that present embodiment provides is used for realizing above-mentioned each embodiment of the method.
In the present embodiment, clock equipment inserts the network delay of existing network for the clock equipment of simulation with from clockwork, so that the PDV data of existing network can be inserted playback in the environment of simulation, realize the process of simulation existing network PDV, can in the environment of simulation, carry out the PDV test to existing network thus.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a simulation existing network packet delay dither method is characterized in that, comprising:
Comprise first constantly the first clock bag take t as the cycle to sending from clockwork, so that describedly after clockwork receives described the first clock bag, return the second clock bag; Described first is the moment of described the first clock bag of transmission and the difference of existing network first network time delay constantly; The described moment that receives described the first clock bag from clockwork is second constantly; The described moment that sends described second clock bag from clockwork is the 3rd constantly;
After receiving described second clock bag, sent for the 4th moment to described from clockwork, so that described synchronous from clock and master clock according to described first moment, second moment, the 3rd moment and the adjustment of the 4th moment from clockwork; The described the 4th constantly for receiving the moment and existing network second network time delay sum of described second clock bag;
Particularly, described from clockwork according to described first constantly, second constantly, the 3rd constantly and the 4th constantly adjust from the synchronous process of clock and master clock, comprising:
Describedly obtain the circuit time delay from clock according to formula 1, obtain described time deviation from clock and described master clock according to formula 2, then synchronous according to described time deviation adjustment and described master clock;
Formula 1 is: D=[(t2-t1)+(t4-t3)]/2; Formula 2 is: P=t2-t1-D; Wherein, t1 represents first constantly, and t2 represents second constantly, and t3 represents the 3rd constantly, and t4 represents the 4th constantly, and D represents the circuit time delay, and P represents time deviation;
Described existing network first network time delay in each cycle and described existing network second network time delay are what get access to from existing network successively take t as the cycle.
2. simulation existing network packet delay dither method according to claim 1 is characterized in that:
Described existing network first network time delay is that the existing network main equipment sends message receives message to existing network from equipment network delay;
Described existing network second network time delay is that described existing network sends message receives message to described existing network main equipment network delay from equipment.
3. simulation existing network packet delay dither method according to claim 2 is characterized in that, obtains in the following manner described existing network first network time delay and described existing network second network time delay:
By resolving described existing network from the message of the described existing network main equipment transmission of equipment reception, within each cycle, obtain at least one existing network first network time delay and at least one existing network second network time delay;
According to described at least one the existing network first network time delay in each cycle and described at least one existing network second network time delay, choose existing network first network time delay and existing network second network time delay in this cycle.
4. simulation existing network packet delay dither method according to claim 3, it is characterized in that, described according to described at least one the existing network first network time delay in each cycle and described at least one existing network second network time delay, existing network first network time delay in this cycle of choosing and the process of existing network second network time delay comprise:
The Yanzhong selects of numerical value minimum as the existing network first network time delay in this cycle during described at least one existing network first network within each cycle, and the Yanzhong selects of numerical value minimum as the existing network second network time delay in this cycle during described at least one existing network second network within each cycle; Perhaps
With the mean value of the numerical value of all the existing network first network time delays in each cycle as the existing network first network time delay in this cycle, with the mean value of the numerical value of all the existing network second network time delays in each cycle as the existing network second network time delay in this cycle; Perhaps
The numerical value of all the existing network first network time delays in each cycle is removed mean value after maximum and the minimum value as the existing network first network time delay in this cycle, the numerical value of all the existing network second network time delays in each cycle is removed mean value after maximum and the minimum value as the existing network second network time delay in this cycle; Perhaps
With the minimum value sum of the numerical value of the minimum value of the numerical value of all the existing network first network time delays in each cycle and all second network time delays 1/2 simultaneously as the existing network first network time delay in this cycle and existing network second network time delay.
5. arbitrary described simulation existing network packet delay dither method according to claim 2-4, it is characterized in that: described existing network main equipment is the main control unit of base station controller or base station controller; Described existing network is the main control unit of base transceiver station or base transceiver station from equipment.
6. a simulation existing network packet delay jittering device is characterized in that, comprising:
The first sending module is used for take t as the cycle comprising first constantly the first clock bag to sending from clockwork, so that describedly return the second clock bag after clockwork receives described the first clock bag; Described first is the moment of described the first clock bag of transmission and the difference of existing network first network time delay constantly; The described moment that receives described the first clock bag from clockwork is second constantly; The described moment that sends described second clock bag from clockwork is the 3rd constantly;
The second sending module for after receiving described second clock bag, sent for the 4th moment to described from clockwork, so that described synchronous from clock and master clock according to described first moment, second moment, the 3rd moment and the adjustment of the 4th moment from clockwork; The described the 4th constantly for receiving the moment and existing network second network time delay sum of described second clock bag;
Described the second sending module specifically is used for: obtains the circuit time delay according to formula 1, obtains described time deviation from clock and described master clock according to formula 2, and then synchronous according to described time deviation adjustment and described master clock;
Formula 1 is: D=[(t2-t1)+(t4-t3)]/2; Formula 2 is: P=t2-t1-D; Wherein, t1 represents first constantly, and t2 represents second constantly, and t3 represents the 3rd constantly, and t4 represents the 4th constantly, and D represents the circuit time delay, and P represents time deviation;
Described existing network first network time delay in each cycle and described existing network second network time delay are what get access to from existing network successively take t as the cycle.
7. simulation existing network packet delay jittering device according to claim 6 is characterized in that:
Described existing network first network time delay is that the existing network main equipment sends message receives message to existing network from equipment network delay;
Described existing network second network time delay is that described existing network sends message receives message to described existing network main equipment network delay from equipment.
8. simulation existing network packet delay jittering device according to claim 7 is characterized in that, comprises that also described acquisition module comprises be used to the acquisition module that obtains described existing network first network time delay and described existing network second network time delay:
Resolution unit is used for obtaining at least one existing network first network time delay and at least one existing network second network time delay by resolving described existing network from the message of the described existing network main equipment transmission of equipment reception within each cycle;
Choose the unit, be used for according to described at least one the existing network first network time delay in each cycle and described at least one existing network second network time delay, choose existing network first network time delay and existing network second network time delay in this cycle.
9. simulation existing network packet delay jittering device according to claim 8 is characterized in that the described unit of choosing comprises:
The first subelement, the Yanzhong selects of numerical value minimum as the existing network first network time delay in this cycle when being used for described at least one the existing network first network within each cycle, and the Yanzhong selects of numerical value minimum as the existing network second network time delay in this cycle during described at least one existing network second network within each cycle; And/or
The second subelement, be used for mean value with the numerical value of all the existing network first network time delays in each cycle as the existing network first network time delay in this cycle, with the mean value of the numerical value of all the existing network second network time delays in each cycle as the existing network second network time delay in this cycle; And/or
The 4th subelement, be used for numerical value with all the existing network first network time delays in each cycle and remove mean value after maximum and the minimum value as the existing network first network time delay in this cycle, the numerical value of all the existing network second network time delays in each cycle is removed mean value after maximum and the minimum value as the existing network second network time delay in this cycle; And/or
The 5th subelement is used for 1/2 while with the minimum value of the numerical value of all the existing network first network time delays in each cycle and the minimum value sum of the numerical value of all second network time delays as the existing network first network time delay in this cycle and existing network second network time delay.
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| PCT/CN2011/072611 WO2011100906A2 (en) | 2011-04-11 | 2011-04-11 | Method and apparatus for simulating packet delay variation in current network |
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| CN103580846B (en) * | 2013-08-23 | 2017-03-01 | 北京东土科技股份有限公司 | A kind of method and system across non-1588 network transmission precision interval clock messages |
| CN103986601B (en) * | 2014-05-16 | 2017-10-10 | 北京东土科技股份有限公司 | A kind of message transmissions time delay acquisition methods and device |
| CN106210708B (en) * | 2015-04-30 | 2019-02-01 | 杭州海康威视数字技术股份有限公司 | A kind of detection method and system of picture delay |
| CN106211306B (en) | 2015-04-30 | 2020-04-03 | 华为技术有限公司 | Communication network delay jitter smoothing method, device and system |
| CN110971489A (en) * | 2019-12-04 | 2020-04-07 | 盛科网络（苏州）有限公司 | Simulation test method and device for variable deflection based on simulation clock generator |
| CN116266818A (en) * | 2021-12-17 | 2023-06-20 | 中兴通讯股份有限公司 | Information measurement method and device |
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| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
| US7848242B2 (en) * | 2007-06-14 | 2010-12-07 | Agere Systems Inc. | Methods and apparatus for testing adaptive timing characteristics of packet-based timing protocol |
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| US7848242B2 (en) * | 2007-06-14 | 2010-12-07 | Agere Systems Inc. | Methods and apparatus for testing adaptive timing characteristics of packet-based timing protocol |
| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
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