WO2011089424A2

WO2011089424A2 - Electronic circuit assembly

Info

Publication number: WO2011089424A2
Application number: PCT/GB2011/050083
Authority: WO
Inventors: Sheila Hamilton; Charles Jonathan Kennett
Original assignee: T H Group Limited
Priority date: 2010-01-20
Filing date: 2011-01-19
Publication date: 2011-07-28
Also published as: WO2011089424A3; GB201000858D0

Abstract

There is herein described a method and apparatus for the assembly of electronic circuits. In particular, there is described a method and apparatus for the assembly of electronic circuits comprising positioning and maintaining a plurality of discrete electronic components in a pre-determined spatial relationship and thereafter performing a photoimaging process on a wet film of photoresist polymer.

Description

ELECTRONIC CIRCUIT ASSEMBLY

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for the assembly of electronic circuits. More particularly, the present invention relates to a method and apparatus for the assembly of electronic circuits comprising positioning and maintaining a plurality of discrete electronic components in a pre-determined spatial relationship and thereafter performing a photoimaging process on a wet film of photoresist polymer. BACKGROUND OF THE INVENTION

Printed circuits for use in electronic assembles are normally produced as printed circuit boards (PCBs), and are manufactured by applying a sequence of processing steps to a rigid substrate. The rigid substrate is typically of fibre-reinforced plastics or of non-reinforced resin (e.g. phenolic resin) and each substrate is the size of the finished circuit or a small multiple of circuits. Moreover, conventional PCB manufacture involves passing a large number of discrete, rigid assembles through a relatively complex sequence of processes.

Conventionally, electronic circuits are assembled by mounting discrete electronic components on a pre-fabricated PCB. The PCB includes conductive tracks providing all of the required electrical connections between the individual components. The circuit components may include integrated circuits and individual passive and active components. As component densities increase and circuits become more complex, it becomes increasingly difficult and/or expensive to implement the required circuit layouts using conventional PCB technology. Circuit topologies often require multiple layers of conductive tracks in order to establish all of the required connections. Multiple layers of conductors may be provided using PCB technology by laminating multiple PCB substrates, each having one layer of conductive tracks thereon. Interconnections between conductive layers in a laminated PCB of this type require the use of plated through-holes ("via-holes") extending through the laminates. There are practical limitations on the circuit densities and topologies which can be implemented in this fashion.

More recently, "sequential manufacturing" or "additive circuitry" techniques have been used for PCB manufacture, wherein multiple conductive layers are applied sequentially to a PCB substrate with layers of dielectric between successive conductive layers. These techniques avoid the need for laminating multiple substrates. Also, electrical connections are easily established between adjacent conductive layers, avoiding the need for via-holes. However, there are still limitations on the circuit densities which can be achieved.

Existing PCB technologies use a variety of methods for patterning conductive and dielectric materials, principally photo-imaging techniques and the like, which are well known to those skilled in the art and which will be described in detail herein.

In conventional PCB technologies, the PCB substrate(s) and all conductive and dielectric layers are pre-fabricated prior to the placement of the components thereon. The bare PCB also includes solder pads at the required component terminal locations. The final assembly of the components involves locating the components on the solder pads and heating the assembly to fuse the solder pads to the component terminals. Again, there are limitations on the tolerances within which solder pads can be formed and components reliably connected thereto. In addition, solder paste material is toxic and its use creates environmental and health and safety problems.

Moreover, although prior photoimaging techniques exist in the art for producing thin lines suitable for forming PCBs, many of these techniques suffer from a number of significant disadvantages. For example, many previous techniques suffer from poor resolution. Moreover, techniques which do provide high resolution usually require complex apparatus such as sophisticated laser equipment. A further problem is that previous techniques have required the use of partially cured dry films of photopolymer which are usually supported on a polyester (e.g. Mylar) film. The thickness of these dry films has a detrimental effect on the resolution and/or definition of photoimaged surfaces as this allows unwanted undercutting (i.e. light shadowing) to occur during the photoimaging process. There are also problems in adhering partially cured dry films to substrates and contamination problems which once again causes problems in the photoimaging process. Partially cured dry films are also expensive when used in large quantities. Such systems are described in US 4,888,270 and US 4,954,421 , which are incorporated herein by reference.

It is an object of at least one aspect of the present invention to obviate or mitigate at least one or more of the aforementioned problems.

It is an object of the present invention to provide improved methods and apparatus for assembling electronic circuits from discrete components. It is a yet further object of at least one aspect of the present invention to provide a cost efficient method for producing electrical circuits with high resolution and small track widths (i.e. fine lines).

It is a further object of at least one aspect of the present invention to provide a cost efficient method for producing high density electrical circuits suitable for PCBs.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided a method of assembling an electronic circuit comprising:

positioning and maintaining a plurality of discrete electronic components in a predetermined spatial relationship such that terminals of the components are exposed; and applying dielectric and conductive material to said electronic components such that said terminals are electrically connected in a pre-determined circuit topology.

The present invention therefore relates to a method of positioning and maintaining a plurality of discrete electronic components in a pre-determined spatial relationship and then applying a fabrication process to form an electronic circuit. This is in direct contrast to prior art methods wherein electronic circuits are assembled by mounting discrete electronic components on a pre-fabricated PCB which leads to manufacturing problems. The process described in the present invention is therefore fundamentally different from conventional PCB manufacture and assembly. The circuit topology in the present invention is fabricated directly in situ on top of a component array formed by electronic components, rather than being pre-fabricated prior to installation of the components thereon.

As will be described below in more detail the present invention also relates to performing a photoimaging process on a wet film of photoresist polymer once the electronic circuits have been pre-assembled.

Typically, the plurality of discrete electronic components may be positioned and maintained in a pre-determined spatial relationship using any suitable means. The plurality of discrete electronic components may therefore be arranged in a pre-set arrangement.

The plurality of discrete electronic components may be positioned and maintained in a pre-determined spatial relationship using a supporting body. For example, the supporting body may be a supporting matrix body with at least one or more or a plurality of cavities and/or recesses adapted for receiving the discrete electronic components. The discrete electronic components may therefore fit snugly within the plurality of cavities and/or recesses in the supporting body. The position of the discrete electronic components located within the cavities and/or recesses of the supporting body may therefore maintain their pre-determined position. There may be any number of electronic components.

The discrete electronic components may be of any appropriate shape.

The matrix body may be made from plastics such as polyester films.

The electronic circuit may comprise a plurality of electronic components having terminals. There may also be a plurality of dielectric layers and conductive tracks formed in layers between the dielectric layers and interconnected through the dielectric layers as required by circuit topology

The electronic circuit may further include an outer, relatively rigid layer of material overlying an outermost dielectric layer.

The formed electronic circuit may therefore reside on a matrix body which surrounds the electronic components and maintains them in a pre-determined spatial relationship such that their terminals may, for example, be substantially co-planar and exposed prior to application of dielectric layers and conductive tracks.

In particular embodiments, the electronic circuit according to the present invention may be assembled as follows. Firstly, the electronic components may be located in the matrix body, arranged as required in the final electronic circuit. Typically, the matrix body may comprise a compartmented tray, with each electronic component located in one compartment (i.e. cavities and/or recesses) of complementary size and shape. Each of the electronic components may therefore fit snugly within cavities/recesses in the matrix body. The matrix body may thus maintain the electronic components in the required spatial pre-determined relationship during subsequent processing. The terminals may project upwardly from the matrix body such that those portions of the terminals which are to be connected to the conductive tracks may be exposed and, for example, may also be substantially co-planar.

A first layer of dielectric material may be applied over the matrix body, covering the electronic components, and patterned to expose the terminals. This may be done by any of a variety of techniques, such as by using photo-imageable dielectric material, which may be analogous to techniques employed in conventional PCB technologies or as described later on. A first layer of conductive material may be applied to establish a first set of connections between the component terminals. Some circuits may only require a single layer of conductive material, but complex circuit topologies will typically require multiple layers. The conductive material may also be applied by any of a variety of techniques, which again may be adapted from existing PCB technologies. For example, the conductive material may be applied by means of standard photo-imaging techniques or as described later on. The conductive material may be in direct electrical contact with the terminals, avoiding the need for the use of solder paste or the like.

Successive layers of dielectric and conductive material may be applied in sequence to complete the required interconnections between electronic components. Existing sequential manufacturing or additive circuitry processes currently employed in conventional PCB manufacture may be adapted for this purpose.

The form of the matrix body, its manner of manufacture, and the method of locating the electronic components therein may vary. The matrix body may typically be formed of dielectric material, for example, any suitable plastics. Besides its function in arranging the electronic components for the fabrication of the electronic circuit, the matrix body may provide protection for the electronic components against the process environment (particularly against heat and corrosion) and subsequent handling and use. The matrix body may be engineered, for example, to provide mechanical protection and/or shielding against electromagnetic interference ("EMI shielding") and/or thermal management functions. The matrix body may be of composite construction, formed from a plurality of different materials having different desirable characteristics for these and other purposes.

Alternatively, if required, the matrix body may be removable after the circuit assembly is complete.

The tray formed by the matrix body may be pre-fabricated and the electronic components may be placed therein. A pre-fabricated tray of this type may typically be vacuum-formed, injection moulded, machined or cast. Alternatively, the electronic components may be arranged as required on a supporting surface and the matrix body may be formed in situ on and around the electronic components. For example, the electronic components may be placed in a jig configured to temporarily receive the component terminals in their required positions and the matrix body material vacuum- formed, moulded or cast directly onto the electronic components. The matrix body may be a contoured, relatively thin, tray-like structure. Alternatively, the matrix body may be a solid body of material (again, possibly of composite construction), encapsulating the electronic components.

In particular embodiments, components such as heat sinks may also project through the matrix body.

The matrix body may also include apertures at electronic component positions or elsewhere, if necessary.

The matrix body and/or other materials may be configured to provide the electronic circuit with any required degree of rigidity or flexibility or combinations thereof.

Where particular sub-assemblies of electronic components are used in different circuits, the electronic components of the sub-assembly may be incorporated into a primary matrix body, and a final circuit may be fabricated from one or more such subassemblies and/or additional discrete electronic components combined together in a secondary matrix body. As such, the present invention includes an assembly of electronic components incorporated into a matrix body, as well as completed circuits including such assembles. There may therefore be a plurality of matrix bodies.

According to a second aspect of the present invention, there is provided an electronic circuit fabricated in accordance with the method of the first aspect of the invention.

The formed electronic circuit may be used in the formation of PCBs.

According a third aspect of the invention, there is provided an electronic assembly comprising a plurality of discrete electronic components arranged in a matrix body in a predetermined spatial relationship such that terminals of the components are exposed and aligned so as to be substantially co-planar.

According to a fourth aspect of the present invention there is provided a method of making a printed circuit, comprising the steps of:

providing a supporting substrate;

temporarily securing a metal foil to the supporting substrate;

forming a patterned dielectric layer on the metal foil;

forming a patterned conductive layer over the dielectric layer to define desired circuit tracks;

removing the supporting substrates from the metal foil; and

selectively removing parts of the metal foil to leave a desired conductive pattern. As will be described below in more detail the present invention also relates to performing a photoimaging process on a wet film of photoresist polymer during the method of manufacture.

The method may also comprise optionally forming further dielectric and conductive patterned layers until a desired circuit topography may be attained.

Typically, the supporting substrate may be temporarily secured to the metal foil by means of a peelable adhesive.

The method may also include the further step of incorporating a rigidifying layer, most preferably before the supporting substrate is removed. The rigidifying layer may most conveniently form an outer layer, but other positions within the laminate are possible.

In particular embodiments, the supporting substrate may be a continuous, flexible web, for example of polyester film, upon which a succession of circuits may be formed in a continuous process.

The metal foil may be a continuous web of, for example, copper foil, one surface of which may be polished, and which polished surface may be contacted with the peelable adhesive.

The printed circuits may be manufactured using, for example, a continuous web of flexible polyester film as a supporting substrate.

The polyester web may be coated with an adhesive at an adhesive coating station. A continuous strip of metal foil such as copper foil may be secured to the polyester web by the adhesive. The cooper foil may be applied such that its polished side may contact the adhesive and its matt side may face outwardly.

The laminated web may then pass through at least one dielectric layer forming process, and at least one conductive layer forming process to provide a series of patterned layers, alternatively dielectric and conductive.

In particular embodiments, a first dielectric layer may be formed with gaps, a first conductive layer may be patterned to form conductive tracks. There may also be substantially upward and substantially downward contact portions, and a second dielectric layer which may be positioned over the first conductive layer and fill non- patterned portions in the first conductive layer.

There may be two, four, six, eight, ten or twelve or more dielectric layers and conductive layers, each applied by a process defined herein sequentially. The process for applying a dielectric layer may be any of the processes known in the printed circuit art. For example, the dielectric layer may be formed by applying a photoimageable material, exposing the desired pattern, and chemically stripping the unexposed material. The conductive layer may be applied by electroless plating to form a continuous layer of conductor, followed by: photosensitive etch resist, exposure of the desired pattern, etching, and removal of exposed etch resist. However, other methods of forming imaged dielectric and conductive layers may be employed, such as silk screen printing, offset-lithography, or spraying. In this regard we also refer to a specific photoimaging process which is ideally suited for the present invention. This is discussed in more detail below.

After the desired number of dielectric and conductive layers have been applied and the required photoimaging, a further layer may optionally be added to impart a desired degree of structural rigidity to the final product. This may conveniently be done by applying, for example, a web of a stiff plastics material to adhesive from an adhesive coating station.

The layered web may then be passed to a stripping station at which the polyester web, no longer required as a mechanical substrate, and the adhesive layer may be separated and discarded. For this purpose, the adhesive layer may be of an adhesive material chosen to be peelable cleanly, and to adhere more strongly to the polyester web than to the copper foil. Clean separation of the adhesive from the copper foil may be assisted by contacting the polished face of the copper foil to the adhesive.

The continuous web, with one face now consisting of continuous copper foil, may be passed to a process in which the copper may be reduced to a desired pattern of conductive tracks. This may suitably be done by photo-imaging and etching techniques.

Finally, the web may be cut to produce individual printed circuits.

In some embodiments, the use of a rigidifying layer may not be necessary. Where it is used, the rigidifying layer may be incorporated in an intermediate position in the laminate, rather than at one side.

According to a fifth aspect of the present invention, there is provided a printed circuit fabricated in accordance with the fourth aspect of the invention.

As indicated above although any type of photoimaging may be used in the different aspects of the present invention a preferred type of photoimaging is described below. The photoimaging described below may be used in any one of or combination of the photoimaging processes described in the first to the fifth aspects. The photoimaging process relates to performing photoimaging on a wet film of photoresist polymer. This is in contrast to prior art methods which photoimage dry films.

In particular, the photoimaging method may comprise:

depositing a liquid photoresist polymer to form a film of photoresist polymer with a thickness of less than about 178 μηη (0.007 inch); and

positioning a phototool onto the liquid photoresist polymer.

Typically, radiation may then be applied to the liquid photoresist polymer to cure the photoresist layer in exposed areas through the phototool.

The photoimaging method therefore relates to a method of photoimaging, for example, a substrate covered with a wet curable photopolymer (i.e. a wet resist), wherein the photoimaged substrate may be used to form electrical circuits such as PCBs and flat panel displays. The present invention may also relate to forming dielectric images on dielectrics. In contrast to many prior art photoimaging techniques, the photoimaging method therefore relates to the use of wet films rather than expensive dry films such as Mylar (Trade Mark). Dry films are considerably more expensive than the use of wet films. The use of wet films also overcomes the need for curing of the wet films and therefore leads to a very controllable process.

In the photoimaging method there is also no drying step (i.e. a pre-drying step) before the film of wet photoresist polymer is irradiated with, for example, UV radiation. This is in complete contrast to prior art techniques which dry a wet film before irradiation occurs.

The liquid photoresist polymer may be deposited onto a cladding. The cladding may be made from or comprise any appropriate material or composite and may, for example, be metallic or non-metallic.

Typically, the metal cladding may comprise or consist of conductive material.

The substrate which may, for example, be a dielectric material which may therefore be fully or at least substantially encapsulated by the metal cladding. The metal cladding may comprise or consist of conducting material such as any suitable metal material. Suitable metals may, for example, be copper, silver, gold and the like.

In embodiments where the cladding is non-metallic, the cladding may comprise or consist of dielectric material.

The substrate with the cladding may be substantially flat and may range in size up to about 1 m x 1 m. The present invention has the advantage in that there is, in effect, no size limitation on the substrate apart from the apparatus actually performing the photoimaging process.

The liquid photoresist polymer is in a wet form (i.e. in a flowable form). The physical properties of the liquid photoresist polymer may be matched to the required curing properties.

Typically, the liquid photoresist polymer may be deposited with a thickness of less than or equal to about 150 μηη, 125 μηη, 100 μηη, 75 μηη, 50 μηη, 25 μηη, 10 μηη, 5 μηη, 1 μηη, 0.5 μηη or 0.1 μηη. Alternatively, the liquid photoresist polymer may be deposited with a thickness ranging from about 177 μηη to about 0.1 μηη, about 125 μηη to about 0.1 μηη, about 100 μηη to about 0.1 μηη, about 75 μηη to about 0.1 μηη, about 50 μηη to about 0.1 μηη, about 25 μηη to about 0.1 μηη or about 10 μηη to about 0.1 μηη. Preferably, the liquid photoresist polymer may have a thickness of about 5 μηη.

By the use of thin liquid photoresist polymer films allows low intensity radiation (e.g. UV light) to be used in the photoimaging process.

The liquid photoresist polymer may be deposited in a substantially even and continuous manner using any suitable technique. For example, the liquid photoresist layer may be deposited using a spray, a brush and/or a roller system.

Prior to application of the liquid photoresist polymer, the substrate comprising the cladding may be cleaned using a contact cleaning process to remove debris and/or contamination from the surface of the cladding.

Once the liquid photoresist polymer has been applied to the substrate with the cladding, the phototool may be positioned onto the substrate. A compressive force may then be applied to the deposited liquid photoresist polymer. By applying a compressive force, the liquid photoresist polymer may be spread out and/or squeezed so that a substantially even, continuous film of photoresist may be achieved with a substantially even thickness. In particular embodiments, a roller based system may be used to apply a compressive rolling force and may therefore be used to spread the liquid photoresist polymer. Typically, a rubber cylindrical roller may be rolled over the phototool which applies the compressive to the liquid photoresist polymer. The spreading out and/or squeezing may occur on both sides of the substrate at substantially the same time. A particular function of the spreading out and/or squeezing is that this helps to ensure that substantially no air and therefore substantially no oxygen is trapped underneath the liquid photoresist polymer. It is preferred that there is no air and no oxygen trapped underneath the liquid photoresist polymer. This overcomes the need to have complex light systems and also provides significant improvements to the speed of the process as trapped oxygen slows down the photoimaging (i.e. curing) process.

A phototool may be used in the photoimaging process. The phototool may be a negative or positive image of desired electrical circuitry and may allow light to pass through some parts of the phototool but not others. The phototool may be made from flexible plastics material and may be connected to a mechanism which correctly positions the phototool on the substrate on at least one or both sides of the substrate. The phototool may be tensioned and wound around rollers such as solid steel rollers. In particular embodiments, the phototool may also comprise a protective layer which may facilitate the phototool being peeled off the substrate after the imaging has taken place. The protective layer may be any suitable non-stick material. The phototool has the further advantage in that this provides the ability to control the temperature and humidity during the photoimaging process and along the full length of the photoimaged area. This allows the temperature and humidity to be maintained at substantially constant levels which provides a very controllable process.

The radiation used may be any suitable radiation which cures the liquid photoresist polymer. In particular embodiments, UV radiation may be used to polymerise and/or harden and/or set the exposed liquid (e.g. wet) photoresist polymer. The UV radiation may have a wavelength of about 200 - 400 nm and may have an intensity matched to cure the photopolymer being used. A particularly preferred UV light source may be UV LEDs as they produce very small amounts of heat, have a long lamp life, start up immediately, have substantially no fall-off in power output, are low maintenance and can produce high levels of light intensity. LEDs may therefore be used to print fine lines in an inexpensive photoimaging process according to the present invention. An alternative light source may be a laser light source.

In particular embodiments of the present invention, the radiation may be collimated to improve the quality and/or resolution and/or definition of the photoimaging process.

The photoimaging apparatus of the present invention may be used to process about one panel of substrate about every ten seconds.

After applying the radiation of the photoimaging process, liquid photoresist polymer which has not been exposed to radiation may be removed using standard wash off processes. The method of the present invention may also be self-contained in a mini-clean room which therefore provides significant cost savings in the photoimaging process as large industrial clean rooms are not required.

Using the method as described in the present invention, high definition fine lines suitable for electrical circuitry may be obtained. The fine lines may have a width of any of the following: less than or equal to about 200 μηη; less than or equal to about 150 μηη; less than or equal to about 100 μηη; less than or equal to about 75 μηη; less than or equal to about 70 μηη; less than or equal to about 60 μηη; less than or equal to about 50 μηη; less than or equal to about 40 μηη; less than or equal to about 30 μηη; less than or equal to about 20 μηη; less than or equal to about 10 μηη; or less than or equal to about 5 μηη. Alternatively the fine lines may have a width of any of the following: greater than about 200 μηη; greater than about 150 μηη; greater than about 100 μηη; greater than about 75 μηη; greater than about 50 μηη; greater than about 20 μηη; or greater than about 10 μηη. Alternatively the fine lines may have a width of any of the following: about 0.1 - 200 μιτι; about 1 - 150 μηη; about 1 - 100 μηη; about 20 - 100 μηη or about 5 - 75 μηη. The fine lines may be used in PCBs and other electrical components such as flat screen displays.

The method of the present invention may have the added advantage in that all steps such as the deposition of the liquid photoresist polymer and the removal of the phototool may occur in a single pass through apparatus according to the present invention. For example, the depositing of a liquid photoresist polymer on at least one or both sides of the substrate, the positioning of phototool(s) over the liquid photoresist polymer on at least one or both sides of the substrate, the application of a compressive force to the deposited liquid photoresist polymer to form a film of photoresist polymer, and the application of radiation to the liquid photoresist polymer to cure the photoresist layer may all occur in a single pass through photoimaging apparatus of the present invention. This one-step process therefore increases the throughput of photoimaged substrates through the apparatus and also provides an apparatus which is easy to control and monitor.

The present invention has a number of advantages which are obtained by photoimaging through a much smaller depth in comparison to the prior art. For example, the depth formed by the thin film of photoresist polymer and optionally a protective layer for the phototool through which the photoimaging may occur may be any of the following: about 0.1 - 50 μηη; about 1 - 50 μηη; about 1 - 25 μηη; about 1 - 10 μηη; about 1 - 8 μηη or about 1 - 5 μηη. Typically, the depth formed by the thin film of photoresist polymer and optionally a protective layer for the phototool may be about 8 μηη. By having a relatively small depth through which the photoimaging occurs provides reduced undercut and allows very small line widths to be formed. The amount of undercut occurring in the present invention, may be any of the following: less than about 10 μηη; less than about 5 μηη; less than about 2 μηη; less than about 1 μηη; less than about 0.84 μηη; less than about 0.8 μηη; less than about 0.5 μηη; or less than about 0.25 μηη.

The photoimaging may also have a low power consumption due to there being no curing process required for the wet film (i.e. no pre-drying step). The apparatus may therefore be operated at low power such as less than about 10 kW or preferably less than about 5 kW. In comparison, prior art techniques operate in the region of greater than about 100 kW. The apparatus of the present invention may therefore provide about a 50 times or even about a 100 times improvement in energy consumption. The apparatus may therefore have a low environmental impact.

The photoimaging process may also produce tracks and/or electrical circuitry by: providing ink jet deposits comprising conductive particles;

depositing a liquid photoresist polymer on the ink jet deposits;

positioning a phototool onto the liquid photoresist polymer;

applying a compressive force to the deposited liquid photoresist polymer to form a film of photoresist polymer with a thickness less than about 178 μηη (0.007 inch); and applying radiation to the liquid photoresist polymer to cure the photoresist layer in exposed areas through the phototool.

Typically, the ink jet deposits may comprise conductive particles such as silver, gold and/or copper.

The ink jet deposits may have a width of about 50 μηη - 500 μηη, 50 μηη - 250 μηη, 75 μηη - 150 μηη or typically about 100 μηη. The ink jet deposits may therefore be modified using the photoimaging concept described in the present invention. For example, the ink jet deposits may be formed on a substrate of, for example, a plastics sheeting. The ink jet deposits may form an approximate required track on the plastics sheeting. Typically, at least one or multiple tracks may then be formed within the ink jet deposits using the photoimaging concept described in the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 is a schematic cross-sectional view of an electronic circuit according to an embodiment of the present invention;

Figure 2 is a schematic cross-sectional view of an electronic circuit according to a further embodiment of the present invention;

Figure 3 is a schematic cross-sectional view of an electronic circuit according to a yet further embodiment of the present invention.

Figure 4 is a schematic flow diagram illustrating one form of the method of fabrication and apparatus according to a further embodiment of the present invention;

Figure 5 is a schematic cross-sectional view of a printed circuit during the course of manufacture according to a further embodiment of the present invention; and

Figure 6 is a schematic cross-sectional view of the printed circuit of Figure 5 at a later stage of the manufacturing process according to an embodiment of the present invention;

Figure 7 is a sectional side view of a substrate with a wet photoresist layer deposited thereon according to a further embodiment of the present invention;

Figure 8 is a sectional side view of a substrate with a wet photoresist layer used in a photoimaging process according to an embodiment of the present invention;

Figures 9a and 9b are representations of an alternative photoimaging process according to a further embodiment of the present invention.

Figure 10a is a sectional view of a photoimaging process according to the prior art;

Figure 10b is a sectional view of a photoimaging process according to an embodiment of the present invention;

Figure 1 1 a is a sectional view of a photoimaging process according to the prior art showing undercut occurring;

Figure 1 1 b is a sectional view of a photoimaging process according to an embodiment of the present invention showing undercut occurring;

Figure 12a is a sectional view of a photoimaging process according to the prior art showing cured line width; and

Figure 12b is a sectional view of a photoimaging process according to an embodiment of the present invention showing cured line width. BRIEF DESCRIPTION

It should be understood that the accompanying drawings are highly schematic and merely illustrative. The invention is applicable to a wide range of types and sizes of components and terminal configurations, circuit topologies etc. The relative dimensions of components and layers have been distorted for clarity of illustration.

Figure 1 is a schematic cross-sectional view of an electronic circuit, generally designated 5, according to an embodiment of the present invention. The electronic circuit 5 shown is a portion of an electronic circuit assembled in accordance with the present invention. The circuit 5 comprises a plurality of electronic components 10 having terminals 12, a plurality of dielectric layers 14,16,18,20 and conductive tracks 22, formed in layers between the dielectric layers 14,16,18,20 and interconnected through the dielectric layers 14,16,18,20 as required by the circuit topology. The electronic circuit 5 is shown inverted, with the electronic components 10 facing downwards.

The electronic circuit 5 may further include an outer, relatively rigid layer of material 24 overlying the outermost dielectric layer 20.

As shown in Figure 1 , the electronic circuit 5 resides on a matrix body 26 which surrounds the electronic components 10 and maintains them in a pre-determined spatial relationship such that their terminals 12 may, for example, be substantially co-planar and exposed prior to application of the dielectric layers 14,16,18,20 and conductive tracks 22, as shall be described in more detail below. The matrix body 26 is made from plastics such as polyester film.

In accordance with the invention, the electronic circuit 5 may be assembled as follows.

Firstly, the electronic components 10 are located in the matrix body 26, arranged as required in the final electronic circuit 5. In this embodiment, the matrix body 26 comprises a compartmented tray, with each electronic component 10 located in one compartment of complementary size and shape. Each of the electronic components 10 therefore fit snugly within cavities/recesses in the matrix body 26. The matrix body 26 thus maintains the electronic components 10 in the required spatial pre-determined relationship during subsequent processing. The terminals 12 project upwardly from the matrix body 26 such that those portions of the terminals 12 which are to be connected to the conductive tracks 22 are exposed and substantially co-planar.

The first layer of dielectric material 14 is applied over the matrix body 26, covering the electronic components 10, and patterned to expose the terminals 12. This may be done by any of a variety of techniques, such as by using photo-imageable dielectric material, which may be analogous to techniques employed in conventional PCB technologies or as described later on.

A first layer of conductive material 22 is applied to establish a first set of connections between the component terminals 12. Some circuits may only require a single layer of conductive material 22, but complex circuit topologies will typically require multiple layers. The conductive material 22 may also be applied by any of a variety of techniques, which again may be adapted from existing PCB technologies. For example, the conductive material 22 may be applied by means of photo-imaging techniques or as described later on. The conductive material 22 is in direct electrical contact with the terminals 12, avoiding the need for the use of solder paste or the like.

Successive layers of dielectric and conductive material are applied in sequence to complete the required interconnections between electronic components 10. Existing sequential manufacturing or additive circuitry processes currently employed in conventional PCB manufacture may be adapted for this purpose.

This process is fundamentally different from conventional PCB manufacture and assembly. The circuit topology is fabricated directly in situ on top of a component array formed by the electronic components 10, rather than being pre-fabricated prior to installation of the components thereon.

The form of the matrix body 26, its manner of manufacture, and the method of locating the components 1 10 therein may vary. The matrix body 26 will typically be formed of dielectric material, for example, any suitable plastics. Besides its function in arranging the electronic components 10 for the fabrication of the electronic circuit 5, the matrix body 26 may provide protection for the components against the process environment (particularly against heat and corrosion) and subsequent handling and use. The matrix body 26 may be engineered, for example, to provide mechanical protection and/or shielding against electromagnetic interference ("EMI shielding") and/or thermal management functions. The matrix body 26 may be of composite construction, formed from a plurality of different materials having different desirable characteristics for these and other purposes.

Alternatively, if required, the matrix body 26 could be removable after the circuit assembly is complete.

In Figure 1 , the tray formed by the matrix body 26 could be pre-fabricated and the electronic components 10 placed therein (e.g. using "pick-and-place" apparatus of the type used in PCB assembly). A pre-fabricated tray of this type would typically be vacuum-formed, injected moulded, machined or cast. Alternatively, the electronic components 10 could be arranged as required on a supporting surface and the matrix body 26 formed in situ on and around the electronic components 10. For example, the electronic components 10 could be placed in a jig configured to temporarily receive the component terminals 12 in their required positions and the matrix body material vacuum- formed, moulded or cast directly onto the electronic components 10.

Figure 1 shows the matrix body 26 as a contoured, relatively thin, tray-like structure. Alternatively, as shown in Figure 2, the matrix body 28 could be a solid body of material (again, possibly of composite construction), encapsulating the electronic components 10.

Although not shown, if necessary, components such as heat sinks could project through the matrix body 26 or 28.

The matrix body 26,28 may also include apertures at electronic component 10 positions or elsewhere, if necessary or desirable for any reason.

The matrix body 26,28 and/or other materials may be configured to provide the electronic circuit 5 with any required degree of rigidity or flexibility or combinations thereof.

Where particular sub-assemblies of electronic components 5 are used in different circuits, the electronic components 5 of the sub-assembly could be incorporated into a primary matrix body, and a final circuit could be fabricated from one or more such subassemblies and/or additional discrete electronic components combined together in a secondary matrix body. As such, the present invention includes an assembly of electronic components incorporated into a matrix body, as well as completed circuits including such assembles. For example, Figure 3 illustrates a circuit 5a comprising two sub-assemblies 30 and 32 comprising electronic components 10a and 10b incorporated into primary matrix bodies 34a and 34b, and additional discrete electronic components 10c, all of which are incorporated into a secondary matrix body 36, with layers of dielectric and conductive material collectively indicated at 38 applied thereto as previously described.

Referring now to Figure 4, printed circuits according to the present invention are manufactured using a continuous web 1 10 of flexible polyester film as a supporting substrate. The polyester web 1 10 is coated with an adhesive 1 12 (see also Figure 5) at an adhesive coating station 1 14. A continuous strip of copper foil 1 16 is secured to the polyester web 120 by the adhesive 1 12. The cooper foil 1 16 is applied such that its polished side contacts the adhesive 1 12 and its matt side faces outwardly.

The laminated web 1 10,1 12,1 16 then passes through at least one dielectric layer forming process 1 18, and at least one conductive layer forming process 120 to provide a series of patterned layers, alternatively dielectric and conductive.

Figure 5 shows, by way of an example, a first dielectric layer 122 formed with gaps 124, a first conductive layer 126 which is patterned to form conductive tracks 128 and upward and downward contact portions 130, and a second dielectric layer 132 which overlies the first conductive layer 126 and fills the non-patterned portions, for example as seen at 134, in the first conductive layer 126.

In practical embodiments of the invention, there may be twelve or more dielectric layers and conductive layers, each applied by a process such as 18 and 20 sequentially.

The process 1 18 for applying a dielectric layer may be any of the processes known in the printed circuit art. For example, the dielectric layer 122 may be formed by applying a photoimageable material, exposing the desired pattern, and chemically stripping the unexposed material. The conductive layer 126 may be applied by electroless plating to form a continuous layer of conductor, followed by: photosensitive etch resist, exposure of the desired pattern, etching, and removal of exposed etch resist. However, other methods of forming imaged dielectric and conductive layers may be employed, such as silk screen printing, offset-lithography, or spraying. In this regard we also refer to Figures 7 to 12b herein which refer to a specific photoimaging process which is ideally suited for the present invention. This is discussed in more detail below.

Reverting to Figure 4, after the desired number of dielectric and conductive layers has been applied and the required photoimaging, a further layer 136 (see also Figure 6) may optionally be added to impart a desired degree of structural rigidity to the final product, This may conveniently be done by applying a web 138 of a stiff plastics material to adhesive from an adhesive coating station 140.

The layered web 138 is then passed to a stripping station 143 at which the polyester web 1 10, no longer required as a mechanical substrate, and the adhesive layer 1 12 are separated and discarded. For this purpose, the adhesive layer 1 12 should be of an adhesive material chosen to be peelable cleanly, and to adhere more strongly to the polyester web 1 10 than to the copper foil 1 16. Clean separation of the adhesive 1 10 from the copper foil 1 16 is assisted by contacting the polished face of the copper foil 1 16 to the adhesive 1 10. The continuous web 1 10, with one face now consisting of continuous copper foil 1 16, passes to a process 144, in which the copper 1 16 is reduced to a desired pattern of conductive tracks 1 16' (Figure 6). This may suitably be done by photo-imaging and etching techniques.

Finally, the web is cut at 146 to produce individual printed circuits 150.

The use of a continuous production process operating on a continuous web 1 10 is preferred, as offering the greatest speed and efficiency. However, the invention may be carried out using discrete substrates each of which carries one circuit or a number of circuits.

The use of a rigidifying layer 136 may not be necessary in some cases. Where it is used, the rigidifying layer 136 may be incorporated in an intermediate position in the laminate, rather than at one side.

As indicated above although any type of photoimaging may be used in the different aspects of the present invention a preferred type of photoimaging is described below and is shown in Figures 7 to 12b.

Figure 7 is a sectional side view of a laminated structure, generally designated 200, according to an embodiment of the present invention. The laminated structure 200 comprises a substrate 210 such as a dielectric layer and a metal cladding 212 on both sides. (Although the description below is for a metal cladding it should be noted that a similar process may be used for a non-metallic cladding). On top of the laminated structure 200 there is a layer of a liquid photoresist polymer 214. The photoresist layer 214 is therefore wet. The liquid photoresist polymer layer 214 has a thickness of about 5 μηη. On one side of the substrate 210 there may be a plurality of discrete electronic components in a pre-determined spatial relationship as described above.

The photoresist layer 214 is first of all deposited in a substantially even and continuous or at least substantially continuous manner using any suitable technique onto the laminated structure 200. For example, the photoresist layer 214 is applied using a spray, a brush and/or a roller system. In this type of photoimaging according to the present invention there is no drying step (i.e. a pre-drying step) before the film of wet photoresist polymer is irradiated with, for example, UV radiation.

Once the photoresist layer 214 has been applied to the laminated structure 200, a phototool 216 is applied to the photoresist layer 214. The phototool 216 is a negative (or positive) image of a desired electrical circuitry and allows light to pass through some parts of the phototool 216 but not others. The phototool is made from flexible plastics material.

Figure 8 represents the phototool 216 being applied to the laminated structure 200. After the phototool 216 has been applied to the laminated structure 200 comprising the liquid photoresist layer 214, a compression system is used to spread out and/or squeeze the photoresist layer 214 so that an even spread of the photoresist layer 214 is achieved with a substantially even thickness of about 5 μηη. The compression system also ensures that no air and hence oxygen is trapped underneath the photoresist layer 214. For example, a roller based system applies a compressive force and is used to spread the photoresist layer 214. A rubber cylindrical roller may therefore be used to spread the photoresist layer 214. This overcomes the need to have complex light systems including parabolic mirrors as all air and oxygen is eliminated.

As shown in Figure 8, UV radiation is used to polymerise and/or harden and/or set the exposed liquid photoresist layer 214. The UV radiation has a wavelength of about 200 - 400 nm and has an intensity matched to cure the exposed liquid photoresist layer 214. Any suitable UV light source may be used but UV LEDs are particularly suitable as they produce very small amounts of heat, have a long lamp life, start up immediately, have substantially no fall-off in power output, are low maintenance and can produce high levels of light intensity. LEDs can therefore be used to print fine lines in an inexpensive photoimaging process. Alternatively, a laser light source is used. A significant advantage to note is that no partially cured dry films of photopolymer (e.g. Mylar) are required which therefore significantly reduces any undercutting of the light (i.e. light shadows) during the imaging process which will have a detrimental effect on the resolution. The resolution of the method of the present invention is therefore enhanced by overcoming the need to have no partially cured dry films.

The photoimaging apparatus can be used to process about one panel of laminated structure 200 every ten seconds. Once the photoimaging has occurred, phototools are removed from the laminated structure 200 using any suitable mechanical means. The photoimaging process is extremely quick as no air and oxygen is trapped under the liquid photoresist layer 214. This therefore provides a drying time of less than about 5 seconds or preferably less than 1 second for the photoresist layer 214.

After the photoimaging process, liquid photoresist 214 which has not been exposed to UV radiation is removed using, for example, an aqueous alkali solution via a washing procedure. A standard chemical etching process may then be used. For example, acid or alkali may be used to produce a dielectric substrate containing the required metal (e.g. copper) circuitry covered by polymerised photoresist. The polymerised photoresist can then be removed to yield a substrate with the required electrical conductive circuitry.

The apparatus as described in the present invention can also be fully contained in a mini-clean room which therefore provides significant cost savings in the photoimaging process.

Using the method as described in the present invention high definition fine lines suitable for electrical circuitry are obtained. The fine lines have a width of any of the following: less than or equal to about 200 μηη; less than or equal to about 150 μηη; less than or equal to about 100 μηη; less than or equal to about 75 μηη; less than or equal to about 70 μηη; less than or equal to about 60 μηη; less than or equal to about 50 μηη; less than or equal to about 40 μηη; less than or equal to about 30 μηη; less than or equal to about 20 μηη; less than or equal to about 10 μηη; or less than or equal to about 5 μηη. Alternatively the fine lines have a width of any of the following: greater than about 200 μηη; greater than about 150 μηη; greater than about 100 μηη; greater than about 75 μηη; greater than about 50 μηη; greater than about 20 μηη; or greater than about 10 μηη.

Alternatively the fine lines have a width of any of the following: about 0.1 - 200 μιτι; about 1 - 150 μηη ; about 1 - 100 μηη ; about 20 - 100 μηη or about 5 - 75 μηη.

The fine lines are used in PCBs and other electrical components such as flat screen displays.

Figures 9a and 9b are representations of a yet further alternative photoimaging process according to the present invention. Figure 9a represents a deposit of ink from an ink jet, the ink jet deposit is generally designated 300. The ink jet deposit 300 comprises conductive particles such as silver, gold and/or copper and is therefore conductive. As shown in Figure 9a, the ink jet deposit 300 does not have straight sides but has a series of outer undulations 302 due to the ink being deposited in a series of small droplets. The ink jet deposit 300 has a width 'd' of about 100 μηη. Using such ink jet deposits 300 it is difficult to form fine tracks for electrical circuits. However, the ink jet deposits 300 can be modified using the photoimaging concept described in the present invention. For example, the ink jet deposits 300 can be formed on a plastics sheeting. The ink jet deposit 300 is used to form the approximate required electrical conductive track onto the plastics sheeting. The process as described above is then used to improve the quality of the formed track. A photoresist layer as described above is applied over the plastics sheeting. A phototool is then applied to the plastics sheeting, a compressive force is applied and then radiation. As shown in Figure 9b, the applied photoimaging can be used to produce an improved track 310 within the ink jet deposit 300. For example, if the ink jet deposit 300 has a width 'd' of about 100 μηη, multiple separate high resolution tracks can be formed within the previous single track formed by the ink jet deposit 300. For example, four tracks can be formed within a 100 m ink deposit track.

Figures 10a and 10b are comparisons of existing prior art processes and the photoimaging process described herein. Figure 10a relates to a prior art process which is generally designated 400. Figure 10a shows that there is a copper panel 410 with a dry film layer 412 with a thickness of about 35 μηη residing on top of the copper panel 410, a protective Mylar layer 414 with a thickness of about 25 μηη and an emulsion protective film 416 with a thickness of about 9 μηη used with a phototool 416. The formed thin line or track images 320 are also shown. Figure 10b relates to a photoimaging process according to the present invention which is generally designated 500. Figure 10b shows that there is a copper panel 510, a wet resist layer 512 with a thickness of about 5 μηη and an ultra-thin protective film 514 with a thickness of about 3 μηη used with a phototool 516. The formed thin line or track images 518 are also shown. Figures 10a and 10b clearly show that the photoimaging process of the present invention provides a much smaller depth through which the photoimaging must occur. As shown the prior art process 400, images through a total thickness of about 69 μηη whereas the process 500 of the present invention 500 images through a total thickness of about 8 μηη. There is also no need for a Mylar layer.

Figures 1 1 a and 1 1 b illustrate a further advantage of the photoimaging process described herein relating to undercut. In Figure 1 1 a which is the process 400 of the prior art shows that there is a large amount of undercut of about 14.5 μηη whereas in the process 500 of the present invention there is a small undercut of about 0.84 μηη. The small undercut in the present invention is achieved by having a much reduced depth through which the photoimaging occurs. It should be noted that both Figures 1 1 a and 1 1 b relate to the comparison of the formation of a 5 μηη track where Θ = 6^s.

Figures 12a and 12b illustrate a yet further advantage of the photoimaging process described herein relating to cured line widths where a light source 450, 550 is used, respectively. Both Figures 12a and 12b relate to the comparison of the formation of a 20 μηη space where Θ = 6^s. In the prior art process 400, the resulting cured line width is 49 μιτι (representing a line growth of 145%) whereas in the present invention photoimaging process 500 the resulting cured line width is 21.7 μηη (representing a line growth of only 8%).

As indicated above this photoimaging of a wet film of photoresist polymer in combination of positioning and maintaining a plurality of discrete electronic components in a pre-determined spatial relationship is capable of forming improved electronic circuits.

Whilst specific embodiments of the present invention have been described above, it will be appreciated that departures from the described embodiments may still fall within the scope of the present invention. For example, any suitable type of means may be used to hold electronic components in place during their fabrication.

Claims

1. A method of assembling an electronic circuit comprising:

positioning and maintaining a plurality of discrete electronic components in a pre- determined spatial relationship such that terminals of the components are exposed; and applying dielectric and conductive material to said electronic components such that said terminals are electrically connected in a pre-determined circuit topology.

2. A method of assembling an electronic circuit according to claim 1 , wherein the plurality of discrete electronic components are positioned and maintained in a predetermined spatial relationship using a supporting matrix body comprising at least one or more or a plurality of cavities and/or recesses adapted for receiving the discrete electronic components.

3. A method of assembling an electronic circuit according to any of claims 1 or 2, wherein the electronic circuit comprises a plurality of electronic components having terminals, a plurality of dielectric layers and conductive tracks formed in layers between the dielectric layers and interconnected through the dielectric layers as required by circuit topology.

4. A method of assembling an electronic circuit according to any preceding claim, wherein the electronic circuit further includes an outer, rigid layer of material overlying an outermost dielectric layer

5. A method of assembling an electronic circuit according to any preceding claim, wherein the formed electronic circuit resides on a matrix body which surrounds the electronic components and maintains them in a pre-determined spatial relationship such that their terminals are substantially co-planar and exposed prior to application of dielectric layers and conductive tracks.

6. A method of assembling an electronic circuit according to any preceding claim, wherein the method of manufacture involves the following steps: locating the electronic components in a matrix body as required in a final electronic circuit wherein the matrix body comprises a compartmented tray, with each electronic component located in a compartment;

applying a layer of dielectric material over the matrix body;

patterning the dielectric material to expose terminals on the electronic components; and

applying a layer of conductive material on the patterned dielectric material.

7. A method of assembling an electronic circuit according to claim 6, wherein a plurality of alternating dielectric and dielectric layers are applied.

8. A method of assembling an electronic circuit according to any preceding claim, wherein the matrix body is formed of dielectric material.

9. A method of assembling an electronic circuit according to any preceding claim, wherein the matrix body is removable after the electronic circuit is complete.

10. A method of assembling an electronic circuit according to any preceding claim, wherein the matrix body is pre-fabricated and the electronic components are placed therein.

1 1 . A method of assembling an electronic circuit according to any of claims 1 to 9, wherein the matrix body is formed in situ on and around the electronic components.

12. A method of assembling an electronic circuit according to any preceding claim, wherein a sub-assembly is incorporated into a primary matrix body and a final circuit is incorporated into a secondary matrix body.

13. A method of assembling an electronic circuit according to any preceding claim, wherein a photoimaging technique comprising depositing a wet film of photoresist polymer is used in the fabrication of the electronic circuit.

14. A method of assembling an electronic circuit according to any preceding claim, wherein a photoimaging technique comprising the following is used to form the required circuitry:

providing a substrate with a cladding on top of the electronic components;

depositing a liquid photoresist polymer on at least part of the cladding to form a film of photoresist polymer with a thickness of less than about 178 μηη (0.007 inch); positioning a phototool onto the liquid photoresist polymer; and

applying radiation to the liquid photoresist polymer to cure the photoresist layer in exposed areas through the phototool.

15. A method of assembling an electronic circuit according to claim 14, wherein the substrate is a dielectric material.

16. A method of assembling an electronic circuit according to any of claims 14 or 15, wherein the cladding is metallic and comprises any one of or combination of the following: copper, silver and gold.

17. A method of assembling an electronic circuit according to any of claims 14 to 16, wherein the liquid photoresist polymer is deposited with a thickness of less than about 150 μηη, 125 μηη, 100 μηη, 75 μηη, 50 μηη, 25 μηη, 10 μηη, 5 μηη, 1 μηη, 0.5 μηη or 0.1 μηη.

18. A method of assembling an electronic circuit according to any of claims 14 to 17, wherein the liquid photoresist polymer is deposited with a thickness ranging from about 177 μηη to about 0.1 μηη, about 125 μηη to about 0.1 μηη, about 100 μηη to about 0.1 μηη, about 75 μηη to about 0.1 μηη, about 50 μηη to about 0.1 μηη, about 25 μηη to about 0.1 μηη or about 10 μηη to about 0.1 μηη.

19. A method of assembling an electronic circuit according to any of claims 14 to 18, wherein the liquid photoresist layer is deposited using a spray, a brush and/or a roller system.

20. A method of assembling an electronic circuit according to any of claims 14 to 19, wherein once the liquid photoresist polymer is applied to the substrate with the cladding and the phototool is positioned onto the substrate, a compressive force is applied to the deposited liquid photoresist polymer.

21 . A method of assembling an electronic circuit according to claim 20, wherein the compressive force is a roller based system which applies a compressive rolling force.

22. A method of assembling an electronic circuit according to any of claims 14 to 21 , wherein the phototool is a negative or positive image of desired electrical circuitry.

23. A method of assembling an electronic circuit according to any of claims 14 to 22, wherein UV LEDs or lasers are used as a source of the radiation.

24. A method of assembling an electronic circuit according to any of claims 13 to 23, wherein after the photoimaging has occurred a wash off process is performed to produce electrical circuitry.

25. A method of assembling an electronic circuit according to any of claims 13 to 24, wherein the photoimaging process produces fine lines of less than about 70 μηη, 60 μηη, 50 μηη, 40 μηη, 30 μηη, 20 m, 10 μηη or 5 μηη.

26. A method of assembling an electronic circuit according to any of claims 13 to 25, wherein there is no pre-drying step of the wet film of photoresist polymer before being irradiated.

27. A method of assembling an electronic circuit according to any of claims 13 to 26, wherein the photoimaging process comprises:

providing ink jet deposits comprising conductive particles;

depositing a liquid photoresist polymer on the ink jet deposits;

positioning a phototool onto the liquid photoresist polymer;

28. Electronic circuits made according to any of preceding method claims 1 to 27.

29. A method of making a printed circuit, comprising the steps of:

providing a supporting substrate;

temporarily securing a metal foil to the supporting substrate;

forming a patterned dielectric layer on the metal foil;

removing the supporting substrates from the metal foil; and

selectively removing parts of the metal foil to leave a desired conductive pattern.

30. A method of making a printed circuit according to claim 29, wherein dielectric and conductive patterned layers are formed until a desired circuit topography is attained.

31 . A method of making a printed circuit according to any of claims 29 or 30, wherein the supporting substrate is temporarily secured to the metal foil by means of a peelable adhesive.

32. A method of making a printed circuit according to any of claims 29 to 31 , wherein the method also includes the further step of incorporating a rigidifying layer which forms an outer layer.

33. A method of making a printed circuit according to any of claims 29 to 32, wherein the supporting substrate is a continuous, flexible web, upon which a succession of circuits are capable of being formed in a continuous process.

34. A method of making a printed circuit according to any of claims 29 to 33, wherein, the metal foil is a continuous web of copper foil, one surface of which is polished, and which polished surface is contacted with the peelable adhesive.

35. A method of making a printed circuit according to any of claims 29 to 34, wherein

36. A method of making a printed circuit according to any of claims 29 to 35, wherein the supporting substrate is coated with an adhesive at an adhesive coating station and the metal foil is secured to the supporting substrate by the adhesive.

37. A method of making a printed circuit according to any of claims 29 to 36, wherein at least one dielectric layer forming process and at least one conductive layer forming process are used to provide a series of patterned layers.

38. A method of making a printed circuit according to any of claims 29 to 37, wherein a dielectric layer is formed by applying a photoimageable material, exposing the desired pattern, and chemically stripping the unexposed material.

39. A method of making a printed circuit according to any of claims 29 to 38, wherein a conductive layer is applied by electroless plating to form a continuous layer of conductor, followed by: photosensitive etch resist, exposure of the desired pattern, etching, and removal of exposed etch resist.

40. A method of making a printed circuit according to any of claims 29 to 39, wherein a photoimaging technique comprising depositing a wet film of photoresist polymer is used to form the patterned conductive layers.

41 . A method of making a printed circuit according to any of claims 29 to 40, wherein a photoimaging technique comprising the following is used to form the required circuitry: depositing a liquid photoresist polymer to form a film of photoresist polymer with a thickness of less than about 178 μηη (0.007 inch);

positioning a phototool onto the liquid photoresist polymer; and

42. A method of making a printed circuit according to any of claims 40 or 41 , wherein the liquid photoresist polymer is deposited with a thickness of less than about 150 μηη, 125 μηη, 100 μηη, 75 μηη, 50 μηη, 25 μηη, 10 μηη, 5 μηη, 1 μηη, 0.5 μηη or 0.1 μηη.

43. A method of making a printed circuit according to any of claims 40 to 42, wherein the liquid photoresist polymer is deposited with a thickness ranging from about 177 μηη to about 0.1 μηη, about 125 μηη to about 0.1 μηη, about 100 μηη to about 0.1 μηη, about 75 μηη to about 0.1 μηη, about 50 μηη to about 0.1 μηη, about 25 μηη to about 0.1 μηη or about 10 m to about 0.1 m.

44. A method of making a printed circuit according to any of claims 40 to 43, wherein the liquid photoresist layer is deposited using a spray, a brush and/or a roller system.

45. A method of making a printed circuit according to any of claims 40 to 44, wherein once the liquid photoresist polymer is applied and a phototool is positioned, a compressive force is applied to the deposited liquid photoresist polymer.

46. A method of making a printed circuit according to claim 45, wherein the compressive force is a roller based system which applies a compressive rolling force.

47. A method of making a printed circuit according to any of claims 40 to 46, wherein the phototool is a negative or positive image of desired electrical circuitry.

48. A method of making a printed circuit according to any of claims 40 to 47, wherein UV LEDs or lasers are used as a source of the radiation.

49. A method of making a printed circuit according to any of claims 40 to 47, wherein after the photoimaging has occurred a wash off process is performed to produce electrical circuitry.

50. A method of making a printed circuit according to any of claims 40 to 49, wherein the photoimaging process produces fine lines of less than about 70 μηη, 60 μηη, 50 μηη, 40 μηη, 30 μηη, 20 m, 10 μηη or 5 μηη.

51 . A method of making a printed circuit according to any of claims 40 to 49, wherein there is no pre-drying step of the wet film of photoresist polymer before being irradiated.

52. A method of making a printed circuit according to any of claims 40 to 51 , wherein the photoimaging process comprises: providing ink jet deposits comprising conductive particles;

depositing a liquid photoresist polymer on the ink jet deposits;

positioning a phototool onto the liquid photoresist polymer;

53. A method of making a printed circuit according to any of claims 29 to 52, wherein a stripping station is used to remove unwanted supporting substrate and adhesive.

54. A printed circuit fabricated according to any of claims 29 to 53.