WO2011084336A1 - System and method for controlling central processing unit power with reduced frequency oscillations - Google Patents
System and method for controlling central processing unit power with reduced frequency oscillations Download PDFInfo
- Publication number
- WO2011084336A1 WO2011084336A1 PCT/US2010/059562 US2010059562W WO2011084336A1 WO 2011084336 A1 WO2011084336 A1 WO 2011084336A1 US 2010059562 W US2010059562 W US 2010059562W WO 2011084336 A1 WO2011084336 A1 WO 2011084336A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- previous
- cycle
- busy
- frequency
- busy cycle
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000012545 processing Methods 0.000 title claims abstract description 15
- 230000010355 oscillation Effects 0.000 title description 6
- 238000012552 review Methods 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 description 13
- 238000004422 calculation algorithm Methods 0.000 description 12
- 230000006870 function Effects 0.000 description 6
- 230000007704 transition Effects 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 3
- 238000004590 computer program Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002924 energy minimization method Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000013515 script Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- Portable computing devices are ubiquitous. These devices may include cellular telephones, portable digital assistants (PDAs), portable game consoles, palmtop computers, and other portable electronic devices. In addition to the primary function of these devices, many include peripheral functions.
- a cellular telephone may include the primary function of making cellular telephone calls and the peripheral functions of a still camera, a video camera, global positioning system (GPS) navigation, web browsing, sending and receiving emails, sending and receiving text messages, push-to-talk capabilities, etc.
- GPS global positioning system
- the computing or processing power required to support such functionality also increases. Further, as the computing power increases, there exists a greater need to effectively manage the processor, or processors, that provide the computing power.
- FIG. 1 is a front plan view of a first aspect of a portable computing device
- FIG. 2 is a front plan view of the first aspect of a PCD in an open position
- FIG. 3 is a block diagram of a second aspect of a PCD
- FIG. 4 is a block diagram of a processing system
- FIG. 5 is a flowchart illustrating a first aspect of a method of dynamically controlling power within a CPU
- FIG. 6 is a flowchart illustrating a first portion of a second aspect of a method of dynamically controlling power within a CPU
- FIG. 7 is a flowchart illustrating a second portion of the second aspect of a method of dynamically controlling power within a CPU
- FIG. 8 is a flowchart illustrating a third portion of the second aspect of a method of dynamically controlling power within a CPU.
- FIG. 9 is an exemplary graph showing the dynamic clock and voltage scaling (DCVS) controlled CPU frequency plotted over time.
- an “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches.
- an "application” referred to herein may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
- content may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches.
- content referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
- a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
- an application running on a computing device and the computing device may be a component.
- One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers.
- these components may execute from various computer readable media having various data structures stored thereon.
- the components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).
- an exemplary portable computing device is shown and is generally designated 100.
- the PCD 100 may include a housing 102.
- the housing 102 may include an upper housing portion 104 and a lower housing portion 106.
- FIG. 1 shows that the upper housing portion 104 may include a display 108.
- the display 108 may be a touch screen display.
- the upper housing portion 104 may also include a trackball input device 110.
- the upper housing portion 104 may include a power on button 112 and a power off button 114.
- the upper housing portion 104 of the PCD 100 may include a plurality of indicator lights 116 and a speaker 118. Each indicator light 116 may be a light emitting diode (LED).
- LED light emitting diode
- the upper housing portion 104 is movable relative to the lower housing portion 106. Specifically, the upper housing portion 104 may be slidable relative to the lower housing portion 106.
- the lower housing portion 106 may include a multi-button keyboard 120.
- the multi-button keyboard 120 may be a standard QWERTY keyboard. The multi-button keyboard 120 may be revealed when the upper housing portion 104 is moved relative to the lower housing portion 106.
- FIG. 2 further illustrates that the PCD 100 may include a reset button 122 on the lower housing portion 106.
- the PCD 320 includes an on-chip system 322 that includes a multicore CPU 324.
- the multicore CPU 324 may include a zeroth core 325, a first core 326, and an Nth core 327.
- FIG. 3 further indicates that a video encoder 334, e.g., a phase alternating line (PAL) encoder, a sequential 07 a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the multicore CPU 324.
- a video encoder 334 e.g., a phase alternating line (PAL) encoder, a sequential 07 a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder
- PAL phase alternating line
- SECAM sequential 07 a memoire
- NTSC national television system(s) committee
- a video amplifier 336 is coupled to the video encoder 334 and the touch screen display 332.
- a video port 338 is coupled to the video amplifier 336.
- a universal serial bus (USB) controller 340 is coupled to the multicore CPU 324. Also, a USB port 342 is coupled to the USB controller 340. A memory 344 and a subscriber identity module (SIM) card 346 may also be coupled to the multicore CPU 324. Further, as shown in FIG. 3, a digital camera 348 may be coupled to the multicore CPU 324. In an exemplary aspect, the digital camera 348 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.
- CCD charge-coupled device
- CMOS complementary metal-oxide semiconductor
- a stereo audio CODEC 350 may be coupled to the multicore CPU 324.
- an audio amplifier 352 may be coupled to the stereo audio CODEC 350.
- a first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352.
- FIG. 3 shows that a microphone amplifier 358 may be also coupled to the stereo audio CODEC 350.
- a microphone 360 may be coupled to the microphone amplifier 358.
- a frequency modulation (FM) radio tuner 362 may be coupled to the stereo audio CODEC 350.
- an FM antenna 364 is coupled to the FM radio tuner 362.
- stereo headphones 366 may be coupled to the stereo audio CODEC 350.
- FIG. 3 further indicates that a radio frequency (RF) transceiver 368 may be coupled to the multicore CPU 324.
- An RF switch 370 may be coupled to the RF transceiver 368 and an RF antenna 372.
- a keypad 374 may be coupled to the multicore CPU 324.
- a mono headset with a microphone 376 may be coupled to the multicore CPU 324.
- a vibrator device 378 may be coupled to the multicore CPU 324.
- FIG. 3 also shows that a power supply 380 may be coupled to the on-chip system 322.
- the power supply 380 is a direct current (DC) power supply that provides power to the various components of the PCD 320 that require power.
- the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.
- DC direct current
- FIG. 3 further indicates that the PCD 320 may also include a network card 388 that may be used to access a data network, e.g., a local area network, a personal area network, or any other network.
- the network card 388 may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PeANUT) network card, or any other network card well known in the art.
- the network card 388 may be incorporated into a chip, i.e., the network card 388 may be a full solution in a chip, and may not be a separate network card 388.
- the touch screen display 332, the video port 338, the USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the microphone 360, the FM antenna 364, the stereo headphones 366, the RF switch 370, the RF antenna 372, the keypad 374, the mono headset 376, the vibrator 378, and the power supply 380 are external to the on-chip system 322.
- one or more of the method steps described herein may be stored in the memory 344 as computer program instructions. These instructions may be executed by the multicore CPU 324 in order to perform the methods described herein. Further, the multicore CPU 324, the memory 344, or a combination thereof may serve as a means for executing one or more of the method steps described herein in order to dynamically control the power within a CPU, or core, of the multicore CPU 324.
- a processing system is shown and is generally designated 500.
- the processing system 500 may be incorporated into the PCD 320 described above in conjunction with FIG. 3.
- the processing system 500 may include a multicore central processing unit (CPU) 402 and a memory 404 connected to the multicore CPU 402.
- the multicore CPU 402 may include a zeroth core 410, a first core 412, and an Nth core 414.
- the zeroth core 410 may include a zeroth dynamic clock and voltage scaling (DCVS) algorithm 416 executing thereon.
- the first core 412 may include a first DCVS algorithm 417 executing thereon.
- the Nth core 414 may include an Nth DCVS algorithm 418 executing thereon.
- each DCVS algorithm 416, 417, 418 may be independently executed on a respective core 412, 414, 416.
- the memory 404 may include an operating system 420 stored thereon.
- the operating system 420 may include a scheduler 422 and the scheduler 422 may include a first run queue 424, a second run queue 426, and an Nth run queue 428.
- the memory 404 may also include a first application 430, a second application 432, and an Nth application 434 stored thereon.
- the applications 430, 432, 434 may send one or more tasks 436 to the operating system 420 to be processed at the cores 410, 412, 414 within the multicore CPU 402.
- the tasks 436 may be processed, or executed, as single tasks, threads, or a combination thereof.
- the scheduler 422 may schedule the tasks, threads, or a combination thereof for execution within the multicore CPU 402.
- the scheduler 422 may place the tasks, threads, or a combination thereof in the run queues 424, 426, 428.
- the cores 410, 412, 414 may retrieve the tasks, threads, or a combination thereof from the run queues 424, 426, 428 as instructed, e.g., by the operating system 420 for processing, or execution, of those task and threads at the cores 410, 412, 414.
- FIG. 4 also shows that the memory 404 may include a parallelism monitor 440 stored thereon.
- the parallelism monitor 440 may be connected to the operating system 420 and the multicore CPU 402. Specifically, the parallelism monitor 440 may be connected to the scheduler 422 within the operating system 420.
- a first aspect of a method of dynamically controlling the power of a central processing unit is shown and is generally designated 500.
- the method 500 may commence at block 502 with a do loop in which when device is powered on, the following steps may be performed.
- a power controller e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may monitor one or more CPUs.
- the power controller may determine whether the CPU is idle. If not, the method 500 may return to block 504 and continue as described herein. Otherwise, if the CPU is idle, the method 500 may proceed to block 508 and the power controller may review a busy cycle, i.e., operation window, immediately prior to the current idle state.
- the power controller may determine the total work load during the previous busy cycle. Further, at block 512, the power controller may review the operational frequencies utilized during the previous busy cycle.
- the power controller may determine whether the previous busy cycle ended at the steady state level. If so, the method 500 may proceed to block 516 and the power controller may set the CPU frequency to a steady state value. Then, the method 500 may proceed to decision 518. At decision 518, the power controller may determine whether the device is powered off. If the device is powered off, the method may end. Otherwise, if the device remains powered on, the method 500 may return to block 504 and the method 500 may continue as described.
- the method 500 may move to decision 514 and the power controller may determine whether the previous busy cycle included any frequency jumps or is at the maximum performance level, e.g., due to workload increases. If so, the method 500 may proceed to block 517 and the power controller may reset the longest normalized busy period. The method 500 may continue block 520 and continue as described herein.
- the method 500 may proceed to block 520 and the power controller may determine the longest normalized busy period since being reset.
- the power controller may determine a minimum operational frequency that would not have caused a frequency jump had it been used starting at the time the longest busy period was last reset.
- the power controller sets the CPU frequency to the minimum frequency determined above and resets the longest busy period if the minimum frequency is not the same as the previous CPU frequency.
- the method 500 may then proceed to decision 518.
- the power controller may determine whether the device is powered off. If the device is powered off, the method may end. Otherwise, if the device remains powered on, the method 500 may return to block 504 and the method 500 may continue as described.
- the method 500 may include a steady state and a transient state. Decision 513 may be used to control the transition between the steady state and the transient state. Having the ability to transition between the steady state and the transient state may reduce excessive oscillation in the frequency. Further, the method 500 may be considered self-tuning and may provide dynamic window sizes. [0038] Referring to FIG. 6, a second aspect of a method of dynamically controlling the power of a central processing unit is shown and is generally designated 600.
- a central processing unit may enter an idle state.
- a power controller e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may set a start idle time (StartldleTime) equal to a current time
- the power controller may determine a busy time (Busy Time) by subtracting a start idle time (StartldleTime) from an end idle time (EndldleTime).
- the CPU may enter a software wait for interrupt (SWFI) condition.
- SWFI software wait for interrupt
- the CPU may exit the SWFI condition.
- the power controller may set an end idle time (EndldleTime) equal to a current time (CurrentTime).
- the power controller may determine whether the highest CPU frequency of the previous busy cycle is greater than a steady state frequency. If not, the method 600 may end. Otherwise, the method 600 may proceed to decision 702 of FIG. 7.
- the power controller may determine if the previous busy cycle included any frequency jumps or is at the maximum performance level. If so, the method may proceed to block 704 and the power controller may determine a busy time at the maximum CPU frequency (BusyTimeAtMax), i.e., how long the CPU would have been busy if it had been running at the maximum frequency during the complete busy period.
- the BusyTimeAtMax is a normalized value. In other words, the BusyTimeAtMax is normalized to a single performance level, e.g., the maximum frequency.
- the BusyTimeAtMax may be determined using the following formula: MaxCPUFreq
- BusyTimeAtMax ⁇ (BusyTimeAtFreq[N] * (N / MaxCPUFreq))
- BusyTimeAtFreq[N] The total amount of time that the CPU was busy during the previous busy cycle at frequency N,
- the BusyTimeAtMax would be equal to 1.1 ms.
- the power controller may determine a CPU frequency (CPUFreq) that would not have caused any frequency jumps. Specifically, the power controller may determine the lowest CPU frequency that would have eliminated any frequency jumps. This is determined by calculating the slack budget for each CPU frequency that would be calculated by the transient filter and determining if the slack budget is sufficient that it would not cause the transient filter to make frequency jump.
- CPUFreq CPU frequency
- MaxCPUFreq The maximum CPU frequency
- SteadyStateAdjustment Any adjustment required due to the steady state filter design.
- BusyTimeAtMax The normalized value of how long the CPU was operating at the maximum CPU frequency
- the CPU frequency may be set to the CPUFreq above that meets the condition.
- the power controller may initialize the state of the energy minimization algorithm described herein.
- the power controller may set a last lower time
- the power controller may set a maximum busy time at maximum (MaxBusyTimeAtMax) equal to zero.
- the power controller may set a total busy time
- the power controller may determine a busy time at max
- the power controller may determine whether the BusyTimeAtMax is greater than a maximum busy time at the maximum CPU (MaxBusyTimeAtMax). If the
- BusyTimeAtMax is greater than the MaxBusyTimeAtMax
- the method 600 may proceed to block 806 and the power controller may set the MaxBusyTimeAtMax equal to the BusyTimeAtMax. Then, the method 800 may move to block 808. At decision 804, if the BusyTimeAtMax is not greater than the MaxBusyTimeAtMax, the method 800 may move directly to block 808.
- the power controller may determine a running total busy time (TotalBusyTime) by adding the busy time (BusyTime) to the total busy time
- the power controller may determine a non jumping frequency (NonJumpingFrequency) using the same do loop described above in conjunction with block 706.
- the power controller may determine an energy saving frequency (EnergySavingFrequency).
- the Energy SavingFrequency is the lowest frequency (starting from the level calculated in block 810) that the CPU should be set too in order to save on energy consumption.
- the assumption may be made that the system will not need to jump for at least as long as the amount of time since the last lowering of frequency. Also, the assumption may be made that immediately after the same time period a jump will occur. This step also includes the clock switching overhead and the scheduling overhead.
- the amount of energy consumed at the current CPU frequency is determined. That value may be denoted DCVSFloorEnergy. Then, the CPU frequency may be raised until a value is found that has at most a one percent (1%) clock switch overhead, or that uses less energy than the current performance level. In a particular aspect, the one percent (1%) value is arbitrary and may be eliminated.
- the system may determine how long to run at the CPU frequency in order to see the exact same workload as the previous busy cycle. That value may be denoted as the DCVSJFloorBusyTime and may be determined using the following formula:
- the system may determine the amount of energy that the CPU would consume at the CPUFreq with the same workload as the previous busy cycle.
- the power controller may determine whether the
- the method 600 may return to block 708 of FIG. 7 and the method 600 may continue as described herein. Otherwise, the method 600 may end.
- PCD portable computing device
- the PCD may be a mobile telephone device, a portable digital assistant device, a smartbook computing device, a netbook computing device, a laptop computing device, a desktop computing device, or a combination thereof.
- a DCVS algorithm is a mechanism which measures CPU load/idle time and dynamically adjusts the CPU clock frequency to track the workload in an effort to reduce power consumption while still providing satisfactory system performance.
- the change in CPU throughput may track, but also necessarily lag, the changes in the workload.
- QoS Quality of Service
- the DCVS algorithm may not track the workload quickly enough.
- tasks may fail.
- the performance (QoS) issues may be solved with the introduction of transient performance deadlines, i.e., explicit panics to a higher performance level, however this may result in an actual increase in power due frequency oscillations induced when transitioning between steady state and transient CPU frequencies.
- the system and methods described herein may be used to manage the transition between transient and steady state performance levels. Further, the system and methods described herein may substantially reduce any oscillation. As a result, there may be substantial savings in net power consumed. As shown in FIG. 9, the systems and methods described herein provide dynamic CPU power control without excessive oscillation.
- the present methods introduce an energy minimization algorithm which may control the transitions between the steady state and transient state, i.e., explicit panics to a higher performance levels.
- the energy minimization methods, or algorithms, described herein may effectively managing the jumps between the maximum performance level caused by the transient response guarantee, i.e., the explicit jumps to higher performance levels, and the lower steady state performance level.
- the energy minimization algorithm can just set the CPU performance level to the steady state value.
- the methods described herein may determine how to lower the performance level down to the steady state level in the most energy efficient manner. Further, these methods may actively manage the performance level from the moment in time that a transient pulse, i.e., an explicit panic to a higher frequency, completes, until the performance level is taken back down to the level indicated by the steady state level.
- the performance level may be taken down in discrete steps that will eliminate the possibility of needing a jump to a higher performance level if the exact same idle/busy profile was repeated, that was just seen since the last drop in frequency (performance level).
- the energy minimization methods may set the performance level to that which would have eliminated the jump.
- a controller may determine the lowest frequency at or above the steady state performance level that would have saved energy, assuming that the exact same idle/busy profile is repeated from the point in time that the last frequency reduction was made.
- steps may be time
- steps may be linear
- steps may be non- linear
- a low pass filter based on jumps per second may be used, or any combination thereof
- the system and method described herein may ensure that excessive frequency changes may not be made, despite the presence of QoS deadlines, or explicit panics to higher performance levels. Accordingly, power consumption may be substantially lowered.
- Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
- a storage media may be any available media that may be accessed by a computer.
- such computer-readable media may comprise RAM, ROM,
- any connection is properly termed a computer-readable medium.
- the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
- DSL digital subscriber line
- Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201080056342.5A CN102652298B (en) | 2009-12-16 | 2010-12-08 | System and method for controlling central processing unit power with reduced frequency oscillations |
JP2012544634A JP5605960B2 (en) | 2009-12-16 | 2010-12-08 | System and method for controlling central processing unit power with reduced frequency variation |
EP10795853.0A EP2513747B1 (en) | 2009-12-16 | 2010-12-08 | System and method for controlling central processing unit power with reduced frequency oscillations |
KR1020127018609A KR101411729B1 (en) | 2009-12-16 | 2010-12-08 | System and method for controlling central processing unit power with reduced frequency oscillations |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US28697909P | 2009-12-16 | 2009-12-16 | |
US61/286,979 | 2009-12-16 | ||
US12/944,378 US9128705B2 (en) | 2009-12-16 | 2010-11-11 | System and method for controlling central processing unit power with reduced frequency oscillations |
US12/944,378 | 2010-11-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011084336A1 true WO2011084336A1 (en) | 2011-07-14 |
Family
ID=44144380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2010/059562 WO2011084336A1 (en) | 2009-12-16 | 2010-12-08 | System and method for controlling central processing unit power with reduced frequency oscillations |
Country Status (6)
Country | Link |
---|---|
US (1) | US9128705B2 (en) |
EP (1) | EP2513747B1 (en) |
JP (1) | JP5605960B2 (en) |
KR (1) | KR101411729B1 (en) |
CN (1) | CN102652298B (en) |
WO (1) | WO2011084336A1 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8909962B2 (en) * | 2009-12-16 | 2014-12-09 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US8775830B2 (en) | 2009-12-16 | 2014-07-08 | Qualcomm Incorporated | System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature |
US8689037B2 (en) | 2009-12-16 | 2014-04-01 | Qualcomm Incorporated | System and method for asynchronously and independently controlling core clocks in a multicore central processing unit |
US8650426B2 (en) * | 2009-12-16 | 2014-02-11 | Qualcomm Incorporated | System and method for controlling central processing unit power in a virtualized system |
US9176572B2 (en) | 2009-12-16 | 2015-11-03 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US9104411B2 (en) | 2009-12-16 | 2015-08-11 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US20110145559A1 (en) * | 2009-12-16 | 2011-06-16 | Thomson Steven S | System and method for controlling central processing unit power with guaranteed steady state deadlines |
US9563250B2 (en) | 2009-12-16 | 2017-02-07 | Qualcomm Incorporated | System and method for controlling central processing unit power based on inferred workload parallelism |
US20130060555A1 (en) * | 2011-06-10 | 2013-03-07 | Qualcomm Incorporated | System and Apparatus Modeling Processor Workloads Using Virtual Pulse Chains |
US9086883B2 (en) | 2011-06-10 | 2015-07-21 | Qualcomm Incorporated | System and apparatus for consolidated dynamic frequency/voltage control |
JP5982588B2 (en) * | 2013-02-05 | 2016-08-31 | クアルコム,インコーポレイテッド | System and method for controlling central processing unit power with guaranteed transient deadlines |
US20160116954A1 (en) * | 2014-10-28 | 2016-04-28 | Linkedln Corporation | Dynamic adjustment of cpu operating frequency |
KR102528692B1 (en) * | 2016-01-04 | 2023-05-08 | 한국전자통신연구원 | Apparatus and method for dynamic frequency control of the cpu |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0098169A2 (en) * | 1982-06-30 | 1984-01-11 | Fujitsu Limited | Data processing system |
US20060123253A1 (en) * | 2004-12-07 | 2006-06-08 | Morgan Bryan C | System and method for adaptive power management |
US20090249347A1 (en) * | 2008-03-27 | 2009-10-01 | Panasonic Corporation | Virtual multiprocessor, system lsi, mobile phone, and control method for virtual multiprocessor |
Family Cites Families (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0351902A (en) | 1989-07-20 | 1991-03-06 | Tokyo Electric Co Ltd | Data processor |
US5644769A (en) | 1993-06-14 | 1997-07-01 | Matsushita Electric Industrial Co., Ltd. | System for optimizing program by virtually executing the instruction prior to actual execution of the program to invalidate unnecessary instructions |
JPH086681A (en) | 1994-04-18 | 1996-01-12 | Hitachi Ltd | Power saving control system |
JP2770760B2 (en) | 1995-01-04 | 1998-07-02 | 日本電気株式会社 | Power distribution multiprocessor |
JPH10268963A (en) * | 1997-03-28 | 1998-10-09 | Mitsubishi Electric Corp | Information processor |
JPH11184554A (en) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | Clock control type information processor |
US6230183B1 (en) | 1998-03-11 | 2001-05-08 | International Business Machines Corporation | Method and apparatus for controlling the number of servers in a multisystem cluster |
KR100613201B1 (en) * | 2000-08-28 | 2006-08-18 | 마이크로코넥트 엘엘씨 | Measuring method for cpu usage |
TW521177B (en) | 2000-08-31 | 2003-02-21 | Primarion Inc | Apparatus and system for providing transient suppression power regulation |
KR100487543B1 (en) | 2000-09-01 | 2005-05-03 | 엘지전자 주식회사 | Cpu scheduling method |
US6718474B1 (en) | 2000-09-21 | 2004-04-06 | Stratus Technologies Bermuda Ltd. | Methods and apparatus for clock management based on environmental conditions |
JP2002099433A (en) | 2000-09-22 | 2002-04-05 | Sony Corp | System of computing processing, control method system for task control, method therefor and record medium |
US7596709B2 (en) * | 2000-12-30 | 2009-09-29 | Intel Corporation | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US6829713B2 (en) * | 2000-12-30 | 2004-12-07 | Intel Corporation | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US7017060B2 (en) | 2001-03-19 | 2006-03-21 | Intel Corporation | Power management system that changes processor level if processor utilization crosses threshold over a period that is different for switching up or down |
US6901522B2 (en) | 2001-06-07 | 2005-05-31 | Intel Corporation | System and method for reducing power consumption in multiprocessor system |
US7058824B2 (en) * | 2001-06-15 | 2006-06-06 | Microsoft Corporation | Method and system for using idle threads to adaptively throttle a computer |
US6804632B2 (en) | 2001-12-06 | 2004-10-12 | Intel Corporation | Distribution of processing activity across processing hardware based on power consumption considerations |
US7318164B2 (en) * | 2001-12-13 | 2008-01-08 | International Business Machines Corporation | Conserving energy in a data processing system by selectively powering down processors |
US6978389B2 (en) | 2001-12-20 | 2005-12-20 | Texas Instruments Incorporated | Variable clocking in an embedded symmetric multiprocessor system |
JP2003271401A (en) * | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | Microprocessor having load monitoring function |
US7634668B2 (en) | 2002-08-22 | 2009-12-15 | Nvidia Corporation | Method and apparatus for adaptive power consumption |
US6908227B2 (en) | 2002-08-23 | 2005-06-21 | Intel Corporation | Apparatus for thermal management of multiple core microprocessors |
US7194385B2 (en) | 2002-11-12 | 2007-03-20 | Arm Limited | Performance level setting of a data processing system |
US7240223B2 (en) | 2003-05-07 | 2007-07-03 | Apple Inc. | Method and apparatus for dynamic power management in a processor system |
GB2403823B (en) | 2003-07-08 | 2005-09-21 | Toshiba Res Europ Ltd | Controller for processing apparatus |
US7134031B2 (en) | 2003-08-04 | 2006-11-07 | Arm Limited | Performance control within a multi-processor system |
JP4549652B2 (en) | 2003-10-27 | 2010-09-22 | パナソニック株式会社 | Processor system |
US7107187B1 (en) * | 2003-11-12 | 2006-09-12 | Sprint Communications Company L.P. | Method for modeling system performance |
US7133806B2 (en) | 2004-05-13 | 2006-11-07 | Ittiam Systems (P) Ltd | Method and apparatus for measurement of processor-utilization |
US7401240B2 (en) | 2004-06-03 | 2008-07-15 | International Business Machines Corporation | Method for dynamically managing power in microprocessor chips according to present processing demands |
US7219245B1 (en) | 2004-06-03 | 2007-05-15 | Advanced Micro Devices, Inc. | Adaptive CPU clock management |
KR100716730B1 (en) | 2004-06-11 | 2007-05-14 | 삼성전자주식회사 | Method for decreasing the power consumption in cpu idle-state and mobile device using the same |
JP3805344B2 (en) | 2004-06-22 | 2006-08-02 | 株式会社ソニー・コンピュータエンタテインメント | Processor, information processing apparatus and processor control method |
US7739527B2 (en) * | 2004-08-11 | 2010-06-15 | Intel Corporation | System and method to enable processor management policy in a multi-processor environment |
US7761874B2 (en) * | 2004-08-13 | 2010-07-20 | Intel Corporation | Managing processing system power and performance based on utilization trends |
US7711966B2 (en) * | 2004-08-31 | 2010-05-04 | Qualcomm Incorporated | Dynamic clock frequency adjustment based on processor load |
US7437581B2 (en) | 2004-09-28 | 2008-10-14 | Intel Corporation | Method and apparatus for varying energy per instruction according to the amount of available parallelism |
US7370189B2 (en) | 2004-09-30 | 2008-05-06 | Intel Corporation | Method and apparatus for establishing safe processor operating points in connection with a secure boot |
US7543161B2 (en) | 2004-09-30 | 2009-06-02 | International Business Machines Corporation | Method and apparatus for tracking variable speed microprocessor performance caused by power management in a logically partitioned data processing system |
US7346787B2 (en) * | 2004-12-07 | 2008-03-18 | Intel Corporation | System and method for adaptive power management |
DE102004059996B4 (en) * | 2004-12-13 | 2006-10-05 | Infineon Technologies Ag | Method and apparatus for adjusting the clock frequency of a processor |
US7228446B2 (en) | 2004-12-21 | 2007-06-05 | Packet Digital | Method and apparatus for on-demand power management |
US7369967B1 (en) * | 2004-12-27 | 2008-05-06 | Sprint Communications Company L.P. | System and method for monitoring and modeling system performance |
US7502948B2 (en) | 2004-12-30 | 2009-03-10 | Intel Corporation | Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores |
US7467291B1 (en) * | 2005-02-28 | 2008-12-16 | Sun Microsystems, Inc. | System and method for calibrating headroom margin |
JP4082706B2 (en) | 2005-04-12 | 2008-04-30 | 学校法人早稲田大学 | Multiprocessor system and multigrain parallelizing compiler |
CN101223490A (en) | 2005-07-14 | 2008-07-16 | Nxp股份有限公司 | Using historic load profiles to dynamically adjust operating frequency and available power to a handheld multimedia device processor core |
US7490254B2 (en) * | 2005-08-02 | 2009-02-10 | Advanced Micro Devices, Inc. | Increasing workload performance of one or more cores on multiple core processors |
US7548859B2 (en) * | 2005-08-03 | 2009-06-16 | Motorola, Inc. | Method and system for assisting users in interacting with multi-modal dialog systems |
US7904912B2 (en) | 2005-08-30 | 2011-03-08 | International Business Machines Corporation | Adaptive processor utilization reporting handling different processor frequencies |
US7689838B2 (en) * | 2005-12-22 | 2010-03-30 | Intel Corporation | Method and apparatus for providing for detecting processor state transitions |
US7233188B1 (en) | 2005-12-22 | 2007-06-19 | Sony Computer Entertainment Inc. | Methods and apparatus for reducing power consumption in a processor using clock signal control |
US7263457B2 (en) | 2006-01-03 | 2007-08-28 | Advanced Micro Devices, Inc. | System and method for operating components of an integrated circuit at independent frequencies and/or voltages |
US7650527B2 (en) * | 2006-02-07 | 2010-01-19 | Broadcom Corporation | MIPS recovery technique |
US7574613B2 (en) | 2006-03-14 | 2009-08-11 | Microsoft Corporation | Scaling idle detection metric for power management on computing device |
US20070260898A1 (en) | 2006-05-03 | 2007-11-08 | Edward Burton | Voltage regulator with suspend mode |
US20080005591A1 (en) | 2006-06-28 | 2008-01-03 | Trautman Mark A | Method, system, and apparatus for dynamic thermal management |
US7584369B2 (en) * | 2006-07-26 | 2009-09-01 | International Business Machines Corporation | Method and apparatus for monitoring and controlling heat generation in a multi-core processor |
JP4808108B2 (en) | 2006-08-29 | 2011-11-02 | パナソニック株式会社 | Processor system |
WO2008047179A1 (en) | 2006-10-20 | 2008-04-24 | Freescale Semiconductor, Inc. | Device having redundant core and a method for providing core redundancy |
US7949887B2 (en) * | 2006-11-01 | 2011-05-24 | Intel Corporation | Independent power control of processing cores |
JP2008129846A (en) | 2006-11-21 | 2008-06-05 | Nippon Telegr & Teleph Corp <Ntt> | Data processor, data processing method, and program |
GB2445167A (en) | 2006-12-29 | 2008-07-02 | Advanced Risc Mach Ltd | Managing performance of a processor |
US7793125B2 (en) * | 2007-01-10 | 2010-09-07 | International Business Machines Corporation | Method and apparatus for power throttling a processor in an information handling system |
CN101241390B (en) | 2007-02-07 | 2011-04-13 | 华硕电脑股份有限公司 | Multi- core processor efficiency regulation method |
US7783906B2 (en) | 2007-02-15 | 2010-08-24 | International Business Machines Corporation | Maximum power usage setting for computing device |
US7730340B2 (en) | 2007-02-16 | 2010-06-01 | Intel Corporation | Method and apparatus for dynamic voltage and frequency scaling |
US7849349B2 (en) * | 2007-03-28 | 2010-12-07 | Qimonda Ag | Reduced-delay clocked logic |
JP4739271B2 (en) | 2007-04-19 | 2011-08-03 | 株式会社富士通アドバンストエンジニアリング | Power supply control device, virtual server management system, power supply control method, and power supply control program |
US7865751B2 (en) * | 2007-06-18 | 2011-01-04 | Intel Corporation | Microarchitecture controller for thin-film thermoelectric cooling |
US7902800B2 (en) * | 2007-07-13 | 2011-03-08 | Chil Semiconductor Corporation | Adaptive power supply and related circuitry |
US8356306B2 (en) * | 2007-07-31 | 2013-01-15 | Hewlett-Packard Development Company, L.P. | Workload management controller using dynamic statistical control |
JP4834625B2 (en) | 2007-07-31 | 2011-12-14 | 株式会社東芝 | Power management apparatus and power management method |
US20090049314A1 (en) | 2007-08-13 | 2009-02-19 | Ali Taha | Method and System for Dynamic Voltage and Frequency Scaling (DVFS) |
CN101414268A (en) | 2007-10-15 | 2009-04-22 | 南京大学 | Method for managing processor hot plug on ARM MPCore processor |
US7945804B2 (en) * | 2007-10-17 | 2011-05-17 | International Business Machines Corporation | Methods and systems for digitally controlled multi-frequency clocking of multi-core processors |
JP5433837B2 (en) | 2007-12-05 | 2014-03-05 | 株式会社日立製作所 | Virtual computer system, virtual computer control method, and program |
US20090150696A1 (en) | 2007-12-10 | 2009-06-11 | Justin Song | Transitioning a processor package to a low power state |
US8024590B2 (en) | 2007-12-10 | 2011-09-20 | Intel Corporation | Predicting future power level states for processor cores |
JP4488072B2 (en) * | 2008-01-18 | 2010-06-23 | 日本電気株式会社 | Server system and power reduction method for server system |
US8245236B2 (en) * | 2008-02-27 | 2012-08-14 | International Business Machines Corporation | Lock based moving of threads in a shared processor partitioning environment |
US20090271646A1 (en) * | 2008-04-24 | 2009-10-29 | Vanish Talwar | Power Management Using Clustering In A Multicore System |
US8892916B2 (en) | 2008-08-06 | 2014-11-18 | International Business Machines Corporation | Dynamic core pool management |
US8170845B2 (en) * | 2008-09-24 | 2012-05-01 | International Business Machines Corporation | Method and apparatus for automatic performance modeling with load dependent service times and overheads |
US8195962B2 (en) * | 2008-11-11 | 2012-06-05 | Globalfoundries Inc. | Method and apparatus for regulating power consumption |
CN101436098A (en) | 2008-12-24 | 2009-05-20 | 华为技术有限公司 | Method and apparatus for reducing power consumption of multiple-core symmetrical multiprocessing system |
US8245070B2 (en) | 2008-12-30 | 2012-08-14 | Intel Corporation | Method for optimizing voltage-frequency setup in multi-core processor systems |
JP5091912B2 (en) | 2009-05-21 | 2012-12-05 | 株式会社東芝 | Multi-core processor system |
US8924975B2 (en) * | 2009-07-23 | 2014-12-30 | Empire Technology Development Llc | Core selection for applications running on multiprocessor systems based on core and application characteristics |
US20110145559A1 (en) * | 2009-12-16 | 2011-06-16 | Thomson Steven S | System and method for controlling central processing unit power with guaranteed steady state deadlines |
US8909962B2 (en) * | 2009-12-16 | 2014-12-09 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US9104411B2 (en) * | 2009-12-16 | 2015-08-11 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US8650426B2 (en) * | 2009-12-16 | 2014-02-11 | Qualcomm Incorporated | System and method for controlling central processing unit power in a virtualized system |
US8689037B2 (en) * | 2009-12-16 | 2014-04-01 | Qualcomm Incorporated | System and method for asynchronously and independently controlling core clocks in a multicore central processing unit |
US9563250B2 (en) * | 2009-12-16 | 2017-02-07 | Qualcomm Incorporated | System and method for controlling central processing unit power based on inferred workload parallelism |
US8775830B2 (en) | 2009-12-16 | 2014-07-08 | Qualcomm Incorporated | System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature |
US9176572B2 (en) * | 2009-12-16 | 2015-11-03 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
-
2010
- 2010-11-11 US US12/944,378 patent/US9128705B2/en active Active
- 2010-12-08 KR KR1020127018609A patent/KR101411729B1/en active IP Right Grant
- 2010-12-08 JP JP2012544634A patent/JP5605960B2/en active Active
- 2010-12-08 CN CN201080056342.5A patent/CN102652298B/en active Active
- 2010-12-08 EP EP10795853.0A patent/EP2513747B1/en active Active
- 2010-12-08 WO PCT/US2010/059562 patent/WO2011084336A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0098169A2 (en) * | 1982-06-30 | 1984-01-11 | Fujitsu Limited | Data processing system |
US20060123253A1 (en) * | 2004-12-07 | 2006-06-08 | Morgan Bryan C | System and method for adaptive power management |
US20090249347A1 (en) * | 2008-03-27 | 2009-10-01 | Panasonic Corporation | Virtual multiprocessor, system lsi, mobile phone, and control method for virtual multiprocessor |
Also Published As
Publication number | Publication date |
---|---|
CN102652298A (en) | 2012-08-29 |
US20110145824A1 (en) | 2011-06-16 |
KR101411729B1 (en) | 2014-06-25 |
EP2513747A1 (en) | 2012-10-24 |
JP5605960B2 (en) | 2014-10-15 |
US9128705B2 (en) | 2015-09-08 |
EP2513747B1 (en) | 2018-02-21 |
CN102652298B (en) | 2015-02-18 |
KR20120112579A (en) | 2012-10-11 |
JP2013513899A (en) | 2013-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2513746B1 (en) | System and method for controlling central processing unit power with guaranteed transient deadlines | |
EP2513747B1 (en) | System and method for controlling central processing unit power with reduced frequency oscillations | |
KR101409141B1 (en) | System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature | |
JP5601731B2 (en) | System and method for dynamically controlling a processor | |
JP5893568B2 (en) | System and method for controlling central processing unit power based on estimated workload parallelism | |
US8689037B2 (en) | System and method for asynchronously and independently controlling core clocks in a multicore central processing unit | |
KR101516859B1 (en) | System and method for controlling central processing unit power with guaranteed steady state deadlines | |
EP2524272B1 (en) | System and method of sampling data within a central processing unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080056342.5 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10795853 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2010795853 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1245/MUMNP/2012 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012544634 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20127018609 Country of ref document: KR Kind code of ref document: A |