JPH0351902A - Data processor - Google Patents

Abstract

PURPOSE:To increase the lifetime of a battery without deteriorating the processing ability of a CPU by actuating the CPU with a basic clock of a low frequency when a load factor is small. CONSTITUTION:A CPU 1 performs an idle process and outputs the idle pulses from an I/O port 3 via a bus line 5. A CPU load detecting part 4 counts these idle pulses and compares the count value with the 1st and 2nd comparison values when a clear/latch signal is inputted from the CPU 1. Then a selection signal is outputted to a clock switch 2 for selection of a basic clock CLK1 of a comparatively low frequency when the count value is larger than the 1st comparison value. Meanwhile a selection signal is outputted to the switch 2 for selection of a basic clock CLK2 of a comparatively high frequency when the count value is smaller than the 2nd comparison value which is smaller than the 1st comparison value. Thus it is possible to control each part and to increase the battery lifetime without deteriorating the processing ability of the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device using a central processing unit capable of operating with a plurality of basic clocks having different frequencies as a control unit main body.

[Prior Art] This type of data processing device includes, for example, a Japanese word processor and a personal computer, but in recent years, in order to drive these devices with batteries, low power consumption elements have been used in the central processing unit, memory, etc. C-MOS ICs are being widely used.

It is known that the power consumption of C-MOS IC increases in proportion to the switching frequency of the element.

Therefore, if the frequency of the basic clock that operates the central processing unit is high, the processing capacity will be high, but the power consumption will be high, so if the central processing unit is driven by a battery, the life of the battery will be shortened.

For this reason, in this type of battery-powered data processing equipment, the battery life is shortened, but there are modes in which the central processing unit operates with a relatively high frequency basic clock to increase processing capacity, and a mode in which the central processing unit operates with a relatively low frequency basic clock to process processing. There is a known device that allows the user to select a mode that reduces performance but extends battery life.

[Problem to be Solved by the Invention] However, in such a device where mode switching is performed on the user side, the mode is set regardless of the processing status of the central processing unit, so the central processing unit is not configured to perform processing according to the processing status. It is difficult to operate the central processing unit flexibly according to the capacity, and therefore it has not been possible to operate the central processing unit without reducing the processing capacity and to extend the life of the battery.

Accordingly, the present invention is capable of operating the central processing unit flexibly with processing capacity according to the processing situation, and therefore, it is possible to operate the central processing unit without reducing the processing capacity, and also to extend the life of the battery. The aim is to provide a data processing device that can perform

[Means for Solving the Problems] The present invention provides a data processing device in which a central processing unit capable of operating with a plurality of basic clocks having different frequencies is used in the main body of the control unit. load factor detection means for detecting the load factor of the central processing unit; and clock selection means for selecting one from a plurality of basic clocks as the basic clock for operation according to the load factor detected by the load factor detection means. The clock selection means is configured to select a basic clock having a higher frequency as the load factor becomes larger, and select a basic clock having a lower frequency as the load factor becomes smaller.

[Operation] In the present invention having such a configuration, the load factor of the central processing unit is detected by checking the length of the idle period and other periods, and the frequency of the basic clock to be used is determined according to the load factor. choose whether to When the load factor is high, a high-frequency basic clock is selected to increase the processing capacity of the central processing unit, and when the load factor is small, a low-frequency basic clock is selected to reduce the processing capacity of the central processing unit and reduce power consumption. Reduce.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows the configuration of the main parts of the data processing device, where 1 is a central processing unit (hereinafter referred to as F, CPU) that constitutes the main body of the controller, and 2 is a relatively low frequency basic clock CLK.
, and a clock switcher as a clock selection means for selecting a relatively high frequency basic clock CLK2, 3 is an I
/O boat 4 is a CPU load detection section as a load factor detection means.

The CPU 1 and I/O boat 3 are connected to a bus line 5.

The CPU inputs the clock selected by the clock switch 2 as the basic clock CLK, and controls each unit (for example, a keyboard, display, printer, etc. separately connected to the bus line 5) with a processing capacity according to the frequency of the basic clock. ). Also, the CP
The UI is in the second state when an idle cycle is being performed.
As shown in the figure, after idle processing is performed, pulse output processing is performed. In this pulse output processing, the I/O port 3 is accessed at regular intervals via the bus line 5, and the I/O port 3 outputs an idle pulse.

Note that in the idle processing, loop processing such as device self-diagnosis and key manual search is performed.

As shown in FIG. 3, the CPU load detection section 4 includes an up counter 5, first and second comparators 6, 7, and counts idle pulses from the I/O boat 3 using the up counter. When a clear/love signal is input from the counter 5, the count value of the counter 5 is compared by the first and second comparators 6.7, and the counter 5 is cleared.

and the first one whose count value is set in the M1 comparator 6.
When larger than the comparison value, the basic clock CLK. CLK. The selection signal is sent to the clock switch 2.
CLK for selecting the basic clock CLK2 when the count value is smaller than a second comparison value which is smaller than the first comparison value set in the second comparator 7.
2 selection signal is output to the clock switch 2.

Note that the basic clock CLK from the clock switch 2
is supplied not only to the CPU but also to the circuits of the entire device.

In this embodiment having such a configuration, when the idle cycle period occupies a large proportion of the processing cycles executed by the CPU 1, the previous clear/latch signal is manually input to the counter 5, and then the next clear/latch signal is input to the counter 5. The number of idle pulses generated from the I/O boat 3 increases until they are input to the I/O boat 3. That is, the CPU
The load factor of I becomes smaller.

Therefore, the count value of the counter 5 when the clear/latch signal is input to the counter 5 becomes larger than the first comparison value set in the first comparator 6. In this way, the CLK and selection signals from the CPU load detection section 4 are sent to the clock switch 2.
As a result, the clock switch 2 performs a switching operation to set the basic clock CLK to the basic clock CLK. In this way, the CPU performs processing operations using the basic clock of relatively low frequency. Therefore, during this period, processing capacity decreases, but power consumption decreases and battery life increases.

Furthermore, if the idle cycle period occupies a small proportion of the processing cycles executed by the CPU, the I
The number of idle pulses generated from /O boat 3 is reduced. In other words, the CPUI load factor becomes thick.

Therefore, the count value of the counter 5 when the clear/latch signal is input to the counter 5 becomes smaller than the second comparison value set in the second comparator 7. In this way, the CLK and selection signals from the CPU load detection section 4 are sent to the clock switch 2.
As a result, the clock switch 2 performs a switching operation to set the basic clock CLK2 as the basic clock CLK.

In this way, the CPU 1 performs processing operations using a relatively high frequency basic clock. Therefore, the processing capacity is high during this period.

In this way, when the CPU load factor increases, the basic clock frequency can be increased to increase processing capacity, and when the load factor is low, the basic clock frequency can be lowered to extend battery life. , each part can be controlled without reducing the processing capacity of the CPU 1, and the life of the battery can be extended.

In the embodiment described above, the CPU load detection section 4 is constructed of a circuit that performs digital processing, but is not necessarily limited to this, and may be constructed of a circuit that performs analog processing as shown in FIG.

That is, in the circuit shown in FIG. 4, a series circuit of a charging resistor 12 and a charging/discharging capacitor 13 is connected between the +V cc power supply terminal and the ground via an analog switch 11, and a discharging resistor 14 is connected in parallel to the capacitor 13. Connected. Further, a series voltage dividing circuit including resistors 15, 16, and 17 is connected between the +VCC power supply terminal and the ground.

The connection point voltage of the resistor 15.16 and the charging voltage of the capacitor 13 are compared by a first comparator 18, and the connection point voltage of the resistor 16.17 and the charging voltage of the capacitor 13 are compared by a second comparator 18. I'm trying to compare.

The analog switch 11 is turned on when an idle pulse from the I/O boat 3 is input. The first comparator 18 outputs CLK when the charging voltage of the capacitor 13 becomes higher than the voltage at the connection point of the resistor 15.16.
, and a selection signal, and the second comparator 19 outputs a CLK2 selection signal when the charging voltage of the capacitor 13 becomes smaller than the voltage at the connection point of the resistor 16.17.

In this circuit, the analog switch 11 is turned on every time an idle pulse is manually applied, and the capacitor 13 is charged via the resistor 12. Further, the capacitor 13 is always discharged at a constant rate via the resistor 14.

Therefore, when the CPUI load factor is small and many idle pulses occur within a certain period of time, the charging voltage of the capacitor 13 becomes high, and as a result, the first comparator 18 outputs CLK. A selection signal is output. As a result, the CPU is operated with a low frequency basic clock CLK.

In addition, when the CPU load factor is large and idle pulses occur only a few times within a certain period of time, the charging voltage of the capacitor 13 becomes low, and as a result, the second comparator 19 outputs CLK.
2 selection signal is output.

This allows the CPU to use the high frequency basic clock CLK.
2 will be activated.

In this way, even if a CPU load detection section having an analog configuration is used, the same effects as in the embodiment described above can be obtained.

In each of the above embodiments, the number of basic clocks to be selected is two, but one may be selected from three or more basic clocks with different frequencies. In that case, the comparator Also, three or more basic clocks are required, and by using a priority encoder, it is possible to select the optimal basic clock.

Furthermore, in each of the above embodiments, the CPU load detection section detects the CPU load factor using the hardware configuration, but the invention is not limited to this. It may also be detected.

Hereinafter, an embodiment in which the CPU load factor is detected by software will be described with reference to the drawings.

As shown in FIG. 5, n basic clocks CLKl, CLK2 . ...CLK. is supplied to the clock switch 20, the switch 20 selects one basic clock, and the CPU 21 selects one basic clock as the basic clock CLK.
and supplies it to the entire system.

The CPU 21 connects to the latch circuit 2 via the bus line 22.
3 so that the latch circuit 23 outputs a clock selection signal to the clock switch 20.

Note that the clock switch 20 is configured so that no clock pulses are dropped or the pulse width is reduced during switching.

A memory 24, an I/O port 25, etc. are also connected to the bus line 22.

The software configuration is shown in FIG. 6. That is, the application executed by the CPU 21 consists of many tasks, and the CPU 21 can temporarily execute only one task, which is in the executing state. Further, tasks in an executable state can be executed immediately, and among them, an idle task has the lowest priority. Therefore, when the CPU 21 has no task to execute, the idle task is executed.

Other states include waiting state, stopped state, and suspended state.

Each of these states is controlled by Dis Batch. Then, the time during which this dispatcher is activating an idle task is counted. This allows the time when the idle task is not operating, that is, the load factor of the CPU 21 to be detected.

In this embodiment, the load factor of the CPU 21 is detected, and the load factor of the CPU 21 is detected in contrast to the time the idle task is not operating, which is counted by the dispatcher. The CPU 21 controls the latch circuit 23, and a desired clock selection signal is supplied from the latch circuit 23 to the clock switch 20. As a result, the clock switch 20 selects the basic clock CLK. ~CLK.
A basic clock having a frequency corresponding to the load factor of the CPU is selected and supplied to the CPU 21 and the entire system.

For example, in the case shown in FIG. 7(a), the CPU 21 is in an idle state, and in this case the load factor of the CPU is small, so that a basic clock having a fairly low frequency is selected.

In addition, the case shown in FIG. 7(b) shows a case where task A is started by an interrupt such as key manual processing, and in this case, the CPU load factor is higher than the idle state but not that large. A base clock with a relatively low frequency is selected.

Furthermore, the case shown in FIG. 7(C) shows a case in which task A is started by an interrupt such as processing for manually converting kana conversion keys in a word processor, and task B is further started by task A. The CPU load factor becomes high. Therefore, a relatively high frequency basic clock is selected.

Note that if the unit time for measuring the CPU load factor shown in the figure is set to about 0.1 seconds, for example, it is sufficiently short compared to the time it takes for an operator to operate a key, so it will not cause any operational problems, and moreover, the CPU processing For example, if the processing speed of the CPU is 1 million instructions/second, then 100,000 instructions can be executed in the time required.

In this way, also in this embodiment, the frequency of the basic clock can be changed according to the load factor of the CPU 21, and the same effects as in the previous embodiment can be obtained.

In addition, in the above embodiment, the time during which the idle task is activated by the dispatcher is counted; however,
The present invention is not necessarily limited to this, but a counter may be incorporated into the idle task, and the count value of the counter may be checked at regular intervals by an interval task.

That is, as shown in FIG. 8, after executing the idle task, the idle operation counter is incremented by +1.

Then, as shown in FIG. 9, the interval task checks the count value of the idle operation counter at regular intervals, detects the load factor of the CPU 21 based on the value, and selects the corresponding basic clock from among the basic clocks CLKI to CLK. Controls the latch circuit 23. Then, the idle operation counter is cleared.

Therefore, in this case, the unit time for measuring the CPU load factor is the first
As shown in FIG. 0, ε is reached from the end of the previous interval task until the end of the next interval task.

Even if you incorporate a counter into an idle task like this, C
Since the load factor of the PU can be detected, the same effects as in the embodiment described above can be obtained.

[Effects of the Invention] As detailed above, according to the present invention, the load factor of the central processing unit is detected and the frequency of the basic clock for operating the central processing unit is changed in accordance with the load factor. , the central processing unit can be operated flexibly with the processing capacity according to the processing situation, and therefore the central processing unit can be operated without reducing the processing capacity, and when the load factor is small, the central processing unit can be operated at a low frequency. It is possible to provide a data processing device that operates with a basic clock, reduces power consumption, and extends battery life.

[Brief explanation of drawings]

Figures 1 to 3 show an embodiment of the present invention. Figure 1 is a block diagram of the main part, Figure 2 is a flowchart showing idle cycle processing, and Figure 3 is a CPU load in Figure 1. A specific circuit diagram of the detection section, FIG. 4 is a circuit diagram showing another embodiment of the CPU load detection section, and FIGS. 5 to 7 show other embodiments of the present invention, and FIG. 5 shows the main points. FIG. 6 is a diagram schematically showing the software configuration, FIG. 7 is a graph for explaining the relationship between task execution contents and the load factor at that time, and FIGS. 8 to 10 are This shows another example of load factor detection using software. Fig. 8 is a flowchart showing idle task processing, Fig. 9 is a flowchart showing interval task processing, and Fig. 10 is a flowchart showing CPU load rate detection set by interval task. It is a graph which shows the unit time of load factor measurement. 1,21... central processing unit (CPU), 2.20...
・Clock switch (clock selection means) 3...I/O
board, 4... CPU load detection section, 23... latch circuit.

Claims (1)

[Claims] Load factor detection that detects the load factor of the central processing unit based on the length of the idle period and other periods in a data processing device that uses a central processing unit that can operate with multiple basic clocks with different frequencies as the main body of the control unit. and clock selection means for selecting one from a plurality of basic clocks as a basic clock for operation according to the load factor detected by the load factor detection means, and the clock selection means:
A data processing device characterized in that the larger the load factor is, the higher the frequency basic clock is selected, and the smaller the load factor is, the lower the frequency basic clock is selected.