CN101436098A - Method and apparatus for reducing power consumption of multiple-core symmetrical multiprocessing system - Google Patents

Method and apparatus for reducing power consumption of multiple-core symmetrical multiprocessing system Download PDF

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CN101436098A
CN101436098A CNA200810187572XA CN200810187572A CN101436098A CN 101436098 A CN101436098 A CN 101436098A CN A200810187572X A CNA200810187572X A CN A200810187572XA CN 200810187572 A CN200810187572 A CN 200810187572A CN 101436098 A CN101436098 A CN 101436098A
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system loading
core
cpu core
threshold value
loading
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智伟敏
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The embodiment of the invention provides a method and a device for reducing power consumption of a multi-core symmetric multiprocessing system, which relate to symmetric multiprocessing technology. The method of the embodiment of the inversion adopts the technical proposal that the current system load of the multi-core symmetric multiprocessing system is calculated and compared with an idle threshold of the system load, and the number of operated CPU inner cores is reduced if the current system load is smaller than the idle threshold of the system load. The embodiment of the invention is mainly applied to the multi-core symmetric multiprocessing system.

Description

Reduce the method and the device of the power consumption of multi-core symmetric multiprocessing system
Technical field
The present invention relates to symmetrical multiprocessing technology, relate in particular to a kind of multiprocessing of reduction multinuclear symmetry (Symmetrical Multi-Processing, SMP) method of the power consumption of system and device.
Background technology
Polycaryon processor is meant the processor products that comprises a plurality of CPU core in a chip.Compare traditional monokaryon chip, the polycaryon processor technology can remain under the constant situation of frequency, significantly the performance of elevator system.Wherein, polycaryon processor can be divided into two kinds of isomorphism polycaryon processor and heterogeneous multi-nucleus processors.Described isomorphism polycaryon processor is meant that the structure of each CPU core is identical, and heterogeneous multi-nucleus processor is meant that the structure of each CPU core is different.
And symmetrical multiprocessing system is meant and has compiled one group of CPU on a computing machine, shared drive subsystem and bus structure between each CPU.In this system, though use a plurality of CPU simultaneously, from the angle of management, their performance is just as a unit.System is distributed in task queue on a plurality of CPU symmetrically, thereby has greatly improved the data-handling capacity of total system.All processors are access memory, I/O and external interrupt coequally.In symmetrical multiprocessing system, system resource is shared by all CPU in the system, and operating load can be assigned on all available CPU equably.In concrete the application, polycaryon processor just is similar to such computing machine with many CPU, and each CPU core can adopt the SMP mode to move.
In realizing process of the present invention, the inventor finds: though though operation has the polycaryon processor of smp system that powerful computing ability can be provided, also the increase owing to CPU core quantity has consumed more electric energy.This is because under the less situation of the data volume that whole polycaryon processor is handled, number of C PU kernel may be in " idle running " state.That is to say when polycaryon processor was carried out a certain task, number of C PU kernel can constantly go inquiry whether to have data or incident to need to handle.So like this, because these CPU are in the executive system of not stopping instruction, thereby also consumed power accordingly.
Summary of the invention
The embodiment of the invention provides a kind of method and device that reduces the power consumption of multi-core symmetric multiprocessing system.
The embodiment of the invention adopts following technical scheme:
A kind of method that reduces the multi-core symmetric multiprocessing system power consumption comprises:
The current system loading of statistics multi-core symmetric multiprocessing system;
Described current system loading and the idle threshold value of system loading are compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
A kind of device that reduces the multi-core symmetric multiprocessing system power consumption comprises:
Statistic unit is used to add up the current system loading of multi-core symmetric multiprocessing system;
Operating unit is used for described current system loading and the idle threshold value of system loading are compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
The method and the device of the power consumption of the reduction multi-core symmetric multiprocessing system that the embodiment of the invention provides, by adding up the current system loading of described multi-core symmetric multiprocessing system, and during less than the idle threshold value of described system loading, reduce the quantity of the CPU core of operation at described current system loading.Therefore, utilize the described method and apparatus of the embodiment of the invention can adjust the quantity of the CPU core of operation, therefore can reach and reduce system power dissipation, purpose of energy saving according to the load condition of system.
Description of drawings
Fig. 1 reduces the process flow diagram of the method for multi-core symmetric multiprocessing system power consumption for one embodiment of the invention;
Fig. 2 reduces the process flow diagram of the method for multi-core symmetric multiprocessing system power consumption for another embodiment of the present invention;
Fig. 3 reduces the schematic representation of apparatus of multi-core symmetric multiprocessing system power consumption for the embodiment of the invention;
Fig. 4 reduces the structural drawing of the device of multi-core symmetric multiprocessing system power consumption for the embodiment of the invention.
Embodiment
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the accompanying drawing of required use is done an introduction simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
As shown in Figure 1, the embodiment of the invention provides a kind of method that reduces the multi-core symmetric multiprocessing system power consumption, comprising:
The current system loading of step 11, statistics multi-core symmetric multiprocessing system.
In this step, can add up the current system loading of described system by following at least dual mode: the one, add up by the control module of outside, the 2nd, itself add up by each CPU core.
Under first kind of mode, can obtain the preload of working as of each CPU core of moving by described control module respectively, then with the adding up when preload of described each CPU core, and obtain the mean value when preload of described each CPU core of moving.Then, with the current system loading of described mean value as described system.
Under the second way, can be by on each CPU core, creating the task T (1) of each CPU core of statistics load respectively, T (2) ... T (n) (n is the number of CPU core in the system) is used for adding up respectively the preload of working as of each corresponding C PU kernel.Then, create the task TT (x) when preload of each CPU core that is used to add up moving therein at least one CPU core, calculate each CPU core when preload add up and, and calculate described each CPU core of moving when the mean value of preload.Then, with the current system loading of described mean value as described system.
In addition, under above-mentioned dual mode, the control module of described outside or each CPU core basis are worked as in the process of preload in each CPU core of statistics, can periodically add up.Wherein, measurement period can be provided with arbitrarily by the user.
Certainly, in concrete the application, can utilize other modes to realize being not limited to statistics to current system loading at these cited two kinds.
Step 12, the idle threshold value of described current system loading and system loading is compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
In concrete application process, if described current system loading is less than the idle threshold value of described system loading, can send message on hold at least one CPU core of described operation, make the CPU core of described operation after receiving described message on hold, stop reading system directive.
In concrete the application,, can take once to hang up the mode of a CPU core for avoiding that system is produced excessive impact.After hanging up one of them CPU core of moving, and then current system loading added up, described current system loading and the idle threshold value of system loading are compared, and during less than the idle threshold value of described system loading, hang up a CPU core of moving once more at described current system loading.Constantly repeat said process then, up to reaching best reduction power consumption, energy-conservation effect.
By above description as can be seen, the method of the power consumption of the reduction multi-core symmetric multiprocessing system that the embodiment of the invention provides, by adding up the current system loading of described multi-core symmetric multiprocessing system, and during less than the idle threshold value of described system loading, reduce the quantity of the CPU core of operation at described current system loading.Therefore, utilize the described method of the embodiment of the invention can adjust the quantity of the CPU core of operation, therefore can reach and reduce system power dissipation, purpose of energy saving according to the load condition of system.
In addition, system normally moves for assurance, if described current system loading greater than the busy threshold value of system loading, also can increase the quantity of the CPU core of operation.In concrete the application, can be by sending wakeup message at least one CPU core that is in suspended state, can make as interrupt message or other message that CPU wakes up etc. to make the described CPU core that is in suspended state after receiving described wakeup message, restart reading system directive.Equally, in the process of at every turn waking CPU core up, also can once wake the CPU core of a hang-up up, and then current system loading added up, described current system loading and the idle threshold value of system loading are compared, and when described current system loading is had much to do threshold value greater than system loading, wake the CPU core of a hang-up once more up.Constantly repeat said process then, can satisfy the needs of the normal operation of system up to the quantity of the CPU core of moving.
As shown in Figure 2, the method for another embodiment of the present invention reduction multi-core symmetric multiprocessing system power consumption comprises:
Step 21, respectively idle threshold value of described system loading and the busy threshold value of system loading are set, to improve efficient to current system loading statistics.In concrete the application, idle threshold value of described system loading and the busy threshold value of system loading can be provided with by the user according to system's own resources situation.
The current system loading of step 22, statistics multi-core symmetric multiprocessing system.
Identical with embodiment shown in Figure 1, in this embodiment, also can add up the current system loading of described system by following at least dual mode: the one, add up by the control module of outside, the 2nd, itself add up by each CPU core.As for how under different modes, to realize the statistics of current system loading is not repeated them here.
Step 23, the idle threshold value of described current system loading and system loading is compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
In concrete application process, if described current system loading is less than the idle threshold value of described system loading, can send message on hold at least one CPU core of described operation, make the CPU core of described operation after receiving described message on hold, stop reading system directive.
In addition, for avoiding that system is produced excessive impact, can take once to hang up the mode of a CPU core.After hanging up one of them CPU core of moving, and then current system loading added up, described current system loading and the idle threshold value of system loading are compared, and during less than the idle threshold value of described system loading, hang up a CPU core of moving once more at described current system loading.Constantly repeat said process then, up to reaching best reduction power consumption, energy-conservation effect.
In addition, in this embodiment, system normally moves for assurance, if described current system loading greater than the busy threshold value of system loading, also can increase the quantity of the CPU core of operation.In concrete the application, can be by sending wakeup message at least one CPU core that is in suspended state, can make as interrupt message or other message that CPU wakes up etc. to make the described CPU core that is in suspended state after receiving described wakeup message, restart reading system directive.Equally, in the process of at every turn waking CPU core up, also can once wake the CPU core of a hang-up up, and then current system loading added up, described current system loading and the idle threshold value of system loading are compared, and when described current system loading is had much to do threshold value greater than system loading, wake the CPU core of a hang-up once more up.Constantly repeat said process then, can satisfy the needs of the normal operation of system up to the quantity of the CPU core of moving.
By above description as can be seen, the method of the power consumption of the reduction multi-core symmetric multiprocessing system that the embodiment of the invention provides, by adding up the current system loading of described multi-core symmetric multiprocessing system, and during less than the idle threshold value of described system loading, reduce the quantity of the CPU core of operation at described current system loading.Therefore, utilize the described method of the embodiment of the invention can adjust the quantity of the CPU core of operation, therefore can reach and reduce system power dissipation, purpose of energy saving according to the load condition of system.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
In addition, the embodiment of the invention also provides a kind of device that reduces the multi-core symmetric multiprocessing system power consumption.
As shown in Figure 3, comprising: statistic unit 31 and operating unit 32.Wherein, described statistic unit 31 is used to add up the current system loading of multi-core symmetric multiprocessing system; Described operating unit 32 is used for described current system loading and the idle threshold value of system loading are compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
In concrete the application, as shown in Figure 4, described operating unit 32 can comprise: comparison module 321 is used for described current system loading and the idle threshold value of system loading are compared; Operational module 322 is used at described current system loading reducing the quantity of the CPU core of operation during less than the idle threshold value of described system loading.In addition, described operating unit also can comprise: first message transmission module 323, be used for when described current system loading during less than the idle threshold value of described system loading, at least one CPU core to described operation sends message on hold, make the CPU core of described operation after receiving described message on hold, stop reading system directive.
In addition, system normally moves for assurance, when described operational module 322 also is used in described current system loading greater than the busy threshold value of system loading, increases the quantity of the CPU core of operation.At this moment, described operating unit 32 also can comprise second message transmission module 324, be used for when described current system loading is had much to do threshold value greater than system loading, send wakeup message at least one CPU core that is in suspended state, make the described CPU core that is in suspended state after receiving described wakeup message, restart reading system directive.
Wherein, as shown in Figure 4, described statistic unit 31 can comprise: statistical module 311 is used for obtaining respectively the preload of working as of each CPU core of moving; Computing module 312 is used for the adding up when preload of described each CPU core, and obtains the mean value when preload of described each CPU core of moving, and with described mean value as current system loading.
The device of the power consumption of the reduction multi-core symmetric multiprocessing system that the embodiment of the invention provides, by adding up the current system loading of described multi-core symmetric multiprocessing system, and during less than the idle threshold value of described system loading, reduce the quantity of the CPU core of operation at described current system loading.Therefore, utilize the described device of the embodiment of the invention can adjust the quantity of the CPU core of operation, therefore can reach and reduce system power dissipation, purpose of energy saving according to the load condition of system.
In addition, for improving the efficient to current system loading statistics, as shown in Figure 4, described device also can comprise: unit 33 is set, is used for being provided with respectively the busy threshold value of idle threshold value of the described load of system and system loading.
The described method and apparatus of the embodiment of the invention not only can also be applied in the symmetrical multiprocessing system that is made of two or more discrete monokaryon CPU with being used in the multi-core symmetric multiprocessing system.
In sum, the method and the device of the power consumption of the reduction multi-core symmetric multiprocessing system that the embodiment of the invention provides, by adding up the current system loading of described multi-core symmetric multiprocessing system, and during less than the idle threshold value of described system loading, reduce the quantity of the CPU core of operation at described current system loading.Therefore, utilize the described method and apparatus of the embodiment of the invention can adjust the quantity of the CPU core of operation, therefore can reach and reduce system power dissipation, purpose of energy saving according to the load condition of system.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection domain with claim.

Claims (13)

1, a kind of method that reduces the multi-core symmetric multiprocessing system power consumption is characterized in that, comprising:
The current system loading of statistics multi-core symmetric multiprocessing system;
Described current system loading and the idle threshold value of system loading are compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
2, reduction multi-core symmetric multiprocessing system power consumption method according to claim 1 is characterized in that described method also comprises:
If described current system loading greater than the busy threshold value of system loading, increases the quantity of the CPU core of operation.
3, the method for reduction multi-core symmetric multiprocessing system power consumption according to claim 1 and 2 is characterized in that, before the step of the current system loading of adding up multi-core symmetric multiprocessing system, described method also comprises:
Idle threshold value of described system loading and the busy threshold value of system loading are set respectively.
4, the method for reduction multi-core symmetric multiprocessing system power consumption according to claim 1 is characterized in that, the step of the current system loading of described statistics multi-core symmetric multiprocessing system comprises:
Obtain the preload of working as of each CPU core of moving respectively;
With adding up when preload of described each CPU core, and obtain the mean value when preload of described each CPU core of moving, and with described mean value as current system loading.
5, the method for reduction multi-core symmetric multiprocessing system power consumption according to claim 1 is characterized in that, less than the idle threshold value of described system loading, the step that reduces the quantity of the CPU core of moving is specially as if described current system loading:
If described current system loading is less than the idle threshold value of described system loading, send message on hold at least one CPU core of described operation, make the CPU core of described operation after receiving described message on hold, stop reading to system directive.
6, the method for reduction multi-core symmetric multiprocessing system power consumption according to claim 2 is characterized in that, greater than the busy threshold value of system loading, the step that increases the quantity of the CPU core of moving is specially as if described current system loading:
If described current system loading is less than the idle threshold value of described system loading, send wakeup message at least one CPU core that is in suspended state, make the described CPU core that is in suspended state after receiving described wakeup message, restart reading system directive.
7, a kind of device that reduces the multi-core symmetric multiprocessing system power consumption is characterized in that, comprising:
Statistic unit is used to add up the current system loading of multi-core symmetric multiprocessing system;
Operating unit is used for described current system loading and the idle threshold value of system loading are compared, if described current system loading less than the idle threshold value of described system loading, reduces the quantity of the CPU core of operation.
8, the device of reduction multi-core symmetric multiprocessing system power consumption according to claim 7 is characterized in that, described operating unit comprises:
Comparison module is used for described current system loading and the idle threshold value of system loading are compared;
Operational module is used at described current system loading reducing the quantity of the CPU core of operation during less than the idle threshold value of described system loading.
9, the device of reduction multi-core symmetric multiprocessing system power consumption according to claim 8 is characterized in that,
Described operational module also is used for increasing the quantity of the CPU core of operation when described current system loading is had much to do threshold value greater than system loading.
10, according to the device of claim 7 or 8 or 9 described reduction multi-core symmetric multiprocessing system power consumptions, it is characterized in that described device also comprises:
The unit is set, is used for being provided with respectively the busy threshold value of idle threshold value of the described load of system and system loading.
11, the device of reduction multi-core symmetric multiprocessing system power consumption according to claim 7 is characterized in that, described statistic unit comprises:
Statistical module is used for obtaining respectively the preload of working as of each CPU core of moving;
Computing module is used for the adding up when preload of described each CPU core, and obtains the mean value when preload of described each CPU core of moving, and with described mean value as current system loading.
12, the device of reduction multi-core symmetric multiprocessing system power consumption according to claim 8 is characterized in that, described operating unit also comprises:
First message transmission module, be used for when described current system loading during less than the idle threshold value of described system loading, at least one CPU core to described operation sends message on hold, makes the CPU core of described operation after receiving described message on hold, stops reading system directive.
13, the device of reduction multi-core symmetric multiprocessing system power consumption according to claim 9 is characterized in that, described operating unit also comprises:
Second message transmission module, be used for when described current system loading is had much to do threshold value greater than system loading, send wakeup message at least one CPU core that is in suspended state, make the described CPU core that is in suspended state after receiving described wakeup message, restart reading system directive.
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CN102445978B (en) * 2010-10-12 2016-02-17 深圳市金蝶中间件有限公司 A kind of method and apparatus of management data center
CN102445978A (en) * 2010-10-12 2012-05-09 深圳市金蝶中间件有限公司 Method and device for managing data center
CN102841808B (en) * 2011-06-21 2017-12-08 技嘉科技股份有限公司 The enhancing efficiency method and its computer system of computer system
CN102841808A (en) * 2011-06-21 2012-12-26 技嘉科技股份有限公司 Computer system and method for improving efficiency of computer system
WO2013013408A1 (en) * 2011-07-28 2013-01-31 天津海润恒通高性能计算系统科技有限公司 Method and device for reducing power consumption of pc-architecture software radio device
CN102520782A (en) * 2011-12-15 2012-06-27 江苏中科梦兰电子科技有限公司 Power supply management method based on automatic adjustment of processor nuclear number
CN108763129A (en) * 2011-12-22 2018-11-06 英特尔公司 The asymmetry energy multicore architecture of instruction set architecture (ISA) having the same
CN108763129B (en) * 2011-12-22 2021-12-07 英特尔公司 Asymmetric performance multi-core architecture with identical Instruction Set Architecture (ISA)
US9436266B2 (en) 2012-08-30 2016-09-06 Huawei Device Co., Ltd. Method and apparatus for controlling central processing unit in a group of central processing units by acquiring power consumption factors for each central processing unit and comparing a mean of power consumption factors with a threshold
CN103037109B (en) * 2012-12-12 2015-02-25 中国联合网络通信集团有限公司 Multicore equipment energy consumption management method and device
CN103037109A (en) * 2012-12-12 2013-04-10 中国联合网络通信集团有限公司 Multicore equipment energy consumption management method and device
CN103150005A (en) * 2013-03-01 2013-06-12 福州瑞芯微电子有限公司 Multi-core structure for asymmetric low-power mobile device
CN103793041A (en) * 2014-02-21 2014-05-14 珠海全志科技股份有限公司 Power management method and device of multi-core symmetrical multi-processing-system
CN103870338A (en) * 2014-03-05 2014-06-18 国家电网公司 Distributive parallel computing platform and method based on CPU (central processing unit) core management
CN105608049A (en) * 2015-12-23 2016-05-25 魅族科技(中国)有限公司 Method and device for controlling CPU of intelligent terminal
CN105700664A (en) * 2016-01-17 2016-06-22 苏黎 Mobile terminal power saving method and mobile terminal
CN105700664B (en) * 2016-01-17 2019-03-26 创启科技(广州)有限公司 A kind of method and mobile terminal of electricity saving of mobile terminal
CN107193229A (en) * 2017-04-06 2017-09-22 联想(北京)有限公司 A kind of control method and electronic equipment
CN108958449A (en) * 2017-05-26 2018-12-07 中兴通讯股份有限公司 A kind of CPU power consumption method of adjustment and device
CN113221611A (en) * 2020-02-05 2021-08-06 丰田自动车株式会社 Emotion estimation device, method, program, and vehicle
CN113221611B (en) * 2020-02-05 2024-03-15 丰田自动车株式会社 Emotion estimation device, method, program, and vehicle

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