WO2011083160A2

WO2011083160A2 - Micro-electromechanical semiconductor component and method for the production thereof

Info

Publication number: WO2011083160A2
Application number: PCT/EP2011/050211
Authority: WO
Inventors: Reinhard Senf
Original assignee: Elmos Semiconductor Ag
Priority date: 2010-01-11
Filing date: 2011-01-10
Publication date: 2011-07-14
Also published as: US20130087864A1; US9126826B2; EP2523896A2; WO2011083158A3; WO2011083162A3; US20130200439A1; WO2011083161A2; EP2524390B1; US8975671B2; US20130087865A1; US20130193529A1; US20130087866A1; CN102742012B; WO2011083158A2; WO2011083159A3; EP2523895B1; WO2011083161A3; US20150166327A1; EP2524198B1; US8841156B2

Abstract

The micro-electromechanical semiconductor component is provided with a first silicon semiconductor substrate (16) having an upper face, into which a cavity (18) delimited by lateral walls and a floor wall is introduced, and having a second silicon semiconductor substrate (13) comprising a silicon oxide layer (14) and a polysilicon layer (15) applied thereon having a defined thickness. The polysilicon layer (15) of the second silicon semiconductor substrate (13) faces the upper face of the first silicon semiconductor substrate (16), the two silicon semiconductor substrates are bonded, and the second silicon semiconductor substrate (13) covers the cavity (18) in the first silicon semiconductor substrate (16). Grooves (19) that extend up to the polysilicon layer (15) are arranged in the second silicon semiconductor substrate (13) in the region of the section thereof that covers the cavity (18).

Description

Microelectromechanical semiconductor device and method for setner manufacture

The invention relates to a microelectromechanical semiconductor component and to a method for the production thereof. Such a Haibieiteerbauelement can be used for example as a pressure sensor or acceleration sensor. In this case, the microelectromechanical semiconductor component should be compatible with conventional semiconductor production methods. In particular, the microelectromechanical semiconductor component should be a CMOS-compatible micromechanical component with low power consumption, high production accuracy and high precision. It is known, using lithographic processes, to produce semiconductor components which, in addition to electrical functions, also perform mechanical functions. For example, it is possible to produce microelectromechanical semiconductor components with reversibly deformable mechanical elements. An example is a semiconductor device having a cavity that is covered by a flexible top wall or membrane. To achieve consistent, reproducible properties of such semiconductor devices, it is essential, inter alia, that the thickness of the membrane is precisely adjustable in terms of process technology and reproducible. The object of the invention is to provide a microelectromechanical semiconductor component which has a reversibly deformable element whose mechanical function can be precisely predefined and reproducibly produced. Furthermore, it is an object of the invention to specify a production method for such a microelectromechanical semiconductor component.

To solve this problem, a microelectromechanical semiconductor component is proposed with the invention, which is provided with a first silicon semiconductor substrate having an upper surface into which a cavity bounded by sidewalls and a bottom wall is inserted, and

a second silicon semiconductor substrate having a silicon oxide layer and a thickness of Polysiüziumschicht defined thickness, wherein the second silicon semiconductor substrate is bonded with its polysilicon layer of the top of the first silicon semiconductor substrate facing the latter and the second silicon semiconductor substrate, the cavity in the first silicon Covered and covered

- Wherein are arranged in the second silicon semiconductor substrate in the region of the cavity-covering portion of trenches extending to the polysilicon layer.

To achieve the above-mentioned object, there is further provided a method of manufacturing a microelectromechanical semiconductor device having the following steps;

Providing a first silicon semiconductor substrate with a top side, introducing a cavity into the top side of the first silicon semiconductor substrate, wherein the cavity is defined by sidewalls and a bottom wall in the first silicon semiconductor substrate,

Providing a second silicon semiconductor substrate having a silicon oxide layer and a thickness of polysilicon layer deposited thereon and forming an upper side of the second silicon semiconductor substrate,

Bonding the polysilicon layer of the second silicon semiconductor substrate to the top of the first silicon semiconductor substrate and

Introducing trenches into the second silicon semiconductor substrate in the region of its cavity-covering section,

wherein the trenches are made by etching and extend to the PolysiSizium- layer. An alternative manufacturing method for a microelectromechanical semiconductor device comprises the following steps:

Providing a first silicon semiconductor substrate having a top, introducing a cavity into the top of the first silicon semiconductor substrate, wherein the cavity is defined by sidewalls and a bottom wall in the first silicon semiconductor substrate,

wherein the trenches are made by etching and extend to the polysilicon layer,

- And bonding the polysilicon layer of the second silicon Halbieitersub- strats with the top of the first silicon semiconductor substrate.

The microelectromechanical semiconductor component according to the invention is a component which is produced by bonding two silicon semiconductor substrates (the so-called handie wafer and the so-called device wafer). In the first silicon semiconductor substrate, a cavity is first formed, which is open to the top of the Halbieitersubstrats. This one-sided open cavity is then covered with the help of the second silicon Halbieitersubstrats and thus closed. The cavity-covering section of the second silicon semiconductor substrate serves as a membrane which deforms under the influence of mechanical forces or under the influence of external pressures. This construction can be used, for example, as an absolute pressure sensor; However, the invention is not limited to such pressure sensors. Thus, it is possible, for example, to use the inventive structure also for use in a differential pressure sensor. The same applies to the application of the invention in acceleration sensors. Thus, the deformation of the membrane is a measure of the forces acting or the pressure applied. Crucial for good reproducibility and equalization of the functionality of a plurality of structurally identical semi-precious construction elements according to the invention is that the membrane has an exact, previously predetermined thickness. It is known to introduce trenches into the cavity covering portion of the semiconductor substrate in semiconductor device constructions of the aforementioned type in order to increase the flexibility of the membrane and in particular the flexibility of its connection to the region of the semiconductor substrate around the cavity. These trenches are conventionally realized by etching techniques. The depth of the trenches is adjusted by the duration over which etching takes place, which, however, is possible only with limited accuracy.

According to the invention, a polysilicon layer produced on the second silicon semiconductor substrate during the manufacturing process is used to determine the thickness of the membrane (at the locations where the trenches are located). For example, polysilicon layers can be adjusted very precisely in terms of their thicknesses in CMOS processes. In one of the later etching processes for creating the trenches, the polysilicon layer additionally acts as an etch stop, as it were, and thus fulfills two functions. First, it serves to limit the "deep etching" and on the other hand, it represents the thickness of the membrane covering the cavity.

In order to be able to better bond the two silicon semi-conductor substrates together, it is advantageous if at least the upper side of one of the two silicon semi-conductor substrates is provided with a silicon oxide layer. Conveniently, this silicon oxide layer is deposited on top of the first silicon semiconductor substrate (the handle wafer) before the cavity is formed. But also on the polysilicon layer of the second silicon semiconductor substrate, an (possibly extremely thin) silicon oxide layer could be located. For metrological detection of a bending of the membrane, it is expedient to form after the bonding of the two silicon Halbieitersubstrate using an example CMOS process electrical / electronic components that are sensitive to mechanical stress. In addition to these components, however, general circuit-technical elements can then also be realized, specifically in the second silicon semiconductor substrate (the so-called device wafer), as is known, for example, from CMOS processes. The formation of these components sensitive to mechanical stress (as well as of the other circuit components) in the device wafer is less relevant to the invention, since at this time the poly silicon layer is already applied and thus the thickness of the membrane is fixed.

The invention will be explained in more detail with reference to the drawing. In detail, they show:

1 process for the production of a structure according to the invention:

a) raw wafer

b) oxidation and window opening

c) etching of the cavity

d) bonding the top wafer (the CMOS process follows, which will not be shown separately)

e) etching the trenches (according to the CMOS process), FIG. 2 shows a three-dimensional simplified section through a pressure sensor which was produced according to the process from FIG.

Fig. 3 Alternative second process for the preparation of an inventive

Structure:

a) raw wafer

b) oxidation and window opening

c) etching of the cavity d) Bonding of the handle wafer {the CMOS process follows on the top wafer with cavity, which is not shown separately) e) etching of the trenches (after CMOS process).

FIG. 4 shows a three-dimensional view of a simplified section through a pressure sensor that has been produced according to the process from FIG. 3.

Fign, 5 to 10

Alternative third process for producing a structure according to the invention:

a) raw wafer

b) oxidation

c) applying a polysilicon layer and anoxidation

d) 2. Raw wafer

e) oxidation and opening of a window

f) etching of the cavity

g) bonding the handle wafer

h) Grinding (the CMOS process follows on the top wafer with cavity, which is not shown separately)

i) etching the trenches (CMOS process)

j) Three-dimensional simplified section through a pressure sensor, which after the process of FIGS. 5 to 9 was made.

Fig. 11 Example of the layout of a transistor.

Fig. 12 interconnection of four transistors to a Wheatstone bridge (operation of the transistors as resistors).

Fig. 13 Exemplary interconnection of four transistors and two others to a Wheatstone bridge with reference voltage source.

14 shows layout example for a Wheatstone bridge, 15 Connection of eight transistors to a Wheatstone bridge with a second short-circuited Wheatstone bridge as a reference voltage source. FIG. 16 Placement example of four Wheatstone bridges according to FIG. 12 on a sensor die with trench structure.

17 placement example! of four Wheatstone bridges with four Wheatstone bridges as stress-free references according to Fig. 15 on a sensor die with trench structure (The voltage references are not shown for clarity.) For each Wheatstone bridge pair, in principle, a third, short-circuited Wheatstone is sufficient Bridge next to the stress-free reference bridge, so 12 Wheatstone bridges would be found on the die).

Fig. 18 layout example for a differential stage.

Fig. 19 Schaitungsbeispie! for a circuit with a differential amplifier and a reference differential amplifier as a reference voltage source.

Fig. 20 view of an exemplary membrane geometry with square

grave system

a) supervision

b) Bottom view.

Fig. 21 view of an exemplary membrane geometry with square

Trench system and diamond-shaped centra!

a) supervision

b) Bottom view. Fig. 22 perspective view of an exemplary membrane geometry with square trench system, which was phased in the corners, and rhombic central part

a) supervision

b) Bottom view.

Fig. 23 view of an exemplary membrane geometry with square

Trench system and webs in the corners

a) supervision

b) Bottom view.

Fig. 24 View of an exemplary membrane geometry with round trench system and round cavity

a) supervision

b) Bottom view.

Fig. 25 view of an exemplary membrane geometry with square

Trench system and not solid webs

a) supervision

b) Bottom view.

FIGS. 26 and 27

Sensors with additional trenches.

FIG. 28 Boss (central membrane stiffening) with mass reduction by etched supporting structure 97. FIG.

FIGS. 29 and 30

Exemplary differential pressure sensors, which arise from the above sensors by etching an opening 119. Fig. 31 View of an exemplary membrane geometry with round cavity, round outer edge of the trench system and diamond-shaped central part

a) supervision

b) Bottom view.

FIG. 32 A view of an exemplary round-well membrane geometry, round outer edge of the trench system and diamond-shaped central part and additional trenches to protect the system against propagation of externally imposed stress

a) supervision

b) Bottom view.

33 shows a circuit diagram of a bridge according to FIG. 34 and FIG. 35 as a measuring bridge with

Reference voltage source,

Fig. 34 Layout example of a bridge with common gate.

Fig. 35 Further layout example of a bridge with a common gate.

Fig. 36 equivalent circuit diagram of a transistor according to Fig. 37 as a measuring bridge with

Referenzspannungsqueiie.

37 shows a layout example of a particularly small four-terminal measuring bridge transistor.

Fig. 38 A detail view.

Fig. 39 Schematic representation of three process steps for generating a

Siiizium semiconductor substrate having a Poiysiliztumschicht on a silicon oxide layer, wherein both layers are deposited on the actual silicon semiconductor substrate. 40 shows three process steps for the schematic representation of the formation of the cavity in a silicon Haiblettersubstrat with a Süiziumoxid- layer at its top. FIG. 41 The construction after the bonding of the two silicon semiconductor substrates produced according to FIGS. 39 and 40.

42 Further production steps (schematic) to obtain a pressure sensor with a membrane of defined thickness spanning the cavity.

43 A perspective view of the according to the previous FIG

The invention is illustrated by the example of a pressure sensor for the detection of low pressures. A first essential point for the invention is the preparation of the pressure sensor cavity 4 before the processing of the CMOS steps. This allows any standard CMOS processes to be performed on the surface. This makes it possible as a second essential step to place CMOS transistors on a membrane so that they are within a range of optimum mechanical stress when the membrane is deflected. This point can be determined by analytical considerations and / or finite element simulations. A first exemplary process is shown in essential steps in FIGS. 1 and 2 shown. Variations of this first process will be described later.

The basic manufacturing process begins with a first wafer 1, which is preferably of the same material as a second wafer 5 used later. On this wafer, a layer 2 is deposited, which serves the later connection. For silicon wafers, these are formed as a Si0 ₂ - Layer 2 by oxidation. In this layer, a window is opened and the subsequent pressure sensor cavity 4 is etched, (FIG. 1 c). This etching is preferably carried out by a D IE or plasma etching step, since in particular the former leads to straight walls 3.

The upper wafer 5 is also provided with an oxide layer and bonded and ground on the first wafer 1. (FIG. 1 d) The bonding process is preferably carried out in a vacuum. This leads to a cavity which is not filled with gas and excludes a later temperature dependence of the internal pressure in the cavity. This process creates in the area of the cavity 4 a membrane whose thickness is determined by the grinding process.

The result is a wafer package that can be used in a standard CMOS process or standard bipolar process like normal SOI material.

After the CMOS processing, which need not be described here in more detail, since the processing of the standard literature can be taken, further micromechanical structures 6 can then be etched into the surface 11. (Fig le).

In the case of the exemplary pressure sensor, these micromechanical structures 6 are, for example, trench structures which form approximately closed rings or quadrilaterals which are interrupted only by a few webs 8 (FIG. 2). This creates in the middle of a central plate 12 - Boss called - which represents a stiffener due to the greater thickness. The bottom of the trenches 6 is a membrane of lesser thickness. This typically absorbs significantly less force. It is important here that the outer edge of the trench 6 is sufficiently far away from the wall of the cavity 3, since otherwise small adjustment errors in the production would have a great effect on the mechanical stress and thus on the measurement result. this is a Significant innovation, the manufacturing reproducibility of the sensor properties would thus suffer, resulting in increased calibration effort and thus corresponding costs would result, Thus, the pressure on the central plate 12 is derived almost exclusively via mechanical tension on the webs 8. Therefore, it makes sense to place on these webs the components 9, which are sensitive to mechanical stress and should detect this stress. These are then connected via lines to the terminals 10. The trenches thus adjust the mechanical stress field compared to the stress-sensitive electronic components.

Alternatively, the cavity can also be etched into the upper wafer. This is shown in FIGS. 3 and 4 are shown correspondingly in steps a to f.

A significant disadvantage of the two preceding processes is the lack of a natural etching stop for the etching of the trenches 6, Therefore, the thickness of the membrane at the bottom of the trenches 7 is difficult to control, the relative error is therefore relatively high, resulting in a scattering of the sensor - parameter leads.

A third exemplary process that does not suffer from this disadvantage is illustrated in essential steps in FIGS. 5 to 10 and steps a to j shown. The manufacturing process begins with a first wafer 13, which is preferably of the same material as the second wafer 16 used later. On this wafer, a connecting layer, in the case of silicon wafers a Si0 ₂ layer 14 On this Si0 ₂ layer, a further layer, such as a poly-silicon layer or amorphous silicon layer 15 is deposited and superficially oxidized (Fig. 5c The deposition of this layer can typically be very well controlled and is therefore much more precise in its result than the etching of the trenches in the first two described. The second wafer 16 is likewise oxidized, so that an oxide layer 17 is likewise formed. In this at least one window is opened and the later cavity 18 is etched. This etching is preferably carried out by means of a DRIE etching step, since this leads to straight walls (FIG. 6f). The etching of the cavity 18 into the upper wafer 13 will not be described any further in the following, but is of course also possible.

The upper first wafer 13 is bonded to the second wafer 16 (FIG. 7) and then ground (FIG. 8). In this case, the bonding process is preferably carried out again in a vacuum in order to preclude a later temperature dependence of the internal pressure in the cavity 18. This creates a diaphragm in the region of the cavity whose thickness is determined by the grinding process. The result is again a wafer package, which in principle can be used like a standard wafer in a standard CMOS process or standard bipolar process.

After CMOS or bipolar processing, as in the previously described processes, further micromechanical structures, e.g. trenches

19 are etched into the surface 24 (FIG. 10).

In the case of a pressure sensor, these micromechanical structures 19 are again trench structures, for example, which form approximately closed rings or quadrilaterals which are interrupted only by a few webs 20. This results again in the middle of a central plate 21, which represents a stiffener due to the greater thickness. The bottom of the trenches 19 is a membrane of lesser thickness 25. This takes again virtually no forces. In contrast to the first method, the additional layer 15 and subsequent additional oxide layer 14 can stop the etching of the trenches 19 more precisely than in the first method. This allows the e! electromechanical properties can be manufactured more precisely with better repeat accuracy, which significantly reduces the calibration costs.

As in the case of the first process result, the pressure (see FIG. 10) is discharged to the central plate 21 virtually exclusively via the webs 20. Therefore, it is again useful to place on these webs the electronic components 22, which are sensitive to mechanical stress and should detect this stress. These are then connected via lines to the terminals 23.

Of course, it is also conceivable to produce the additional layer 15 instead of by deposition by bonding and grinding a third wafer. Furthermore, it is conceivable to integrate more than one buried isolated layer of the type of additional layer 15 in a wafer package.

With a wafer package produced in this way, in turn, stress-sensitive sensors can be fabricated on the membrane after their manufacture prior to fabrication of the trenches (6 or 19). For this purpose, sensitive electronic components are manufactured and interconnected on the respective surface 11, 24 in a CMOS or bipolar process. For a CMOS process, a p-doped substrate is preferably used. For example, piezoresistive resistors can be placed on the webs 20.8 and interconnected as a Wheatstone bridge. However, these have the disadvantage that they must first be brought to operating temperature and consume relatively much electrical energy in a measurement, they are therefore unsuitable for energy self-sufficient systems. The invention thus also has the object, as already described above, of eliminating this problem. Therefore, it makes sense to use active amplifying elements such as bipolar transistors and MOS transistors instead of such simple electronic components. These can also be interconnected as a Wheatstone bridge, but do not require a warm-up time and consume less energy. An exemplary interconnection is shown in FIG. 12.

Here are four p-anai transistors 85,86,87,88 a Wheatstone bridge, which can be tapped at the two terminals 89,90. Here, the transistors 87 and 85 are constructed similarly oriented and the transistor pair 88,86 also the same orientation, but perpendicular to the transistor pair 87,85. However, this circuit is very sensitive to manufacturing errors.

In order to be able to produce such a MOS transistor circuit with sufficient accuracy, it is necessary to design the transistors such that the electrically active part is self-adjusting. Fig. 11 shows the exemplary layout of such a self-aligned transistor. In this case, the p + contact implantations 80 and 79 are shaded by the poly gate 81 in such a way that the same transistor channel length and transistor width always remain at offset. Likewise, poly gate 81 shades the n + channel stop implant. The gate is connected via a low-resistance poly line.

It is thus ensured that the transistors of the same design geometry have an identical geometry in their physical realization. This is essentially determined by the design of the poly-silicon surface.

In order to bring the transistors in the respective correct operating point, it is expedient to integrate a reference voltage source with the pressure sensor. In the example (FIG. 13), the exemplary reference voltage source consists of the transistors 30 and 29. The transistors 31, 32, 33, 34 again form a Wheatstone bridge, which can be tapped off at the terminals 28, 36. Both are connected as MOS diodes by the gate with drain connected is. The reference voltage of transistor 30 is connected to the gate of transistor 31 and 33. The reference voltage of transistor 29 is connected to the gate of transistors 32 and 34. In the example of FIG. 13, the drain of transistor 29 is at the potential of terminal 26. This terminal is typically grounded in p-channel transistors. Therefore, the drain contacts of transistors 32 and 34 are also connected to this terminal. The transistors are preferably made with the same geometric dimensions. The layout example of a local Wheatstone MOS bridge is given in FIG. If the transistors are arranged as in FIG. 14, the transistors 31 and 34 are oriented identically. The transistors 23 and 33 are also equally aligned with each other, but perpendicular to the transistors 31 and 34. Fig. 14 shows an exemplary arrangement.

In order to keep the mechanical strains on the membrane small, this is not provided with a field oxide but only with a very thin and very thin gate oxide of a few nm and a suitable passivation. If the application of a field oxide is unavoidable, a high degree of symmetry makes sense, in order to keep parasitic effects the same on all stress-sensitive components. The passivation can, for example, consist of silicon nitride in the case of a silicon pressure sensor. This has a low hydrogen diffusion coefficient and therefore protects the device against ingress and egress of protons, which can lead to a drift of the p-resistors and p-channel transistors, in particular with permanently applied voltage and high operating temperature. This effect is known as NBTI. In order to avoid any kind of mechanical strain, no field oxide or the like is made near mechanical components or even on them. Therefore, in particular, the diaphragm of the exemplary pressure sensor is only covered with the gate oxide and the passivation layer silicon nitride. Furthermore, the feed lines on the die are preferably not in metal, which has a high coefficient of thermal expansion, in particular with respect to silicon, but in the wafer material, in the case of silicon as highly doped layer or as heavily doped poly-silicon or, unless otherwise possible, designed as highly doped amorphous or polycrystalline silicon. The drain and source leads of transistors 26, 28, 35, 36 are implemented in this example (FIG. 14), for example as p + implantations 36, 35, 26, 28. The gates and their leads are exemplified in poly-Siiizium executed 33,39,31 and 32,34,38. In area 40, which is n-doped, no channel is formed due to the field swelling in the example. This is possible only at the edge of the poly gates. Therefore, an n + channel stopper 37 is implanted which cuts off parasitic channels. This exemplary all-silicon design thus makes it possible to build the element sensitive to mechanical stress very small and insensitive to manufacturing tolerances and thermo-mechanical stress by foreign materials, which further reduces the sensitivity to inhomogeneous stress distributions. Despite these efforts, there are still marginal differences between the materials. Therefore, when designing the electronic components on the die, and especially those located on the membrane, attention is paid to maintaining the greatest possible symmetry. Therefore, it makes sense to place components that are used for differentiation - for example those in Wheatstone bridges or differential amplifiers - as close to each other as possible in order to minimize the influence of manufacturing inhomogeneities.

Fig. 15 shows another expression of the Wheatstone bridge. Here, the reference voltage with which the bridge is operated consisting of the transistors 31,32,33,34, from one of these same bridge, consisting of the transistors 30,29,55,56 generated. Conveniently, this is the same layout module! related. The reference bridge is short-circuited and thus generates the reference voltage 35, with which the transistors 31,32,33,34 of the first bridge are driven. The second bridge is placed on the substrate as far away from the mechanical stresses as possible but still as close to the first bridge as possible. The latter serves to keep the manufacturing fluctuations between the two bridges low. The first bridge will be incorporated into the point of appropriate mechanical stress ses placed. This is the point at which the highest possible mechanical stress results from deflection of the exemplary membrane, but this stress is still so homogeneous that manufacturing fluctuations can not be noticeable too strongly.

To further minimize misalignment influences, it may be useful to place multiple bridges on a die. This can be done, for example, by a placement as shown in FIG. 16. Here, the possible placement of four bridges according to FIG. 12 is shown. Fig. 17 shows the placement of the bridges and reference bridges according to Fig.15. In an arrangement according to FIG. 17, three levels of compensation arise. In the first level, that of the four transistors, the direction of mechanical stress is detected. This is done by comparing the values of perpendicular to each other transistors. In the next level, these four transistors in their entirety 43 are compared with four other identically arranged transistors 58 which are ideally located on the neutral fiber, close to the first four 43 but in a mechanically less stressed region. As a result, the mechanically induced offset of the bridge is distinguished from that by adjusting during production. If the sensor is symmetrical, then it makes sense to install another eight transistors according to the symmetry axis. in the

For example (Figure 17), these are four pairs of sensors 44, 57, 41, 60, 42, 59, 43, 58, each pair consisting of two by four transistors.

Theoretically, the placement of a single transistor already suffices for the stress measurement. In this case, however, all manufacturing errors are already having a massive impact.

A first alternative layout arrangement is shown in FIG. FIG. 33 shows the associated interconnection with a reference voltage source consisting of the transistors 108, 109. Here, the four transistors 104, 105, 106, 107 connected to a Wheatstone bridge have a common gate 110, which simplifies the layout. The bridge is connected via terminals 103 and 102 with Voltage supplied. In the case of mechanical stressing of the bridge, an electrical voltage occurs at the clamps 111, 112, FIG. 35 shows a further development of this bridge. If the channel stopper 37 in the middle of the bridge is omitted, a transistor 115 with four similar to a field plate results The equivalent circuit of transistor 115 is shown in FIG. 36. Then transistors 114 and 113 are added which, on the one hand, increase the power consumption 114 and, on the other hand, reduce the signal level 113. However, the design and thus the The need for space is minimized, which is very useful in some applications.

An alternative layout arrangement of the transistors of a sensor element 41, 42, 43, 44, 57, 58, 59, 60 is shown in FIG. Here, the four transistors 44,45,46,47 are arranged in a star shape. They have a common drain contact 50, which is connected via a feed line 49 to a power source which is not located on the diaphragm of the pressure sensor. The gates of transistors 44, 45, 46, 47 are connected to a poly line 48. The source contacts are each connected to a heavily doped p + line 51,52,53,54. The four transistors are, for example, parts of a differential amplifier, as shown in FIG. 19. All other transistors of Fig. 19 are not on the membrane but the substrate without underlying cavity. It will be appreciated that half of the four transistors, such as transistors 45 and 44, would already be sufficient to form a differential amplifier. For reasons of symmetry, however, the variant with four transistors makes sense,

The circuit consists of two differential amplifiers. The left-hand one (transistors 65 to 73) is short-circuited in the output and input and operates as a reference voltage source for the operation of the second one. These transistors are free of mechanical stress in an area. The previously discussed transistors 44, 45, 46, 47 form the differential stage with the respectively associated "working resistances" 61, 62, 63, 64. The current source 74 energizes the differential amplifier formed in this way. The transistor 74 is in this example! an n-channel Transistor. The outputs of the differential amplifier 77,78 mirror in operation an unbalancing of the transistors 44,45,46,47 due to mechanical stress. Since transistors 46 and 44 are oriented differently than transistors 45 and 47, uniaxial mechanical stress leads to an output signal 77, 78. The differential amplifier is brought to the operating point in this example by an identically constructed shorted reference differential amplifier. This and the transistors 61,62,63,64,74 are expediently not on the membrane but in a region of the die which is almost free from mechanical stress. In order to ensure that the electrical parameters of the components are in a stress-free state, they should nevertheless be placed as close as possible to the other transistors. Appropriately, therefore, the orientation and the layout of all elements as close to each other in the same orientation and the same layout is performed so that in particular the Stromspiegeipaare are well matched.

The Fign. 20 to 25 show different designs of the trenches and cavities. When designing Race Track 6 and Cavity 3, several factors must be considered:

1. A suitable distance between the race track outer wall and the cavity wall shall be maintained,

2. The circle passing through the outer points of contact of the ridges with the race track outer wall shall not be cut by the race track outer wall as this would distort the mechanical stress field in the boss 12. 3, The connecting lines between the foot points of the webs 8 on the boss 12 must not be cut by the outside edge of the boss, as this would result in a distortion of the mechanical stress field in the boss. 4. The construction ought to have as few corners as possible, since these can cause very high stresses which can lead to nonlinear effects and bistability.

This is offset by requirements with regard to bursting pressure. If the race track surface is too big, the race track membrane breaks faster.

For decoupling the membrane of mechanical stress, which is caused by the construction and connection technique, it is therefore useful, for example, to make another trench 93 around the sensor. (Fig. 26) and so produce a virtually larger race track membrane without the mentioned risk of breakage.

Here, the sensor is suspended on webs 94. These are ideally no extension of the webs 8, where the boss 12 is attached. As a result, mechanical stress is transmitted only indirectly from outside to the sensors 9.

This principle can be continued by a further trench 95 and further webs 96 (FIG. 27).

The construction with the help of a boss leads to an increased sensitivity to seismic loads. This sensitivity can be reduced by reducing the boss mass (FIG. 28). In this case, a suitable support structure is etched in the boss 97. There are webs stand, which produce a sufficient area moment of inertia with a suitable choice to ensure mechanical stability. The sensor 22 is placed as before on a web 20 which interrupts the race track trench 19. If a differential pressure sensor is to be produced instead of an absolute pressure sensor, this can be done by subsequent etching of an opening 119 in the lower wafer. FIGS. 29 and 30 show corresponding exemplary embodiments. The advantage of such a design lies in the small opening and thus in the only very small loss of stability compared to a sensor in which the cavity was etched from the rear side.

The bond system is in progress! made of metal with a significantly different thermal expansion coefficient. Furthermore, the metal leads to hysteresis effects. Therefore, it makes sense to decouple the bond pads 10 as far as possible from the rest of the sensors. This can be done by mechanical guard rings in the form of trenches 157, which for example are placed around the pads or parts to be protected as far as possible (FIG. 32).

Based on the Fign. 39 to 43 will be discussed below with reference to the method according to the invention for producing a microelectromechanical semiconductor component according to the invention. Here, however, reference is also made to the above.

According to FIG. 39, a silicon oxide layer 14 is deposited on a first silicon semiconductor substrate 13 (the so-called device wafer - see FIG. 39 a) (see FIG. 39 b). A polysilicon layer 15 is then applied to this silicon oxide layer 14 (see FIG. 39c). The thickness of these polysilicon shears 15 can be controlled very precisely in terms of process technology.

On a second silicon semiconductor substrate 16 (the so-called handle wafer - see FIG. 40d), a silicon oxide layer 17 is oxidized (see FIG. 40e). A cavity 18 is then etched into the silicon oxide layer 17 and the semiconductor substrate 16 (see FIG. 40f). The two according to FIGS. 39 and 40 prepared wafers are then bonded together as shown in FIG. 41. In this case, the polysilicon layer 15 of the first silicon semiconductor substrate 13 is located on the silicon oxide layer 17 of the second silicon semiconductor substrate 16. If appropriate, an extremely thin silicon oxide layer may have previously been applied to the polysilicon layer 15.

After bonding, the silicon semiconductor substrate 13 of the device wafer is returned (see Fig. 42h).

After grinding back the device wafer, a CMOS process is performed to structure the semiconductor device and provide it with the required mechanical and electrical functions. For this purpose, trenches 19 are etched in the device wafer (see FIG. 421). The silicon oxide 14 of the device wafer serves as a (first) etch stop. Subsequently, a second two-stage etching process takes place (see FIG. 42j) in order to etch the trenches 19 as far as the polysilicon layer 15. After the first stage, during which the silicon material is etched, the second stage, in which the silicon oxide is etched, follows, wherein the polysilicon layer 15 in turn acts as an etch stop for this silicon oxide etching step. The result of the CMOS process and the process steps described above is shown in FIG. In the handle wafer 16 is the cavity 18. On the handle wafer surface is the silicon oxide layer 17 and thereon the polysilicon layer 15, on which in turn the polysilicon layer 14 and then the monocrystalline layer 13 as the remainder of the ground down device wafer located. In these, the trenches 19 are etched. These delimit an area on the membrane 21. In this example, the trenches 19 are interrupted by webs 20. On these are, for example, stress-sensitive electrical or electronic components 22, which are connected via lines 24 with pads 23. It is essential that the thickness 25 of the remaining in the trenches 19

Polysilicon layer 15 can be precisely controlled. As a result, the manufacturability is increased due to the higher precision. Further characteristics of the invention and an exemplary application can be described as follows;

1, photolithographically fabricated transistor on a doped substrate or in a doped well, wherein

i, the transistor is electrically connected only to materials having a similar coefficient of mechanical expansion as the substrate or tub in which it is placed,

iL the transistor is not or only in a very small mechanical Verbmdung with other materials in particular such materials with different mechanical properties than the substrate or the tub - this particular field oxides - is,

iii. the transistor has symmetries,

iv. the transistor is fabricated by lithography of various geometrically matched structures in different process steps, and

v. These geometrical structures, whose superimposition and interaction in the manufacturing process results in the transistor, are chosen such that process fluctuations within the process specification limits the changes in the geometries of the individual

Lithography step results in the form of fabricated geometric structures have little or no effect on the electrical and / or mechanical properties of the transistor, 2, transistor according to para. 1, which is a MOS transistor.

3. MOS transistor for the detection of mechanical stress, which has four channel connections. 4. MOS transistor according to para. 3, the fourfold rotational symmetry and a gate plate with just this symmetry and Kanalanschiüsse in one Arrangement with just this symmetry, without having to have a symmetry of the terminals of this gate plate. Transistor according to no. 1, which is a bipolar transistor. Transistor according to no. 1 to 4, which has a channel stopper. Transistor according to no. 1 to 4, whose source and / or drain regions are electrically connected by a highly doped region or low-resistance poly-silicon. Transistor according to Ziff 1 to 7, which is used for the detection of mechanical stress. Transistor according to Ziff, 1 to 8, which is used as an electrical resistance in particular in a measuring bridge. Transistor according to no. 1 to 9, which is a pnp transistor. Transistor according to no. 1 to 9, which is an npn transistor. Transistor according to no. 1 to 9, which is a p-channel transistor. Transistor according to no. 1 to 9, which is an n-anai transistor. Electronic circuit, the transistors according to one or more of the Ziff. 1 to 13 contains. Electronic circuit, which is in a functional relationship with a micromechanical device according to para. 41 stands. 16. Circuit according to para. 14 or 15, which includes discrete and / or integrated electronic components

17. Circuit according to para. 14 to 16, which is at least partially made by monolithic integration see integration.

18. Circuit according to para. 14 to 17, the at least two geometrically identically constructed transistors according to para. 1 to 13 contains. 19. Arrangement according to para. 18, which generates a signal suitable for measuring a different state in at least one physical parameter of the two transistors.

20. Circuit according to para. 19, where the physical parameter is mechanical stress and / or temperature

21. Circulation according to para. 18 to 20, wherein at least two of the transistors according to para. 1 to 13 are symmetrically arranged without viewing the Anschiussleitungen to each other.

22. Circuit according to para. 18 to 20, wherein for at least two of the transistors after one or more of the Ziff. 1 to 13, that their geometry can be made to coincide with one another by rotation through 90 ° without viewing the connection lines,

23. Circuit according to para. 14 to 22, the at least four transistors according to para.

1 to 13 contains.

24. Circuit according to para. 23, in which the four transistors are connected to a measuring bridge. SHARE according to no. 24, at the gate and source of at least one transistor according to no. 1 to 13 are short-circuited, circuit according to para. 24 or 25, wherein the gate of at least one of the transistors according to para. 1 to 13 is connected to a reference voltage source. Circuit according to para. 26, in which the reference voltage source a second, but short-circuited bridge according to para. 24 to 27 is. Circuit according to para. 27, in which the second measuring bridge of the first measuring bridge is the same and in particular in the dimensioning of the transistors and / or the Verschaitung and / or the manufactured geometry and / or in extreme cases, a geometric copy of the first measuring bridge, circuit according to no. 14 to 28, in which each two of the four transistors are aligned the same geometry, circuit according to no. 29, in which the transistors of the one transistor pair are oriented perpendicular to the other transistor pair, circuit according to Ziff. 30, in which the four transistors are arranged symmetrically in a square. Circuit according to para. 30, in which the four transistors are arranged symmetrically in a cross. Circuit according to para. 14 to 23 or 29 to 32, which includes at least one differential amplifier circuit. Circuit according to para. 33, wherein at least one of the transistors of at least one differential amplifier, a transistor according to para. 1 to 13 is. Circuit according to para. 33 or 34, which includes at least one reference voltage source coupled to at least a first differential amplifier. Circuit according to para. 35, in which the reference voltage source is a second, but short-circuited differential amplifier, a differential amplifier according to para. 33 to 35 is. Circuit according to para. 36, in which the second differential amplifier is the same as the first differential amplifier, specifically in the dimensioning of the transistors and / or the interconnection of the transistors and / or the fabricated geometry of the transistors and / or in extreme cases a geometric copy of the first differential amplifier. Circuit according to para. 14 to 37, at least a Tei! the same is simultaneously part of a micromechanical device. Circuit according to para. 38, in which at least part of the circuit is functionally connected to at least one micromechanical functional element in such a way that at least one mechanical parameter of at least one micromechanical functional element is coupled to the state function of the circuit or to at least one electrical parameter of the state function of at least one circuit part. Circuit according to para. 39, wherein the functional element is in particular a bar or web, a membrane, a resonator, a lip clamped on one or two sides or three sides, an aperture, a needle. Micromechanical device produced by lithographic processes and bonding, in particular bonding, at least two wafers, wherein

I. before the connection of the at least two wafers at least one mik.ro- mechanical functional element in the form of at least one surface structure on at least one surface of at least one of the two wafers have been applied, and

II. At least one of the micromechanical functional elements or surface structures produced in this way after the connection of the wafers in the vicinity of the interface between them within the resulting wafer package

III. at least one process for producing electronic components for producing at least one electronic component has been carried out on at least one surface of the resulting wafer package following the connection of the wafers, and

IV. At least one of the electronic components produced in this way is sensitive to at least one non-electrical physical quantity and should detect it and

V. this device is made self-adjusting. Micromechanical device according to para. 41, wherein at least one of the self-aligned components, a transistor according to para. 1 to 10 or part of a circuit according to para. 14 to 40 is. Micromechanical device according to para. 41 or 42, which is made of silicon. Micromechanical device according to para. 41 to 43, wherein at least one micromechanical functional element is at least one cavity. Micromechanical device according to para. 44, in which at least one cavity with at least one surface of the wafer package defines a membrane, micromechanical device according to para. 44 and 45, wherein at least one cavity has no oxides on its walls. Micromechanical device according to para. 41 to 46, wherein at least one micromechanical functional element is located on the surface of the device. Micromechanical device according to para. 47, wherein at least one micromechanical functional element is a web, a trench, a diaphragm, an aperture and a buried cavity or a blind hole. Micromechanical device according to para. 38, wherein at least one micromechanical functional element on the surface after performing a process, in particular a CMOS process, for the production of a transistor according to para. 1 to 13 or a circuit according to para. 14 to 40 was made. Micromechanical device according to para. 41 to 49, in which at least one micromechanical functional element was produced inter alia by using D IE or plasma etching processes. Micromechanical device according to para. 41 to 50, which can be used as a pressure sensor. Micromechanical device according to para. 44 to 51, wherein the geometric shape of at least one cavity with respect to the connection plane of the wafer symmetries 53. Micromechanical device according to para. 41 to 52, wherein on at least one surface of the wafer package, the trenches are made by DRIE or Piasma etching.

Micromechanical device according to para. 53, in which at least a subset of the trenches form a closed structure, for example a ring, an ellipse, a quadrangle, a star or the like, which are interrupted only in a few places by thin webs 8,20. 55. Micromechanical device according to para. 53 and 54, wherein at least a part of the trenches is arranged symmetrically to each other.

56, micromechanical device according to para. 52 and 55, at the symmetry axes of a part of the trenches and at least one cavity coincide or coincide with ideal preparation.

57. Micromechanical device according to para. 52, 55 and 56, wherein at least one of the trenches is in a mechanical functional relationship with at least one cavity

58. Micromechanical device according to para. 57, wherein the bottom of at least one of the trenches with at least one of the cavities results in a membrane dilution or an opening into this cavity. 59, micromechanical device according to para. 41 to 58, in the micromechanical functional elements of the top, in particular those in no. 47 to 58 mentioned trenches, with their shape defining edges do not lie over the shape defining edges of micromechanical structures of the bottom and micromechanical structures of the top.

60. Micromechanical device according to para. 59, in which the lever length 116 between the attachment point of a structure below 121, in particular particular, of a buried cavity 4, and the point of attachment of a structure above 119, in particular a trench 6, is larger than the smaller one of the vertical elevations 118 and 120 (see Fig. 38). Micromechanical device according to para. 44 to 60, in which at least one cavity is located within the body of the micromechanical device, in particular during production thereof within the wafer package, which is connected to the underside or upper side of the wafer package by at least one micromechanical functional element, in particular a tube. communicates. Micromechanical device according to para. 61, which can be used as a differential pressure sensor against a defined reference pressure or ambient pressure. Micromechanical device according to para. 61 and 62, which has at least one microfluidic functional element. Micromechanical device according to para. 63, in which at least one microfluidic functional element serves or can serve for the supply of media such as liquids and gases. Micromechanical device in which at least one microfiuidisches functional element according to para. 63 to 64 or a micromechanical radio ^¬ tion element according to para. 61 after performing a process, in particular a CMOS process, for the manufacture of a transistor according to para. 1 to 13 or a circuit according to para. 14 to 40 was made. Micromechanical device according to para. 1-65, in which a p-doped semiconductor material was used as at least a sub-substrate or substrate. Micromechanical device according to para. 1 to 65, where at least a! a substrate or substrate is an n-doped semi-conductor material! has been used.

Micromechanical device according to para. 44 to 67, in which there is present in at least one substrate a material modification, for example a SiO ₂ layer, which serves as an etching stop for the etching of at least one cavity.

Micromechanical device according to para. 53 to 68, in which a material modification 14 is present in at least one substrate which serves as an etching stop for the etching of at least a part of the trenches.

Micromechanical device according to para. 69, in which at least one material modification 15 is present in at least one substrate, which acts as a membrane in the region of the trenches.

Micromechanical device according to para. 70, wherein at least one material modification 15 of poly-silicon and / or amorphous silicon and was deposited on one of the wafer of the wafer package before the wafer bonding.

Micromechanical device according to para. 44 to 67 and 69 to 71, in which at least one cavity was etched time-controlled in at least one substrate.

73. Micromechanical device according to para. 53 to 68 and 70, in which at least part of the trenches were etched into the substrate in a time-con- trolled manner, 74. Micromechanical device according to para. 53 to 73, wherein prior to etching of the trenches a Halbieiterprozess for producing electrical functional eiemente was performed on at least one surface of the wafer package. Micromechanical device according to para. 74, which has at least one electrical functional element, which in the process according to para. 74 was made. Micromechanical device according to para. 75, wherein at least one electrical functional element, the function of an electrical line or a contact or a Durchkontaktterung or an electrical

Line insulation or a resistor or a transistor or a diode or a capacitor or a coil has. Micromechanical device according to para. 76, in which at least one of the functional elements at least one parameter - in particular electrical parameters - in response to mechanical variables, in particular tensile, compressive and shear stress changes. Micromechanical device according to para. 77, whereby this parameter change can be measured outside the sensor. Micromechanical device according to para. 77 and 54, wherein at least one of the functional elements is in a mechanical functional relationship with at least one web 8,20. Micromechanical device according to para. 77 and 36, in which at least one electronic function so opposite

a) at least one first micromechanical functional element, in particular a membrane (12 or 21),

b) at least two further, second micromechanical functional elements, in particular trenches (6 or 19), and c) at least one third micromechanical functional element, in particular a web (8 or 20),

wherein the functional elements according to a) to c) are in a mechanical functional relationship, is positioned on the third micromechanical functional element, in particular web, that it is at or near the point of maximum mechanical stress, if the first micromechanical functional element, in particular a membrane or an inertia mass (12 or 21), deformed, in particular deflected, becomes.

81. Micromechanical device according to para. 80, wherein at least a third micromechanical functional element, in particular a web is shaped so that this has a range of high homogenized mechanical stress in the case of deformation of the first micromechanical functional element, in particular a membrane or inertia.

82. Micromechanical device according to para. 81, wherein at least one electronic functional element is located at least one said place of high homogenized mechanical stress.

83. Micromechanical device according to para. 41 to 82, in which at least two wafers were made of different thickness,

84. Micromechanical device according to para. 41 to 82, wherein a wafer material is silicon or SOI material.

85. Micromechanical device according to para. 44-79 wherein the cavity is made prior to bonding three wafers in the lowermost wafer.

86. Micromechanical device according to para. 86, wherein the three wafers were made different thickness. 87. Micromechanical device according to para. 53 to 86, wherein at least one of the second mskromechanischen Funktionsseiemente is a trench (6 or 19), whose width is not constant.

88. Micromechanical device according to para. 54 to 87, in which at least one web does not divide a trench (6 or 19) but only projects into it (for example Fig. 25).

89. Micromechanical device according to para. 54 to 88, in which between the webs and trenches an area is created on a membrane which is suspended from the webs, quadrangular (eg Fig. 20 or 23), diamond - shaped (eg Fig. 21 or Fig. 22) or round (eg Fig 24)

90. Micromechanical device according to para. 89, wherein at least one trench has no bottom and is therefore associated with at least one avitat.

91. Micromechanical device according to para. 41 to 90, which can be used as a pressure sensor and / or Beschieunigungssensor.

92. Micromechanical device according to para. 41 to 91, the symmetrically arranged mechanical first Funktionsseiemente, in particular webs, which are connected to at least one further second micromechanical Funktionsseiement, in particular a membrane or inertia and on each of which the same circuit parts of a circuit according to para. 14 to 40 are located.

93. The micromechanical device and circuit according to Ziff, 92, wherein the circuit parts located on the first micromechanical functional elements are electrically connected to one another such that mean values and / or differences are formed. Micromechanical device according to para. 41 to 93, which at least at a first position, a first mechanical functional element, in particular a web, which is mechanically connected to at least one further second micromechanical functional element, in particular a membrane and having a second position which has no mechanical function and no or is exposed to only a slight mechanical influence, and that at least the two positions are in each case equivalent circuit parts of a circuit according to para. 14 to 40 are located. Micromechanical device and circuit according to para. 94, wherein the circuit parts located on the two positions are electrically connected to each other so that averages and / or differences are formed. Micromechanical device and circuit according to para. 92 to 95, wherein the micromechanical device of at least two complete micromechanical Teüvorrichtungen, in particular two pressure sensors, according to para. 92 to 95, which are again in a functional context. Micromechanical device and circuit according to para. 96, wherein within the circuit mathematical operations, in particular the formation of averages and differences, are applied to the electrical output values of the sub-devices. Micromechanical device and circuit according to para. 94 to 97, in which at least one second circuit part, which is similar to a first circuit part at the first position, in particular on a web, is used as reference, in particular voltage reference, and is not in a functional relationship with a micromechanical functional element. 99. Micromechanical device and circuit according to para. 92 to 98, wherein for each circuit part on a first position, at least one circuit part, which equals the circuit part on the respective web, is assigned as a reference and wherein this reference is not in a functional relationship with a micromechanical functional element.

100. Micromechanical device and circuit according to para. 99, where the reference is on the neutral fiber.

101. Micromechanical device and circuit in particular according to para. 92 to 100, wherein at least one amplifier is part of the same.

102. Micromechanical device and circuit in particular according to para.

101, wherein the amplifier circuit has a positive and negative input.

103. Micromechanical device and circuit according to para. 1 to 201, which are provided in many parts with protection against moisture and / or proton in and outdiffusion.

104. Micromechanical device and circuit according to para. 103, wherein the diffusion protection consists of a silicon nitride layer.

Further features of the invention are:

1. Reduction in the number of wafer bond connections required

2. reduction of parasitic elements

a) Elimination of sources of mechanical stress

b) Protection against the spread of unavoidable mechanical stress c) Maximization, homogenization and linearization of mechanical stress fields

d) Reduction of the scattering of electronic components

e) Reduction of the dispersion of electronic circuits

f) Reduction of the dispersion of micromechanical functional elements

3. Increasing the tolerance of the design to mechanical and electrical manufacturing variations 4. Reducing the effects of unavoidable parasitic elements

5. Reduction of the influence of the construction and connection technology

6, Flexibility of the use of the sensors by the user

7. Reduction of the necessary die area

8, possibility of coupling to high-volume standard CMOS lines, in particular those with p-doped substrates

These properties are realized in particular by the measures described below, which can be used individually or in total or partial combination: 1. Reduction of the number of necessary wafer bond connections by a) production of cavities prior to CMOS processing

2. reduction of parasitic elements by

a) Elimination of sources of mechanical stress, in particular by i) avoidance of unnecessary layers on the micromechanical

Functional elements, in particular on pressure sensor membranes b) protection against propagation of unavoidable mechanical stress, in particular by

i) containment of the stress by means of mechanical guard rings and ii) reduction of the depth of cavities in the material whereby this has a higher area moment of inertia

c) maximization, homogenization and linearization of Nutz-stress fields especially by

i) etching of trenches in pressure membranes

ii) choice of trench shape

üi) Distance between backside structures and buried structures on the one side and front side structures on the other side to reduce the alignment errors

d) reduction of the scattering of electronic components by

i) Use of self-aligning structures

e) reduction of the dispersion of electronic circuits by

i) Use of a compact, symmetrical self-adjusting special transistor

ii) Use of a compact, balanced, self-aligned differential amplifier stage

iii) Use of a compact self-aligning symmetrical active Wheatstone bridge

f) reduction of the dispersion of micromechanical functional elements

i) Use of defined, C OS-compatible etch stops

ii) Use of special miniaturizable special transistors Increasing the tolerance of the construction against mechanical and electrical manufacturing variations by

a) Distinction of the stress direction

b) Distinction between stressed and unstressed circuit parts c) Distinction between circuit parts at different symmetry positions

d) suitable compensating interconnection of circuit parts, which can detect the distinctions i to iii measuring,

e) Use of particularly miniaturizable self-adjusting special tran- sistors

f) minimization of the mechanical structure by targeted reduction of the layer stack in the field of micromechanical functional elements

Reduction of the effects of unavoidable parasitic elements a) Compensation circuits

b) Use of particularly miniaturizable Speziaitransistoren

Reduction of the influence of the construction and connection technique by a) the reduction of the depth of cavities in the material, whereby this has a higher area moment of inertia

b) Use of round cavities, whereby the vertical moment of inertia is increased

Flexibility of the use of the sensors by the user by a) adjustability of the gain by the user

Reduction of the necessary die area by

a) reduction of the depth of cavities in the material, whereby this has a higher area moment of inertia and the sensor can be reduced without loss of stability

b) Use of particularly miniaturizable Speziaitransistoren c) Creation of a minimum access opening for gases and liquids to a buried cavity

Possibility of coupling to high-volume standard CMOS lines in particular those with p-doped substrates by Production of the cavities with defined etch stop before the CMOS process

Production of micromechanical functional elements on the surface such as trenches after CMOS processing by plasma or DRIE etching

Production of minimal access openings to buried cavities after CMOS processing

LIST OF REFERENCES First Wafer Oxide Layer Straight Wall of the Cavity 4 Cavity Second Wafer Trenches in the Wafer Package Thin membrane areas defined by the trenches 6 and the cavity 4

Webs interrupting the trenches 6. Components for detecting the mechanical stress Connections with the connecting lines Surface of the wafer package Central plate of the membrane First wafer Si02 Layer Poly-silicon layer Second wafer Second oxide layer Cavity Trenches Webs which interrupt the trenches 19 Diaphragm central plate Mechanical stress components Connections to leads Surface of wafer bundle Diaphragm of smaller thickness Negative connection of the Wheatstone bridge Positive connection of the Wheatstone bridge First terminal for picking up the voltage at the Wheatstone bridge

Lower p-channel MOS diode of the reference voltage source for the Wheatstone bridge

Upper p-channel MOS diode of the reference voltage source for the Wheatstone bridge

Wheatstone bridge first p-channel MOS transistor Wheatstone bridge second p-channel MOS transistor Third Wheatstone bridge p-channel MOS transistor Fourth p-channel MOS transistor Wheatstone bridge reference voltage line Second terminal for tapping the voltage at the Wheatstone bridge

n + Channel stop Implantation Gate connection Transistor 32 and 34 in low-resistance polysilicon

Gate terminal transistor 33 and 31 in low-ohmic polysilicon

n-doped surface (non-conductive) Upper structure sensitive to mechanical stress, for example a Wheatstone bridge according to FIG. 12

Rights against mechanical stress sensitive structure, for example, a Wheatstone bridge according to FIG. 12

Lower structure susceptible to mechanical stress, for example a Wheatstone bridge according to FIG. 12

First differential amplifier p-type transistor second differential amplifier p-channel transistor third differential amplifier p-channel transistor fourth differential amplifier p-channel transistor reference voltage for transistors 44, 45, 46, 47 current supply line for p-channel transistors 44, 45,46,47 Common Drain Contact of p-channel transistors

44,45,46,47

Terminal transistor 46, negative output terminals of the differential amplifier

Terminal transistor 45, positive output node of the differential amplifier

Terminal transistor 44, negative output terminals of the differential amplifier

Terminal transistor 47, positive output node of the differential amplifier

Third p-channel transistor for reference bridge circuit Fourth p-channel transistor for reference bridge circuit Upper structure susceptible to mechanical stress, for example a Wheatstone bridge according to FIG. 12 as reference structure for 41 structure free of mechanical stress Rights against stress sensitive structure, for example a wheatstone Bridge according to Fig. 12 as a reference structure for 42 in the area free of mechanical stress Lower structure sensitive to mechanical stress, for example a Wheatstone bridge according to FIG. 12 as a reference structure for 43 in the region free of mechanical stress

Left mechanical stress sensitive structure, for example, a Wheatstone bridge of FIG. 12 as a reference structure for 44 in the area free of mechanical stress

Differential Amplifier: Current mirror transistor corresponding to Transitor 69

Differential Amplifier: Current mirror transistor corresponding to Transitor 70

Differential Amplifier: Current mirror transistor corresponding to Transitor 71

Differential Amplifier: Current mirror transistor corresponding to Transitor 72

Reference amplifier: First differential amplifier p-channel transistor

Reference amplifier: second differential amplifier p-channel transistor

Reference amplifier: Third differential amplifier p-anal transistor

Reference amplifier: Fourth differential amplifier p-channel transistor

Reference Amplifier: Current mirror transistor corresponding to Transitor 61

Reference Amplifier: Current mirror transistor corresponding to Transitor 62

Reference Amplifier: Current mirror transistor corresponding to Transitor 63

Reference Amplifier: Current mirror transistor corresponding to Transitor 64

Reference amplifier: n channel current-queuing transistor (current mirror)

Differential amplifier: n channel current source transistor (current mirror)

Negative connection 76 Positive connection

77 Negative output signal

78 Positive output signal

79 p + contact imitation

80 p + contact imitation

81 poly gate of a self-aligned p-channel MOS transistor

82 n + implantation area (channel stop)

83 n + implant area (channel stop)

84 Supply line made of highly doped poly-silicon

85 First p-channel MOS transistor of the Wheatstone bridge

86 Second Wheatstone bridge p-channel MOS transistor

87 Third p-channel MOS transistor of the Wheatstone bridge

88 Fourth p-channel MOS transistor of the Wheatstone bridge

89 Left tap

90 Right tap

91 negative pole

92 Positive pole

93 Second group of trenches for decoupling the membrane from the die body

94 webs that interrupt the group of second trenches 93

Third group of trenches for further decoupling of the

Diaphragm of the die body

96 webs that interrupt the third group of trenches 95 97 Boss with grid structure (structure)

98 Drilling into the cavity for differential pressure sensors

99 Mechanical guard ring to prevent the propagation of mechanical stress introduced by the bonding system

100 left structure susceptible to mechanical stress, for example a Wheatstone bridge according to FIG. 12

101 Etn transistor element

102 Negative connection

103 Positive Approach

104 Upper left transistor (p-Kanai)

105 upper transistor right (p-channel)

106 Lower left transistor (p-channel)

107 Lower right transistor (p-channel)

108 upper reference transistor (p-channel)

109 lower reference transistor (p-channel)

110 Internal reference voltage

111 First exit

112 Second exit

113 Parasitic first transistor

114 Parasitic second transistor

115 total transistor field plate

116 lever length (here the example cavity wall 3 to trench wall) 117 Example: trench wall

_{1: L} g height of the upper structure (here exemplified depth of the trench

6)

119 Aufpunkt the upper structure (here example trench 6)

• L20 Height of the lower structure (here, for example, depth of the cavity

4)

121 Aufpunkt of the lower structure (here, for example, cavity 4)

Claims

CLAIMS, microelectromechanical semiconductor device with

a first silicon semiconductor substrate (16) having a top into which a cavity (18) bounded by side walls and a bottom wall is inserted, and

a second silicon semiconductor substrate (13) having a silicon oxide layer (14) and a polysilicon layer applied thereto

(15) of defined thickness,

wherein the second silicon semiconductor substrate (13) with its polysilicon layer (15) of the upper side of the first silicon semiconductor substrate

(16) facing the latter and the second silicon semiconductor substrate (13) covers the cavity (18) in the first silicon semiconductor substrate (16) and

wherein in the second silicon semiconductor substrate (13) in the region of the cavity (18) covering portion trenches (19) are arranged, which extend to the polysilicon layer (15). A microelectromechanical semiconductor component according to claim 1, characterized in that adjacent trenches (19) are separated from one another by bending webs (20) which extend between the region (21) of the second silicon semi-conductor substrate (13) surrounding the trenches (19) and the A microelectromechanical semiconductor component according to claim 1 or 2, which extends around the cavity (18) of the first silicon semi-conductor substrate (16), characterized in that within the portion of the cavity covering the cavity (18) of the first silicon semi-conductor substrate (16) second silicon Halbieitersubstrats (13) at least one for mechanical stress sensitive electrical or electronic component (22) is formed.

4. The microelectromechanical semi-ferritic component according to claim 1, wherein a silicon oxide layer is arranged on the upper side of the first silicon semi-conductor substrate and that the silicon layer is in contact with the silicon oxide layer the top of the first silicon semiconductor substrate (16) is bonded.

5. A process for producing a microelectromechanical semi-ferritic device comprising the steps of:

Providing a first silicon substrate (16) having an upper side,

Introducing a cavity (18) into the top surface of the first silicon semi-conductor substrate (16), wherein the cavity (18) is defined by sidewalls and a bottom wall in the first silicon semiconductor substrate (16),

Providing a second silicon semiconductor substrate (13) with a silicon oxide layer (14) and a thickness of polysilicon (15) of defined thickness applied thereto, forming an upper side of the second silicon semiconductor substrate (13),

Bonding the polysilicon layer (15) of the second silicon semiconductor substrate (13) to the top of the first silicon semiconductor substrate (16) and

Introducing trenches (19) into the second silicon semiconductor substrate (13) in the area of its portion covering the cavity (18),

wherein the trenches (19) are made by etching and extend to the polysilicon layer (15).

6. A method of making a microelectromechanical hatched conductor element comprising the steps of;

Providing a first silicon semiconductor substrate (16) having an upper side, Introducing a cavity (18) into the top surface of the first silicon semi-conductor substrate (16), the cavity (18) being defined by sidewalls and a bottom wall in the first silicon semiconductor substrate (16),

Providing a second silicon semiconductor substrate (13) with a silicon oxide layer (14) and a poly silicon layer (15) of defined thickness applied thereto, forming an upper side of the second silicon semiconductor substrate (13),

Introducing trenches (19) into the second silicon semi-conductor substrate (13) in the region of its portion covering the cavity (18),

wherein the trenches (19) are made by etching and extend to the polysilicon layer (15),

and bonding the polysilicon layer (15) of the second silicon semiconductor substrate (13) to the top of the first silicon semiconductor substrate (16).

7. The method according to claim 5 or 6, characterized in that on the top of the first silicon semiconductor substrate (16) prior to introduction of the cavity (19) a silicon oxide layer (17) is applied and that the polysilicon layer (15) of the second silicon Semiconductor substrate (13) is bonded to the silicon oxide layer (17) on top of the first silicon semiconductor substrate (16),

8. Method according to claim 5, characterized in that at least one electrical and / or electronic component (22 is trained.