WO2011077676A1

WO2011077676A1 - Wiring component

Info

Publication number: WO2011077676A1
Application number: PCT/JP2010/007314
Authority: WO
Inventors: 浩一竹村; 徳昭安道; 博鳥屋尾
Original assignee: 日本電気株式会社
Priority date: 2009-12-24
Filing date: 2010-12-16
Publication date: 2011-06-30
Also published as: JPWO2011077676A1

Abstract

A first conductor (100) extends in the form of a sheet. A second conductor (200) is a small conductor strip and is disposed in a repeating fashion, for example periodically, in an area facing the first conductor (100). A third conductor (300) is positioned on the opposite side of the first conductor (100) when using the plurality of second conductors (200) as a reference, and extends over the area facing the plurality of second conductors (200). A connecting member connects each of the plurality of second conductors (200) to the third conductor (300). The connecting member is provided with a first wire (420) and a first via (512). The first wire (420) is formed on a different layer from the second conductor (200), and one end of the first wire does not overlap the center of the second conductor (200) in plan. The first via (512) connects one side of the first wire (420) to the second conductor (200).

Description

Wiring parts

The present invention relates to a wiring component exhibiting characteristics as a metamaterial.

In recent years, it has become clear that the propagation characteristics of electromagnetic waves can be controlled by periodically arranging conductors having a specific structure (hereinafter referred to as metamaterials). By using a metamaterial, for example, the antenna can be reduced in size and thickness, and a noise filter can be formed by utilizing the band gap characteristic exhibited by the metamaterial.

As specific metamaterial structures, for example, there are structures described in Patent Document 1, Patent Document 2, and Non-Patent Document 1. The technique described in Patent Document 1 has a problem of providing a ground plane in which surface current is suppressed. Specifically, in Patent Document 1, thumbtack-like conductor elements composed of polygonal flat plate-like conductor pieces and conductor pillars are periodically arranged on a conductor plane, and each conductor element is connected to the conductor plane. The disclosed structure is disclosed.

In Patent Document 2 and Non-Patent Document 1, thumbtack-like conductor elements composed of polygonal flat plate-like conductor pieces and conductor pillars are periodically arranged on a conductor plane, and each conductor element is formed into a conductor plane. A structure in which another conductor plane is laminated on a conductor piece via a dielectric layer via a dielectric layer is disclosed.

Japanese translation of PCT publication No. 2002-510886 US Patent Application Publication No. 2005/0029632

As described above, since the metamaterial exhibits characteristics as a band rejection filter, it is conceivable that a structure as a metamaterial is inserted into a wiring component such as a wiring board to provide a noise filtering function. On the other hand, in recent years, electronic devices including wiring components such as wiring boards have been downsized. For this reason, downsizing of wiring parts is strongly desired.

The band gap band of the metamaterial can be lowered to a practical frequency range (for example, several GHz band) by increasing the product of the capacity component and the inductor component of the unit cell. In a miniaturized wiring component, the electrode cannot be made large, so that it is necessary to make the dielectric thin in order to increase the capacitance component. On the other hand, since the inductor component of the metamaterial is provided by a via that penetrates the dielectric, the inductor component of the metamaterial becomes small when the dielectric is thinned. Thus, when introducing a metamaterial structure into a miniaturized wiring component, it is difficult to increase the product of the capacity component and the inductor component of the unit cell.

An object of the present invention is to provide a wiring component that can increase the product of the capacity component and the inductor component of a unit cell of a metamaterial and can suppress an increase in size.

According to the present invention, a first conductor extending in a sheet shape;
A plurality of island-shaped second conductors repeatedly disposed in a region facing the first conductor;
A sheet-like third conductor located on the opposite side of the first conductor when the plurality of second conductors are used as a reference, and extending in a region facing the plurality of second conductors;
A plurality of connecting members connecting each of the plurality of second conductors to the third conductor;
With
The connecting member is
A first wiring that is formed in a layer different from the second conductor and has one end not overlapping the center of the second conductor in plan view;
A first via connecting the one end of the first wiring and the second conductor;
A wiring component is provided.

According to the present invention, it is possible to provide a wiring component capable of increasing the product of the capacity component and the inductor component of the unit cell of the metamaterial and suppressing the increase in size.

The above-described object and other objects, features, and advantages will be further clarified by a preferred embodiment described below and the following drawings attached thereto.

It is sectional drawing which shows the structure of the wiring component which concerns on 1st Embodiment. (A) is a top view which shows the pattern of a 3rd conductor, (b) is a top view which shows the pattern of 1st wiring, (c) is a top view which shows the pattern of a 2nd conductor. It is sectional drawing which shows an example of the manufacturing method of wiring components. It is sectional drawing which shows an example of the manufacturing method of wiring components. It is sectional drawing which shows an example of the manufacturing method of wiring components. It is a graph which shows the example of examination result of the area of a capacitor and an inductor required when LC resonance frequency is 2.4 GHz. It is sectional drawing which shows the structure of the wiring component which concerns on 2nd Embodiment. It is a top view which shows the pattern of a conductor. It is sectional drawing which shows the structure of the wiring component which concerns on 3rd Embodiment. (A) is a top view which shows the pattern of a 3rd conductor, (b) is a top view which shows the pattern of 1st wiring, (c) is a top view which shows the pattern of a 2nd conductor. It is sectional drawing which shows the structure of the electronic device which concerns on 4th Embodiment. It is sectional drawing which shows the structure of the wiring component which concerns on 5th Embodiment. FIG. 13 is a diagram illustrating an example in which the wiring component illustrated in FIG. 12 is used as a discrete component having a noise filter function.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of the wiring component 50 according to the first embodiment. The wiring component 50 includes a first conductor 100, a plurality of second conductors 200, a third conductor 300, and a plurality of connection members. The first conductor 100 extends in a sheet shape. The second conductor 200 is a small conductor piece, and is repeatedly arranged, for example, periodically in a region facing the first conductor 100. The third conductor 300 is located on the side opposite to the first conductor 100 when the plurality of second conductors 200 are used as a reference, and extends in a region facing the plurality of second conductors 200. The connection member connects each of the plurality of second conductors 200 to the third conductor 300. The connection member includes a first wiring 420 and a first via 512. The first wiring 420 is formed in a layer different from the second conductor 200, and one end thereof does not overlap the center of the second conductor 200 in plan view. The first via 512 connects one end of the first wiring 420 and the second conductor 200.

The other end of the first wiring 420 is connected to the third conductor 300 by the second via 602. That is, the second conductor 200 is connected to the third conductor 300 via the first via 512, the first wiring 420, and the second via 602.

Since the first conductor 100 and the second conductor 200 face each other, a capacitance is formed by these. In the present embodiment, a dielectric layer 500 is provided between the first conductor 100 and the second conductor 200. The dielectric layer 500 may contain an oxide of at least one element selected from Mg, Al, Si, Ti, Ta, Hf, and Zr, or a metal element such as Sr, Ba, Pb, Bi. A composite oxide may be contained. These oxides or composite oxides constitute the main component of the dielectric layer 500. Here, the main component means 50% or more in terms of the number of atoms. The dielectric layer 500 is made of, for example, strontium titanate. Examples of the composite oxide include perovskite oxides represented by a chemical formula ABO ₃ (A and B are metal elements) such as strontium titanate, barium titanate, and lead titanate, and chemical formulas A ₂ B ₂ O ₇ (A, P is a pyrochlore type oxide represented by (B is a metal element), a Bi layered ferroelectric such as SrBi ₂ Ta ₂ O ₉ , or a complex oxide containing these as constituent components.

Further, the first conductor 100 may have a configuration in which an intermediate layer and a high melting point conductor layer are laminated in this order. The intermediate layer is formed, for example, by providing one or more layers made of at least one material selected from Ti, Ta, Cr, Ti nitride, Ta nitride, and Cr nitride. The high melting point conductor layer is formed by providing one or more layers composed of at least one element selected from Pt, Pd, Ru, and Ir.

The wiring component 50 has a substrate 10. The substrate 10 is formed of a conductor, a semiconductor, or an insulator, but may have heat resistance necessary for the manufacturing process of the wiring component 50 described later. When the substrate 10 is a conductor or a semiconductor, the substrate 10 is formed of at least one selected from, for example, Si, GaAs, stainless steel, tungsten, molybdenum, and titanium. When the substrate 10 is an insulator, the substrate 10 is formed of at least one material selected from, for example, glass, sapphire, quartz, and alumina.

The first conductor 100 is formed on the intermediate layer 20 formed on one surface of the substrate 10. The intermediate layer 20 has at least one layer composed of at least one material selected from the group consisting of, for example, Ti, Ta, Cr, Ti nitride, Ta nitride, and Cr nitride. Yes. On the first conductor 100, the dielectric layer 500, the plurality of second conductors 200, the insulating layer 510, the first wiring 420, the insulating layer 600, the third conductor 300, and the insulating layer 610 are stacked in this order.

The first via 512 is embedded in the insulating layer 510, and the second via 602 is embedded in the insulating layer 600. The intermediate layer 20, the first conductor 100, the dielectric layer 500, the first via 512, the second conductor 200, the insulating layer 510, and the first wiring 420 are multilayer wiring layers formed by a vapor deposition method. The insulating

layers

600 and 610 are formed by coating, and the second via 602 and the third conductor 300 are formed by a plating method.

In such a configuration, the first conductor 100, the second conductor 200, the first via 512, the first wiring 420, the second via 602, and the third conductor 300 form a structure that exhibits characteristics as a metamaterial. ing. In this structure, the metamaterial has a configuration in which a plurality of unit cells 40 are repeatedly arranged, for example, periodically. The unit cell 40 has a two-dimensional array, for example, but may be a one-dimensional array. The unit cell 40 is a so-called mushroom-type metamaterial unit cell, and the third conductor 300 corresponds to a conductor plane connected to the mushroom. The second via 602, the first wiring 420, and the first via 512 correspond to the inductance portion of the mushroom, and the second conductor 200 that is a conductor piece corresponds to the head portion of the mushroom. The first conductor 100 corresponds to a second conductor plane facing the mushroom. In such a configuration, the size of each capacitor of the metamaterial is controlled by the thickness and material of the dielectric layer 500 and the size and arrangement of the second conductor 200 that is a conductor piece, and the first via 512, The inductance component of the metamaterial is controlled by the length and thickness of the first wiring 420 and the second via 602. By adjusting these, it is possible to adjust a band gap band when the structure functions as an EBG (Electromagnetic Band Gap).

Here, when the “repetitive” unit cells 40 are arranged, in the unit cells 40 adjacent to each other, the interval (center distance) between the same vias (for example, the first via 512) is the electromagnetic wave assumed as EBG noise. It is preferable to be within half of the wavelength λ. “Repetition” includes a case where a part of the configuration is missing in any unit cell 40. When the unit cell 40 has a two-dimensional array, “repetition” includes a case where the unit cell 40 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 40 and a case where the arrangement of some unit cells 40 themselves is deviated. In other words, even when the periodicity in the strict sense collapses, if the unit cell 40 is repeatedly arranged, the characteristics as a metamaterial can be obtained, so that “periodicity” has a certain amount of defects. Permissible. These defects may be caused when wiring or vias are passed between the unit cells 40, when adding a metamaterial structure to an existing wiring layout, and when the unit cells 40 cannot be arranged by existing vias or patterns, A case where an error and an existing via or pattern are used as a part of the unit cell 40 can be considered.

The conductors and vias shown in FIG. 1 may be formed by laminating a metal layer such as Cu on a barrier metal layer such as TiN, or at least some of the conductors may be Pt, Pd, Ru. , And Ir may be formed as a refractory conductor layer by laminating one or more layers composed of at least one element selected from Ir.

The first conductor 100 is electrically connected to a first external connection terminal (not shown) of the wiring component 50, and the third conductor 300 is electrically connected to a second external connection terminal (not shown) of the wiring component 50. Connected. The first external connection terminal and the second external connection terminal are formed in the same layer as the third conductor 300, for example, and are exposed to the outside through an opening provided in the insulating layer 610.

FIG. 2A is a plan view showing a pattern of the third conductor 300 included in the wiring component 50 corresponding to two unit cells 40. As shown in FIG. 2A, the third conductor 300 is a sheet-like conductor pattern and does not have an opening or the like.

FIG. 2B is a plan view showing a pattern of the first wiring 420 included in the wiring component 50 corresponding to two unit cells 40. A first via 512 is connected to one end of the first wiring 420, and a second via 602 is connected to the other end of the first wiring 420. The first wiring 420 does not connect the first via 512 and the second via 602 with a straight line, and extends so as to have at least one bent portion so as to increase the wiring length. In the example shown in the figure, the first wiring 420 extends in a substantially U shape so as to have two bent portions.

FIG. 2C is a plan view showing a pattern of the second conductor 200 included in the wiring component 50. As described above, the second conductor 200 is a small conductor piece, but its planar shape is, for example, a square or a rectangle. In the example shown in this drawing, the second conductor 200 completely includes the first wiring 420 shown in FIG. 2B in plan view. However, the second conductor 200 may be laid out so as to overlap only a part of the first wiring 420 (that is, only the region where the first via 512 is provided and its periphery) in plan view.

3, 4, and 5 are cross-sectional views illustrating an example of a method for manufacturing the wiring component 50 illustrated in FIGS. 1 and 2. First, a substrate 10 is prepared as shown in FIG. When a silicon substrate is used as the substrate 10, a low resistance substrate having a specific resistance of 0.02 Ω · cm or less is used as the substrate 10, for example. When the substrate 10 is a silicon substrate, the natural oxide film formed on the surface of the substrate 10 is removed. Next, the intermediate layer 20 is formed on the substrate 10. The intermediate layer 20 includes, for example, a Ti layer having a thickness of 10 nm to 100 nm, a TiN layer having a thickness of 10 nm to 100 nm, a Mo layer having a thickness of 100 nm to 2 μm, and a Ti layer having a thickness of 10 nm to 100 nm. Are stacked in this order. The intermediate layer 20 has a function as a barrier metal film for strengthening adhesion to the substrate 10 and Si diffusion, and is formed by a vapor deposition method such as a sputtering method. The Mo layer of the intermediate layer 20 is effective in reducing the resistance of the first conductor layer, and is desirably provided when the substrate is an insulator. When the substrate 10 is a low resistance substrate, the Mo layer of the intermediate layer 20 can be omitted.

Next, the first conductor 100 is formed on the substrate 10. The first conductor 100 is formed by, for example, a sputtering method. The first conductor 100 is, for example, a high melting point conductor, and is formed by laminating one or more layers composed of at least one element selected from Pt, Pd, Ru, and Ir. The first conductor 100 is formed of, for example, a Pt layer. The film thickness of the first conductor 100 is, for example, not less than 50 nm and not more than 500 nm.

Next, the dielectric layer 500 is formed on the first conductor 100 by a sputtering method such as an RF sputtering method. When the dielectric layer 500 is formed of strontium titanate, the substrate 10 is heated to, for example, 300 ° C. or more and 600 ° C. or less, and a mixed gas of Ar and O ₂ , for example, 80% Ar + 20% O ₂ is used as the atmosphere. The thickness of the dielectric layer 500 is, for example, not less than 10 nm and not more than 3 μm. The dielectric layer 500 can be formed by a CVD method, a sol-gel method, an aerosol deposition method, or a spin coating method.

Next, a plurality of second conductors 200 as conductor pieces are formed by selectively forming a conductive film on the dielectric layer 500. The second conductor 200 is formed, for example, by forming a conductive film by sputtering or CVD, forming a resist pattern (not shown) on the conductive film, and etching the conductive film using the resist pattern as a mask. The The second conductor 200 has a configuration in which, for example, a Cu layer having a thickness of 100 nm to 10 μm is stacked on a TiN layer having a thickness of 10 nm to 100 nm as a barrier metal film. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 3B, an insulating layer 510 is formed on the dielectric layer 500 and the plurality of second conductors 200 by, for example, a CVD method. The insulating layer 510 is a silicon oxide film, for example, and in this case, is formed by a plasma CVD method. The thickness of the insulating layer 510 is, for example, not less than 100 nm and not more than 1 μm. Next, a resist pattern (not shown) is formed over the insulating layer 510, and the insulating layer 510 is etched using the resist pattern as a mask. As a result, a connection hole 511 for embedding the first via 512 is formed in the insulating layer 510. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 4A, a Ti layer as a barrier metal layer and a Cu layer as a plating seed layer are formed on the insulating layer 510 and on the inner wall and bottom surface of the connection hole 511 by sputtering. The thickness of the Ti layer is, for example, 10 nm or more and 100 nm or less, and the thickness of the plating seed layer is, for example, 50 nm or more and 500 nm or less. Next, a resist pattern is formed on the Cu layer as a plating seed layer, and a Cu layer is formed on the plating seed layer by plating using the resist pattern as a mask. The thickness of the plating layer is, for example, 1 μm or more and 20 μm or less at a portion located on the insulating layer 510. Thereby, the first via 512 and the first wiring 420 are formed. Thereafter, the resist pattern and the portion of the plating seed layer and the barrier metal layer that are not covered with the plating layer are removed.

Next, as shown in FIG. 4B, an insulating layer 600 is formed on the first wiring 420 and the insulating layer 510. The insulating layer 600 is formed, for example, by applying a photosensitive polyimide layer. Next, a connection hole 601 for embedding the second via 602 in the insulating layer 600 is formed. In the case where the insulating layer 600 is formed of a photosensitive polyimide layer, the connection hole 601 is formed by exposing and developing the insulating layer 600. The finally formed insulating layer 600 has a thickness of, for example, 5 μm or more and 30 μm or less.

Next, as shown in FIG. 5, a Ti layer as a barrier metal layer and a Cu layer as a plating seed layer are formed on the insulating layer 600 and on the inner wall and bottom surface of the connection hole 601 by sputtering. The thickness of the Ti layer is, for example, 10 nm or more and 100 nm or less, and the thickness of the plating seed layer is, for example, 50 nm or more and 500 nm or less. Next, a Cu layer is formed on the plating seed layer by a plating method. Next, a resist pattern is formed on the Cu layer as a plating seed layer, and a Cu layer is formed on the plating seed layer by plating using the resist pattern as a mask. The thickness of the plating layer is, for example, 1 μm or more and 20 μm or less at a portion located on the insulating layer 600. As a result, the second via 602, the third conductor 300, the first external connection terminal (not shown), and the second external connection terminal (not shown) are formed.

Thereafter, an insulating layer 610 is formed on each of the insulating layer 600, the third conductor 300, the first external connection terminal, and the second external connection terminal. The insulating layer 610 is formed, for example, by applying a photosensitive polyimide layer and curing (heat treatment). Next, openings are formed in the insulating layer 610 to expose the first external connection terminals and the second external connection terminals. In the case where the insulating layer 610 is formed of a photosensitive polyimide layer, these openings are formed by exposing and developing the insulating layer 610. The thickness of the finally formed insulating layer 610 is, for example, not less than 5 μm and not more than 30 μm.

Next, functions and effects of this embodiment will be described. As shown in FIG. 1, since the wiring component 50 has a plurality of unit cells 40, it exhibits characteristics as a metamaterial. For example, when the metamaterial is used as the EBG, in order to reduce the size while keeping the band gap frequency constant, the product of the inductance and the capacitance in the unit cell 40 must be kept constant. The capacitance in the unit cell 40 can be increased by making the dielectric layer 500 thin or using a high dielectric constant material for the dielectric layer 500, but the inductance in the unit cell 40 is required using a high permeability material. It is necessary to shorten the wiring length or increase the wiring density while maintaining a constant wiring length by fine processing of the wiring.

When the present inventors examined the EBG structure in which the band gap frequency appears at several GHz, when the size of the second conductor 200, which is a conductor piece, is small enough to prevent the inductor from turning, the necessary inductance is reduced. It became clear that it was difficult to maintain. If the unit cell is approximately the same size as the conductor strip, adopting a linear inductor with one end of the inductor in the center of the conductor strip, the diagonal distance from the center of the conductor strip to the corner of the conductor strip ( The length of the inductor cannot be secured more than 1 / √2 times the length of the unit cell).

FIG. 6 shows the size of a small piece (length of one side) of a mushroom-type EBG structure and the required length of an inductor when the LC resonance frequency, that is, the frequency with the largest attenuation of the band gap is 2.4 GHz. A result example (when the conductor piece is square and the minimum wiring width and interval are both 20 μm) is shown. As the conductor piece becomes smaller and the capacitance becomes smaller, the required inductance increases to make the LC product constant, so a longer inductor is required.

In this example of examination results, an area of 140 μm □ or more is required to turn the inductor. On the other hand, as shown in FIG. 6, when the size of the conductor piece is approximately 100 μm or less, the required inductor length becomes larger than 1 / √2 times the size of the conductor piece, so that the first via 512 is formed by the second conductor 200. If it is at the center, the required inductance cannot be secured. When the wiring length is secured by using a region other than the region immediately above the second conductor 200, the substantial area of the unit cell 40 is increased as a result, and the occupied area is increased even with the same number of unit cells. Also, shortening the length of the inductor by introducing a high magnetic permeability material is difficult due to the complicated structure and increased process costs.

In contrast, in this embodiment, one end of the first wiring 420 and the first via 512 connected to the first wiring 420 do not overlap the center of the second conductor 200 in plan view. Therefore, it is possible to turn the first wiring 420 in a region immediately above the second conductor 200 and to extend the first wiring 420, and to increase the inductance without increasing the area of the unit cell 40. As a result, when the EBG is formed by the repetitive arrangement of the unit cells 40, the band gap frequency band can be lowered (for example, a region of several GHz) without increasing the size of the EBG.

In the present embodiment, since the dielectric layer 500 is formed by a thin film process, a material having a high relative dielectric constant, good insulation, and a thin film can be used as the dielectric layer 500. For example, a strontium titanate thin film has a dielectric constant of 200, and has a good insulating property with a breakdown voltage of 10 V or more. By using such a strontium titanate thin film, the capacitance per unit area can be increased 10,000 times or more as compared with the case of using a resin film having a thickness of 50 μm. If the same capacitance is obtained in order to generate a band gap in the frequency band desired for the EBG structure, the conductor piece can be greatly reduced to 1 / 10,000 or less. As described above, even if a composite material other than strontium titanate is used as the material of the dielectric layer, such an effect can be obtained. Note that these films can be formed of a high-quality insulating film by film formation or heat treatment at a high temperature of 300 ° C. or higher and in an oxygen atmosphere. Therefore, the first conductor 100 is preferably formed of the above-described high melting point conductor layer.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the configuration of the wiring component 50 according to the second embodiment. In the present embodiment, the second via 602, the third conductor 300, and the insulating layer 610 are not provided, the conductor 400 is provided in the same layer as the first wiring 420, and the layout of the first wiring 420 is excluded. The configuration is the same as that of the wiring component 50 according to the first embodiment.

FIG. 8 is a plan view showing a pattern of the conductor 400. The conductor 400 is a sheet-like conductor pattern, but has a plurality of openings 410. The opening 410 is provided to face each of the plurality of second conductors 200, and the first wiring 420 is provided in the opening 410. The opening 410 is square or rectangular, and the center overlaps the center of the second conductor 200. Further, neither end of the first wiring 420 overlaps the center of the opening 410. The first wiring 420 has one end connected to the first via 512 and the other end connected to the main body of the conductor 400.

In this embodiment, on the equivalent circuit, the conductor 400 has the same function as the third conductor 300 in the first embodiment. That is, the unit cell 40 is configured by the first conductor 100, the second conductor 200, the first via 512, the first wiring 420, and the conductor 400. The unit cell 40 is a so-called mushroom-type metamaterial unit cell. The conductor 400 corresponds to a conductor plane connected to the mushroom, the first wiring 420 and the first via 512 correspond to an inductance portion of the mushroom, and the second conductor 200 that is a conductor piece is the head portion of the mushroom. It corresponds to.

Also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the number of layers can be reduced as compared with the first embodiment, the wiring component 50 can be made thin.

(Third embodiment)
FIG. 9 is a cross-sectional view showing the configuration of the wiring component 50 according to the third embodiment. FIGS. 10A, 10B, and 10C are plan views showing layouts of the third conductor 300, the first wiring 420, and the second conductor 200 in the wiring component 50 shown in FIG. 9, respectively. This embodiment is the same as the first embodiment except for the following points.

First, the third conductor 300 is provided with a plurality of openings 310 and a plurality of second wirings 320. The opening 310 is provided to face each of the plurality of second conductors 200, and the second wiring 320 is provided in the opening 310. The second wiring 320 has one end connected to the second via 602 and the other end connected to the main body of the third conductor 300. The opening 310 is square or rectangular, and the center overlaps the center of the second conductor 200. The other end of the second wiring 320 does not overlap the center of the opening 310.

Also in this embodiment, the unit cell 40 is a so-called mushroom-type metamaterial unit cell. The third conductor 300 corresponds to a conductor plane connected to the mushroom, and the second wiring 320, the second via 602, the first wiring 420, and the first via 512 correspond to an inductance portion of the mushroom. The second conductor 200, which is a conductor piece, corresponds to the head portion of the mushroom, and the first conductor 100 corresponds to the second conductor plane facing the mushroom.

Also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the opening 310 and the second wiring 320 are provided in the third conductor 300, the inductance portion of the mushroom can be lengthened. For this reason, the inductance can be increased without increasing the area of the unit cell 40.

(Fourth embodiment)
FIG. 11 is a cross-sectional view illustrating a configuration of an electronic device according to the fourth embodiment. In this electronic device, a semiconductor chip 60 is mounted on a wiring component 50 as an interposer. In the example shown in this figure, the semiconductor chip 60 is flip-chip mounted on the wiring component 50, but may be mounted on the wiring component 50 by other methods (for example, wire bonding).

In the example shown in the figure, the unit cell 40 of the wiring component 50 has the same configuration as that of the third embodiment. However, the unit cell 40 may have the same configuration as that of the first embodiment or the second embodiment.

The wiring component 50 has a first external connection terminal 330 and a second external connection terminal 340. The first external connection terminal 330 is electrically connected to the first conductor 100 and is connected to the power supply pad 61 of the semiconductor chip 60 via the bump 801. The second external connection terminal 340 is electrically connected to the third conductor 300 and is connected to the ground pad 62 of the semiconductor chip 60 via the bump 802.

Specifically, the intermediate layer 20 and the first conductor 100 are provided except for the peripheral portion of the substrate 10. An insulating layer 510 is directly formed on the substrate 10 at the periphery of the substrate 10. The insulating layer 510 in the peripheral portion of the substrate 10 is thicker than the insulating layer 510 in other regions because the intermediate layer 20 and the first conductor 100 are not provided. In the periphery of the substrate 10, through

vias

31 and 32 are provided. The through

vias

31 and 32 penetrate the substrate 10 and the insulating layer 510. The through via 31 is connected to the first external connection terminal 330 via the conductor 430 and the via 603 provided on the insulating layer 510, and the through via 32 is connected to the conductor 440 and the via provided on the insulating layer 510. It is connected to the second external connection terminal 340 via 604.

The first external connection terminal 330 and the second external connection terminal 340 are formed in the same layer as the third conductor 300 and are exposed from the opening provided in the insulating layer 610. The

conductors

430 and 440 are provided in the same layer as the first wiring 420.

Further, the dielectric layer 500 and the second conductor 200 are not formed in the region located next to the through via 31 in the first conductor 100. In this region, the first conductor 100 faces the conductor 430 and is connected to each other through the via 101 embedded in the insulating layer 510.

In such a configuration, the first conductor 100 is connected to the through via 31 that supplies the power supply potential via the via 101 and the conductor 430, and is connected to the first external connection via the via 101, the conductor 430, and the via 603. The terminal 330 is connected. Further, the third conductor 300 is directly connected to the second external connection terminal 340 and is connected to the through via 32 that gives a ground potential via the second external connection terminal 340, the via 604, and the conductor 440. However, the through via 31 applies a ground potential, the first external connection terminal 330 is connected to the ground potential pad 62, and the through via 32 supplies a power supply potential, and the second external connection terminal 340 is connected to the power supply pad 61. good.

In this embodiment, a metamaterial composed of a plurality of unit cells 40 is electrically located between the power supply potential of the semiconductor chip 60 and the ground potential. For this reason, it can suppress that the semiconductor chip 60 becomes a noise source and noise mixes into a power supply potential and a ground potential. Further, noise can be prevented from entering the semiconductor chip 60 through the power supply potential and the ground potential. Further, as described above, since the band gap frequency band can be lowered (for example, a region of several GHz) without increasing the size of the unit cell 40, it is possible to suppress an increase in size of the electronic device.

(Fifth embodiment)
FIG. 12 is a cross-sectional view showing the configuration of the wiring component 50 according to the fifth embodiment. In the present embodiment, the wiring component 50 is the wiring component shown in any of the first to third embodiments, except that a conductor is used as the substrate 10 and the intermediate layer 20 is not formed. 50. That is, in the present embodiment, the first conductor 100 is directly formed on the substrate 10 that is a conductor. This figure shows the case of the same configuration as the wiring component 50 shown in the second embodiment.

FIG. 13 shows an example in which the wiring component 50 shown in FIG. 12 is used as a discrete component having a noise filter function. In the example shown in the figure, the wiring component 50 has a rectangular planar shape and is attached to a wiring board 70 (for example, a mother board) externally. The wiring component 50 includes a first external connection terminal 441, a second external connection terminal 442, a third external connection terminal 443, and a fourth external connection terminal 444.

The first external connection terminal 441 is electrically connected to the power supply plane 701 in the wiring board 70 via the solder balls 811 and the conductor patterns and vias in the wiring board 70. The second external connection terminal 442 is electrically connected to the power plane 702 in the wiring board 70 through the solder balls 812 and the conductor patterns and vias in the wiring board 70. The power supply planes 701 and 702 are not connected in the wiring board 70 but are electrically connected via the first conductor 100 of the wiring component 50.

The third external connection terminal 443 is electrically connected to the ground plane 711 in the wiring board 70 via the solder balls 813 and the conductor patterns and vias in the wiring board 70. The fourth external connection terminal 444 is electrically connected to the ground plane 712 in the wiring board 70 through the solder balls 814 and the conductor patterns and vias in the wiring board 70. The ground planes 711 and 712 are not connected in the wiring board 70 but are electrically connected via the conductor 400 of the wiring component 50.

The first external connection terminal 441, the second external connection terminal 442, the third external connection terminal 443, and the fourth external connection terminal 444 are exposed from the opening provided in the insulating layer 600. The first conductor 100 is provided except for the peripheral portion of the substrate 10. An insulating layer 510 is directly formed on the substrate 10 at the periphery of the substrate 10. The insulating layer 510 in the peripheral portion of the substrate 10 is thicker than the insulating layer 510 in other regions because the first conductor 100 is not provided.

Further, the dielectric layer 500 and the second conductor 200 are not formed in at least a part of the region of the first conductor 100 facing the

vias

111 and 112. In the region where the dielectric layer 500 and the second conductor 200 are not formed, the first conductor 100 is connected to the first external connection terminal 441 through the via 111 embedded in the insulating layer 510, and the insulating layer The second external connection terminal 442 is connected via a via 112 embedded in 510. The

external connection terminals

443 and 444 are directly connected to the conductor 400. The connection structure between the

external connection terminals

441 and 442 and the first conductor 100 is not limited to the example shown in this figure.

In plan view, at least one second conductor 200, that is, the unit cell 40 is located between the first external connection terminal 441 and the second external connection terminal 442, and the third external connection terminal 443 and the fourth external connection are connected. At least one second conductor 200, that is, the unit cell 40 is located between the terminals 444. In the example shown in the figure, the first external connection terminal 441 and the third external connection terminal 443 are provided on one side of the wiring component 50, and the second external connection terminal 442 and the fourth external connection terminal 444 are the wiring component 50. Among these, it is provided on the side opposite to the one side described above.

According to the present embodiment, the wiring component 50 as a noise filter is attached to the wiring board 70 externally. The power planes 701 and 702 in the wiring board 70 are electrically connected via the first conductor 100 of the wiring component 50, and the ground planes 711 and 712 are electrically connected via the conductor 400 of the wiring component 50. It is connected. For this reason, it can suppress that noise propagates through the power plane and ground plane of the wiring board 70. Further, since the metamaterial functioning as the EBG is provided as an external component rather than in the wiring substrate 70, the band gap frequency band of the EBG can be changed by simply replacing the wiring component 50 without changing the design of the wiring substrate 70. Can do. The first external connection terminal 441 and the second external connection terminal 442 may be connected to the ground planes 711 and 712, and the third external connection terminal 443 and the fourth external connection terminal 444 may be connected to the power supply planes 701 and 702, respectively. Good.

The first conductor 100 is directly formed on the conductive substrate 10. For this reason, since the board | substrate 10 functions also as a part of 1st conductor 100, the resistance of the 1st conductor 100 can be made low substantially.

Further, in the present embodiment, a form in which discrete components are surface-mounted is illustrated, but a form in which discrete parts created separately from the wiring board 70 are embedded in the wiring board 70 may be used. In this case, the area can be reduced as compared with the case where the EBG structure is formed only by wiring of a normal printed wiring board, and a space for mounting other components on the surface of the wiring board is created, which is advantageous for higher density mounting. It becomes.

As described above, the embodiments of the present invention have been described with reference to the drawings. However, these are exemplifications of the present invention, and various configurations other than the above can be adopted.

This application claims priority based on Japanese Patent Application No. 2009-291817 filed on Dec. 24, 2009, the entire disclosure of which is incorporated herein.

Claims

A first conductor extending in a sheet shape;
A plurality of island-shaped second conductors repeatedly disposed in a region facing the first conductor;
A sheet-like third conductor located on the opposite side of the first conductor when the plurality of second conductors are used as a reference, and extending in a region facing the plurality of second conductors;
A plurality of connecting members connecting each of the plurality of second conductors to the third conductor;
With
The connecting member is
A first wiring that is formed in a layer different from the second conductor and has one end not overlapping the center of the second conductor in plan view;
A first via connecting the one end of the first wiring and the second conductor;
Wiring parts comprising.
The wiring component according to claim 1,
A plurality of openings formed in the third conductor and provided in regions overlapping with each of the plurality of second conductors in plan view;
The first wiring is a wiring component that is located in the same layer as the third conductor, is provided in each of the plurality of openings, and has the other end connected to the third conductor.
The wiring component according to claim 1,
The first wiring is formed in a conductor layer located between the plurality of second conductors and the third conductor,
Furthermore, a wiring component comprising a second via for connecting the other end of the first wiring and the third conductor.
The wiring component according to claim 1,
The first wiring is formed in a conductor layer located between the plurality of second conductors and the third conductor,
further,
A plurality of openings formed in the third conductor and provided in regions overlapping with each of the plurality of second conductors in plan view;
A second wiring located in the same layer as the third conductor, provided in each of the plurality of openings, and having one end connected to the third conductor;
A second via connecting the other end of the first wiring and the other end of the second wiring;
Wiring parts comprising.
The wiring component according to any one of claims 1 to 4,
A substrate,
A multilayer wiring layer formed on the first surface of the substrate;
With
The wiring component in which the first conductor and the plurality of second conductors are formed in different wiring layers of the multilayer wiring layer.
In the wiring component according to claim 5,
A dielectric layer positioned between the first conductor and the second conductor;
The dielectric layer is a wiring component containing an oxide of at least one element selected from Mg, Al, Si, Ti, Ta, Hf, and Zr.
In the wiring component according to claim 5,
A dielectric layer positioned between the first conductor and the second conductor;
The dielectric layer is a wiring component containing a complex oxide of a metal element.
The wiring component according to any one of claims 1 to 7,
An intermediate layer in which the first conductor is provided with at least one layer composed of at least one material selected from Ti, Ta, Cr, or a nitride of Ta, a nitride of Ta, and a nitride of Cr; A wiring component comprising a refractory conductor layer formed on the intermediate layer and provided with one or more layers composed of at least one element selected from Pt, Pd, Ru, and Ir.
The wiring component according to any one of claims 5 to 8,
A wiring component in which the substrate is formed of a conductor or a semiconductor.
In the wiring component according to claim 9,
The wiring component, wherein the conductor or semiconductor is at least one selected from Si, GaAs, stainless steel, tungsten, molybdenum, and titanium.
The wiring component according to any one of claims 5 to 8, wherein the substrate is formed of at least one material selected from glass, sapphire, quartz, and alumina.
The wiring component according to any one of claims 1 to 11,
The wiring component is an interposer,
A first external connection terminal electrically connected to one of the first conductor and the third conductor and connected to a power supply pad of the semiconductor chip;
A second external connection terminal electrically connected to the other of the first conductor and the third conductor and connected to a ground pad of the semiconductor chip;
Wiring parts comprising.
The wiring component according to any one of claims 1 to 11,
The wiring component is externally attached to the wiring board,
A first external connection terminal electrically connected to one of the first conductor and the third conductor and electrically connected to a power plane of the wiring board;
A second external connection terminal electrically connected to the one of the first conductor and the third conductor at a position different from the first external connection terminal and electrically connected to a power plane of the wiring board; ,
A third external connection terminal electrically connected to the other of the first conductor and the third conductor and electrically connected to a ground-in of the wiring board;
A fourth external connection terminal electrically connected to the other of the first conductor and the third conductor at a position different from the third external connection terminal, and electrically connected to a ground plane of the wiring board; ,
With
In plan view, at least one second conductor is located between the first external connection terminal and the second external connection terminal, and between the third external connection terminal and the fourth external connection terminal. A wiring component in which at least one second conductor is located.