WO2011076056A1

WO2011076056A1 - Chip with version number and method for modifying chip version number thereof

Info

Publication number: WO2011076056A1
Application number: PCT/CN2010/079364
Authority: WO
Inventors: 桂阳; 齐亚军
Original assignee: 炬力集成电路设计有限公司
Priority date: 2009-12-21
Filing date: 2010-12-01
Publication date: 2011-06-30
Also published as: CN102103644A

Abstract

A chip with a version number and a method for modifying the chip version number thereof, belonging to the field of chip design, are provided. The chip structure comprises a pair of independent channels (channel 1, channel 2) running through the chip from the bottom to the top and connecting to a high voltage and a low voltage respectively, wherein one of the channels is led out as a bit of the version number, so that the modification of the chip version number is no longer dependent on a specific layer, and each of metal layers (metal 1, metal 2, metal 3, metal 4) can achieve the chip version number modification. A cross-layer structure is set in each via layer (via 1, via 2, via 3). As long as any via layer is changed, the chip version number is modified.

Description

Chip with version number and method for modifying chip version number

Technical field

The present invention relates to the field of chip design, and in particular to a modification technique of a chip version number.

Background technique

Chip version is used to identify integrated circuits (Integrated Circuit) , referred to as the 'IC') version of the chip.

In IC design, chip version is usually represented by a number of binary digits. Take 4 digits as an example, version 1 The ID is 4'b0000, the version 2 is identified as 4'b0001, the version 3 is identified as 4'b0010, and so on, and the version 15 is identified as 4'b1111. In the present invention, 4'b0000 is a flag indicating that all 4 bits are 0. Other similar tags have similar meanings.

When the IC is revised, the chip version information will change and the corresponding bits need to be modified. For example, from version 1 (4'b0000) to version 2 (4'b0001), the least significant bit needs to be modified; from version 2 (4'b0001) to version 3 (4'b0010), the least significant bit and the second lowest bit need to be modified... Other cases can be analogized.

In the prior art, a read-only register is usually used to record the chip version number, which is done at the time of IC design. The normal IC design process is shown in Figure 1. Shown.

First, the design of the Register Transfer Level ('RTT') is completed. in In RTL design, the behavior of a circuit is defined as the signal transmission between registers, or the logical operation of these signals. Simply put, RTL is a hardware description language (such as Verilog or VHDL). ) Describe the features you want to achieve.

After that, perform network synthesis (logic synthesis) to get netlist (netlist).

Then use placer (placer) to layout, get placed netlist (layout netlist).

Then use router (router) to route, get placed & routed netlist (A netlist with layout and wiring).

If you need to modify the RTL due to a design bug (defect) or new requirements, you will usually use a new RTL Repeat the entire design process, as shown in Figure 2, to get a new complete layout and routing netlist.

Using the modification method shown in Figure 2, due to re-synthesis and re-layout, the resulting netlist and Figure 1 The netlists obtained in this are quite different. In the foundry factory, it is necessary to re-make all the metal layers (metal layers), and the fab cost (factory cost) is high.

In order to solve the problem in the process in Figure 2, there is a design modification method that is different from the normal IC design flow--engineering change instruction ( Engineering Change Order, referred to as 'ECO'). ECO is less risky, shorter, and less costly than normal design modifications. So at the IC The ECO method is often used in revision design.

The process of ECO is shown in Figure 3. After the engineer modified the RTL and got the new RTL, the logic is no longer executed. The steps of synthesis, placer, and router (these steps are removed in a single line in Figure 3), but are modified directly on the old netlist that is laid out and routed, resulting in layout and routing. ECO netlist.

Using the ECO method shown in Figure 3, the resulting netlist is only modified as necessary (modify the design bug) compared to the original netlist. Or meet new requirements), so in the foundry factory, only one or several layers of metal need to be re-masked instead of all, thus greatly reducing the cost of fab.

In order to modify design bugs or meet new requirements, when using ECO for IC revision, you may only need to modify one or several of them. The metal layer may even need to modify a via layer (via layer) without changing the metal layer at all. However, modifying the metal layer or via involved in the chip version number The layer may not be in it. In this way, in order to modify the chip version number, it is necessary to modify one or more layers of metal or via, which greatly increases the fab cost.

technical problem

It is an object of the present invention to provide a chip having a version number and a method of modifying the version number of the chip, and the modification of the chip version number can be implemented at any layer, and is no longer dependent on a specific layer.

Technical solution

In order to solve the above technical problem, an embodiment of the present invention provides a chip having a version number, including N stacked in sequence. a metal layer, a via layer between each two adjacent metal layers, and a device layer, wherein the N metal layers are sequentially from the first metal layer to the Nth metal layer, and N is greater than 1 An integer of the device layer adjacent to the first metal layer; at least one set of channels in the chip, each set of channels having the following characteristics:

Each group of channels includes two independent channels that are not connected to each other;

Each channel starts from the first metal layer, runs through each metal layer and the via layer, and is connected to the Nth a metal layer; each channel behaves as a metal line in each metal layer, and represents a through hole in each of the via layers;

One channel is connected to the low level of the device layer through the first metal layer, and the other channel is connected to the high level of the device layer through the first metal layer;

In the Nth metal layer, one of the two channels is taken out as a bit of the version number.

An embodiment of the present invention further provides a method for modifying a version number of the above chip, comprising the following steps:

Determining a set of channels corresponding to the bits to be modified;

For this set of channels, if the specified metal layer that can be modified is neither the top N a metal layer, which is not the first metal layer at the bottom, cuts two metal wires corresponding to two channels in the specified metal layer to form four portions, the first portion and the first channel in the channel group The upper layers are connected, the second part is connected to the lower layers of the original first channel, the third part is connected to the upper layers of the original second channel in the channel group, and the fourth part is connected to the original second channel The following layers are connected;

In the specified metal layer, the first portion and the fourth portion are connected by a metal wire, and the second portion and the third portion are connected by a metal wire.

Embodiments of the present invention also provide a method of modifying a version number of a chip, the chip including N stacked in sequence a metal layer, a via layer between each two adjacent metal layers, and a device layer, wherein the N metal layers are sequentially from the first metal layer to the Nth metal layer, and N is greater than 1 An integer of the device layer adjacent to the first metal layer; at least one set of channels in the chip, each set of channels having the following characteristics:

One channel is connected to the low level of the device layer through the first metal layer, and the other channel is connected to the high level of the device layer through the first metal layer. ;

In the Nth metal layer, one of the two channels is taken out as a bit of the version number;

There is at least one cross structure in each group of channels;

Each cross structure includes eight nodes centered on one via layer, wherein

The first to fourth nodes are located adjacent to the metal layer above the via layer, and the fifth to eighth nodes are located adjacent to the metal layer below the via layer;

The first and second nodes are connected by metal wires, the third and fourth nodes are connected by metal wires, the fifth and sixth nodes are connected by metal wires, and the seventh and eighth nodes are connected by metal wires;

Corresponding to the first and fifth node positions, the second and eighth node positions, the third and seventh node positions, and the fourth and sixth node positions;

There is a through hole between the first node and the fifth node, and a through hole between the third node and the seventh node;

In the set of channels in which the intersecting structure is located, the first and fifth nodes and the through holes therebetween form part of one channel, and the third and seventh nodes and the through holes therebetween form part of the other channel;

The method includes the following steps:

Determining a set of channels corresponding to the bits to be modified;

For the set of channels, in the specified through hole layer that can be modified, the through hole between the original first and fifth nodes is disconnected, and the through hole between the third and seventh nodes is disconnected, in the second and eighth A new through hole is set between the nodes, and a new through hole is set between the fourth and sixth nodes.

Beneficial effect

Compared with the prior art, the main differences and effects of the embodiments of the present invention are as follows:

A pair of mutually independent channels are arranged in the chip, and the high-level and low-level are respectively connected from the bottom layer to the top layer, and one of the channels is selected as a bit of the version number, so that the modification of the chip version number is no longer dependent on the specific layer. The chip version number can be modified in any metal layer. Thus, in The foundry factory does not modify one or more layers of metal or via to modify the chip version number, which greatly saves the fab cost.

Further, at least one cross structure is set in each group of channels, and only one through hole layer can be modified to implement the modification of the chip version number.

Further, a cross structure is provided for each of the via layers, and the modification of the chip version number can be realized by modifying any one of the via layers.

Further, a set of channels is set for each bit in the version number, and any change of each bit of the version number can be realized as long as it is modified at any one layer.

DRAWINGS

1 is a schematic diagram of a normal IC design flow in the prior art;

2 is a schematic diagram of a normal IC design modification process in the prior art;

Figure 3 is a schematic diagram of the ECO modification process in the prior art;

4 is a schematic view showing the structure of a chip of four metal layers in the first embodiment of the present invention;

5 is a schematic flow chart of a method for modifying a chip version number in a first embodiment of the present invention;

6 is an example of modifying a bit of a version number at the metal2 layer in the first embodiment of the present invention;

7 is an example of modifying a bit of a version number at the metal4 layer in the first embodiment of the present invention;

8 is a schematic flow chart of a method for modifying a chip version number in a second embodiment of the present invention;

9 is a schematic view showing the structure of a chip of four metal layers in a second embodiment of the present invention;

Figure 10 is a plan view of the cross structure of Figure 9;

11 is a schematic diagram of modifying a chip version number in a via layer in a second embodiment of the present invention;

Figure 12 is a plan view showing the modified cross structure in the second embodiment of the present invention;

13 is a first wiring manner of four metal layer chips in a third embodiment of the present invention;

14 is a second wiring manner of four metal layer chips in the third embodiment of the present invention;

Fig. 15 is a third wiring pattern of four metal layer chips in the third embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous technical details are set forth in order to provide the reader with a better understanding of the present application. However, those skilled in the art can understand that the technical solutions claimed in the claims of the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

A first embodiment of the present invention relates to a chip having a version number and a method of modifying a chip version number.

First, the structure of the chip will be described.

The chip comprises N metal layers stacked in sequence, one via layer between each two adjacent metal layers, and one and N a device layer adjacent to one side of the metal layer, wherein the N metal layers are sequentially a first metal layer to an Nth metal layer, N is an integer greater than 1, and the device layer is adjacent to the first metal layer .

There are one or more sets of channels in the chip, each set of channels has the following characteristics:

Each group of channels includes two independent channels that are not connected to each other.

Each channel starts from the first metal layer, runs through each metal layer and the via layer, and is connected to the Nth Metal layer. Each channel behaves as a length of metal wire in each metal layer and as a through hole in each via layer.

One channel is connected to the low level of the device layer through the first metal layer, and the other channel is connected to the high level of the device layer through the first metal layer. . It can be understood that the low level and the high level are the terms in the art. In the embodiment of the present invention, the low level is the level representing the logic '0', and the high level is the logic '1'. 'Level. Preferably, one channel is connected to a unit providing a stable low level (TieLO), and the other channel is connected to a unit providing a stable high level (TieHI) ) Connect. It can also be one channel grounded (low level) and the other channel connected to the supply voltage (high level).

At the Nth Of the metal layers, only one of the two channels is taken out as a bit of the version number. Another channel that is not exported as the version number, if it is to be extracted, can be used as the inverse of the corresponding bit in the version number.

Which of the two channels is derived depends entirely on the current version number at design time, if the current version number needs to represent logic '0' in the specified bit ', then the channel that is connected to the low level is drawn. If the current version number needs to represent the logic '1' in the specified bit, the channel with the high level is drawn.

A pair of mutually independent channels are arranged in the chip, and the high-level and low-level are respectively connected from the bottom layer to the top layer, and one of the channels is selected as a bit of the version number, so that the modification of the chip version number is no longer dependent on the specific layer. The chip version number can be modified in any metal layer.

At the time of chip design, if it is expected that only some of the bits in the version number may be modified, it is only necessary to set the paired channels for these potentially modified bits, and other bits that cannot be modified can be designed using conventional methods. This allows for both the convenience of modification and the simplification of chip design.

If all the bits in the version number may be modified, assuming that the version number consists of M bits, you need to set M in the chip. Group channel, each group of channels corresponding to one bit of the version number. After setting a set of channels for each bit in the version number, any change in the bits of the version number can be achieved by modifying any of the metal layers.

The following is a detailed description of the core structure by taking a chip of four metal layers as an example. The structure of the chip is shown in Figure 4.

The chip has four metal layers, namely metal1, metal2, metal3, and Metal4 has three via layers sandwiched between four metal layers, namely via1, via2, and via3.

Two channels (channel 1 and channel 2), starting from metal1, running through the metal layers and via layers, all the way to Metal4. At metal1, channel 1 is connected to the TieLO of the device layer, and channel 2 is connected to the TieHI of the device layer. In metal4, channel 1 A read-only logic '1' can be derived, and channel 2 can lead to a read-only logic '0'. As one of the chip version numbers, if the bit is designed to be logical '0', then the channel 1 is taken out. If the bit is designed to be logical '1', then channel 2 is drawn.

The method of modifying the chip version number in the chip of the above structure will be described below, and the flow of the method is as shown in FIG. 5.

At step 501 Medium, determining a set of channels corresponding to the bits of the version number to be modified. Not every bit changes every time a chip is redesigned, sometimes it only changes by one or a few bits.

Thereafter, proceeding to step 502, it is determined which layer of the specified metal layer is available for modification, and if it is the top layer, the process proceeds to step 503. If it is the bottom layer, the process proceeds to step 506, and otherwise, the process proceeds to step 504. Generally speaking, with ECO When the mode is modified, only part of the metal layer will be modified, and the revision of the chip version number should be performed in the metal layers to be modified. These metal layers are the metal layers that can be modified. Because the modification of the version number can be implemented as long as any metal layer is modified, if there are multiple metal layers that can be modified, it is necessary to specify one of the metal layers to implement the modification of the version number. This metal layer is in the embodiment of the present invention. It is referred to as the specified metal layer that can be modified.

In step 503, if the specified metal layer that can be modified is the Nth The metal layer (top layer) determines the channel of the group channel that was originally extracted as the version number, cuts off the channel, and introduces another channel in the group channel as a bit of the version number. This process ends thereafter.

In step 504, if the specified metal layer that can be modified is neither the top N a metal layer, which is not the first metal layer at the bottom, cuts two metal wires corresponding to two channels in the specified metal layer to form four portions, the first portion and the first channel in the channel group The upper layers are connected, the second part is connected to the lower layers of the original first channel, the third part is connected to the upper layers of the original second channel in the channel group, and the fourth part is connected to the original second channel The following layers are connected.

Then proceed to step 505 In the specified metal layer, the first portion and the fourth portion are connected by a metal wire, and the second portion and the third portion are connected by a metal wire. This process ends thereafter.

At step 506 If the specified metal layer that can be modified is the first metal layer, the channel that was originally connected to the low level is changed to the high level, and the channel that was originally connected to the high level is changed to the low level.

In addition to the method shown in Figure 5, a similar step 503 can be used regardless of which layer of the specified metal layer is available for modification. The method is processed in 504, that is, the two metal wires in the specified metal layer are cut off, and the four portions formed after the switching are cross-connected. In other words,

steps

502, 503, and 506 are omitted.

The following takes the chip in FIG. 4 as an example to specifically describe the method for modifying the chip version number.

It is assumed that modifications are required at the metal2 layer, and the version number bits that need to be modified correspond to channel 1 and channel 2.

As shown in Figure 6, the metal2 The two metal wires in the middle are cut, and the four portions formed after the cutting are cross-connected. In the figure, × indicates that the line is disconnected, and the curve indicates that the corresponding node is reconnected.

It should be noted that the two curves in Figure 6 are two metal lines implemented in metal2, and there is no adjacent via2. And through via1. In Figure 6, in order to clearly show the connection relationship, it is not very accurate to draw a part of the curve in via2 and via1, which is clarified here. Similarly, Figure 7 There are four curves in it, two of which are the two metal lines implemented in metal2, and the other two are the two metal wires implemented in metal4 and do not pass through the adjacent via layers.

If it needs to be revised again on the basis of Figure 6, the bit of the version number will change again, and it is assumed that this time can only be If it is modified in metal4, it can be modified in the way shown in Figure 7, the two wires in metal4 are cut, and the four parts formed after cutting are cross-connected. Of course, you can also use the steps In the method of 503, if channel 1 is originally drawn, this time, channel 2 can be extracted.

In order to clarify the description and reduce unnecessary repetition, the embodiments in the present invention are exemplified by 4 The chips of the metal layers are described as an example, but it is easy to see that the technical solution of the present invention can be applied to chips of two or more metal layers without any creative labor.

A second embodiment of the present invention relates to a chip having a version number, and a method of modifying a chip version number.

The second embodiment is improved on the basis of the first embodiment, and the main improvement is that one or more cross structures are arranged in each group of channels, so that only one through hole layer can be modified to realize the modification of the chip version number. Especially suitable for When the ECO is modified, only the via layer needs to be modified. Specifically:

There is at least one cross structure in each set of channels.

Each cross structure includes eight nodes centered on one via layer, wherein

The first to fourth nodes are located on one side of the metal layer adjacent to the via layer, and the fifth to eighth nodes are located on the other metal layer adjacent to the other side of the via layer.

The first and second nodes are connected by metal wires, the third and fourth nodes are connected by metal wires, the fifth and sixth nodes are connected by metal wires, and the seventh and eighth nodes are connected by metal wires.

Corresponding to the first and fifth node positions, the second and eighth node positions, the third and seventh node positions, and the fourth and sixth node positions.

There is a through hole between the first and fifth nodes, and a through hole between the third and seventh nodes.

In the set of channels in which the intersecting structure is located, the first and fifth nodes and the through holes therebetween form part of one channel, and the third and seventh nodes and the through holes therebetween form part of the other channel.

A method of modifying the version number of the chip described in the second embodiment will be described below, and a flowchart thereof is shown in FIG.

In step 801, a set of channels corresponding to the bits to be modified are determined.

Then proceed to step 802 For the set of channels, the through holes between the original first and fifth nodes are disconnected in the specified via layer that can be modified.

Thereafter, the process proceeds to step 803, where the through holes between the third and seventh nodes are disconnected.

Thereafter, proceeding to step 804, a new via hole is provided between the second and eighth nodes.

Thereafter, proceeding to step 805, a new via hole is provided between the fourth and sixth nodes.

Steps 802 to 805 The four steps can be interchanged in any order.

The chip structure is specifically described below by taking a chip of four metal layers as an example. Figure 9 shows the via layer via1 A chip structure with a cross structure is set.

In the cross structure in the figure, B2 corresponds to the first node, C2 corresponds to the second node, and B2' corresponds to the third node, C2' Corresponding to the fourth node, B1 corresponds to the fifth node, C1 corresponds to the sixth node, B1' corresponds to the seventh node, and C1' corresponds to the eighth node.

Figure 9 is a schematic diagram, and the information of each node in the corresponding relationship is not fully expressed. Figure 10 is Figure 9. The plan view of the middle cross structure can better represent the correspondence of each node.

As can be seen from Figure 10, in the normal direction of via1, B1 corresponds to B2, and B1' corresponds to B2'. C1' corresponds to C2, and C1 corresponds to C2'. In the figure, B1(B2) means that B1 and B2 have the same plane coordinates, and B1'(B2') means B1' and B2'. The plane coordinates are the same, C1(C2') means C1 and C2' plane coordinates are the same, C1'(C2) means C1' and C2 The plane coordinates are the same. The small circle in the figure indicates that there is a through hole, such as B1(B2) and B1'(B2'). Two locations. The × in the figure indicates that there is no actual through hole, and only one through hole is reserved in the two metal layers adjacent to the via layer, such as C1 (C2') and C1' (C2). .

Assume that only the via1 layer is modified, the original B1 (B2) and B2 (B2') vias are discarded, and the new vias will be C1 and C2' are connected, and C1' and C2 are connected. The same can be achieved by modifying the chip version number. Specific modifications can be seen in Figure 11 and Figure 11 The two curves in the pair correspond to two new through holes. The state of the modified cross structure in the plan view is shown in Figure 12.

It should be noted that the two curves in Figure 11 only represent the new connection relationship, and there is no real slave2. Passing through, the drawing is just to show the connection relationship more clearly.

A third embodiment of the present invention relates to a chip having a version number, and a method of modifying a chip version number.

The third embodiment is improved on the basis of the second embodiment, and the main improvement is that a cross structure is provided for each of the via layers, so that the chip version number can be realized by modifying any one of the via layers. Modifications.

In the second embodiment, only a part of the via layer is provided with a cross structure, which is suitable for knowing in advance which of the via layers may be modified.

In the third embodiment, N-1 exists in each group of channels. A cross structure, each of which is centered on a different via layer.

Taking a chip with 4 metal layers as an example, Figure 13 can be used. The structure, in which the traces of different layers are represented by different line types, as shown in the figure. If there is a need to modify the chip version number by modifying a specific via layer, the original two via holes of the via layer are discarded, and the original unconnected position (marked with × on the figure) is used for the new pass. The hole can be opened.

Those skilled in the art will appreciate that there are many ways to route a particular layout, even for 4 The case of a metal layer chip can also have a lot of routing methods, two of which are listed in Figure 14 and Figure 15.

The third embodiment can realize the purpose of modifying the chip version number by modifying any metal layer or the via layer, making the modification more flexible and effectively saving the revision cost.

Although the invention has been illustrated and described with reference to the preferred embodiments of the present invention, it will be understood The spirit and scope of the invention.

Embodiments of the invention

Industrial applicability

Sequence table free content

Claims

1 . A chip having a version number, comprising N metal layers stacked in sequence, a via layer between each two adjacent metal layers, and a device layer, said N The metal layers are in order from the first metal layer to the Nth metal layer, and N is greater than 1 An integer of the device layer adjacent to the first metal layer; wherein the chip has at least one set of channels, each set of channels having the following characteristics:

2 . The chip with a version number according to claim 1, wherein at least one cross structure exists in each group of channels;

Each of the intersecting structures includes eight nodes centered on one via layer, wherein

The first to fourth nodes are located on one side of the metal layer adjacent to the via layer, and the fifth to eighth nodes are located on the other metal layer adjacent to the other side of the via layer;

3 . The chip with a version number according to claim 2, wherein N-1 exists in each group of channels A cross structure, each of which is centered on a different via layer.

4 . A chip having a version number according to any one of claims 1 to 3, characterized in that M is present in the chip A group channel, each group channel corresponding to one bit of the version number, where M is the number of bits of the version number.

5 . The chip with a version number according to claim 4, wherein one channel passes through the first metal layer and the device layer provides a stable low level unit. The TieLO connection, the other channel is connected to the TieHI unit that provides a stable high level in the device layer through the first metal layer.

6 . According to claim 4 The chip with a version number is characterized in that, in each of the groups of channels, a channel that is not drawn as a version number is taken out as a signal after the corresponding bit in the version number is inverted.

7 . A method of modifying a chip version number, characterized in that the chip comprises N stacked in sequence a metal layer, a via layer between each two adjacent metal layers, and a device layer, wherein the N metal layers are sequentially from the first metal layer to the Nth metal layer, and N is greater than 1 An integer of the device layer adjacent to the first metal layer; at least one set of channels in the chip, each set of channels having the following characteristics:

The method includes the following steps:

Determining a set of channels corresponding to the bits to be modified;

8 . According to claim 7 The method for modifying a chip version number is characterized in that, after the step of determining a group of channels corresponding to the bit to be modified, the method further includes the following steps:

If the specified metal layer that can be modified is the Nth metal layer, then the channel in the group of channels that was originally extracted as the version number is determined at the Nth In the metal layer, the lead of the channel is cut off, and another channel in the set of channels is taken out as a bit of the version number.

9 . According to claim 8 The method for modifying a chip version number is characterized in that, after the step of determining a group of channels corresponding to the bit to be modified, the method further includes the following steps:

If the specified metal layer that can be modified is the first metal layer, the channel that was originally connected to the low level in the device layer is changed to the high level in the device layer, and is connected to the high level in the device layer. The channel is changed to a low level connection in the device layer.

10 . A method of modifying a chip version number, characterized in that the chip comprises N stacked in sequence a metal layer, a via layer between each two adjacent metal layers, and a device layer, wherein the N metal layers are sequentially from the first metal layer to the Nth metal layer, and N is greater than 1 An integer of the device layer adjacent to the first metal layer; at least one set of channels in the chip, each set of channels having the following characteristics:

There is at least one cross structure in each set of channels;

The method includes the following steps:

Determining a set of channels corresponding to the bits to be modified;