EP0424935A2 - Circuit for driving a liquid crystal panel - Google Patents
Circuit for driving a liquid crystal panel Download PDFInfo
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- EP0424935A2 EP0424935A2 EP90120478A EP90120478A EP0424935A2 EP 0424935 A2 EP0424935 A2 EP 0424935A2 EP 90120478 A EP90120478 A EP 90120478A EP 90120478 A EP90120478 A EP 90120478A EP 0424935 A2 EP0424935 A2 EP 0424935A2
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- circuit
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- 1mac
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 229910052729 chemical element Inorganic materials 0.000 claims 1
- 238000003491 array Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Definitions
- the present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit used in an LSI for driving a liquid crystal panel with a MOS structure and displaying data on the liquid crystal panel.
- a semiconductor integrated circuit for driving a liquid crystal panel generally comprises a group of shift registers for transferring data, a wire for fetching the data transferred from each of the shift registers, and a circuit for receiving the data and outputting a signal corresponding to the data.
- Fig. 1 illustrates a circuit which is formed as an LSI.
- the LSI includes shift registers 151a to 15na, signal fetch wires 151b to 15nb, circuit blocks 151c to 15nc, and signal fetch pads 151d to 15nd.
- Fig. 3 is a detail view of a right-side part of the circuit shown in Fig. 2.
- shift register 15nAb comprises clocked inverters 17A1 and 17A2 which are connected in cascade, and circuit block l5nAc includes MOS transistor 17A3.
- shift register 151Ba comprises clocked inverters 17B1 and 17B2 which are connected in cascade, and circuit block 151Bc includes transistor 17B3.
- the direction of current 17AI of transistor 17A3 of the circuit block in the A array is opposite to that of current 17BI of transistor 17B3 of the circuit block in the B array.
- transistors 17A3 and 17B3 whose current directions are opposite to each other are formed on the same chip, the dispersions of output characteristics of these transistors, due to misalignment of the mask caused in the manufacture process, are different as shown in Fig. 4.
- L denotes output characteristics of transistor 17A3, and M indicates those of transistor 17B3.
- Fig. 5 shows glass mask misalignment of source diffusion layer S1, drain diffusion layer D1, and gate electrode G1 of transistor 17A3 and that of source diffusion layer S2, drain diffusion layer D2, and gate electrode G2 of transistor 17B3.
- the misalignment of gate electrode G1 increases the resistance of source diffusion layer S1 and decreases that of drain diffusion layer D1
- the misalignment of gate electrode G2 decreases the resistance of source diffusion layer S2 and increases that of drain diffusion layer D2.
- the increase of resistance of the source diffusion layer is more influential than that of resistance of the drain diffusion layer since a voltage between the gate electrode and source diffusion layer is lowered by not only a variation in value of the resistance but also a drop of voltage of a resistor of the source diffusion layer and a threshold voltage of the transistor is heightened by increase in a voltage between the substrate and source diffusion layer.
- the drain voltage and drain current characteristics of the transistors as shown in Fig. 6, the current of transistor 17A3 whose source resistance increases is smaller than that of transistor 17B3 whose source resistance decreases.
- Fig. 7 illustrates circuit blocks 15nAc and 151Bc including differential amplifiers 15A and 15B, respectively.
- Differential amplifiers 15A and 15B greatly influence the output characteristics of the circuit blocks. Since, however, the differential amplifiers are asymmetric and the currents thereof flow in the directions opposite to each other, they exhibit different output characteristics as shown in Fig. 8.
- a semiconductor integrated circuit for driving a liquid crystal panel comprising: a semiconductor chip; a first group of m data transfer means formed on said semiconductor chip, for transferring data in one direction; a second group of m data transfer means formed on said semiconductor chip, for transferring data from said first group of m data transfer means in a direction opposite to said one direction; and first and second groups of m data output means for temporarily storing data from said first and second groups of m data transfer means and outputting the data outside said semiconductor chip, wherein circuit elements of a first one of said first group of data output means and an m-th one of said second group of data output means, those of a second one of said first group thereof and a (m-1)th one of said second group thereof, ..., and those of an m-th one of said first group thereof and a first one of said second group thereof have output stages for supplying data outside said semiconductor chip, the circuit elements constituting the output
- the transistors of both circuit blocks which greatly influence the circuit characteristics between the blocks, are symmetrical and the currents thereof flow in the same direction. Even though the dispersion of the characteristics due to mask misalignment occurs in the manufacturing process, the uniform characteristics can be obtained between both the circuit blocks.
- Fig. 9 is a block diagram showing a basic arrangement of a semiconductor integrated circuit for driving a liquid crystal panel according to the embodiment of the present invention.
- shift registers 11Aa to 1mAa connected in cascade for transferring data from an LSI for driving a liquid crystal panel to the right and shift registers 11Ba to 1mBa connected in cascade, for transferring the data to the left are arranged so as to turn around a data transfer path.
- Signal lines 11Ab to 1mAb are arranged between shift registers 11Aa to 1mAa and circuit blocks 11Ac to 1mAc, respectively, to supply data from the shift registers to the circuit blocks.
- Signal lines 11Bb to 1mBb are formed between shift registers 11Ba to 1mBa and circuit blocks 1Bc to 1mBc, respectively, to supply data from the shift registers to the circuit blocks.
- Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc include transistors to the gates of which data is input through signal lines 1Ab to 1mAb and 1Bb to 1mBb.
- portions of the circuit blocks directly connected to pads, mentioned later have a symmetrical structure and the same function, and the current flows through the circuit portions in the same direction.
- Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc temporarily store data from shift registers 11Aa to 1mAa and 11Ba to 1mBa, respectively.
- Fig. 10 is a block diagram of the semiconductor integrated circuit shown in Fig. 9, which is formed on chip CH. The circuit is divided into two stages of A and B arrays, and pads 21Ad to 2mAd and 21Bd to 2mBd are pulled out of four sides of chip CH. In Fig. 10, symbol IP indicates an input pad.
- Fig. 11 is a circuit diagram specifically showing part 2c of the circuit shown in Fig. 10.
- the A Array comprises shift register 1mAa including clocked inverters 3AI and 3A2, circuit block 1mAc including MOS transistor 3A3 for receiving transfer data, as a gate signal, from shift register 1mAa through signal line 1mAb, and pad 1mAd serving as a terminal for supplying data from circuit block 1mAc outside the chip.
- the B array comprises shift register 1mBa including clocked inverter 3B1 and 3B2, circuit block 11Bc including MOS transistor 3B3 for receiving transfer data, as a gate signal, from shift register 11Ba through signal line 11Bb, and pad 11Bd serving as a terminal for supplying data from the circuit block outside the chip. Since MOS transistors 3A3 and 3B3 are directly connected to other circuits, each of which constitutes an LSI for driving a liquid crystal panel which is arranged outside the chip, through pads 1mAd and 11Bd, respectively, the MOS transistors greatly influence the characteristics of circuit blocks 1mAc and 11Bc.
- MOS transistors 3A3 and 3B3 are symmetrical, and currents 3AI and 3BI flow in the same direction. Therefore, as shown in Fig. 12, the output characteristics of MOS transistors 3A3 and 3B3 are the same.
- Fig. 13 is a circuit diagram specifically showing another example of part 2c of the circuit shown in Fig. 10.
- reference numerals 15A and 15B denote differential amplifiers
- TR1 and TR2 indicate constant current source transistors
- C1 and C2 show dynamic storing capacitors
- AS1 and AS2 indicate analog switches
- IN1 and IN2 denote inverters. Since differential amplifiers 15A and 15B are directly connected to other circuits, each of which constitutes an LSI for driving a liquid crystal panel which is arranged outside the chip, through pads 1mAd and 11Bd, respectively, the differential amplifiers greatly influence the characteristics of circuit blocks 1mAc and 11Bc.
- the plan patterns of differential amplifiers 15A and 15B are symmetrical, and currents 3AI and 3BI flow in the same direction. Even though mask misalignment occurs in manufacturing an LSI for driving a liquid crystal panel, the output characteristics of differential amplifiers 15A and 15B are the same, as shown in Fig. 14.
- Fig. 15 is a plan pattern view of transistors 3A3 and 3B3 shown in Fig. 11 for explaining the effects obtained by symmetrically arranging the MOS transistors.
- MOS transistors In conventional transistors which are asymmetrically arranged and into which currents flow in different directions, even though they are formed in the same chip, the characteristics of the transistors vary with the misalignment of masks and the angle of ion-implantation for diffusion of an impurity into source and drain regions. If, however, the transistors are symmetrically arranged and the directions of the currents flowing through the transistors are the same, the characteristics of the transistors are uniformed.
- source regions S11 and S12 have the same increase in resistance and drains D11 and D12 have the same decrease in resistance, and the currents of transistors 3A3 and 3B3 flow in the same direction. As shown in Fig. 16, therefore, the drain voltage - drain current characteristics of the transistors are the same.
- MOS transistors 17A3 and 17B3 of the conventional semiconductor integrated circuit for driving a liquid crystal panel shown in Fig. 5 their plan patterns are asymmetrical, and the area of source region S1 of MOS transistor 17A3 is in inverse proportion to that of source region S2 of MOS transistor 17B3. Further, the area of drain regions D1 of MOS transistor 17A3 is in inverse proportion to that of drain region D2 of MOS transistor 17B3.
- the source resistances of MOS transistors 17A3 and 17B3 are in inverse proportion to each other, and the drain resistances the MOS transistors are also in inverse proportion to each other. Hence, the electrical characteristics of the transistors are different.
- the differences in area between source regions S1 and S2 and between drain regions D1 and D2 of MOS transistors 17A3 and 17B3 are caused by the mask misalignment in the manufacturing process. The differences are also caused for the following reason.
- an impurity diffuse from the surface of a semiconductor substrate at a predetermined implantation angle which is shifted from the right angle with the surface of the semiconductor substrate and therefore, a portion where the implantation is intercepted by the gate region is n arrow and the other portion is large.
- the difference in area causes the electrical characteristics of the transistors to differ from each other.
- the plan patterns of MOS transistors 3A3 and 3B3 are symmetrical with respect to line L.
- the areas of source regions S11 and S12 of both the transistors are proportionate to each other and the areas of drain regions D11 and D12 thereof are proportionate to each other.
- the source resistances of transistors 3A3 and 3B3 are proportionate to each other and the drain resistances thereof are proportionate to each other.
- MOS transistors 3A3 and 3B3 are symmetrical with respect to line L, even if source regions S11 and S12 and drain regions D11 and D12 are shifted from polysilicon gates G11 and G12, the electrical characteristics of both the transistors are always the same.
- the drain voltage - drain current characteristics of the transistors are therefore the same, as shown in Fig. 16.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Liquid Crystal Display Device Control (AREA)
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Abstract
Description
- The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit used in an LSI for driving a liquid crystal panel with a MOS structure and displaying data on the liquid crystal panel.
- A semiconductor integrated circuit for driving a liquid crystal panel generally comprises a group of shift registers for transferring data, a wire for fetching the data transferred from each of the shift registers, and a circuit for receiving the data and outputting a signal corresponding to the data. Fig. 1 illustrates a circuit which is formed as an LSI. The LSI includes
shift registers 151a to 15na,signal fetch wires 151b to 15nb, circuit blocks 151c to 15nc, and signal fetch pads 151d to 15nd. - When a semiconductor integrated circuit is formed on a chip as an LSI, in order to reduce the size of the chip, the circuit is divided into A and B arrays to fetch output signals from four sides of the chip, as illustrated in Fig. 2. Since the order of arrangement of output pads 151Ad to 15nBd is the same as that of data transfer, data is transferred from left to right in the A array and from right to left in the B array in shift registers 151Aa to 15nBa, as shown in Fig. 2. The circuit blocks supplied with signals from the shift registers have the same block pattern to easily lay out a mask pattern. Circuit blocks 151Ac to 15nAc in the A array and circuit blocks 151Bc to 15nBc in the B array are, therefore, arranged opposite to each other. In Fig. 2, the direction of character "P" of each circuit block corresponds to that of a mask pattern of the circuit block.
- Fig. 3 is a detail view of a right-side part of the circuit shown in Fig. 2. Referring to Fig. 3, shift register 15nAb comprises clocked inverters 17A1 and 17A2 which are connected in cascade, and circuit block l5nAc includes MOS transistor 17A3. Furthermore, shift register 151Ba comprises clocked inverters 17B1 and 17B2 which are connected in cascade, and circuit block 151Bc includes transistor 17B3. The direction of current 17AI of transistor 17A3 of the circuit block in the A array is opposite to that of current 17BI of transistor 17B3 of the circuit block in the B array. Even though transistors 17A3 and 17B3 whose current directions are opposite to each other are formed on the same chip, the dispersions of output characteristics of these transistors, due to misalignment of the mask caused in the manufacture process, are different as shown in Fig. 4. In Fig. 4, L denotes output characteristics of transistor 17A3, and M indicates those of transistor 17B3.
- An explanation of misalignment of the patterns of, for example, a diffusion mask and a polysilicon mask will be given as follows. Fig. 5 shows glass mask misalignment of source diffusion layer S₁, drain diffusion layer D₁, and gate electrode G₁ of transistor 17A3 and that of source diffusion layer S₂, drain diffusion layer D₂, and gate electrode G₂ of transistor 17B3. The misalignment of gate electrode G₁ increases the resistance of source diffusion layer S₁ and decreases that of drain diffusion layer D₁, and the misalignment of gate electrode G₂ decreases the resistance of source diffusion layer S₂ and increases that of drain diffusion layer D₂. The increase of resistance of the source diffusion layer is more influential than that of resistance of the drain diffusion layer since a voltage between the gate electrode and source diffusion layer is lowered by not only a variation in value of the resistance but also a drop of voltage of a resistor of the source diffusion layer and a threshold voltage of the transistor is heightened by increase in a voltage between the substrate and source diffusion layer. As the drain voltage and drain current characteristics of the transistors, as shown in Fig. 6, the current of transistor 17A3 whose source resistance increases is smaller than that of transistor 17B3 whose source resistance decreases.
- Fig. 7 illustrates circuit blocks 15nAc and 151Bc including
differential amplifiers Differential amplifiers - It is accordingly an object of the present invention to provide a semiconductor integrated circuit for driving a liquid crystal panel in which the output characteristics between elements or circuits are uniformed to obtain uniform outputs.
- According to an aspect of the present invention, there is provided a semiconductor integrated circuit for driving a liquid crystal panel, comprising: a semiconductor chip; a first group of m data transfer means formed on said semiconductor chip, for transferring data in one direction; a second group of m data transfer means formed on said semiconductor chip, for transferring data from said first group of m data transfer means in a direction opposite to said one direction; and first and second groups of m data output means for temporarily storing data from said first and second groups of m data transfer means and outputting the data outside said semiconductor chip, wherein circuit elements of a first one of said first group of data output means and an m-th one of said second group of data output means, those of a second one of said first group thereof and a (m-1)th one of said second group thereof, ..., and those of an m-th one of said first group thereof and a first one of said second group thereof have output stages for supplying data outside said semiconductor chip, the circuit elements constituting the output stages have the same function and are symmetrically arranged, and currents flow through the symmetrically-arranged circuits elements in the same direction.
- In the present invention, the transistors of both circuit blocks, which greatly influence the circuit characteristics between the blocks, are symmetrical and the currents thereof flow in the same direction. Even though the dispersion of the characteristics due to mask misalignment occurs in the manufacturing process, the uniform characteristics can be obtained between both the circuit blocks.
- This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
- Figs. 1 and 2 are block diagrams illustrating a conventional semiconductor integrated circuit for driving a liquid crystal panel;
- Fig. 3 is a circuit diagram illustrating the conventional semiconductor integrated circuit;
- Fig. 4 is a graph of the electrical characteristics of MOS transistors of the conventional semiconductor integrated circuit;
- Fig. 5 is a plan pattern view of the MOS transistors of the conventional semiconductor integrated circuit;
- Fig. 6 is a graph of the electrical characteristics of the MOS transistors of the conventional semiconductor integrated circuit;
- Fig. 7 is a circuit diagram of the conventional semiconductor integrated circuit using differential amplifiers;
- Fig. 8 is a graph of the output characteristics of the differential amplifiers;
- Figs. 9 and 10 are block diagrams showing a semiconductor integrated circuit for driving a liquid crystal panel according to the present invention;
- Fig. 11 is a circuit diagram specifically showing shift registers and circuit blocks of the circuit shown in Figs. 9 and 10;
- Fig. 12 is a graph of the output characteristics of a MOS transistor at the output stage of the circuit blocks shown in Fig. 11;
- Fig. 13 is a circuit diagram specifically showing shift registers and circuit blocks shown in Figs. 9 and 10;
- Fig. 14 is a graph of the output characteristics of a differential amplifier at the output stage of the circuit blocks shown in Fig. 13;
- Fig. 15 is a pattern plan view of the MOS transistor shown in Fig. 12; and
- Fig. 16 is a graph of electrical characteristics of the MOS transistor shown in Fig. 12.
- An embodiment of the present invention will be described with reference to the accompanying drawings.
- Fig. 9 is a block diagram showing a basic arrangement of a semiconductor integrated circuit for driving a liquid crystal panel according to the embodiment of the present invention. In Fig. 9, shift registers 11Aa to 1mAa connected in cascade, for transferring data from an LSI for driving a liquid crystal panel to the right and shift registers 11Ba to 1mBa connected in cascade, for transferring the data to the left are arranged so as to turn around a data transfer path. Signal lines 11Ab to 1mAb are arranged between shift registers 11Aa to 1mAa and circuit blocks 11Ac to 1mAc, respectively, to supply data from the shift registers to the circuit blocks. Signal lines 11Bb to 1mBb are formed between shift registers 11Ba to 1mBa and circuit blocks 1Bc to 1mBc, respectively, to supply data from the shift registers to the circuit blocks. Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc include transistors to the gates of which data is input through signal lines 1Ab to 1mAb and 1Bb to 1mBb. In the upper and lower corresponding circuit blocks in Fig. 9, portions of the circuit blocks directly connected to pads, mentioned later, have a symmetrical structure and the same function, and the current flows through the circuit portions in the same direction. Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc temporarily store data from shift registers 11Aa to 1mAa and 11Ba to 1mBa, respectively.
- Fig. 10 is a block diagram of the semiconductor integrated circuit shown in Fig. 9, which is formed on chip CH. The circuit is divided into two stages of A and B arrays, and pads 21Ad to 2mAd and 21Bd to 2mBd are pulled out of four sides of chip CH. In Fig. 10, symbol IP indicates an input pad.
- Fig. 11 is a circuit diagram specifically showing part 2c of the circuit shown in Fig. 10. The A Array comprises shift register 1mAa including clocked inverters 3AI and 3A2, circuit block 1mAc including MOS transistor 3A3 for receiving transfer data, as a gate signal, from shift register 1mAa through signal line 1mAb, and pad 1mAd serving as a terminal for supplying data from circuit block 1mAc outside the chip. The B array comprises shift register 1mBa including clocked inverter 3B1 and 3B2, circuit block 11Bc including MOS transistor 3B3 for receiving transfer data, as a gate signal, from shift register 11Ba through signal line 11Bb, and pad 11Bd serving as a terminal for supplying data from the circuit block outside the chip. Since MOS transistors 3A3 and 3B3 are directly connected to other circuits, each of which constitutes an LSI for driving a liquid crystal panel which is arranged outside the chip, through pads 1mAd and 11Bd, respectively, the MOS transistors greatly influence the characteristics of circuit blocks 1mAc and 11Bc. The plan patterns of MOS transistors 3A3 and 3B3 are symmetrical, and currents 3AI and 3BI flow in the same direction. Therefore, as shown in Fig. 12, the output characteristics of MOS transistors 3A3 and 3B3 are the same.
- Fig. 13 is a circuit diagram specifically showing another example of part 2c of the circuit shown in Fig. 10. In Fig. 13,
reference numerals differential amplifiers differential amplifiers differential amplifiers - Fig. 15 is a plan pattern view of transistors 3A3 and 3B3 shown in Fig. 11 for explaining the effects obtained by symmetrically arranging the MOS transistors. In conventional transistors which are asymmetrically arranged and into which currents flow in different directions, even though they are formed in the same chip, the characteristics of the transistors vary with the misalignment of masks and the angle of ion-implantation for diffusion of an impurity into source and drain regions. If, however, the transistors are symmetrically arranged and the directions of the currents flowing through the transistors are the same, the characteristics of the transistors are uniformed. Even when misalignment occurs between a diffusion mask pattern and a mask pattern of polysilicon gates G₁₁ and G₁₂, source regions S₁₁ and S₁₂ have the same increase in resistance and drains D₁₁ and D₁₂ have the same decrease in resistance, and the currents of transistors 3A3 and 3B3 flow in the same direction. As shown in Fig. 16, therefore, the drain voltage - drain current characteristics of the transistors are the same.
- In MOS transistors 17A3 and 17B3 of the conventional semiconductor integrated circuit for driving a liquid crystal panel shown in Fig. 5, their plan patterns are asymmetrical, and the area of source region S₁ of MOS transistor 17A3 is in inverse proportion to that of source region S₂ of MOS transistor 17B3. Further, the area of drain regions D₁ of MOS transistor 17A3 is in inverse proportion to that of drain region D₂ of MOS transistor 17B3. The source resistances of MOS transistors 17A3 and 17B3 are in inverse proportion to each other, and the drain resistances the MOS transistors are also in inverse proportion to each other. Hence, the electrical characteristics of the transistors are different.
- The differences in area between source regions S₁ and S₂ and between drain regions D₁ and D₂ of MOS transistors 17A3 and 17B3 are caused by the mask misalignment in the manufacturing process. The differences are also caused for the following reason. To form the source and drain regions, an impurity diffuse from the surface of a semiconductor substrate at a predetermined implantation angle which is shifted from the right angle with the surface of the semiconductor substrate and therefore, a portion where the implantation is intercepted by the gate region is n arrow and the other portion is large. The difference in area causes the electrical characteristics of the transistors to differ from each other.
- As is apparent from Fig. 15, however, the plan patterns of MOS transistors 3A3 and 3B3 are symmetrical with respect to line L. The areas of source regions S₁₁ and S₁₂ of both the transistors are proportionate to each other and the areas of drain regions D₁₁ and D₁₂ thereof are proportionate to each other. Accordingly, the source resistances of transistors 3A3 and 3B3 are proportionate to each other and the drain resistances thereof are proportionate to each other.
- Since the plan patterns of MOS transistors 3A3 and 3B3 are symmetrical with respect to line L, even if source regions S₁₁ and S₁₂ and drain regions D₁₁ and D₁₂ are shifted from polysilicon gates G₁₁ and G₁₂, the electrical characteristics of both the transistors are always the same. The drain voltage - drain current characteristics of the transistors are therefore the same, as shown in Fig. 16.
- Reference signs in the claims are intended for better understanding and shall not limit the scope.
Claims (3)
a semiconductor chip (CH);
a first group of m data transfer means (11Aa, 12Aa, ..., 1mAa) formed on said semiconductor chip (CH), for transferring data in one direction;
a second group of m data transfer means (11Ba, 12Ba, ..., 1mBa) formed on said semiconductor chip (CH), for transferring data from said first group of m data transfer means (11Aa, 12Aa, ..., 1mAa) in a direction opposite to said one direction; and
first and second groups of m data output means (11Ac, 12Ac, ..., 1mAc; 11Bc, 12Bc, ..., 1mBc) for temporarily storing data from said first and second groups of m data transfer means (11Aa, 12Aa, ..., 1mAa; 11Ba, 12Ba, ..., 1mBa) and outputting the data outside said semiconductor chip (CH),
characterized in that circuit elements of a first one (11Ac) of said first group of data output means (11Ac, 12Ac, ..., 1mAc) and an m-th one (1mBc) of said second group of data output means (11Bc, 12Bc, ..., 1mBc), those of a second one (12Ac) of said first group thereof and a (m-1)th one (1m-1Bc) of said second group thereof, ..., and those of an m-th one (1mAc) of said first group thereof and a first one (11Bc) of said second group thereof have output stages for supplying data outside said semiconductor chip (CH), the circuit elements constituting the output stages have the same function and are symmetrically arranged, and currents flow through the symmetrically-arranged circuits elements in the same direction.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1277189A JP2653526B2 (en) | 1989-10-26 | 1989-10-26 | Semiconductor integrated circuit |
JP277189/89 | 1989-10-26 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0424935A2 true EP0424935A2 (en) | 1991-05-02 |
EP0424935A3 EP0424935A3 (en) | 1992-04-29 |
EP0424935B1 EP0424935B1 (en) | 1994-12-21 |
Family
ID=17580048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP90120478A Expired - Lifetime EP0424935B1 (en) | 1989-10-26 | 1990-10-25 | Circuit for driving a liquid crystal panel |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0424935B1 (en) |
JP (1) | JP2653526B2 (en) |
KR (1) | KR940008218B1 (en) |
DE (1) | DE69015316T2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6241246B2 (en) * | 2013-12-10 | 2017-12-06 | セイコーエプソン株式会社 | Detection device, sensor, electronic device, and moving object |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0078402A1 (en) * | 1981-10-29 | 1983-05-11 | Kabushiki Kaisha Toshiba | Drive circuit for display panel having display elements disposed in matrix form |
JPS6418250A (en) * | 1987-07-14 | 1989-01-23 | Toshiba Corp | Semiconductor integrated circuit |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5945248B2 (en) * | 1975-12-24 | 1984-11-05 | 富士通株式会社 | Transversal filter |
JPS61125147A (en) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Semiconductor integrated circuit |
-
1989
- 1989-10-26 JP JP1277189A patent/JP2653526B2/en not_active Expired - Fee Related
-
1990
- 1990-10-25 DE DE69015316T patent/DE69015316T2/en not_active Expired - Fee Related
- 1990-10-25 EP EP90120478A patent/EP0424935B1/en not_active Expired - Lifetime
- 1990-10-26 KR KR1019900017197A patent/KR940008218B1/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0078402A1 (en) * | 1981-10-29 | 1983-05-11 | Kabushiki Kaisha Toshiba | Drive circuit for display panel having display elements disposed in matrix form |
JPS6418250A (en) * | 1987-07-14 | 1989-01-23 | Toshiba Corp | Semiconductor integrated circuit |
Non-Patent Citations (2)
Title |
---|
EDN ELECTRICAL DESIGN NEWS. vol. 30, no. 18, August 1985, NEWTON, MASSACHUSETTS US pages 83 - 88; E. TEJA: 'LCD-driver/controller ICs offer versatility in configuration and function' * |
PATENT ABSTRACTS OF JAPAN vol. 13, no. 196 (E-755)10 May 1989 & JP-A-1 018 250 ( TOSHIBA CO. ) 23 January 1989 * |
Also Published As
Publication number | Publication date |
---|---|
DE69015316T2 (en) | 1995-05-24 |
DE69015316D1 (en) | 1995-02-02 |
EP0424935A3 (en) | 1992-04-29 |
KR940008218B1 (en) | 1994-09-08 |
KR910008864A (en) | 1991-05-31 |
EP0424935B1 (en) | 1994-12-21 |
JP2653526B2 (en) | 1997-09-17 |
JPH03139695A (en) | 1991-06-13 |
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