JPH07161938A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a wiring length between basic cells inside a fast signal transmission logical part and to reduce a signal transmission delay time by concentrating and arranging the fast signal transmission logical part (e.g. a logic functional part) in a desired region central part and by arranging a slow signal transmission logic part (e.g. a scan logical part) in a desired region peripheral part. CONSTITUTION:A basic cell arrangement region 35 of a scan logical part is formed in a peripheral part of a basic cell line 3 inside a block logical part 33. Freedom of basic cell wiring inside a logical functional part can be raised since the basic cell arrangement region 35 of a scan logical part does not get into a basic cell arrangement region 34 of a logical functional part. An input/ output buffer 2 is formed in a peripheral part of this chip 1. A central part of the chip 1 is formed of a plurality of block logical parts 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to the arrangement of basic cells forming the high speed signal propagation logic unit and the low speed signal propagation logic unit.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, a high speed signal propagation logic unit and a low speed signal propagation logic unit coexist. Here, the high-speed signal propagation logic unit will be described as a logic function unit, and the low-speed signal propagation logic unit will be described as a diagnostic scan logic unit of the logic function unit. A semiconductor integrated circuit is a circuit in which a logic function unit and a basic cell constituting a diagnostic scan logic unit of the logic function unit are arranged on a semiconductor substrate, and a logic circuit capable of realizing a function is formed by wiring between the basic cells. . FIG. 1 shows the configuration of a conventional semiconductor integrated circuit. In FIG. 1, reference numeral 1 denotes a chip that constitutes a semiconductor integrated circuit.
An input / output buffer 2 is provided in the peripheral portion of. Chip 1
In the central portion of, the basic cell row 3 is surrounded by the wiring area 4 and arranged at arbitrary intervals. The logical function is realized by wiring between the basic cells forming the basic cell row 3 and between the input / output buffer 2 and the basic cell. A diagnostic circuit is required to detect faults in logic functions. This diagnosis is performed by the scan path logic using the logic circuit shown in FIG. Reference numerals 5 and 6 in FIG. 2 denote flip-flops in the logic function unit, which are connected to the data terminals through selectors 7 and 8 in the form of a shift register. The clock terminals of the flip-flops 5 and 6 are connected to the outputs of the selectors 9 and 10, and the set pin and the reset pin are AND gates 11, 12 and 13, 1 respectively.
4 outputs. The decoder 16 inputs the diagnostic address signal 23 and supplies the output signal of the decoder 16 and the diagnostic clock signal 22 to the selectors 9 and 10 via the AND gate 15. As a result, the selectors 9 and 1
0 transfers the logic function internal clock signal 24 or the diagnostic clock signal 22 to the flip-flops 5 and 6 in response to the mode setting signal 25. The AND gates 13 and 14 respond to the mode setting signal 25 by reset signals 26 and 27.
Is enabled or disabled. The selector 7 transfers the logic function internal signal 19 or the diagnostic input data signal 21 to the flip-flop 5 in response to the mode setting signal 25. The selector 8 transfers the output signal of the flip-flop 5 or the logic function unit internal signal 20 to the flip-flop 6 in response to the mode setting 25. AND gate 11, 1
2 is a set signal 17, 1 in response to the mode setting signal 25
8 is enabled or disabled. Normally, the basic cells of the scan logic unit 35 shown in FIG. 2 are arranged in the basic cell column 3 of FIG. 1 without being distinguished from the basic cells of the logic function unit 34. As a method related to this type of arranging method, there is JP-A-63-300528.

[0003]

The scan logic unit is not directly related to the logical function operation of the semiconductor integrated circuit, and is not related to the high speed operation of the semiconductor integrated circuit. However, in the above arrangement method, as shown in FIG. 3, the area of the basic cells 15 and 16 of the scan logic section and the scan logic section wirings 28 to 32 shorten the signal propagation delay time between the basic cells 5 and 7 of the logic function section. It was an obstacle to the shortest wiring for the purpose.

[0004]

The present invention is a semiconductor integrated circuit having a plurality of basic cell forming portions and a wiring region on a semiconductor chip and realizing a logical function in a wiring process. When arranging a plurality of block logic units having basic cells constituting the diagnostic scan logic unit of the logic function unit on a chip, each logic function unit basic cell is arranged in the central portion of the block logic unit and the peripheral portion is scanned. It is characterized by arranging logic unit basic cells. Further, the wiring length between the block logic units may be longer due to the scan logic unit and the signal propagation delay time may be delayed, but this can be avoided by using the driver cells between the block logic units having high driving capability.

[0005]

When the block logic section is arranged on the chip, the basic cell area of the scan logic section and the wiring channel mixed between the basic cells of the logic function section are arranged in the peripheral section so that between the basic cells of the logic function section. The wiring length is shortened to reduce the signal propagation delay time in the block logic unit.

[0006]

4 and 5 show an embodiment of the present invention. In FIG. 4, reference numeral 3 denotes a basic cell column in the block logic unit 33, and a basic cell column 3 in the block logic unit is provided in the peripheral portion. A basic cell placement area 35 of the scan logic portion is formed. Since the basic cell placement area 35 of the scan logic section does not enter the basic cell placement area 34 of the logic function section, the degree of freedom in the wiring between the basic cells of the logic function section can be increased. Figure 5
It is an embodiment in which a plurality of block logical units shown in FIG. 4 are arranged on a chip. In FIG. 5, reference numeral 1 denotes a chip forming a semiconductor integrated circuit, and an input / output buffer 2 is formed in the peripheral portion of this chip 1. The central part of the chip 1 is formed by a plurality of block logic parts 33. Here, there is a possibility that the scan logic units arranged in the respective peripheral portions of the plurality of block logic units are adjacent to each other and a wide area 36 is generated, which causes an obstacle to the wiring between the block logic units and delays the signal propagation delay time between the block logic units. However, this uses a high drive capability inter-block logic inter-driver cell, shown at 37.

As described above, according to this embodiment, the following effects can be obtained.

(1) Since the basic cells of the scan logic unit do not enter the basic cell placement region of the logic function unit in the block logic unit, the wiring between the basic cells of the logic function unit is shortened, The signal propagation delay time can be shortened.

(2) By shortening the usage rate of the basic inter-cell wiring channel of the scan logic unit in the basic inter-cell wiring channel region of the logic functional unit in the block logic unit, the wiring between the basic cells of the logic functional unit is shortened. The signal propagation delay time between the basic cells of the logic function unit can be shortened.

Although the present invention has been specifically described based on the embodiments of the present invention, it is needless to say that the present invention is not limited to the above-mentioned one embodiment and can be modified without departing from the scope of the invention. Absent. For example, the basic cells of the logic function section are not limited to the plurality of block logic sections, but the basic cells of the logic function section may be arranged in the central portion of the chip basic cell row, and the basic cells of the scan logic section may be arranged in the peripheral basic cell row. Further, the circuit realized in the scan logic area is not limited to the one embodiment, and may have any configuration as long as the scan logic can be realized.

[0011]

The effects obtained by the representative one of the inventions disclosed in the present application are as follows.

By arranging the basic cell region of the scan logic unit and the wiring channel mixed between the basic cells of the logic function unit in the peripheral portion, the wiring between the basic cells of the logic function unit is shortened and the signal propagation delay time in the block logic unit is reduced. Shorten.
As a result, high speed operation in the semiconductor integrated circuit can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of a conventional semiconductor integrated circuit.

FIG. 2 is a circuit diagram illustrating a scan logic unit.

FIG. 3 is a conventional basic cell layout diagram.

FIG. 4 is a block logical block layout diagram of an embodiment of the present invention.

FIG. 5 is a chip layout diagram of an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Chip, 2 ... Input / output buffer, 3 ... Basic cell row, 4 ... Wiring area, 5, 6 ... Flip-flop, 7-10 ... Selector, 11-15 ... AND gate, 16 ... Decoder, 17, 18 ... Set Signals, 19, 20 ... Data signal in logic function part, 21 ... External diagnostic data, 22 ... Diagnostic clock signal, 23 ... Diagnostic address signal, 24 ... Normal clock signal, 25 ... Mode setting signal, 26, 27 ... Reset signal, 33 ... block logic unit, 34 ... logic function unit, 35 ... scan logic unit, 37 ... driver cell.

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Claims (1)

[Claims] 1. In a semiconductor integrated circuit comprising a diffusion layer forming a plurality of basic cells on a semiconductor chip and a wiring layer connecting the basic cells, a high-speed signal propagation logic unit is centrally arranged in a central portion of a desired region. The low-speed signal propagation logic section is arranged in the peripheral portion of the desired area.