WO2011070599A1 - Appareil et procédé pour lire une cellule mémoire à changement de phase - Google Patents

Appareil et procédé pour lire une cellule mémoire à changement de phase Download PDF

Info

Publication number
WO2011070599A1
WO2011070599A1 PCT/IT2009/000557 IT2009000557W WO2011070599A1 WO 2011070599 A1 WO2011070599 A1 WO 2011070599A1 IT 2009000557 W IT2009000557 W IT 2009000557W WO 2011070599 A1 WO2011070599 A1 WO 2011070599A1
Authority
WO
WIPO (PCT)
Prior art keywords
dummy
phase
memory cell
change memory
bitline
Prior art date
Application number
PCT/IT2009/000557
Other languages
English (en)
Inventor
Ferdinando Bedeschi
Original Assignee
Ferdinando Bedeschi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ferdinando Bedeschi filed Critical Ferdinando Bedeschi
Priority to PCT/IT2009/000557 priority Critical patent/WO2011070599A1/fr
Priority to US13/514,532 priority patent/US8953360B2/en
Publication of WO2011070599A1 publication Critical patent/WO2011070599A1/fr
Priority to US14/615,788 priority patent/US9431102B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Definitions

  • Embodiments of the invention are in the field of phase-change memory cells and, in particular, apparatuses and methods for reading phase-change memory cells.
  • PCM Phase-Change Memory
  • Figure 1 illustrates a schematic representing conventional PCM cell biasing.
  • Figure 2 illustrates a schematic representing conventional column biasing for a PCM cell.
  • Figure 3 is a plot of current of a chalcogenide phase-change material (Igst) as a function of the voltage and the resistance of a chalcogenide phase-change material (Vgst), under a conventional PCM sense amplifier bitline voltage biasing with the cell selector being the loadline (Veb), in accordance with an embodiment of the present invention.
  • Figure 4 illustrates a circuit diagram of an apparatus for reading a phase-change memory cell, the circuit including a portion with a dummy bitline and a dummy wordline, in accordance with an embodiment of the present invention.
  • Figure 5 illustrates a layout of a sense amplifier for reading a phase- change memory cell which is biasing both the selected bitline (connected to SIN) and the dummy bitline (connected to RTN) using an unbalanced comparator to read the data (the unbalanced comparator triggers when SIN is equal to or greater than RTN+Vsafe, Vsafe being the unbalancing voltage quantity), in accordance with an embodiment of the present invention.
  • Figure 6A illustrates . a conceptual schematic of a current scan for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 6B illustrates a plot of current ramp as a function of time associated with the current scan of Figure 6A, in accordance with an embodiment of the present invention.
  • Figure 7A illustrates a conceptual schematic of the bitline and dummy bitline voltages during the current scan for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 7B illustrates a plot of current ramp as a function of time associated with the current scan of Figure 7A, in accordance with an embodiment of the present invention.
  • Figure 8 illustrates a conceptual block diagram of a layout of an apparatus for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 9 illustrates a decision tree for a screen out plus current ramp approach to reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 10 illustrates conception diagrams for current ramp generation for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 1 1 illustrates a look-up table for current ramp generation and cell state detection during reading of a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 12 illustrates exemplary output from a current ramp generation using a look-up table, the current ramp generation for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 13 illustrates an array of phase-change memory cells with at least one phase-change memory cell coupled to a circuit with a dummy bitline used for reading the phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 14 illustrates a schematic representation of a wireless architecture that incorporates an array of phase-change memory cells with at least one phase-change memory cell coupled to a circuit with a dummy bitline and a dummy wordline used for reading the phase-change memory cell, in accordance with an embodiment of the present invention.
  • a circuit includes a current ramp circuit.
  • a current forcing module is coupled with the current ramp circuit.
  • a Veb emulation circuit is coupled with the current forcing module by a voltage adder, the voltage adder to sum an output from the Veb emulation circuit and a high impedance voltage source.
  • a method for reading a phase-change memory cell includes forcing a current ramp into both a bitline and a dummy bitline, the dummy bitline having a voltage. The method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with the phase-change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell and added in series to the voltage of the dummy bitline.
  • the predefined value is independent from a resistance value of the phase-change memory cell and it is obtained using a dummy bitline, a dummy wordline and a dummy cell (or any emulation of them) in which the same current ramp is forced at the same time, coupled together with an high impedance voltage source generating a safe voltage.
  • references may be made to (1) a cell voltage, (2) a storage voltage, and (3) a selector voltage.
  • cell voltage is the voltage applied to the series of the storage and the selector, often being assumed equal to bitline voltage (Vbl) if neglecting the contributions of line parasitics, and to the bitline and wordline selectors, where the wordline voltage is assumed equal to zero when a cell is selected.
  • storage voltage Vgst
  • selector voltage Vsel
  • Vsel is the fraction of the cell voltage which drops upon the selector (e.g., on a diode, bipolar, or MOS transistor, etc.).
  • the above observations are addressed by using a biasing technique based on a current ramp and a dummy bitline with a proper voltage added in series.
  • the current ramp causes a comparator to trip when the storage voltage reaches a given, safe, predefined value.
  • the predefined value is independent from the resistance value of the device.
  • a dummy bitline is used, the dummy bitline having a properly adjusted voltage and a current equal to the current flowing into the device.
  • Read window budget (RWB) issues may impact Phase-Change
  • PCM Peripheral Component Interconnect Express
  • a PCM is a kind of resistor which can be altered to provide different resistance values.
  • MLC sensing techniques and circuits may require the largest possible read window (signal). For example, a voltage may be forced in a bitline, a current read, and a delta determined between the signal and a reference.
  • PCM unlike Flash memories where a selector is the storage, PCM requires a dedicated switch in series with a storage element.
  • the voltage dropping on a selector needs to be subtracted from the bitline voltage, reducing the available signal.
  • the more the device or cell is set the lower the available voltage, and the smaller the window becomes.
  • the more the device or cell is reset the higher the available voltage, and the smaller the window becomes. This may lead to a higher risk of disturbing the device or cell by exceeding its safe operating voltage.
  • FIG. 1 illustrates a schematic representing conventional PCM cell biasing.
  • a conventional PCM cell 100 is associated with a wordline 102 and a bitline 104.
  • the wordline voltage (Vwl) is few hundreds of mVolts (e.g., approximately 0 Volts) when the cell is selected, while the bitline voltage is approximately equal to the cell voltage Vcell, if neglecting the line parasitics and the column decoder drops.
  • PCM cell 100 has a voltage (Vcell) which includes contribution from a chalcogenide phase-change element 106 in the form of the voltage associated with the chalcogenide phase-change material (Vgst) and the selector contribution (e.g., in this case, the drop on the diode, Veb in other cases along the text, or more generally Vsel).
  • Vgst is approximately 0 Volts (actually a few hundred mVolts, e.g. approximately in the range of 150 - 200mV) when the chalcogenide phase-change material is crystalline and the bitline is biased around 1.2V.
  • Vgst can be calculated by subtracting Vcell (which is very close to the bitline voltage Vbl) from the voltage of the selector (Vsel). More importantly, Vgst depends on the impedance ratio between the diode and the storage, which is ultimately a resistor provided by, e.g., an amorphous or a crystalline chalcogenide phase-change material. In addition, the safe operating voltage and current (Vsafe, Isafe) are equal to the maximum voltage or current for Vgst which do not induce any disturb along with reading cycles.
  • FIG. 2 illustrates a schematic representing conventional column biasing for a PCM cell.
  • a portion of a circuit 200 includes a bitline 202 and a chalcogenide phase-change element 204 (GST).
  • the bitline voltage (Vbl) is equally to Vsafe added to the product of an emitter base voltage and the maximum current (Isafe).
  • This voltage (SLVREF) whose generation is not shown in the drawings as representing the state of art, is imposed by an operational amplifier 206.
  • the voltage of the chalcogenide phase-change material (Vgst) is equal to SLVREF less the cell emitter base voltage calculated at the cell current (Icell).
  • Vgst is also equal to the product of the resistance of the chalcogenide phase- change material (Rgst) and Icell (as shown and described in association with Figure 1).
  • the output of the operational amplifier 206 may be greater or smaller than SLVREF.
  • the cell current is given by the read reference current coming from the current generator plus the additional current provided by the amplifier and flowing through the RFB resistor.
  • the output is larger than SLFREF.
  • part of the read reference current flows into the RFB, thus the output of the amplifier is lower than SLVREF.
  • the data is sensed by the comparison of the output of the two amplifiers, which are used to have a matched pair.
  • Vgst could be greater than or smaller than Vsafe.
  • Vgst is greater than Vsafe if the cell is well reset, whereas Vgst is less than Vsafe if the cell is well set.
  • Figure 3 is a plot 300 of current of a chalcogenide phase-change material (Igst) as a function of the voltage and the resistance of a chalcogenide phase-change material (Vgst), under a conventional PCM sense amplifier bitline voltage biasing with the cell selector being the loadline (Veb), in accordance with an embodiment of the present invention.
  • plot 300 represents a conventional PCM sense amplifier biasing, such as the sense amplifier biasing described in association with Figure 2) and with the non linear loadline given by the selector.
  • bitline voltage (Vbl, which is approximately 1.2V when no current is flowing) is equal to the sum of an emitter base voltage (Veb) at the Igst current and the storage voltage Vgst.
  • Veb emitter base voltage
  • Vgst storage voltage
  • Vgst increases, and vice versa.
  • Vgst_set/Rgst_set - Vgst_reset/Rgst_reset is affected by Veb, where 'set' represents the crystalline phase (logic "1") of the chalcogenide phase-change material and 'reset' represents the amorphous phase (logic "0") of the chalcogenide phase-change material.
  • Vgst increases indicates an increase in amorphous character of the chalcogenide phase-change material and vice versa.
  • an available window may be compared to a real window.
  • the minimum reset resistance is 200 K
  • the maximum set resistance is 20 K
  • Vsafe is 400 mV
  • Vbl is 1.2 V
  • the available window is 400 mV/20 K - 400 mV/200K, which is approximately 18 microAmps.
  • consideration is taken that a Veb of 950mV is needed when 12.5 microAmps flows into the cell, while a Veb of 0.7V is required when the cell current Icell is 2.5 microAmps.
  • Veb includes into the selector voltage also the wordline parasitics and the wordline drivers drops.
  • the real window is approximately equal to 250, mV/20K - 500 mV/200 , which is approximately equal to 12.5 microAmps - 2.5 microAmps, or 10 microAmps.
  • the approximately 8 microAmps difference between the real window and the available window is due to the manner in which the bitline is biased and to the voltage drop upon the selector, which in one case lowers the Vgst while in the other increases it. This difference is a very large loss, and could otherwise be used to place inner states in an MLC device.
  • a dummy bitline is used in an apparatus and a method for reading a phase-change memory cell.
  • a chalcogenide phase-change material is included in the dummy bitline and set to a proper state, for example during chip wafer testing (it will be referred to as Rgstd).
  • the dummy bitline does not include a chalcogenide phase-change material.
  • a dummy cell essentially includes only a bipolar selector. In both cases, a Vsafe voltage is generated and added in series to a dummy bitline.
  • a current ramp is forced into both the actual bitline and the dummy bitline.
  • the selector of the dummy cell belonging to the dummy bitline is assumed to match the properties of the selector of the matrix cell belonging to the selected bitline, a part negligible process spreads. Accordingly, in an embodiment, if the current forced into the bitline and the dummy bitline have the same value, the emitter base voltage developed upon the dummy selector and the emitter base voltage of the cell selector will be approximately equal.
  • the ramp starting point is at a minimum current of Vsafe/Rreset_min and the ramp stopping point is at a maximum current of Vsafe/Rset_max.
  • the voltage developed at the top of the series of a dummy selector of the dummy bitline, e.g. a diode, and the Vsafe generator when the current ramp is forced (RIN) is compared with the matrix bitline voltage (SIN).
  • the current will eventually reach a given value that renders the cell storage voltage equivalent to Vsafe.
  • the cell selector Veb voltage and the dummy selector Veb have been assumed equal.
  • the comparator used for the comparison will trip and a signal which stops the current ramp will be generated. The content of the cell is read out and latched at the point at which the trip occurs. As such, in a specific embodiment, the sooner the trigger occurs, the greater extent to which the bit is reset, and vice versa.
  • each cell is biased until the voltage dropping on it is equal to Vsafe, thus maximizing the window and the reliability. If the dummy chalcogenide were present, the trip will happen at that given current I where the cell storage is Vsafe+Rgstd*I, thus again independent from cell resistance. This additional contribution (Rgstd*I) will further increase the real window despite some potential reliability issues in the case of an MLC device, but poses no issues in an SLC device. For that reason, a dummy compensator resistor may be added on the cell branch just between the top of the column selector and the SIN node, as described below.
  • FIG. 4 illustrates a circuit diagram of an apparatus for reading a phase-change memory cell, the circuit including a portion with a dummy bitline (BLD) and a dummy wordline (WLD), in accordance with an embodiment of the present invention.
  • a circuit 400 includes memory cells selected by proper X and Y decoders and connected to sense amplifiers 410 for reading.
  • a dummy bitline BLD, and its dummy cell at the cross between BLD and WLD, is associated to the given sense amplifier 410 of the given input-output IO ⁇ i> 402.
  • the BLD is used by all the cells belonging to the bitlines of the IO such as 404 or 406 (at any selected WL) according to the particular address issued to the memory.
  • the dummy bitline is selected at the same time which any of the 404 or 406 are selected in and it is connected by the path 408 to the sense amplifier.
  • the dummy bitlines (one per IOs) and the dummy wordline (shared across all the IOs) can be merged inside the bitlines and the wordlines of a non selected memory array plane in order to best match the selector properties, such as Veb.
  • Figure 5 illustrates a layout of a sense amplifier for reading a phase- change memory cell which is biasing both the selected bitline (connected to SIN) and the dummy bitline (connected to RIN) using an unbalanced comparator to read the data (the unbalanced comparator triggers when SIN is equal to or greater than RIN+Vsafe, Vsafe being the unbalancing voltage quantity), in accordance with an embodiment of the present invention.
  • the sense amplifier represents the SA 410 described in association with Figure 4.
  • a sense amplifier 500 includes two switches, SW1 and SW2.
  • switch SW1 and SW2 are closed during pre-charge of sense-amplifier 500 connecting SIN and RIN to a pre-charge voltage VPRE, while switch SW2 equalizes SIN and RIN when the bitline and the dummy bitline, e.g. bitline 404 or 406 and BLD from Figure 4, are charged and when SW1 is opened.
  • SIN is connected by the Y decoder to the array cell while RIN is connected to the dummy cell by the Y decoders along the path 408 in Figure 4. Both switches are opened when the current ramp starts. The current ramp is forced through VG into bitline and dummy bitline by the classical current mirror configuration.
  • the comparator is assumed unbalanced, e.g., it will trip when SIN is equal to or larger than RIN+Vsafe, being Vsafe the designed offset. Unbalancing the comparator adds a Vsafe voltage to the dummy cell voltage which is essentially the dummy selector voltage drop plus, eventually, the dummy chalcogenide drop (on Rgstd), as described above.
  • a pre-charged capacitor (with the proper polarity) at Vsafe can be put in series between RIN and the minus terminal.
  • a reference current is injected into one leg of the classical input pair which realizes the differential stage of a comparator.
  • a variety of arrangements may be used for the switches SW1 and SW2 or current mirrors configurations (e.g., cascoded mirrors).
  • an Analog to Digital converter receives the trigger (stop) from the output of the comparator (SIN equal to or larger than RIN+Vsafe).
  • This trigger which follows after some time the start signal representing the start of the current ramp, is used to store a given digital representation (N) of the current itself which is sent to a look-up table which finally converts this value into a logical state.
  • N digital representation
  • Figure 6A illustrates a more conceptual schematic with respect to the subject of Figures 4 and 5.
  • Figure 6 A illustrates a current scan for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 6B illustrates a plot 650 of current ramp as a function of time associated with the current scan of Figure 6A, in accordance with an embodiment of the present invention.
  • a conceptual schematic 600 of a current scan for reading a phase-change memory cell is configured to trigger when the voltage of a chalcogenide phase-change material (Vchal), which is on Rchal, is equal to Vsafe which is added in series on top of the dummy bitline, here represented as a pure bipolar selector (without dummy chalcogenide Rgstd).
  • Vchal chalcogenide phase-change material
  • Rchal chalcogenide phase-change material
  • Imin is equal to Vsafe/Rreset min
  • Imax is equal to Vsafe/Rset max.
  • a read of an associated cell is based on a time event or, more likely, a predetermined trip value.
  • the bitlines (+sin/rin) are pre-charged and equalized at a value Vpre.
  • Figure 7A illustrates a conceptual schematic of the bitline and dummy bitline voltages during the current scan for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • Figure 7B illustrates a plot 750 of current ramp as a function of time associated with the current scan of Figure 7 A, in accordance with an embodiment of the present invention.
  • a conceptual schematic 700 of a current scan for reading a phase-change memory cell depicts current for a cell (1) and an associated dummy cell (2).
  • the dashed lines and solid lines represent set and reset states, respectively.
  • the bitline voltage e.g.
  • Vsin is equal to the addition product of the resistance of a chalcogenide phase-change portion of a cell (Rchal) times the current of the cell and the emitter base voltage.
  • bitline voltage e.g. reference voltage Vrin
  • Vrin the bitline voltage
  • the voltage of an associated comparator is equal to Vsin minus Vrin.
  • the comparator trips when Vgst is equal to Vsafe.
  • the ramp is stopped and data is latched.
  • a current ramp as a function of time is shown for a cell in both the set state 752 and the reset state 754.
  • the current ramp is made to be variable over time, e.g., it exhibits a non linear slew rate.
  • a method of reading a phase-change memory cell includes performing a current ramp on a bitline. The method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with a phase-change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell.
  • performing the current ramp includes ramping current on a dummy bitline, the dummy bitline different from a bitline of the phase-change memory cell.
  • tripping the comparator includes providing the storage voltage from the dummy bitline.
  • performing the current ramp includes forcing the current ramp on both the dummy bitline and the bitline of the phase-change memory cell.
  • ramping current on the dummy bitline includes ramping a current on a bitline including a dummy phase-change memory cell.
  • ramping current on the dummy bitline includes ramping a current on a bitline with a dummy selector but absent a dummy phase-change storage memory cell.
  • the method further includes, prior to tripping the comparator, referencing a look-up table to determine the predefined value.
  • FIG 8 illustrates a conceptual block diagram of a layout of an apparatus for . reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • an apparatus 800 includes a current ramp circuit 802 coupled with a current forcing module 804.
  • Current forcing module 804 is coupled with a high output impedance voltage source 806 (Vsafe) and an emitter base voltage emulation module 808 (which can be in a given embodiment a real dummy bitline BLD as shown in Figure 4, connected to a dummy wordline WLD through a dummy cell) as well as with a dummy phase- change compensator circuit 810 (which can compensate Rgstd of dummy bitline, in case dummy bitline includes a dummy calchogenide material).
  • Vsafe high output impedance voltage source 806
  • an emitter base voltage emulation module 808 which can be in a given embodiment a real dummy bitline BLD as shown in Figure 4, connected to a dummy wordline WLD through a dummy cell
  • a dummy phase- change compensator circuit 810 which can compensate Rgstd of dummy bitline, in case dummy bitline includes a dummy calchogenide material.
  • a comparator 812 (whose inputs are RIN from emulation branch and SIN from the matrix branch) couples current forcing module 804, the sum of the high output impedance voltage source 806 and the Veb emulation 808 (RIN), and dummy phase-change compensator circuit 810 (SIN) with a look-up table 814.
  • dummy phase-change compensator circuit 810 includes a phase-change material. In another embodiment, dummy phase- change compensator circuit 810 does not include a phase-change material.
  • dummy phase-change compensator circuit 810 does not include a phase-change material but does include a trimable element such as, but not limited to, an NMOS or a diffusion resistor which emulates the dummy leg phase- change material into the Veb emulation 808, if any.
  • a trimable element such as, but not limited to, an NMOS or a diffusion resistor which emulates the dummy leg phase- change material into the Veb emulation 808, if any.
  • a circuit for reading a phase-change memory cell may be provided.
  • a circuit includes a current ramp circuit coupled with a current forcing module.
  • a Veb emulation circuit is coupled with the current forcing module via a voltage adder.
  • the Veb emulation circuit includes a dummy bitline different from a bitline of the phase-change memory cell.
  • the Veb emulation circuit further includes a dummy phase-change memory cell coupled with the dummy bitline through a dummy wordline.
  • the Veb emulation circuit does not include a dummy phase-change storage memory cell but a dummy wordline and a dummy selector are still present.
  • the circuit further includes a look-up table coupled, via a comparator, with the current forcing module, the sum of the Veb emulation, the high output impedance Voltage source (RIN), and the dummy phase-change compensator circuit (SIN).
  • the dummy GST compensator is not present (SIN is directly connected to the matrix Y select).
  • the phase-change memory cell is a multi-level phase-change memory cell.
  • a highest resistive value is first screened out.
  • the highest resistive value is screened out by a conventional process such as, but not limited to, a cascode or operational amplifier scheme.
  • a current ramp approach such as one of the current ramp approaches described above is applied to a phase-change memory cell.
  • Figure 9 illustrates a decision tree for a first conventional screen out plus current ramp approach to reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • a decision tree 900 includes applying a cascode biasing 902 to a cell at a fixed bitline current. At decision 904, if the data is a highest resistive value, then the reading is complete. If at decision 904, however, the data is not a highest resistive value, then a current ramp biasing 906 with dummy bitline is applied.
  • a look-up table is associated with a current ramp generation for reading a phase-change memory cell.
  • a look-up table is used to convert trigger pulses into digital information for, e.g., a multi-level read in a MLC.
  • a digital current ramp starts at "start” and stops at "stop” when a comparator triggers, e.g., when the storage voltage on the cell is equal to Vsafe.
  • FIG. 10 illustrates conception diagrams for current ramp generation for reading a phase-change memory cell, in accordance with an embodiment of the present invention.
  • I N(start, stop) x Istep.
  • N is equal to zero if start equals zero.
  • N equals N + 1 if start equals 1 and stop equals zero. Otherwise, N is equal to N.
  • current I ramps upward step- wise from Imin during the "start" timeframe.
  • Figure 11 illustrates a look-up table for current ramp generation and cell state detection during reading of a phase-change memory cell, in accordance with an embodiment of the present invention.
  • a circuit 1 100 is coupled with a set of latches 1 102.
  • the set of latches 1102 is inside an N generator 1104, although it is depicted separately in Figure 11.
  • a bitline associated with the set of latches 1102 is disconnected and grounded once a comparator is triggered.
  • the set of latches 1 102 is coupled with a Mux 1 106.
  • the look-up table is associated with an MLC cell and data out is: 00 if N falls in the interval [NO, Nl, Nk], 01 if N falls in the interval [Nk+1 , Nk+2, Nj], 10 if N falls in the interval [Nj+1, Nj+2, Nx], 1 1 if N falls in the interval [Nx+l , Nx+2, ..., Nt].
  • Figure 12 illustrates exemplary output 1200 from a current ramp generation using a look-up table, the current ramp generation for reading a phase- change memory cell, in accordance with an embodiment of the present invention.
  • Vsafe equals 450 mV
  • Imin equals 2 microAmps
  • Imax equals 30 microAmps.
  • 32 levels are ramped by 0.8 microAmps each. It is to be understood that, being the output of the latch a digital representation of the step the trigger has happened in, and being such trigger related to that given current needed to the cell to have a Vsafe voltage dropping on its storage, this reading approach represents a close to analog way to sense the data stored into the memory.
  • a phase-change memory cell array includes memory cells that are composed of a storage material in combination with a selector device.
  • Figure 13 illustrates an array 1310 of phase- change memory cells, in accordance with an embodiment of the present invention.
  • array 1310 includes phase-change memory cells composed of alloys of elements of group VI of the periodic table, elements such as Te or Se that are referred to as chalcogenides or chalcogenic materials. Chalcogenides may be used advantageously in phase change memory cells to provide data retention and remain stable even after the power is removed from the nonvolatile memory.
  • phase change material as Ge 2 Sb 2 Te5 for example, two phases or more are exhibited having distinct electrical characteristics useful for memory storage.
  • Array 1310 includes phase-change memory cells each having a selector device and a memory element. Although the array is illustrated with bipolar selector devices, it should be noted that alternative embodiments may use CMOS selector devices or diodes to identify and selectively change the electrical properties (e.g. resistance, capacitance, etc.) of the chalcogenide material through the application of energy such as, for example, heat, light, voltage potential, or electrical current.
  • the chalcogenic material may be electrically switched between different states intermediate between the amorphous and the crystalline states, thereby giving rise to a multilevel storing capability.
  • this embodiment illustrates a programming voltage potential that is greater than the threshold voltage of the memory select device that may be applied to the memory cell.
  • An electrical current flows through the memory material and generates heat that changes the electrical characteristic and alters the memory state or phase of the memory material.
  • phase-change material heating the phase-change material to a temperature above 900° C in a write operation places the phase change material above its melting temperature (T ). Then, a rapid cooling places the phase-change material in the amorphous state that is referred to as a reset state where stored data may have a "0" value.
  • Tm melting temperature
  • quenching after the local heating to achieve the amorphous phase may be less than 50 nanoseconds.
  • the local temperature is raised higher than the crystallization temperature (Tx) for a time longer than 50 nanoseconds (for Ge 2 Sb 2 Te 5 ) to allow complete crystallization.
  • the phase-change material in the crystalline form is referred to as a set state and stored data may have a "1" value.
  • the cell can be programmed by setting the amplitude and pulse width of the current that will be allowed through the cell.
  • a higher magnitude, fast pulse will amorphize the cell, whereas a moderate magnitude, longer pulse will allow the cell to crystallize.
  • the bit line (BL) and word line (WL) are selected and an external current is provided to the selected memory cell.
  • the current difference resulting from the different device resistance is sensed.
  • a circuit 1302 with a dummy bitline used for reading a phase-change memory cell is coupled to at least one phase-change memory cell 1304 in array 1310.
  • Figure 14 illustrates a schematic representation of a wireless architecture that incorporates an array of phase-change memory cells with at least one phase-change memory cell coupled to a circuit with a dummy bitline and a dummy wordline used for reading the phase- change memory cell, in accordance with an embodiment of the present invention.
  • the wireless architecture embodiment illustrated in Figure 14 shows a communications device 1410.
  • communications device 1410 includes one or more antenna structures 1414 to allow radios to communicate with other over-the-air communication devices.
  • communications device 1410 may operate as a cellular device or a device that operates in wireless networks such as, for example, Wireless Fidelity (Wi-Fi) that provides the underlying technology of Wireless Local Area Network (WLAN) based on the IEEE 802.1 1 specifications, WiMax and Mobile WiMax based on IEEE 802.16-2005, Wideband Code Division Multiple Access (WCDMA), and Global System for Mobile Communications (GSM) networks, although the present invention is not limited to operate in only these networks.
  • Wi-Fi Wireless Fidelity
  • WLAN Wireless Local Area Network
  • WiMax WirelessMax
  • WCDMA Wideband Code Division Multiple Access
  • GSM Global System for Mobile Communications
  • the radio subsystems co-located in the same platform of communications device 1410 provide the capability of communicating with different frequency bands in an RF/location space with other devices in a network.
  • analog front end transceiver 1412 may be a stand-alone Radio Frequency (RF) discrete or integrated analog circuit, or transceiver 1412 may be embedded with a processor having one or more processor cores 1416 and 1418.
  • RF Radio Frequency
  • An interface may be used to provide communication or information between the processor and the memory storage in a system memory 1420.
  • the interface may include serial and/or parallel buses to share information along with control signal lines to be used to provide handshaking between the processor and system memory 1420.
  • the system memory 1420 may optionally be used to store instructions that are executed by the processor during the operation of wireless communication device 1410, and may be used to store user data such as the conditions for when a message is to be transmitted by wireless communication device 1410 or the actual data to be transmitted.
  • the instructions stored in system memory 1420 may be used to perform wireless communications, provide security functionality for communication device 1410, user functionality such as calendaring, email, internet browsing, etc.
  • System memory 1420 may be provided by one or more different types of memory and may include both volatile and a nonvolatile memory 1422 having a phase change material.
  • Nonvolatile memory 1422 may be referred to as a Phase Change Memory (PCM), Phase-Change Random Access Memory (PRAM or PCRAM), Ovonic Unified Memory (OUM) or Chalcogenide Random Access Memory (C-RAM).
  • PCM Phase Change Memory
  • PRAM Phase-Change Random Access Memory
  • OFUM Ovonic Unified Memory
  • C-RAM Chalcogenide Random Access Memory
  • the volatile and nonvolatile memories may be combined in a stacking process to reduce the footprint on a board, packaged separately, or placed in a multi-chip package with the memory component placed on top of the processor.
  • the embodiment also illustrates that one or more of the processor cores may be embedded with nonvolatile memory 1432.
  • at least one phase-change memory cell in nonvolatile memory 1422 or 1432 is coupled to a circuit 1440 with a dummy bitline used for reading a phase-change memory cell and managed in the way described above, as depicted in Figure 14.
  • a wireless communication device includes a transceiver to receive over-the-air signals, a processor core coupled to the transceiver, and a phase-change memory embedded with at least the processor core.
  • the phase-change memory includes a circuit for reading a phase-change memory cell of the phase change memory.
  • the circuit includes a current ramp circuit coupled with a current forcing module.
  • a Veb emulation circuit is coupled with the current forcing module via a voltage adder (RTN node) which sums the Veb output and the high impedance voltage source (Vsafe).
  • the Veb emulation circuit includes a dummy bitline (BLD) different from a bitline of the phase-change memory cell.
  • the Veb emulation circuit further includes a dummy phase-change memory cell coupled with the dummy bitline through a dummy wordline (WLD).
  • WLD dummy wordline
  • the Veb emulation circuit does not include a dummy phase-change storage memory cell but a dummy wordline and a dummy selector are still present.
  • the circuit further includes a look-up table coupled, via a comparator, with the current forcing module, the sum of the Veb emulation and the high output impedance voltage source (RTN node) and the dummy phase-change compensator circuit (SIN node).
  • the dummy GST compensator is not present and SIN node directly connects the matrix Y select (and by them, the bitline of the memory cell) to the current forcing module.
  • a method includes performing a current ramp.
  • the method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with the phase- change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell.
  • performing the current ramp includes ramping current on a dummy bitline, the dummy bitline different from a bitline of the phase-change memory cell.
  • tripping the comparator includes providing the storage voltage from the dummy bitline.
  • performing the current ramp includes forcing the current ramp on both the dummy bitline and the bitline of the phase-change memory cell.
  • a method includes a forcing current ramp into both a bitline and a dummy bitline, and triggering a comparator which stops the ramp when a storage voltage reaches a predefined value independent on the value of a storage resistance, while depending on a safe voltage added in series to the dummy bitline voltage.
  • an apparatus includes a current ramp generator coupled with a 2 legs current forcing means, the current forcing means coupled with a first leg (RJN node) being the sum of an high impedance output voltage source (Vsafe) and a Veb emulation (generated with a dummy bitline, dummy wordline and dummy cell in the preferred embodiment), and a second leg (SIN node), coupled with a dummy gst compensator.
  • the dummy gst compensator connects that leg to the top of the memory column selectors and through those selectors to the memory bitline.
  • the two legs are connected to the inputs of a comparator whose output is fed back to the current ramp and to a look-up table in order to implement a cell reading method.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention porte sur un appareil et sur un procédé pour lire une cellule mémoire à changement de phase. Un circuit comprend un circuit à rampe de courant. Un module de forçage de courant est couplé au circuit à rampe de courant. Un circuit d'émulation de Veb est couplé au module de forçage de courant par un additionneur de tension, l'additionneur de tension servant à sommer une sortie du circuit d'émulation de Veb et une source de tension haute impédance. L'invention porte également sur un procédé qui comprend le forçage d'une rampe de courant tout à la fois dans une ligne de bits et une ligne de bits fictive, la ligne de bits fictive ayant une certaine tension. Le procédé comprend également le déclenchement d'un comparateur lorsque la rampe de courant délivre une tension de stockage avec une valeur prédéfinie, la tension de stockage étant associée à la cellule mémoire à changement de phase, et la valeur prédéfinie étant indépendante d'une valeur de résistance de la cellule mémoire à changement de phase et additionnée en série à la tension de la ligne de bits fictive.
PCT/IT2009/000557 2009-12-10 2009-12-10 Appareil et procédé pour lire une cellule mémoire à changement de phase WO2011070599A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/IT2009/000557 WO2011070599A1 (fr) 2009-12-10 2009-12-10 Appareil et procédé pour lire une cellule mémoire à changement de phase
US13/514,532 US8953360B2 (en) 2009-12-10 2009-12-10 Apparatus and method for reading a phase-change memory cell
US14/615,788 US9431102B2 (en) 2009-12-10 2015-02-06 Apparatus and method for reading a phase-change memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IT2009/000557 WO2011070599A1 (fr) 2009-12-10 2009-12-10 Appareil et procédé pour lire une cellule mémoire à changement de phase

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/514,532 A-371-Of-International US8953360B2 (en) 2009-12-10 2009-12-10 Apparatus and method for reading a phase-change memory cell
US14/615,788 Continuation US9431102B2 (en) 2009-12-10 2015-02-06 Apparatus and method for reading a phase-change memory cell

Publications (1)

Publication Number Publication Date
WO2011070599A1 true WO2011070599A1 (fr) 2011-06-16

Family

ID=41723004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IT2009/000557 WO2011070599A1 (fr) 2009-12-10 2009-12-10 Appareil et procédé pour lire une cellule mémoire à changement de phase

Country Status (2)

Country Link
US (2) US8953360B2 (fr)
WO (1) WO2011070599A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8953360B2 (en) 2009-12-10 2015-02-10 Micron Technology, Inc. Apparatus and method for reading a phase-change memory cell
US9030870B2 (en) 2011-08-26 2015-05-12 Micron Technology, Inc. Threshold voltage compensation in a multilevel memory
US9076547B2 (en) 2012-04-05 2015-07-07 Micron Technology, Inc. Level compensation in multilevel memory

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2502568A (en) 2012-05-31 2013-12-04 Ibm Memory apparatus with gated phase-change memory cells
GB2502569A (en) * 2012-05-31 2013-12-04 Ibm Programming of gated phase-change memory cells
US9911492B2 (en) 2014-01-17 2018-03-06 International Business Machines Corporation Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period
US9384801B2 (en) * 2014-08-15 2016-07-05 Intel Corporation Threshold voltage expansion
US9666273B2 (en) 2015-06-18 2017-05-30 International Business Machines Corporation Determining a cell state of a resistive memory cell
US11942144B2 (en) 2022-01-24 2024-03-26 Stmicroelectronics S.R.L. In-memory computation system with drift compensation circuit
US11894052B2 (en) 2022-04-12 2024-02-06 Stmicroelectronics S.R.L. Compensated analog computation for an in-memory computation system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1538632A1 (fr) * 2003-11-12 2005-06-08 STMicroelectronics S.r.l. Mémoire à changement de phase avec protection contre les surtensions et méthode de protection d'un mémoire à changement de phase contre les surtensions
WO2009134664A2 (fr) * 2008-04-30 2009-11-05 International Business Machines Corporation Procédé et appareil pour mettre en oeuvre une opération de lecture auto-référentielle pour des dispositifs pcram

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1420412B1 (fr) * 2002-11-18 2008-07-09 STMicroelectronics S.r.l. Circuit et méthode pour tracer la température d'éléments chalcogéniques, en particulier d'éléments de mémoire de type changement de phase
EP1526548A1 (fr) * 2003-10-22 2005-04-27 STMicroelectronics S.r.l. Procédé et circuit amelioré pour décharger une ligne de bit d'une mémoire sémiconducteur
JP4529493B2 (ja) * 2004-03-12 2010-08-25 株式会社日立製作所 半導体装置
JP4900977B2 (ja) * 2006-10-12 2012-03-21 ルネサスエレクトロニクス株式会社 半導体集積回路
US20080247216A1 (en) * 2007-04-04 2008-10-09 Lamorey Mark C H Method and apparatus for implementing improved write performance for pcram devices
KR101559445B1 (ko) * 2009-04-23 2015-10-13 삼성전자주식회사 상변화 메모리 장치 및 메모리 시스템
WO2011070599A1 (fr) 2009-12-10 2011-06-16 Ferdinando Bedeschi Appareil et procédé pour lire une cellule mémoire à changement de phase
US8687403B1 (en) * 2010-06-10 2014-04-01 Adesto Technologies Corporation Circuits having programmable impedance elements
JP5711481B2 (ja) * 2010-08-19 2015-04-30 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1538632A1 (fr) * 2003-11-12 2005-06-08 STMicroelectronics S.r.l. Mémoire à changement de phase avec protection contre les surtensions et méthode de protection d'un mémoire à changement de phase contre les surtensions
WO2009134664A2 (fr) * 2008-04-30 2009-11-05 International Business Machines Corporation Procédé et appareil pour mettre en oeuvre une opération de lecture auto-référentielle pour des dispositifs pcram

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8953360B2 (en) 2009-12-10 2015-02-10 Micron Technology, Inc. Apparatus and method for reading a phase-change memory cell
US9431102B2 (en) 2009-12-10 2016-08-30 Micron Technology, Inc. Apparatus and method for reading a phase-change memory cell
US9030870B2 (en) 2011-08-26 2015-05-12 Micron Technology, Inc. Threshold voltage compensation in a multilevel memory
US9087594B2 (en) 2011-08-26 2015-07-21 Micron Technology, Inc. Memory apparatus, systems, and methods
US9520183B2 (en) 2011-08-26 2016-12-13 Micron Technology, Inc. Threshold voltage compensation in a memory
US9620236B2 (en) 2011-08-26 2017-04-11 Micron Technology, Inc. Level compensation in multilevel memory
US9646683B2 (en) 2011-08-26 2017-05-09 Micron Technology, Inc. Memory apparatus, systems, and methods
US9076547B2 (en) 2012-04-05 2015-07-07 Micron Technology, Inc. Level compensation in multilevel memory

Also Published As

Publication number Publication date
US20130040584A1 (en) 2013-02-14
US9431102B2 (en) 2016-08-30
US8953360B2 (en) 2015-02-10
US20150155034A1 (en) 2015-06-04

Similar Documents

Publication Publication Date Title
US9431102B2 (en) Apparatus and method for reading a phase-change memory cell
KR100814608B1 (ko) 비트 특정 기준 레벨을 이용하여 메모리를 판독하는 방법
US7359231B2 (en) Providing current for phase change memories
US7577024B2 (en) Streaming mode programming in phase change memories
US7245526B2 (en) Phase change memory device providing compensation for leakage current
US8031517B2 (en) Memory device, memory system having the same, and programming method of a memory cell
US8134866B2 (en) Phase change memory devices and systems, and related programming methods
KR100875352B1 (ko) 상변화 메모리 및 그 상변화 메모리를 판독하는 방법
US7050328B2 (en) Phase change memory device
US20060221678A1 (en) Circuit for reading memory cells
US20110080775A1 (en) Nonvolatile memory device, storage system having the same, and method of driving the nonvolatile memory device
US10068643B2 (en) Sense amplifier for non-volatile memory devices and related methods
US7986549B1 (en) Apparatus and method for refreshing or toggling a phase-change memory cell
US7940553B2 (en) Method of storing an indication of whether a memory location in phase change memory needs programming
US8264872B2 (en) Column decoder for non-volatile memory devices, in particular of the phase-change type
US20070171705A1 (en) Writing phase change memories
CN102714056B (zh) 重置相变存储器位
KR20150091863A (ko) 저항체를 이용한 비휘발성 메모리 장치
KR20080086243A (ko) 저항체를 이용한 비휘발성 메모리 장치
US8064265B2 (en) Programming bit alterable memories
KR20100013125A (ko) 반도체 장치, 이를 포함하는 반도체 시스템, 및 저항성메모리 셀의 프로그램 방법
US11615820B1 (en) Regulator of a sense amplifier
US11322201B2 (en) Bit-line voltage generation circuit for a non-volatile memory device and corresponding method
US7916527B2 (en) Read reference circuit for a sense amplifier within a chalcogenide memory device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09804211

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 13514532

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 09804211

Country of ref document: EP

Kind code of ref document: A1