WO2011066802A1 - N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
WO2011066802A1
WO2011066802A1 PCT/CN2010/079412 CN2010079412W WO2011066802A1 WO 2011066802 A1 WO2011066802 A1 WO 2011066802A1 CN 2010079412 W CN2010079412 W CN 2010079412W WO 2011066802 A1 WO2011066802 A1 WO 2011066802A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
field oxide
floating
oxide region
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2010/079412
Other languages
French (fr)
Inventor
Hsiao Chia Wu
Zehuang Luo
Guangtao Han
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab1 Co Ltd, CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab1 Co Ltd
Publication of WO2011066802A1 publication Critical patent/WO2011066802A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Definitions

  • the present invention relates to an N type Lateral Double-diffused Metal Oxide Semiconductor (NLDMOS) device, in particular, relates to a NLDMOS having a relatively high breakdown voltage and a relatively low on-resistance and a method of manufacturing the same.
  • NLDMOS N type Lateral Double-diffused Metal Oxide Semiconductor
  • the depletion of drift region is enhanced and the breakdown voltage of device is improved.
  • the P type region is injected into the surface of the drift region by low energy, electrical current can merely flow through the drift region underneath.
  • the junction depth of the P type region should not be too shallow. Therefore, the P type region must be formed through a certain thermal drive-in process, such that impurity concentration in the N type drift region will decrease under effect of the P type impurity, thus increasing the on-resistance.
  • the P type region formed through a thermal process increases in size due to lateral diffusion, which reducing flow path of electrical current and increasing the on-resistance again.
  • a NLDMOS device comprises a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, wherein the floating P type structure is located in the middle portion of the N type drift region along the channel direction of the N type drift region, the width of an active region between the first field oxide region and the second field oxide region is no less than the length of the floating P type structure.
  • a plurality of floating P type structures are provided in the N type drift region.
  • the floating P type structure is in a stripe shape and the cross section of the floating P type structure is in a rectangular shape.
  • the cross section of the floating P type structure is in a circular shape.
  • the length of the first field oxide region is different from that of the second field oxide region.
  • a method of manufacturing a NLDMOS device comprising a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, the method comprises the following five steps of:
  • step 1) forming an epitaxial layer on a buried oxide layer by epitaxial manufacturing process
  • step 2) performing well injection by MOS process to form the N type drift region
  • step 3) growing the first field oxide region and the second field oxide region, an active region located between the first field oxide region and the second field oxide region, wherein the size of the active region matches with the length of the floating P type structure to be injected;
  • step 4) performing injection for a source region, a gate region and a drain region
  • step 5 injecting a floating P type structure into the middle portion of the N type drift region through the active region between the first field oxide region and the second field oxide region.
  • the injection energy of the floating P type structure is 200Kev ⁇ 2000Kev.
  • the breakdown voltage of a NLDMOS device can be increased and on-resistance thereof can be reduced, the requirement on thickness of photoresist during manufacturing process and the requirement of high energy injection machine are lowered.
  • FIG. 1 is a schematic structural view of a NLDMOS device according to an embodiment of the invention.
  • FIG. 2 is a schematic sectional view taken along A-A' direction of Fig. 1. DETAILED DESCRIPTION OF THE INVENTION
  • Fig. 1 illustrates a schematic structural view of a NLDMOS device according to the invention.
  • the NLDMOS device includes a substrate lead-out 101, an source region lead-out 103, a gate lead-out 105, a first field oxide region 107, a second field oxide region 109, a drain end lead-out 111, a N type drift region 113 made by high voltage N well, a floating P type structure (floating P structure) 115, a buried oxide layer 117 and a substrate 119 made by high voltage P well, wherein the N type drift region 113 is located on the buried oxide layer 117, the substrate 119 adjacent to the N type drift region 113 is located on the buried oxide layer 117, and the floating P type structure 115 is disposed within the N type drift region 113.
  • a floating P type structure floating P structure
  • the floating P type structure 115 is located in the middle portion of the N type drift region 113 along the channel direction of the N type drift region 113 and the number thereof is not limited to one, i.e., there can be two and more floating P type structures 115 (as shown in Fig. 2).
  • the floating P type structure 115 is of a stripe shape in layout and the cross section of the floating P type structure is in a rectangular shape.
  • the floating P type structure 115 is injected into the middle portion of the N type drift region 113 by high energy.
  • the injection energy is 200Kev ⁇ 2000Kev and can be suitably adjusted according to the impurity distribution of the N type drift region 113 and the thickness of the epitaxial process.
  • the dose of the floating P type structure 115 is required to achieve an electrical charge balance with the N type drift region 113.
  • the floating P type structure 115 located in the middle portion of the N type drift region 113 can deplete N type impurities in the lateral direction and the longitudinal direction, thus facilitating the depletion of the N type drift region 113, increasing breakdown voltage of the device and reducing on-resistance.
  • electrical current can flow along channels in the N type drift region 113 above and under the floating P type structure 115, and the path through which electrical current flows is relative large.
  • the impurity concentration of the drift region can be suitably increased so as to further reduce resistance.
  • the cross section of the floating P type structure 115 is not limited to rectangle, other shapes are also possible, such as circle, as long as these shapes are advantageous to the depletion of the N type drift region.
  • the first field oxide region 107 and the second field oxide region 109 are disposed on the N type drift region 113 to face each other.
  • the first field oxide region 107 and the second field oxide region 109 do not completely cover the N type drift region 113. Therefore, the region between the first field oxide region 107 and the second field oxide region 109 remains to be an active region.
  • the width of the active region between the first field oxide region 107 and the second field oxide region 109 matches with the length of the injected floating P type structure 115.
  • the length of the first field oxide region 107 can be different from that of the second field oxide region 109.
  • the whole drift region of a NLDMOS device with a breakdown voltage which is above 100V is covered by a field oxide region. Since the floating P type structure 115 has to be injected into a middle portion of the N type drift region, a very high injection energy is necessary, thus requiring that the injection machine must realize a high energy injection and that the photoresist is thick enough so as to block the floating P type structure 115 from being injected into other regions.
  • the active region made between the first field oxide region 107 and the second field oxide region 109 has a relatively thin oxide layer, thus facilitating the injection of the floating P type structure 115 and reducing the requirements on the energy of injection machine and the thickness of photoresist, such that a floating P type structure 115 can be formed with a smaller width and spacing and the injection peak value of the floating P type structure 115 is deeper, making it easier to realize in manufacturing.
  • a method of manufacturing the above-described NLDMOS device includes the following steps of:
  • step 2) performing well injection by conventional MOS process to form the N type drift region
  • step 3) forming the first field oxide region and the second field oxide region by growth, the active region located between the first field oxide region and the second field oxide region, wherein the size of the active region matches with the length of a floating P type structure to be injected;
  • step 4) performing injection for a source region, a gate region and a drain region;
  • step 5 injecting a floating P type structure into the middle portion of the N type drift region through the active region between the first field oxide region and the second field oxide region.
  • SOI silicon-on-insulator
  • the injection of the floating P type structure 115 is performed after the injection for the source region and a drain region, so that the floating P type structure 115 is subject to less thermal process, thus avoiding the reduction of N type impurity concentration caused by diffusion of P type impurity and the increase of on-resistance caused by increase in size of the floating P type structure 115, etc.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An N type lateral double diffused metal oxide semiconductor (NLDMOS) device comprises a floating P type structure (115), a first field oxide region (107), a second field oxide region (109) and an N type drift region (113), wherein the first field oxide region (107) and the second field oxide region (109) are disposed on the N type drift region (113); the floating P type structure (115) is located in the middle portion of the N type drift region (113); the first field oxide region (107) and the second field oxide region (109) are not connected together; and width of active region between the first field oxide region (107) and the second field oxide region (109) matches with length of the injected floating P type structure (115). By employing the construction of the NLDMOS, not only the breakdown voltage of semiconductor device can be raised, but also on-resistance can be effectively lowered. Meanwhile, the requirements of high-energy injection are lowered and the limitation to processing machine is decreased, making the manufacturing easier to be carried out.

Description

N TYPE LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
FIELD OF THE INVENTION
[0001] The present invention relates to an N type Lateral Double-diffused Metal Oxide Semiconductor (NLDMOS) device, in particular, relates to a NLDMOS having a relatively high breakdown voltage and a relatively low on-resistance and a method of manufacturing the same.
BACKGROUND
[0002] With continuous increase of operational voltage of semiconductor devices, Super Junction has been introduced in order to obtain a higher withstand voltage and a lower on-resistance. For example, with respect to an N type Lateral Double-diffused Metal Oxide Semiconductor (NLDMOS), an N type drift region with a relatively high concentration is firstly formed in order to obtain a relatively low on-resistance. Since a drift region with a relatively high concentration makes the breakdown value of device relatively low, a certain P type region is formed in the N type drift region meanwhile. The P type region is generally distributed in stripe along the channel direction in the surface of the drift region. By achieving an electrical charge balance between N type impurities in the drift region and P type impurities introduced, the depletion of drift region is enhanced and the breakdown voltage of device is improved. However, the P type region is injected into the surface of the drift region by low energy, electrical current can merely flow through the drift region underneath. Moreover, in order to deplete the whole drift region in longitudinal direction, the junction depth of the P type region should not be too shallow. Therefore, the P type region must be formed through a certain thermal drive-in process, such that impurity concentration in the N type drift region will decrease under effect of the P type impurity, thus increasing the on-resistance. Besides, the P type region formed through a thermal process increases in size due to lateral diffusion, which reducing flow path of electrical current and increasing the on-resistance again.
SUMMARY OF THE INVENTION
[0003] In view of above, it is necessary to provide a NLDMOS device that can increase breakdown voltage and reduce on-resistance, which addresses the issue of relatively large on-resistance and relatively low breakdown voltage of NLDMOS device.
[0004] Furthermore, it is also necessary to provide a method of manufacturing a NLDMOS device that increases breakdown voltage and reduces on-resistance. [0005] A NLDMOS device comprises a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, wherein the floating P type structure is located in the middle portion of the N type drift region along the channel direction of the N type drift region, the width of an active region between the first field oxide region and the second field oxide region is no less than the length of the floating P type structure.
[0006] Preferably, a plurality of floating P type structures are provided in the N type drift region.
[0007] Preferably, the floating P type structure is in a stripe shape and the cross section of the floating P type structure is in a rectangular shape.
[0008] Preferably, the cross section of the floating P type structure is in a circular shape.
[0009] Preferably, the length of the first field oxide region is different from that of the second field oxide region.
[0010] A method of manufacturing a NLDMOS device comprising a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, the method comprises the following five steps of:
[0011] step 1): forming an epitaxial layer on a buried oxide layer by epitaxial manufacturing process; [0012] step 2): performing well injection by MOS process to form the N type drift region;
[0013] step 3): growing the first field oxide region and the second field oxide region, an active region located between the first field oxide region and the second field oxide region, wherein the size of the active region matches with the length of the floating P type structure to be injected;
[0014] step 4): performing injection for a source region, a gate region and a drain region; and
[0015] step 5): injecting a floating P type structure into the middle portion of the N type drift region through the active region between the first field oxide region and the second field oxide region.
[0016] Preferably, the injection energy of the floating P type structure is 200Kev~2000Kev.
[0017] By using the above construction, the breakdown voltage of a NLDMOS device can be increased and on-resistance thereof can be reduced, the requirement on thickness of photoresist during manufacturing process and the requirement of high energy injection machine are lowered.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic structural view of a NLDMOS device according to an embodiment of the invention.
[0019] FIG. 2 is a schematic sectional view taken along A-A' direction of Fig. 1. DETAILED DESCRIPTION OF THE INVENTION
[0020] Fig. 1 illustrates a schematic structural view of a NLDMOS device according to the invention. The NLDMOS device includes a substrate lead-out 101, an source region lead-out 103, a gate lead-out 105, a first field oxide region 107, a second field oxide region 109, a drain end lead-out 111, a N type drift region 113 made by high voltage N well, a floating P type structure (floating P structure) 115, a buried oxide layer 117 and a substrate 119 made by high voltage P well, wherein the N type drift region 113 is located on the buried oxide layer 117, the substrate 119 adjacent to the N type drift region 113 is located on the buried oxide layer 117, and the floating P type structure 115 is disposed within the N type drift region 113.
[0021] By adjusting concentrations of impurities in various parts, the range of breakdown voltage of the above NLDMOS device can reach 100V-1000V. [0022] The floating P type structure 115 is located in the middle portion of the N type drift region 113 along the channel direction of the N type drift region 113 and the number thereof is not limited to one, i.e., there can be two and more floating P type structures 115 (as shown in Fig. 2). The floating P type structure 115 is of a stripe shape in layout and the cross section of the floating P type structure is in a rectangular shape. The floating P type structure 115 is injected into the middle portion of the N type drift region 113 by high energy. The injection energy is 200Kev~2000Kev and can be suitably adjusted according to the impurity distribution of the N type drift region 113 and the thickness of the epitaxial process. The dose of the floating P type structure 115 is required to achieve an electrical charge balance with the N type drift region 113. The floating P type structure 115 located in the middle portion of the N type drift region 113 can deplete N type impurities in the lateral direction and the longitudinal direction, thus facilitating the depletion of the N type drift region 113, increasing breakdown voltage of the device and reducing on-resistance. Moreover, electrical current can flow along channels in the N type drift region 113 above and under the floating P type structure 115, and the path through which electrical current flows is relative large. By employing the above construction, the impurity concentration of the drift region can be suitably increased so as to further reduce resistance.
[0023] The cross section of the floating P type structure 115 is not limited to rectangle, other shapes are also possible, such as circle, as long as these shapes are advantageous to the depletion of the N type drift region.
[0024] The first field oxide region 107 and the second field oxide region 109 are disposed on the N type drift region 113 to face each other. The first field oxide region 107 and the second field oxide region 109 do not completely cover the N type drift region 113. Therefore, the region between the first field oxide region 107 and the second field oxide region 109 remains to be an active region. The width of the active region between the first field oxide region 107 and the second field oxide region 109 matches with the length of the injected floating P type structure 115. The length of the first field oxide region 107 can be different from that of the second field oxide region 109.
[0025] Conventionally, the whole drift region of a NLDMOS device with a breakdown voltage which is above 100V is covered by a field oxide region. Since the floating P type structure 115 has to be injected into a middle portion of the N type drift region, a very high injection energy is necessary, thus requiring that the injection machine must realize a high energy injection and that the photoresist is thick enough so as to block the floating P type structure 115 from being injected into other regions. In the embodiment, the active region made between the first field oxide region 107 and the second field oxide region 109 has a relatively thin oxide layer, thus facilitating the injection of the floating P type structure 115 and reducing the requirements on the energy of injection machine and the thickness of photoresist, such that a floating P type structure 115 can be formed with a smaller width and spacing and the injection peak value of the floating P type structure 115 is deeper, making it easier to realize in manufacturing. [0026] According to an embodiment of the invention, a method of manufacturing the above-described NLDMOS device includes the following steps of:
[0027] step 1): forming an epitaxial layer on a buried oxide layer by conventional epitaxial manufacturing process;
[0028] step 2): performing well injection by conventional MOS process to form the N type drift region;
[0029] step 3): forming the first field oxide region and the second field oxide region by growth, the active region located between the first field oxide region and the second field oxide region, wherein the size of the active region matches with the length of a floating P type structure to be injected; [0030] step 4): performing injection for a source region, a gate region and a drain region; and
[0031] step 5): injecting a floating P type structure into the middle portion of the N type drift region through the active region between the first field oxide region and the second field oxide region. [0032] Since the device according to the embodiment of the invention is made on a silicon-on-insulator (SOI) wafer, there is a buried oxide layer. It is appreciated by those skilled in the art that the use of the SOI wafer intends to enhance isolation effect of the device and should not be construed as limiting the invention.
[0033] The five steps described above are only main steps required, and it is apparent that those skilled in the art are familiar with well known details that have not been mentioned.
[0034] In the embodiment of the invention, the injection of the floating P type structure 115 is performed after the injection for the source region and a drain region, so that the floating P type structure 115 is subject to less thermal process, thus avoiding the reduction of N type impurity concentration caused by diffusion of P type impurity and the increase of on-resistance caused by increase in size of the floating P type structure 115, etc.
[0035] Described above are only several embodiments of the invention, which are described in a relatively specific and detailed manner. However, they should not be construed as limiting the scope of the invention. It is noted that many variations and modifications can be made by those with ordinary skills in the art under the premise that they do not depart the concept of the invention, which all fall within the scope of protection of the invention. Therefore, the scope of protection of the invention is defined by the appended claims.

Claims

1. An NLDMOS device, comprising a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, wherein the floating P type structure is located in the middle portion of the N type drift region along the channel direction of the N type drift region, and wherein the width of active region between the first field oxide region and the second field oxide region is no less than the length of the floating P type structure.
2. The NLDMOS device according to claim 1, wherein the number of the floating P type structure is no less than two.
3. The NLDMOS device according to claim 1, wherein the floating P type structure is in a stripe shape and the cross section of the floating P type structure is in a rectangular shape.
4. The NLDMOS device according to claim 1, wherein the cross section of the floating P type structure is in a circular shape.
5. The NLDMOS device according to claim 1, wherein the length of the first field region is different from that of the second field oxide region.
6. A method of manufacturing NLDMOS device comprising a floating P type structure, a first field oxide region, a second field oxide region and a N type drift region, wherein the first field oxide region and the second field oxide region are disposed on the N type drift region, wherein the method comprises: step 1): forming an epitaxial layer on a buried oxide layer by epitaxial manufacturing process; step 2): performing well injection by MOS process to form the N type drift region; step 3): growing the first field oxide region and the second field oxide region, an active region located between the first field oxide region and the second field oxide region, wherein size of the active region matches with length of the floating P type structure to be injected; step 4): performing injection for a source region, a gate region and a drain region; and step 5): injecting the floating P type structure into the middle portion of the N type drift region through the active region between the first field oxide region and the second field oxide region.
7. The method of manufacturing NLDMOS device according to claim 6, wherein the injection energy of the floating P type structure is 200Kev~2000Kev.
PCT/CN2010/079412 2009-12-03 2010-12-03 N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof Ceased WO2011066802A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200910188704.5 2009-12-03
CN200910188704.5A CN102088031B (en) 2009-12-03 2009-12-03 N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2011066802A1 true WO2011066802A1 (en) 2011-06-09

Family

ID=44099741

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/079412 Ceased WO2011066802A1 (en) 2009-12-03 2010-12-03 N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN102088031B (en)
WO (1) WO2011066802A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115831757A (en) * 2023-02-08 2023-03-21 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure and semiconductor structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102280481B (en) * 2011-08-01 2016-04-20 上海华虹宏力半导体制造有限公司 Lateral double-diffused metal-oxide semiconductor device and manufacture method thereof
CN104241358B (en) * 2013-06-19 2017-02-08 上海华虹宏力半导体制造有限公司 Radio frequency ldmos device and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274904B1 (en) * 1998-09-02 2001-08-14 Siemens Aktiengesellschaft Edge structure and drift region for a semiconductor component and production method
JP2001274414A (en) * 2000-03-24 2001-10-05 Toshiba Corp Power semiconductor device and driving method thereof
US20060267044A1 (en) * 2005-05-24 2006-11-30 Yang Robert K DMOS transistor with a poly-filled deep trench for improved performance
US20070272978A1 (en) * 2006-05-23 2007-11-29 Infineon Technologies Austria Ag Semiconductor device including a vertical gate zone, and method for producing the same
CN101488526A (en) * 2009-02-27 2009-07-22 东南大学 N type SOI lateral double-diffused metal-oxide semiconductor transistor
CN101593774A (en) * 2009-06-10 2009-12-02 苏州博创集成电路设计有限公司 P-type silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100370625C (en) * 2005-10-14 2008-02-20 西安电子科技大学 Integratable high-voltage P-type LDMOS transistor structure and its preparation method
JP4568325B2 (en) * 2007-12-20 2010-10-27 シャープ株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274904B1 (en) * 1998-09-02 2001-08-14 Siemens Aktiengesellschaft Edge structure and drift region for a semiconductor component and production method
JP2001274414A (en) * 2000-03-24 2001-10-05 Toshiba Corp Power semiconductor device and driving method thereof
US20060267044A1 (en) * 2005-05-24 2006-11-30 Yang Robert K DMOS transistor with a poly-filled deep trench for improved performance
US20070272978A1 (en) * 2006-05-23 2007-11-29 Infineon Technologies Austria Ag Semiconductor device including a vertical gate zone, and method for producing the same
CN101488526A (en) * 2009-02-27 2009-07-22 东南大学 N type SOI lateral double-diffused metal-oxide semiconductor transistor
CN101593774A (en) * 2009-06-10 2009-12-02 苏州博创集成电路设计有限公司 P-type silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115831757A (en) * 2023-02-08 2023-03-21 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure and semiconductor structure
CN115831757B (en) * 2023-02-08 2023-04-28 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor structure and semiconductor structure

Also Published As

Publication number Publication date
CN102088031A (en) 2011-06-08
CN102088031B (en) 2013-04-17

Similar Documents

Publication Publication Date Title
CN107204372B (en) A trench type semiconductor device with an optimized terminal structure and its manufacturing method
EP1803159B1 (en) Mos-gated transistor with reduced miller capacitance
US8748982B2 (en) High breakdown voltage semiconductor device
KR101375887B1 (en) Lateral trench gate fet with direct source-drain current path
EP0718892B1 (en) Semiconductor device including insulated gate bipolar transistor and method of fabricating the same
KR101315699B1 (en) Power mosfet having superjunction trench and fabrication method thereof
CN107482061A (en) Superjunction devices and its manufacture method
JP2004228466A (en) Integrated semiconductor device and method of manufacturing the same
JP2015039010A (en) Super junction trench power mosfet device and manufacturing method therefor
CN106165101B (en) semiconductor device
CN107611167B (en) Super-junction semiconductor device with multiple concentration centers and manufacturing method thereof
KR20180083925A (en) Lateral diffusion metal oxide semiconductor field effect transistor
CN114023821B (en) Super junction device and manufacturing method thereof
CN107170688A (en) A kind of slot type power device and preparation method thereof
US20020125530A1 (en) High voltage metal oxide device with multiple p-regions
WO2011066802A1 (en) N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof
CN103426913A (en) Partial SOI (silicon on insulator) super junction high-voltage power semiconductor device
CN103560148B (en) A kind of junction termination structures of superjunction devices and manufacture method thereof
CN102157377A (en) Super-junction VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN102891088A (en) Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device
CN102130013A (en) A kind of SOI superjunction LDMOS device fabrication method with buffer layer
CN102522338A (en) Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region
CN204144267U (en) A kind of injection reinforced insulation grid bipolar transistor
CN111244158B (en) Super junction device and manufacturing method thereof
CN104332496B (en) One kind injection reinforced insulation grid bipolar transistor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10834235

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10834235

Country of ref document: EP

Kind code of ref document: A1