CN104332496B - One kind injection reinforced insulation grid bipolar transistor - Google Patents
One kind injection reinforced insulation grid bipolar transistor Download PDFInfo
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- CN104332496B CN104332496B CN201410614629.5A CN201410614629A CN104332496B CN 104332496 B CN104332496 B CN 104332496B CN 201410614629 A CN201410614629 A CN 201410614629A CN 104332496 B CN104332496 B CN 104332496B
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- 238000009413 insulation Methods 0.000 title claims abstract description 21
- 238000002347 injection Methods 0.000 title claims abstract description 19
- 239000007924 injection Substances 0.000 title claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims description 24
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 18
- 229910052785 arsenic Inorganic materials 0.000 claims description 18
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims description 18
- 239000011574 phosphorus Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 239000005864 Sulphur Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 6
- -1 proton Chemical compound 0.000 claims description 6
- 229910052711 selenium Inorganic materials 0.000 claims description 6
- 239000011669 selenium Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000003760 hair shine Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 12
- 238000000926 separation method Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000003752 improving hair Effects 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
The present invention relates to power semiconductor field, mainly a kind of injection reinforced insulation grid bipolar transistor, including p-type colelctor electrode, carrier diffusion layer is provided with the p-type colelctor electrode, more grooves are vertically arranged with the carrier diffusion layer, multiple rows of p-type mixed zone is horizontally arranged with the carrier diffusion layer, often arranging p-type mixed zone includes multiple independent p-type active regions and p-type inactive area, is separated between each block by the groove；Striated cycle separation property structure cell is provided with the bipolar transistor of the application, emitter stage is correspondingly formed separation shape, so that build-up effect occurs for the region that hole does not form covering in emitter stage, so as to improve the carrier concentration of groove near zone, conduction voltage drop is further reduced.
Description
Technical field
The present invention relates to power semiconductor field, mainly a kind of injection reinforced insulation grid bipolar transistor.
Background technology
Insulated gate bipolar transistor is widely used in the core control field of power electronics industry, and trench gate is such production
One of core technology of product, its main purpose can realize bigger current density and smaller conduction voltage drop, so as to reduce device
Part size simultaneously reduces power consumption.Traditional insulated gate bipolar transistor is when manufacturing Facad structure（Trench gate one side）, generally adopt
With the mode of cellular region all standing, which will cause device, and emitter stage is overflowed rapidly in hole at work, reduces near groove
Regional carrier concentration it is relatively low so that the reduction of conduction voltage drop is restricted.
Bipolar transistor structure is also improved in the prior art, such as Patent No. CN200920192176.6,
The applying date is 2009-08-31, the utility model patent of entitled " insulated gate bipolar transistor ", and its technical scheme is：This reality
With New insulated grid bipolar transistor, it is included in N- substrate surfaces and carries out the substrate that the N- ion implantings of low concentration are formed,
Formed substrate surface grid oxic horizon, the polysilicon gate being deposited on grid oxic horizon, formed grid oxic horizon with
P+ well regions between N- substrates and the N+ well regions between p+ well regions and grid oxic horizon, the back side note below N- substrates
Enter area, the colelctor electrode below injection region and the emitter stage above grid oxic horizon, the N- below grid oxic horizon
A dense P type trap zone is added on type substrate；
For another example number of patent application is CN201210333321.4, applying date 2012-09-11, a kind of entitled " colelctor electrode
Terminal has the insulated gate bipolar transistor of dielectric layer " patent of invention, its technical scheme is：A kind of colelctor electrode terminal has
The insulated gate bipolar transistor of dielectric layer, belong to power semiconductor and power integrated circuit technical field.The present invention exists
On the basis of traditional insulated gate bipolar transistor structure, one layer is introduced in device terminal collector region continuously or discontinuously
Dielectric layer.
In above-mentioned patent, CN200920192176.6 grid is plane, and CN201210333321.4 innovation exists
In the back side, i.e., terminal correspondence position one layer of dielectric layer of introducing in colelctor electrode, and Facad structure（Trench gate one side）Remain as biography
Unite structure, so there are still the carrier concentration in turn on process it is relatively low the problem of.
The content of the invention
It is restricted to solve the reduction of the conduction voltage drop of existing bipolar transistor, a kind of currently proposed striated week
Phase separation property structure cell, emitter stage are correspondingly formed separation shape so that accumulate in the region that hole does not form covering in emitter stage
Tired effect, so as to improve the carrier concentration of groove near zone, one kind injection for further reducing conduction voltage drop is enhanced absolutely
Edge grid bipolar transistor.
One kind injection reinforced insulation grid bipolar transistor, it is characterised in that：Including p-type colelctor electrode, the p-type current collection
Carrier diffusion layer is provided with extremely, more grooves, the carrier diffusion are vertically arranged with the carrier diffusion layer
Multiple rows of p-type mixed zone is horizontally arranged with layer, it is nonactive including multiple independent p-type active regions and p-type often to arrange p-type mixed zone
Area, separated by the groove between each block；The p-type active region often arranged on p-type mixed zone and p-type inactive area interval are set
Put, and the p-type active region on adjacent row in same row and p-type inactive area interval setting, it is described each to be set on p-type active region
N-type emitter stage is equipped with, the n-type emitter stage is in H types.
Field is provided with by layer between the p-type colelctor electrode and carrier diffusion layer.
The field cutoff layer is heavily doped n-layer.
The carrier diffusion layer is gently to mix n-layer；The n-type emitter stage is heavily doped n-layer.
The transverse width for often arranging p-type mixed zone is 2um-20um, and longitudinally wide is that 2um-40um depth is 2um-
8um。
The trench length direction is vertical with the length direction of p-type mixed zone.
The groove includes U-shaped blanket insulative layer, is that n-type fills polysilicon in the blanket insulative layer.
The blanket insulative layer includes silica and silicon nitride.
Doped with phosphorus or arsenic in the n-type filling polysilicon.
The width of the groove is 0.5um-2um, depth 2um-8um, and the spacing between adjacent trenches is 2um-8um.
By there is the blanket insulative layer, the width of two side is respectively for the side of n-type emitter stage two of the H types
0.5um-3um, the width between the side of H types two is 0.5um-8um, and the depth of the H types is 0.1um-1um.
The impurity of the p-type active region is boron, depth 2um-8um.
The impurity of the p-type inactive area is boron, depth 2um-8um.
The impurity of the p-type colelctor electrode is boron, depth 0.1um-2um.
The field includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 2um-20um by layer impurity.
It is described it is light mix n-type area and be doped to phosphorus or arsenic, mixed using gas or middle shine silicon chip.
P type emitter is provided with the p-type inactive area or/and p-type active region.
The p type emitter is attached most importance to doping p-type layer.
The advantages of the application, is：
1st, striated cycle separation property structure cell is provided with the bipolar transistor of the application, emitter stage is correspondingly formed
Separate shape so that build-up effect occurs for the region that hole does not form covering in emitter stage, so as to improve the load of groove near zone
Sub- concentration is flowed, further reduces conduction voltage drop.
2nd, the application is arranged to as the non-all standing structure in cellular region, and the grid of the application is ditch in trench gate one side
Groove profile, it is entirely different with the structure of documents and prior art.
3rd, because the presence of p-type inactive area, hole will build up effect under p-type inactive area, so as to improve hair
Carrier concentration near emitter-base bandgap grading, strengthen the conductivity modulation effect in the region, reduce conducting resistance, so as to reduce conduction voltage drop.
4th, the p-type active region and p-type inactive area of mixing cause the carrier accumulation near emitter stage to be more uniformly distributed.
5th, " H " the type emitter structure of the application can avoid the position caused by lithographic accuracy from deviateing so that both sides
N-type emitter stage connect together.
Brief description of the drawings
Fig. 1 is the application basic block diagram.
Fig. 2 is cross-sectional view where B-B ' in Fig. 1.
Fig. 3 adds p type emitter to compare Fig. 2.
Fig. 4 increases p type emitter in p-type active region and p-type inactive area.
Fig. 5 is cross-sectional view where A-A ' in Fig. 1.
Fig. 6 is A-A ' places cross-sectional view when cancelling p-type inactive area.
In accompanying drawing：P-type colelctor electrode 101, field is by layer 102, and carrier diffusion layer 103, p-type active region 1041, p-type is non-
Active region 1042, n-type emitter stage 105, p type emitter 106, blanket insulative layer 201, groove 202.
Embodiment
Embodiment 1
One kind injection reinforced insulation grid bipolar transistor includes p-type colelctor electrode 101, is set on the p-type colelctor electrode 101
Carrier diffusion layer 103 is equipped with, more grooves 202 are vertically arranged with the carrier diffusion layer 103, the carrier expands
Dissipate and be horizontally arranged with multiple rows of p-type mixed zone on layer 103, often arranging p-type mixed zone includes multiple independent p-type active regions 1041 and p
Type inactive area 1042, separated by the groove 202 between each block；The p-type active region 1041 often arranged on p-type mixed zone
It is arranged at intervals with p-type inactive area 1042, and the p-type active region 1041 in same row and p-type inactive area on adjacent row
1042 are arranged at intervals, and are provided with n-type emitter stage 105 on each p-type active region 1041, the n-type emitter stage 105 is in H types.
It is provided with striated cycle separation property structure cell in the bipolar transistor of the application, emitter stage is correspondingly formed point
From shape so that build-up effect occurs for the region that hole does not form covering in emitter stage, so as to improve the load of the near zone of groove 202
Sub- concentration is flowed, further reduces conduction voltage drop.The application is arranged to as the non-all standing structure in cellular region in the grid of groove 202 one side,
And the grid of the application is the type of groove 202, entirely different with the structure of documents and prior art.Because p-type is nonactive
The presence in area 1042, hole will build up effect under p-type inactive area 1042, so as to improve the carrier near emitter stage
Concentration, strengthen the conductivity modulation effect in the region, reduce conducting resistance, so as to reduce conduction voltage drop.The p-type active region of mixing
1041 and p-type inactive area 1042 cause emitter stage near carrier accumulation be more uniformly distributed." H " type emitter junction of the application
Structure can avoid the position caused by lithographic accuracy from deviateing so that the n-type emitter stage 105 of both sides connects together.
Embodiment 2
One kind injection reinforced insulation grid bipolar transistor includes p-type colelctor electrode 101, is set on the p-type colelctor electrode 101
Carrier diffusion layer 103 is equipped with, more grooves 202 are vertically arranged with the carrier diffusion layer 103, the carrier expands
Dissipate and be horizontally arranged with multiple rows of p-type mixed zone on layer 103, often arranging p-type mixed zone includes multiple independent p-type active regions 1041 and p
Type inactive area 1042, separated by the groove 202 between each block；The p-type active region 1041 often arranged on p-type mixed zone
It is arranged at intervals with p-type inactive area 1042, and the p-type active region 1041 in same row and p-type inactive area on adjacent row
1042 are arranged at intervals, and are provided with n-type emitter stage 105 on each p-type active region 1041, the n-type emitter stage 105 is in H types.
Field is provided between p-type colelctor electrode 101 and carrier diffusion layer 103 by layer 102.Field cutoff layer is heavily doped n-type
Layer.The carrier diffusion layer 103 is gently to mix n-layer；The n-type emitter stage 105 is heavily doped n-layer.Often arrange p-type mixed zone
Transverse width is 2um-20um, and longitudinally wide is that 2um-40um depth is 2um-8um.
The length direction of groove 202 is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped thin layer insulation
Layer 201, the blanket insulative layer 201 is interior to fill polysilicon for n-type.
Blanket insulative layer 201 includes silica and silicon nitride.Doped with phosphorus and arsenic in n-type filling polysilicon.
The width of groove 202 is 0.5um-2um, depth 2um-8um, and the spacing between adjacent trenches 202 is 2um-
8um.By there is the blanket insulative layer 201, the width of two side is respectively for 105 liang of sides of n-type emitter stage of H types
0.5um-3um, the width between the side of H types two is 0.5um-8um, and the depth of the H types is 0.1um-1um.P-type activity
The impurity in area 1041 is boron, depth 2um-8um.The impurity of p-type inactive area 1042 is boron, depth 2um-
8um.The impurity of p-type colelctor electrode 101 is boron, depth 0.1um-2um.
Field includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 2um-20um by the impurity of layer 102.Gently
Mix n-type area and be doped to phosphorus or arsenic, mixed using gas or middle shine silicon chip.Set in p-type inactive area 1042 or/and p-type active region 1041
It is equipped with p type emitter 106.P type emitter 106 is attached most importance to doping p-type layer.
It is provided with striated cycle separation property structure cell in the bipolar transistor of the application, emitter stage is correspondingly formed point
From shape so that build-up effect occurs for the region that hole does not form covering in emitter stage, so as to improve the load of the near zone of groove 202
Sub- concentration is flowed, further reduces conduction voltage drop.The application is arranged to as the non-all standing structure in cellular region in the grid of groove 202 one side,
And the grid of the application is the type of groove 202, entirely different with the structure of documents and prior art.Because p-type is nonactive
The presence in area 1042, hole will build up effect under p-type inactive area 1042, so as to improve the carrier near emitter stage
Concentration, strengthen the conductivity modulation effect in the region, reduce conducting resistance, so as to reduce conduction voltage drop.The p-type active region of mixing
1041 and p-type inactive area 1042 cause emitter stage near carrier accumulation be more uniformly distributed." H " type emitter junction of the application
Structure can avoid the position caused by lithographic accuracy from deviateing so that the n-type emitter stage 105 of both sides connects together.
Embodiment 3
One kind injection reinforced insulation grid bipolar transistor includes p-type colelctor electrode 101, is set on the p-type colelctor electrode 101
Carrier diffusion layer 103 is equipped with, more grooves 202 are vertically arranged with the carrier diffusion layer 103, the carrier expands
Dissipate and be horizontally arranged with multiple rows of p-type mixed zone on layer 103, often arranging p-type mixed zone includes multiple independent p-type active regions 1041 and p
Type inactive area 1042, separated by the groove 202 between each block；The p-type active region 1041 often arranged on p-type mixed zone
It is arranged at intervals with p-type inactive area 1042, and the p-type active region 1041 in same row and p-type inactive area on adjacent row
1042 are arranged at intervals, and are provided with n-type emitter stage 105 on each p-type active region 1041, the n-type emitter stage 105 is in H types.
Field is provided between p-type colelctor electrode 101 and carrier diffusion layer 103 by layer 102.Field cutoff layer is heavily doped n-type
Layer.The transverse width for often arranging p-type mixed zone is 20um, and longitudinally wide is that 2um depth is 8um.
The length direction of groove 202 is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped thin layer insulation
Layer 201, the blanket insulative layer 201 is interior to fill polysilicon for n-type.
Blanket insulative layer 201 includes silica and silicon nitride.Doped with phosphorus and arsenic in n-type filling polysilicon.
The width of groove 202 is 0.5um, depth 8um, and the spacing between adjacent trenches 202 is 2um.The n-type hair of H types
105 liang of sides of emitter-base bandgap grading are by there is the blanket insulative layer 201, and the width of two side is respectively 3um, the side of H types two
Between width be 0.5um, the depth of the H types is 1um.The impurity of p-type active region 1041 is boron, depth 2um.p
The impurity of type inactive area 1042 is boron, depth 8um.The impurity of p-type colelctor electrode 101 is boron, and depth is
0.1um。
Field includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 20um by the impurity of layer 102.Gently mix n
Type area is doped to phosphorus or arsenic, is mixed using gas or middle shines silicon chip.It is provided with p-type inactive area 1042 or/and p-type active region 1041
P type emitter 106.P type emitter 106 is attached most importance to doping p-type layer.
Embodiment 4
One kind injection reinforced insulation grid bipolar transistor includes p-type colelctor electrode 101, is set on the p-type colelctor electrode 101
Carrier diffusion layer 103 is equipped with, more grooves 202 are vertically arranged with the carrier diffusion layer 103, the carrier expands
Dissipate and be horizontally arranged with multiple rows of p-type mixed zone on layer 103, often arranging p-type mixed zone includes multiple independent p-type active regions 1041 and p
Type inactive area 1042, separated by the groove 202 between each block；The p-type active region 1041 often arranged on p-type mixed zone
It is arranged at intervals with p-type inactive area 1042, and the p-type active region 1041 in same row and p-type inactive area on adjacent row
1042 are arranged at intervals, and are provided with n-type emitter stage 105 on each p-type active region 1041, the n-type emitter stage 105 is in H types.
Field is provided between p-type colelctor electrode 101 and carrier diffusion layer 103 by layer 102.Field cutoff layer is heavily doped n-type
Layer.The carrier diffusion layer 103 is gently to mix n-layer；The n-type emitter stage 105 is heavily doped n-layer.Often arrange p-type mixed zone
Transverse width is 2um, and longitudinally wide is that 40um depth is 2um.
The length direction of groove 202 is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped thin layer insulation
Layer 201, the blanket insulative layer 201 is interior to fill polysilicon for n-type.
Blanket insulative layer 201 includes silica and silicon nitride.Doped with phosphorus and arsenic in n-type filling polysilicon.
The width of groove 202 is 2um, depth 2um, and the spacing between adjacent trenches 202 is 8um.The n-type transmitting of H types
105 liang of pole side is by there is the blanket insulative layer 201, and the width of two side is respectively 0.5um, the side of H types two
Between width be 8um, the depth of the H types is 0.1um.The impurity of p-type active region 1041 is boron, depth 8um.p
The impurity of type inactive area 1042 is boron, depth 2um.The impurity of p-type colelctor electrode 101 is boron, depth 2um.
Field includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 2um by the impurity of layer 102.Gently mix n-type
Area is doped to phosphorus or arsenic, is mixed using gas or middle shines silicon chip.P is provided with p-type inactive area 1042 or/and p-type active region 1041
Type emitter stage 106.P type emitter 106 is attached most importance to doping p-type layer.
Embodiment 5
One kind injection reinforced insulation grid bipolar transistor includes p-type colelctor electrode 101, is set on the p-type colelctor electrode 101
Carrier diffusion layer 103 is equipped with, more grooves 202 are vertically arranged with the carrier diffusion layer 103, the carrier expands
Dissipate and be horizontally arranged with multiple rows of p-type mixed zone on layer 103, often arranging p-type mixed zone includes multiple independent p-type active regions 1041 and p
Type inactive area 1042, separated by the groove 202 between each block；The p-type active region 1041 often arranged on p-type mixed zone
It is arranged at intervals with p-type inactive area 1042, and the p-type active region 1041 in same row and p-type inactive area on adjacent row
1042 are arranged at intervals, and are provided with n-type emitter stage 105 on each p-type active region 1041, the n-type emitter stage 105 is in H types.
Field is provided between p-type colelctor electrode 101 and carrier diffusion layer 103 by layer 102.Field cutoff layer is heavily doped n-type
Layer.The carrier diffusion layer 103 is gently to mix n-layer；The n-type emitter stage 105 is heavily doped n-layer.Often arrange p-type mixed zone
Transverse width is 10um, and longitudinally wide is that 21um depth is 4um.
The length direction of groove 202 is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped thin layer insulation
Layer 201, the blanket insulative layer 201 is interior to fill polysilicon for n-type.
Blanket insulative layer 201 includes silica and silicon nitride.Doped with phosphorus and arsenic in n-type filling polysilicon.
The width of groove 202 is 1um, depth 3um, and the spacing between adjacent trenches 202 is 5um.The n-type transmitting of H types
105 liang of pole side is by there is the blanket insulative layer 201, and the width of two side is respectively 1.2um, the side of H types two
Between width be 3um, the depth of the H types is 0.5um.The impurity of p-type active region 1041 is boron, depth 4um.p
The impurity of type inactive area 1042 is boron, depth 5um.The impurity of p-type colelctor electrode 101 is boron, and depth is
1.1um。
Field includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 12um by the impurity of layer 102.Gently mix n
Type area is doped to phosphorus or arsenic, is mixed using gas or middle shines silicon chip.It is provided with p-type inactive area 1042 or/and p-type active region 1041
P type emitter 106.P type emitter 106 is attached most importance to doping p-type layer.
It is worth noting that, the structure disclosed in this patent is applicable not only to insulated gate bipolar transistor, it is equally applicable
In other channel-type power semiconductors such as MOSFET.Parameter and method disclosed in patent is only for reference, protects content
Parameter described in text is not limited only to, technical staff can apply after appropriate adjustment in the field.
Claims (7)
1. one kind injection reinforced insulation grid bipolar transistor, it is characterised in that：Including p-type colelctor electrode（101）, the p-type
Colelctor electrode（101）On be provided with carrier diffusion layer（103）, in the carrier diffusion layer（103）On be vertically arranged with more
Groove（202）, the carrier diffusion layer（103）On be horizontally arranged with multiple rows of p-type mixed zone, often arrange p-type mixed zone include it is more
Individual independent p-type active region（1041）With p-type inactive area（1042）, by the groove between each block（202）Separate；It is described
Often arrange the p-type active region on p-type mixed zone（1041）With p-type inactive area（1042）It is arranged at intervals, and it is same on adjacent row
P-type active region on row（1041）With p-type inactive area（1042）It is arranged at intervals, each p-type active region（1041）On set
It is equipped with n-type emitter stage（105）, the n-type emitter stage（105）In H types；
The transverse width for often arranging p-type mixed zone is 2um-20um, and longitudinally wide is that 2um-40um depth is 2um-8um；
The groove（202）Include U-shaped blanket insulative layer（201）, the blanket insulative layer（201）It is interior to be filled for n-type
Polysilicon；The groove（202）Length direction is vertical with the length direction of p-type mixed zone；
The blanket insulative layer（201）Including silica and silicon nitride.
A kind of 2. injection reinforced insulation grid bipolar transistor according to claim 1, it is characterised in that：The p-type
Colelctor electrode（101）With carrier diffusion layer（103）Between be provided with a cutoff layer（102）, the field cutoff layer is heavily doped n-type
Layer；The carrier diffusion layer（103）Gently to mix n-layer；The n-type emitter stage（105）For heavily doped n-layer.
A kind of 3. injection reinforced insulation grid bipolar transistor according to claim 1, it is characterised in that：The n-type
Fill in polysilicon doped with phosphorus and arsenic.
A kind of 4. injection reinforced insulation grid bipolar transistor according to claim 3, it is characterised in that：The groove
（202）Width be 0.5um-2um, depth 2um-8um, adjacent trenches（202）Between spacing be 2um-8um；The H types
N-type emitter stage（105）Two sides, which rely on, the blanket insulative layer（201）, the width of two side is respectively 0.5um-
3um, the width between the side of H types two is 0.5um-8um, and the depth of the H types is 0.1um-1um.
A kind of 5. injection reinforced insulation grid bipolar transistor according to claim 2, it is characterised in that：The p-type
Active region（1041）Impurity be boron, depth 2um-8um；The p-type inactive area（1042）Impurity be boron,
Depth is 2um-8um；The p-type colelctor electrode（101）Impurity be boron, depth 0.1um-2um；The field cutoff layer
（102）Impurity includes phosphorus, selenium, proton, sulphur, arsenic or defect doping, depth 2um-20um.
A kind of 6. injection reinforced insulation grid bipolar transistor according to claim 2, it is characterised in that：It is described gently to mix
N-type area is doped to phosphorus or arsenic, is mixed using gas or middle shines silicon chip.
A kind of 7. injection reinforced insulation grid bipolar transistor according to claim 6, it is characterised in that：The p-type
Inactive area（1042）Or/and p-type active region（1041）Inside it is provided with p type emitter（106）, the p type emitter（106）For
Heavily doped p-type layer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| CN103367413A (en) * | 2013-04-27 | 2013-10-23 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN104078494A (en) * | 2013-03-29 | 2014-10-01 | 三星电机株式会社 | Power semiconductor device and method of fabricating the same |
| CN204144267U (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | A kind of injection reinforced insulation grid bipolar transistor |
-
2014
- 2014-11-05 CN CN201410614629.5A patent/CN104332496B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| CN104078494A (en) * | 2013-03-29 | 2014-10-01 | 三星电机株式会社 | Power semiconductor device and method of fabricating the same |
| CN103367413A (en) * | 2013-04-27 | 2013-10-23 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN204144267U (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | A kind of injection reinforced insulation grid bipolar transistor |
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