WO2011060686A1 - Ldmos功率器件 - Google Patents

Ldmos功率器件 Download PDF

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Publication number
WO2011060686A1
WO2011060686A1 PCT/CN2010/078346 CN2010078346W WO2011060686A1 WO 2011060686 A1 WO2011060686 A1 WO 2011060686A1 CN 2010078346 W CN2010078346 W CN 2010078346W WO 2011060686 A1 WO2011060686 A1 WO 2011060686A1
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conductive
conductivity type
substrate
region
power device
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PCT/CN2010/078346
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English (en)
French (fr)
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马强
陈强
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苏州远创达科技有限公司
远创达科技(香港)有限公司
远创达科技(开曼)有限公司
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Priority to CN201080052919.5A priority Critical patent/CN102754211B/zh
Publication of WO2011060686A1 publication Critical patent/WO2011060686A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • the present invention relates to an LDMOS power device.
  • the existing LDMOS power device (RF power device) structure design is shown in Figure 1, including P-type heavily doped substrate, P a P-type epitaxial layer on the heavily doped substrate and a source region and a drain region on the P-type epitaxial layer, wherein the source region is electrically connected to the P-type doped substrate, and the source region and the drain region are A channel region is provided between the channels, and a gate is provided above the channel region.
  • the performance of LDMOS power devices at high frequencies is mainly limited by the gate-to-source capacitance Cgs and the drain-to-source capacitance Cds. Cgs
  • the size is mainly determined by the gate length and the gate oxide thickness. These two parameters also control the device transconductance parameter gm.
  • Cds is determined by the size of the lightly doped region (LDD region), and the LDD region also determines the turn-on resistance Rdson And the size of the breakdown voltage BVdss. Once the LDD area is optimized to achieve the best Rdson and BVdss, it is also difficult to reduce Cds at the same time.
  • LDD region lightly doped region
  • Rdson turn-on resistance
  • BVdss breakdown voltage
  • the object of the present invention is to provide an LDMOS power device that reduces the gate-to-source capacitance without reducing other parameter specifications.
  • Cgs and the drain-to-source capacitance, Cds enable high gain and high efficiency operation of the device under RF conditions.
  • the technical solution of the present invention is: an LDMOS A power device comprising a substrate, a first conductivity type epitaxial layer on the substrate, and a source region and a drain region formed on the first conductivity type epitaxial layer, the source region being electrically connected to the substrate,
  • the substrate is a second conductivity type substrate opposite the first conductivity type.
  • the first conductivity type and the second conductivity type refer to P type or N type, that is, when the first conductivity type is P type, the second conductivity type is N type; when the second conductivity type is P type, the first conductivity type is N type.
  • the first conductivity type epitaxial layer of the present invention has an LDMOS generally having a first conductivity type substrate.
  • the power device should be thick.
  • the source region is connected to the second conductive type substrate through a conductive trench, or the source region is connected to the bottom of the second conductive type substrate through a conductive full via, the source region is provided There is a source ohmic contact region that is electrically connected to the conductive trench or the conductive via.
  • the source ohmic contact region extends from the surface of the source region to the conductive trench or the conductive via and is directly connected to the conductive trench or the conductive via, such that the source region is grounded.
  • the LDMOS The surface of the power device semiconductor is provided with an oxide layer, and the oxide layer is provided with a conductive layer, and the conductive layer is electrically connected to the source ohmic contact region and the conductive trench (or conductive full via), respectively, so that the source region is grounded.
  • the first conductive type epitaxial layer is further provided with a second conductive type heavily doped connection trench connected to the substrate around the conductive trench or the conductive full via hole for enhancing the conductivity of the ground.
  • the present invention provides a first conductivity type epitaxial layer on a second conductivity type substrate such that a capacitance is generated between the first conductivity type epitaxial layer and the second conductivity type substrate, the capacitance being in series with Cgs and Cds, thereby reducing Cgs And Cds, to achieve high gain and high efficiency of the device under RF conditions.
  • the present invention can reduce Cgs and Cds by at least 20%, thereby improving the gain of the LDMOS power device by at least 1 dB and increasing the efficiency by at least 2%.
  • the second conductivity type is N.
  • the working mode only the electron flow passes through the conductive trench (or conductive full via) and the N-type heavily doped connection channel to ground, and there is no empty substream, and the conventional LDMOS power device is in the P-type heavily doped connection trench. Daohe There is a null substream between the P-type heavily doped substrates, so the device design of the present invention only has a higher efficiency.
  • FIG. 1 is a schematic structural view of a prior art LDMOS power device
  • FIG. 2 is a schematic structural view of a first embodiment of the present invention
  • FIG. 3 is a schematic structural view of a second embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a third embodiment of the present invention.
  • an LDMOS power device including a second conductivity type substrate 1a a first conductivity type epitaxial layer 2 on the second conductivity type substrate 1a, and a source region and a drain region formed on the first conductivity type epitaxial layer 2, the source region and the substrate 1 Conductive connection.
  • a first conductivity type doped channel region 9 is also disposed between the source region and the drain region.
  • the drain region includes a second conductivity type heavily doped drain region 10 and is isolated in the first conductivity type doped channel region 9 And a second conductivity type drift region 11 between the second conductivity type heavily doped drain region 10, wherein the surface of the second conductivity type heavily doped drain region 10 is provided with a drain ohmic contact region 16.
  • LDMOS The gate 12 of the power device is disposed in the oxide layer 6 above the doped channel region 9 of the first conductivity type.
  • the LDMOS power device can also be provided with a field plate 15 for grounding in the oxide layer 6.
  • the source region includes a second conductivity type heavily doped source region 13 and a first conductivity type heavily doped source region 14, as shown in FIG. 2 and FIG. Shown.
  • the second conductivity type heavily doped source region 13 is located above the first conductivity type heavily doped source region 14 and the first conductivity type doped channel region 9.
  • the source region may further include only the second conductivity type heavily doped source region 13 , as shown in FIG. 4 , at this time, the first conductive type doped channel region 9 extends outward to surround the second conductive type heavily doped source region 13 .
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the source region is connected to the second conductive type substrate 1a through the conductive trench 4, or the source region is passed through the conductive full via 5 Connected to the bottom of the second conductive type substrate 1a to ground, (the conductive trench 4 and the conductive full via 5 in FIGS. 2 to 4) Also shown, but in actual use, there is only one of them.
  • the surface of the source region is provided with a source ohmic contact region 3 electrically connected to the conductive trench 4 or the conductive via 5 . Making the source region and substrate 1 Connected and grounded.
  • the source ohmic contact region 3 extends from the surface of the source region to the conductive trench 4 or the conductive via 5 and to the conductive trench 4 Or conductive full via 5 is directly connected, as shown in Figure 2.
  • the second conductive type heavily doped source region 13 may also extend outwardly from the conductive trench 4 or the conductive full via 5 as indicated by the dashed line in FIG. Direct connection to enhance grounding.
  • the LDMOS power device semiconductor surface is provided with an oxide layer 6 in which a conductive layer 7 is disposed, the conductive layer 7 and the source ohmic contact region 3, respectively. It is electrically connected to the conductive trench 4 (or conductive via 5), as shown in Figure 3 and Figure 4.
  • the first conductive type epitaxial layer 2 may also be provided with the substrate 1 around the conductive trench 4 or the conductive via 5
  • the connected second conductivity type is heavily doped to the connection trench 8 .
  • the second conductivity type heavily doped connection trench 8 can be used to enhance the conductivity of the ground.
  • the first conductive type doped region is the first conductive type heavily doped source region 14 shown in FIGS. 2 and 3 or the first conductive type doped channel region shown in FIG.
  • the ground portion is a conductive trench 4 or a conductive full via 5 and/or a second conductive type heavily doped connection trench 8 .
  • the second conductivity type heavily doped connection trenches in FIGS. 2 and 3 The distance a from the first conductivity type heavily doped source region 14 is at least 4 microns; between the second conductivity type heavily doped connection trench 8 in FIG. 4 and the first conductivity type doped channel region 9 Distance b At least 4 microns.
  • the invention reduces the gate-to-source capacitance Cgs and the drain-to-source capacitance Cds without reducing other parameter specifications. , to achieve high gain and high efficiency of the device under RF conditions.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

LDMOS功率器件
技术领域
本发明涉及一种 LDMOS 功率器件。
背景技术
现有的 LDMOS 功率器件（射频功率器件）结构设计如图 1 所示，包括 P 型重掺杂衬底、 P 型重掺杂衬底上的 P 型外延层以及 P 型外延层上的源极区和漏极区，其中源极区与 P 型中掺杂衬底导电连接，源极区和漏极区之间设有沟道区，沟道区的上方设有栅。 LDMOS 功率器件在高频率时的性能主要受限于栅极到源极的电容 Cgs 和漏极到源极的电容 Cds 。 Cgs 的大小主要由栅极长度和栅极氧化层厚度来决定，这两个参数同时也控制器件跨导参数 gm 。降低 Cgs 就要牺牲 gm 或器件的可靠性（例如增加窄通道效应），否则很难减小 Cgs 。 Cds 决定于轻掺杂区（ LDD 区）的大小， LDD 区也决定了开启电阻 Rdson 和击穿电压 BVdss 的大小。一旦优化了 LDD 区来实现最佳的 Rdson 和 BVdss ，要同时降低 Cds 也很难。
发明内容
本发明目的是提供一种 LDMOS 功率器件，在不用降低其它参数指标的前提下，减小了栅极到源极的电容 Cgs 和漏极到源极的电容 Cds ，实现了射频条件下器件高增益和高效率的工作。
本发明的技术方案是：一种 LDMOS 功率器件，包括衬底、衬底上的第一导电类型外延层、以及形成于第一导电类型外延层上的源极区和漏极区，所述源极区与衬底导电连接，所述衬底为与第一导电类型相反的第二导电类型衬底。其中第一导电类型和第二导电类型是指 P 型或 N 型，即当第一导电类型为 P 型时，第二导电类型为 N 型；当第二导电类型为 P 型时，第一导电类型为 N 型。对于高电压和高击穿电压的 LDMOS 器件应用，由于第一导电类型外延层和第二导电类型衬底之间存在一个结间耗尽区，本发明第一导电类型外延层相比通常具有第一导电类型衬底的 LDMOS 功率器件要厚。
进一步的，所述源极区通过导电沟槽连接到第二导电类型衬底上，或者所述源极区通过导电全过孔连接到第二导电类型衬底底部，所述源极区表面设有与导电沟槽或导电全过孔导电连接的源欧姆接触区。
进一步的，所述源欧姆接触区由源极区表面延伸到导电沟槽或导电全过孔上方并与导电沟槽或导电全过孔直接连接，使得源极区接地。
或者进一步的，所述 LDMOS 功率器件半导体表面设有氧化层，所述氧化层内设有导电层，所述导电层分别与源欧姆接触区和导电沟槽（或导电全过孔）导电连接，使得源极区接地。
进一步的，所述第一导电类型外延层上还于导电沟槽或导电全过孔周围设有与衬底连接的第二导电类型重掺杂连接沟槽，用来增强接地的导电性。
本发明优点是：
1、本发明在第二导电类型衬底上设置第一导电类型外延层，使得第一导电类型外延层与第二导电类型衬底之间产生一个电容，该电容与Cgs和Cds串联，从而降低了Cgs 和Cds，实现了射频条件下器件高增益和高效率的工作。本发明可以使Cgs和Cds降低至少20%，从而使得LDMOS功率器件的增益改善至少1dB、效率提高至少2%。
2 、当第一导电类型为 P 型，第二导电类型为 N 型时，本发明工作过程中只有电子流通过导电沟槽（或导电全过孔）和 N 型重掺连接沟道接地，不存在空子流，而传统的 LDMOS 功率器件在 P 型重掺连接沟道和 P 型重掺衬底之间存在有空子流，所以本发明只有电子流的器件设计会有较高的效率。
附图说明
图 1 为现有技术 LDMOS 功率器件的结构示意图；
图 2 为本发明具体实施例一的结构示意图；
图 3 为本发明具体实施例二的结构示意图；
图 4 为本发明具体实施例三的结构示意图。
其中： 1 衬底； 1a 第二导电类型衬底； 2 第一导电类型外延层； 3 源欧姆接触区； 4 导电沟槽； 5 导电全过孔； 6 氧化层； 7 导电层； 8 第二导电类型重掺杂连接沟槽； 9 第一导电类型掺杂沟道区； 10 第二导电类型重掺杂漏区； 11 第二导电类型漂移区； 12 栅； 13 第二导电类型重掺杂源区； 14 第一导电类型重掺杂源区； 15 场板； 16 漏欧姆接触区。
具体实施方式
下面结合附图及实施例对本发明作进一步描述：
实施例：如图 2 至图 4 所示，一种 LDMOS 功率器件，包括第二导电类型衬底 1a 、第二导电类型衬底 1a 上的第一导电类型外延层 2 、以及形成于第一导电类型外延层 2 上的源极区和漏极区，所述源极区与衬底 1 导电连接。所述源极区与漏极区之间还设有第一导电类型掺杂沟道区 9 。所述漏极区包括第二导电类型重掺杂漏区 10 以及隔离在第一导电类型掺杂沟道区 9 和第二导电类型重掺杂漏区 10 之间的第二导电类型漂移区 11 ，其中第二导电类型重掺杂漏区 10 的表面设置有漏欧姆接触区 16 。 LDMOS 功率器件的栅 12 设于第一导电类型掺杂沟道区 9 上方的氧化层 6 内，此外 LDMOS 功率器件还可以在氧化层 6 中设置用于接地的场板 15 。
所述源极区包括第二导电类型重掺杂源区 13 和第一导电类型重掺杂源区 14 ，如图 2 和图 3 所示。此时第二导电类型重掺杂源区 13 位于第一导电类型重掺杂源区 14 和第一导电类型掺杂沟道区 9 之上。所述源极区还可以只包括第二导电类型重掺杂源区 13 ，如图 4 所示，此时第一导电类型掺杂沟道区 9 向外延伸包围第二导电类型重掺杂源区 13 。
本实施例中第一导电类型为 P 型，第二导电类型为 N 型。
所述源极区通过导电沟槽 4 连接到第二导电类型衬底 1a 上，或者所述源极区通过导电全过孔 5 连接到第二导电类型衬底 1a 底部接地，（图 2 至图 4 中导电沟槽 4 和导电全过孔 5 同时示出了，但是在实际使用时，二者仅有一个即可）所述源极区表面设有与导电沟槽 4 或导电全过孔 5 导电连接的源欧姆接触区 3 。使得源极区与衬底 1 相连并接地。
其中，所述源欧姆接触区 3 由源极区表面延伸到导电沟槽 4 或导电全过孔 5 上方并与导电沟槽 4 或导电全过孔 5 直接连接，如图 2 所示。本实施例中第二导电类型重掺杂源区 13 还可以如图 2 中虚线所示向外延伸与导电沟槽 4 或导电全过孔 5 直接连接，加强接地效果。或者，所述 LDMOS 功率器件半导体表面设有氧化层 6 ，所述氧化层 6 内设有导电层 7 ，所述导电层 7 分别与源欧姆接触区 3 和导电沟槽 4 （或导电全过孔 5 ）导电连接，如图 3 和图 4 所示。
所述第一导电类型外延层 2 上还于导电沟槽 4 或导电全过孔 5 周围还可以设有与衬底 1 连接的第二导电类型重掺杂连接沟槽 8 。该第二导电类型重掺杂连接沟槽 8 可以用来增强接地的导电性。
第二导电类型重掺杂源区 13 外的第一导电类型掺杂区与接地部之间保持至少 4 微米的距离。其中上述第一导电类型掺杂区为图 2 和图 3 中所示的第一导电类型重掺杂源区 14 或图 4 中所示的第一导电类型掺杂沟道区 9 ；接地部为导电沟槽 4 或导电全过孔 5 和 / 或第二导电类型重掺杂连接沟槽 8 。具体的：图 2 和图 3 中的第二导电类型重掺杂连接沟槽 8 与第一导电类型重掺杂源区 14 之间的距离 a 至少为 4 微米；图 4 中的第二导电类型重掺杂连接沟槽 8 与第一导电类型掺杂沟道区 9 之间的距离 b 至少为 4 微米。
本发明在不用降低其它参数指标的前提下，减小了栅极到源极的电容 Cgs 和漏极到源极的电容 Cds ，实现了射频条件下器件高增益和高效率的工作。

Claims (1)

  1. 1 ．一种 LDMOS 功率器件，包括衬底（ 1 ）、衬底（ 1 ）上的第一导电类型外延层（ 2 ）、以及形成于第一导电类型外延层（ 2 ）上的源极区和漏极区，所述源极区与衬底（ 1 ）导电连接，其特征在于：所述衬底（ 1 ）为与第一导电类型相反的第二导电类型衬底（ 1a ）。
    2 ．根据权利要求 1 所述的 LDMOS 功率器件，其特征在于：所述源极区通过导电沟槽（ 4 ）连接到第二导电类型衬底（ 1a ）上，或者所述源极区通过导电全过孔（ 5 ）连接到第二导电类型衬底（ 1a ）底部，所述源极区表面设有与导电沟槽（ 4 ）或导电全过孔（ 5 ）导电连接的源欧姆接触区（ 3 ）。
    3 ．根据权利要求 2 所述的 LDMOS 功率器件，其特征在于：所述源欧姆接触区（ 3 ）由源极区表面延伸到导电沟槽（ 4 ）或导电全过孔（ 5 ）上方并与导电沟槽（ 4 ）或导电全过孔（ 5 ）直接连接。
    4 ．根据权利要求 2 所述的 LDMOS 功率器件，其特征在于：所述 LDMOS 功率器件半导体表面设有氧化层（ 6 ），所述氧化层（ 6 ）内设有导电层（ 7 ），所述导电层（ 7 ）分别与源欧姆接触区（ 3 ）和导电沟槽（ 4 ）或导电全过孔（ 5 ）导电连接。
    5．根据权利要求2所述的LDMOS功率器件，其特征在于：所述第一导电类型外延层（2）上还于导电沟槽（4）或导电全过孔（5）周围设有与第二导电类型衬底（1a）连接的第二导电类型重掺杂连接沟槽（8）。
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