WO2011052108A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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WO2011052108A1
WO2011052108A1 PCT/JP2010/002717 JP2010002717W WO2011052108A1 WO 2011052108 A1 WO2011052108 A1 WO 2011052108A1 JP 2010002717 W JP2010002717 W JP 2010002717W WO 2011052108 A1 WO2011052108 A1 WO 2011052108A1
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crystal layer
mixed crystal
silicon mixed
shallow
semiconductor substrate
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English (en)
Japanese (ja)
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竹岡慎治
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a transistor capable of improving stress applied to a channel while suppressing deterioration of short channel characteristics and a manufacturing method thereof.
  • the degree of circuit integration has improved dramatically, making it possible to mount more than 100 million field effect transistors (FETs, Field Effect Transistors) on a single chip.
  • FETs Field Effect transistors
  • the reduction of the gate length has been mainly used as a means to realize a high-performance transistor.
  • the gate length is 45 to 65 nm or less, a device with a reduced gate length can be expected to improve characteristics. Disappear. For this reason, in order to realize a fine device, a new technique for improving the performance of a transistor is required.
  • FIG. 7 is a diagram showing a P-channel transistor 20 described in Patent Document 1.
  • a gate electrode 12 is formed on a silicon substrate 10 via a gate insulating film 11, and a side wall spacer 13 is formed so as to cover the side wall of the gate electrode 12.
  • extension regions 14 are formed on both sides of the gate electrode 12 in the silicon substrate 10, and source / drain impurity regions 15 are formed outside the extension region 14 when viewed from the gate electrode 12.
  • buried source / drain regions 16 made of silicon germanium are buried in the source / drain impurity regions 15.
  • the stress applied to the channel may be improved.
  • the buried source / drain region formed of silicon germanium or the like may be brought closer to or deeper than the channel side.
  • a buried source / drain region is formed in a source / drain region using a semiconductor material (for example, silicon germanium) having a lattice constant different from that of a semiconductor substrate, it is formed at the interface between the semiconductor substrate and the buried source / drain region. Leakage current increases due to defects and the like. In order to reduce this, it is necessary to cover the buried source / drain regions with the source / drain impurity regions.
  • a semiconductor material for example, silicon germanium
  • the source / drain impurity regions are also brought closer to the channel side, and the short channel characteristics are deteriorated.
  • the short channel characteristics are deteriorated because the source / drain impurity regions are also deepened.
  • a semiconductor device including a transistor capable of improving stress applied to a channel formation region while suppressing deterioration of short channel characteristics and a manufacturing method thereof will be described below.
  • the inventors of the present application have conceived of embedding a semiconductor material (silicon germanium or the like) for applying stress to the channel formation region in the extension region in addition to the source / drain region.
  • a semiconductor material silicon germanium or the like
  • a semiconductor device of the present disclosure includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film, and a lattice different from the semiconductor substrate embedded in both sides of the gate electrode in the semiconductor substrate.
  • a silicon mixed crystal layer having a constant, and the silicon mixed crystal layer includes a shallow silicon mixed crystal layer and a deep silicon mixed crystal layer formed deeper than the shallow silicon mixed crystal layer. The silicon mixed crystal layer is formed even closer to the gate electrode than the deep silicon mixed crystal layer.
  • the shallow silicon mixed crystal layer that is shallower than the deep silicon mixed crystal layer and close to the gate electrode, the channel formation is performed while suppressing deterioration of short channel characteristics.
  • a larger stress in the gate length direction can be applied to the region.
  • the deep silicon mixed crystal layer functions as a buried source / drain region.
  • the shallow silicon mixed crystal layer which is one of the features of the semiconductor device of the present disclosure, has a configuration that can be called a buried extension region.
  • the silicon mixed crystal layer is embedded to a position closer to the gate electrode, it is more advantageous for applying a stress to the channel formation region.
  • the source / drain region is prevented from approaching and becoming deeper on the channel side. And deterioration of the short channel characteristics can be suppressed.
  • the extension impurity region is formed at a depth of 5 nm or more in the semiconductor substrate from the boundary between the shallow silicon mixed crystal layer and the semiconductor substrate, and the source / drain impurity regions are formed in the deep silicon mixed crystal layer and the semiconductor. It is preferably formed in the semiconductor substrate at a depth of 5 nm or more from the boundary with the substrate.
  • the shallow silicon mixed crystal layer is in contact with only the side surface of the deep silicon mixed crystal layer.
  • a deep silicon mixed crystal layer is formed outside the shallow silicon mixed crystal layer formed on the side of the gate electrode.
  • the shallow silicon mixed crystal layer is preferably formed so as to cover the upper surface of the deep silicon mixed crystal layer.
  • a shallow silicon mixed crystal layer is stacked on the deep silicon mixed crystal layer, and the shallow silicon mixed crystal layer is formed closer to the gate electrode than the deep silicon mixed crystal layer.
  • An example of the arrangement of the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer may be as described above.
  • the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are P-type, and the lattice constant of the shallow silicon mixed crystal layer and the lattice constant of the deep silicon mixed crystal layer are both lattice constants of the semiconductor substrate. Is preferably larger.
  • the lattice constant of the shallow silicon mixed crystal layer is preferably larger than the lattice constant of the deep silicon mixed crystal layer.
  • the silicon mixed crystal layer is difficult to increase in thickness as the difference in lattice constant with the semiconductor substrate increases, it is necessary to increase the lattice constant of the shallow silicon mixed crystal layer that is relatively thin and close to the channel formation region. This is useful for improving the performance.
  • the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are preferably P-type, and it is preferable that both the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are made of silicon germanium.
  • germanium concentration in the shallow silicon mixed crystal layer is preferably higher than the germanium concentration in the deep silicon mixed crystal layer.
  • germanium is difficult to increase in thickness as the germanium concentration increases, increasing the germanium concentration in the shallow silicon mixed crystal layer that is relatively thin and close to the channel formation region is useful for improving the transistor performance.
  • the impurity constituting the extension impurity region and the source / drain impurity region is preferably at least one of boron and indium.
  • the above impurities can be given as examples of impurities used when forming a P-channel transistor.
  • the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are N-type, and the lattice constant of the shallow silicon mixed crystal layer and the lattice constant of the deep silicon mixed crystal layer are both from the lattice constant of the semiconductor substrate. Is preferably small.
  • a tensile stress can be applied in the gate length direction to the channel formation region of the N-channel transistor, and the performance of the transistor can be improved.
  • the lattice constant of the shallow silicon mixed crystal layer is preferably smaller than the lattice constant of the deep silicon mixed crystal layer.
  • the silicon mixed crystal layer is difficult to increase in thickness as the difference in lattice constant with the semiconductor substrate increases. Therefore, it is possible to reduce the lattice constant of the shallow silicon mixed crystal layer that is relatively thin and close to the channel formation region. This is useful for improving the performance.
  • the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are N-type, and it is preferable that both the shallow silicon mixed crystal layer and the deep silicon mixed crystal layer are made of silicon carbon.
  • a tensile stress can be applied in the gate length direction to the channel formation region of the N-channel transistor, and the performance of the transistor can be improved.
  • the carbon concentration in the shallow silicon mixed crystal layer is preferably higher than the carbon concentration in the deep silicon mixed crystal layer.
  • the impurity constituting the extension impurity region and the source / drain impurity region is preferably at least one of arsenic and phosphorus.
  • the above impurities can be given as examples of impurities used for forming an N-channel transistor.
  • a side wall spacer that covers the side wall of the gate electrode is further provided, and a portion of the silicon mixed crystal layer that is not covered with the side wall spacer is formed to a position higher than the lower surface of the gate insulating film. preferable.
  • a silicide layer is formed on the silicon mixed crystal layer formed up to a position higher than the lower surface of the gate insulating film.
  • the resistance can be reduced by forming the silicide layer, and the silicide layer is formed in the silicon mixed crystal layer in the part higher than the lower surface of the gate insulating film, thereby suppressing the silicidation from proceeding to the extension region. can do.
  • the step (a) of forming an offset sidewall covering the side wall of the gate electrode after forming the gate electrode on the semiconductor substrate, and both sides of the gate electrode The step (b) of forming a shallow recess in the semiconductor substrate, the step (c) of forming a shallow silicon mixed crystal layer having a lattice constant different from that of the semiconductor substrate in the shallow recess, a gate electrode, Using the offset sidewall as a mask, a step (d) of introducing an impurity for forming an extension region into the semiconductor substrate, and a step of forming a sidewall spacer so as to cover the sidewall of the offset sidewall after the step (d) ( e) and a deep recess deeper than the shallow recess in the semiconductor substrate and the shallow silicon mixed crystal layer on the side of the sidewall spacer.
  • Step (f) forming a deep silicon mixed crystal layer having a lattice constant different from that of the semiconductor substrate in the deep recess, and using the gate electrode, the offset sidewall and the sidewall spacer as a mask And (h) introducing an impurity for forming source / drain regions into the semiconductor substrate.
  • the semiconductor device of the present disclosure that is, formed to a position shallower than the deep silicon mixed crystal layer that is a part of the source / drain region and close to the gate electrode, and a part of the extension region
  • a semiconductor device having the shallow silicon mixed crystal layer can be manufactured.
  • the effects of such a semiconductor device are as already described.
  • the deep silicon mixed crystal layer is arranged outside the shallow silicon mixed crystal layer.
  • a step (a) of forming a gate electrode on a semiconductor substrate and a step of introducing an impurity for forming an extension region into the semiconductor substrate using the gate electrode as a mask After (b) and step (b), a first sidewall spacer that covers the side wall of the gate electrode is formed, and then a stacked sidewall spacer that includes a second sidewall spacer that covers the side surface of the first sidewall spacer is formed.
  • step (E) forming a deep recess in the semiconductor substrate, and in the deep recess, A step (f) of forming a deep silicon mixed crystal layer having a lattice constant different from that of the body substrate, a step (g) of removing the second sidewall spacer after the step (f), and a step (g) Later, on the side of the first sidewall spacer, a step (h) of forming a shallow recess shallower than the deep recess in the semiconductor substrate and the deep silicon mixed crystal layer, and in the shallow recess, the semiconductor substrate and Comprises a step (i) of forming a shallow silicon mixed crystal layer having a different lattice constant.
  • the semiconductor device of the present disclosure can also be manufactured by doing so.
  • the shallow silicon mixed crystal layer is stacked on the deep silicon mixed crystal layer and is formed to a position closer to the gate electrode than the deep silicon mixed crystal layer. It becomes the composition which was done.
  • a high-performance transistor with high carrier mobility can be realized while suppressing increase in leakage current and deterioration of short channel characteristics.
  • FIG. 1 is a diagram illustrating a cross section of an exemplary semiconductor device according to the first embodiment.
  • 2A to 2F are cross-sectional views showing respective steps in the exemplary semiconductor device manufacturing method according to the first embodiment.
  • 3A to 3D are cross-sectional views illustrating each step of the manufacturing method for the exemplary semiconductor device according to the first embodiment, following FIG. 2F.
  • FIG. 4 is a diagram illustrating a cross section of an exemplary semiconductor device according to the second embodiment.
  • FIGS. 5A to 5F are cross-sectional views illustrating respective steps in the exemplary semiconductor device manufacturing method according to the second embodiment.
  • 6A to 6E are cross-sectional views illustrating respective steps of the manufacturing method for the exemplary semiconductor device according to the second embodiment, following FIG. 5F.
  • FIG. 7 is a cross-sectional view of a conventional semiconductor device.
  • a semiconductor device 150 including a P-channel FET is formed using a semiconductor substrate 100 as shown in FIG.
  • An N-type well region 110 is formed on the semiconductor substrate 100, and a gate electrode 102 is formed thereon via a gate insulating film 101.
  • the gate insulating film 101 may be made of, for example, a silicon oxynitride film, and the gate electrode 102 may be made of, for example, polysilicon.
  • an element isolation region is formed in the semiconductor substrate 100, and a gate insulating film 101 and a gate electrode 102 are formed on a well region 110 surrounded by the element isolation region. Yes.
  • An offset side wall 103 made of a silicon oxide film or the like is formed so as to cover the side wall of the gate electrode 102, and a side wall spacer 104 made of a silicon nitride film is further formed on the side wall of the offset side wall 103.
  • a P-type deep silicon mixed crystal layer 108 is embedded in the well region 110 outside the sidewall spacer 104 as viewed from the gate electrode 102. Further, a P-type source / drain impurity region 107 is formed at least between the deep silicon mixed crystal layer 108 and the well region 110. This configuration can also be considered that the deep silicon mixed crystal layer 108 is embedded in the source / drain impurity region 107 formed in the well region 110.
  • the source / drain impurity region 107 and the deep silicon mixed crystal layer 108 as described above function as a source / drain region in the P-channel FET formed in the semiconductor device 150.
  • a P-type shallow silicon mixed crystal layer 106 which is shallower than the deep silicon mixed crystal layer 108, is buried in the well region 110. It is.
  • the shallow silicon mixed crystal layer 106 is located below the sidewall spacer 104.
  • a P-type extension impurity region 105 is formed at least between the shallow silicon mixed crystal layer and the well region 110. This configuration can also be considered that the shallow silicon mixed crystal layer 106 is embedded in the extension impurity region 105 formed in the well region 110.
  • the extension impurity region 105 and the shallow silicon mixed crystal layer 106 as described above function as an extension region in the P-channel FET formed in the semiconductor device 150.
  • the extension impurity region 105 is formed using boron as an impurity, and its junction depth is, for example, 20 nm.
  • the source / drain impurity region 107 is also formed using boron as an impurity, and its junction depth is 60 nm.
  • the shallow silicon mixed crystal layer 106 provided in the extension impurity region 105 is formed of silicon germanium having a germanium concentration of 25%, and the depth from the lower surface of the gate insulating film 101 is 15 nm.
  • the deep silicon mixed crystal layer 108 provided in the source / drain impurity region 107 is formed of silicon germanium having a germanium concentration of 25% and has a depth of 50 nm.
  • silicon germanium having a lattice constant larger than that of silicon constituting the well region 110 is embedded in the extension impurity region 105 in addition to the source / drain impurity region 107. This is one of the characteristics.
  • the gate length applied to the channel formation region The compressive stress in the direction can be improved.
  • the impurity profiles of the extension impurity region 105 and the source / drain impurity region 107 can be made the same as those in the background art, the deterioration of the short channel characteristics can be prevented or suppressed.
  • the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108 have a structure embedded in the extension impurity region 105 and the source / drain impurity region 107 in order. From this, it is possible to suppress an increase in leakage current that occurs when an interface between the silicon mixed crystal layer and the well region 110 exists.
  • the extension depth of the extension impurity region 105 and the source / drain impurity region 107 is set to 20 nm and 60 nm in this order, but is not limited thereto. It can be adjusted according to the shape of the transistor, particularly the gate size.
  • the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108 have a depth of 15 nm and 50 nm in this order, but the depth is not limited thereto.
  • the extension impurity region 105 and the source / drain impurity region 107 are preferably formed in order, and in particular, in order to effectively suppress an increase in leakage current, respectively, from the junction depth of the corresponding impurity region. Also, it is desirable that the film be formed to be shallower than 5 nm.
  • boron is taken as an example of the impurities forming the extension impurity region 105 and the source / drain impurity region 107, but indium may be used instead, and both boron and indium may be used.
  • the germanium concentration is the same (25%) for the silicon germanium used for the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108, this is not essential. Thickening by deposition of silicon germanium is more difficult as the concentration of germanium is higher. In view of this, the germanium concentration of the shallow silicon mixed crystal layer 106 is higher than that of the deep silicon mixed crystal layer 108 and silicon germanium capable of applying a large stress to the channel formation region is used, thereby improving the performance of the transistor. It can be realized more reliably. As specific examples of the germanium concentration, the shallow silicon mixed crystal layer 106 is in the range of 10% to 60%, and the deep silicon mixed crystal layer 108 is in the range of 10% to 40%.
  • the gate insulating film 101 is formed of a silicon oxynitride film
  • the gate electrode 102 is formed of polysilicon
  • the offset sidewall 103 is formed of a silicon oxide film
  • the sidewall spacer 104 is formed of a silicon nitride film.
  • the gate insulating film 101 may have a structure in which a high dielectric constant insulating film (for example, an insulating film made of a material containing hafnium oxide) is stacked on a base film made of a silicon oxide film.
  • the gate electrode 102 may have a structure in which a polysilicon gate is stacked on a metal gate.
  • What is important as a feature of the semiconductor device 150 of this embodiment is a configuration in which the shallow silicon mixed crystal layer 106 is embedded in the extension impurity region 105 and the deep silicon mixed crystal layer 108 is embedded in the source / drain impurity region 107.
  • the offset sidewall 103 and the sidewall spacer 104 are not essential in the completed semiconductor device 150.
  • the silicide layer 109 on the deep silicon mixed crystal layer 108 is positioned above the bottom surface of the sidewall spacer 104, the silicide layer 109 is silicided to the shallow silicon mixed crystal layer 106 and the channel formation region is formed. Since it can suppress affecting the stress to apply, it is desirable.
  • cobalt, titanium, or the like can be used in addition to the exemplified nickel.
  • the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108 are formed using a material having a lattice constant smaller than that of the semiconductor substrate 100 instead of silicon germanium.
  • silicon carbon may be used.
  • an impurity for forming the extension impurity region 105 and the source / drain impurity region 107 at least one of arsenic and phosphorus may be used.
  • FIGS. 3A to 3D are cross-sectional views schematically showing these steps.
  • a P-channel FET is described as an example, an N-channel FET can be manufactured by a similar process.
  • the structure shown in FIG. 2A is formed using a general semiconductor manufacturing technique. That is, the N-type well region 110 is formed in the semiconductor substrate 100 by N-type impurity implantation or the like.
  • the well region 110 for example, a gate insulating film 101 having a thickness of 2 nm made of a silicon oxynitride film, a gate electrode 102 made of polysilicon having a thickness of 100 nm, and a protective film 111 made of a silicon oxide film having a thickness of 5 nm. They are stacked in this order from the bottom.
  • the gate length is, for example, 50 nm.
  • an offset sidewall 103 that covers the sidewall of the gate electrode 102 is formed.
  • a silicon oxide film having a thickness of 5 nm is formed on the well region 110, covering the sidewall of the gate electrode 102 and the protective film 111, and then etched back to leave the silicon oxide film on the sidewall of the gate electrode 102. This is the offset sidewall 103.
  • a shallow recess 112 having a depth of 15 nm is formed on the side of the gate electrode 102.
  • the well region 110 is etched by dry etching, for example, using the gate electrode 102 and the offset sidewall 103 as a mask.
  • a shallow silicon mixed crystal layer 106a is formed so as to fill the shallow recess 112.
  • silicon germanium having a germanium concentration of 25% is epitaxially grown on the shallow recess 112 formed by etching in the step of FIG. This growth is performed up to substantially the same position as the lower surface of the gate insulating film 101.
  • a CVD (Chemical Vapor Deposition) method is used for example.
  • monosilane (SiH 4 ) is used as the silicon source gas
  • monogermane (GeH 4 ) is used as the germanium source gas.
  • SiH 4 monosilane
  • GeH 4 monogermane
  • silicon germanium can be selectively grown only in a region where silicon is exposed, that is, in the shallow recess 112. Since doping of impurity ions is not performed, the shallow silicon mixed crystal layer 106a at this point is neither P-type nor N-type.
  • extension injection is performed as shown in FIG. That is, boron is ion-implanted into the well region 110 using the gate electrode 102 and the offset sidewall 103 as a mask.
  • the conditions at this time are, for example, an implantation energy of 0.5 keV and a dose of 5 ⁇ 10 14 / cm 2 .
  • the P-type region 105a is formed by such ion implantation, and the shallow silicon mixed crystal layer 106a becomes the P-type shallow silicon mixed crystal layer 106.
  • boron ions are present in the shallow silicon mixed crystal layer 106 mainly made of silicon germanium.
  • the shallow silicon mixed crystal layer 106 becomes P-type.
  • boron ions are diffused to the well region 110 which is a silicon region, and an extension impurity region 105 having a depth of 20 nm is formed.
  • the P-type region 105 a into which boron is implanted is shown to extend to the outside of the shallow silicon mixed crystal layer 106.
  • such illustration is for clarifying the positional relationship between the extension impurity region 105 finally formed and the shallow silicon mixed crystal layer 106 formed inside thereof.
  • the P-type region 105 a does not need to be formed outside the shallow silicon mixed crystal layer 106.
  • sidewall spacers 104 are formed.
  • a silicon nitride film of, eg, a 50 nm-thickness is deposited on the well region 110 including the gate electrode 102 and then etched back.
  • a sidewall spacer 104 having a width of 50 nm is formed on the sidewall of the offset sidewall 103.
  • a deep recess 113 having a depth of 50 nm is formed outside the sidewall spacer 104 as viewed from the gate electrode 102.
  • the well region 110 is etched by dry etching, for example, using the gate electrode 102, the sidewall spacer 104, etc. as a mask.
  • the shallow silicon mixed crystal layer 106 is also etched at the same time.
  • a deep silicon mixed crystal layer 108a is formed so as to fill the deep recess 113.
  • silicon germanium having a germanium concentration of 25% is epitaxially grown on the deep recess 113 formed by etching in the step of FIG. At this time, it may be grown to the same height as the bottom surface portion of the sidewall spacer 104, but in order to reduce the influence on the channel formation region of the silicide layer 109 described later, it is positioned higher than the bottom surface. It is preferable to form up to.
  • a CVD method is used for the epitaxial growth.
  • monosilane (SiH 4 ) is used as the silicon source gas
  • monogermane (GeH 4 ) is used as the germanium source gas.
  • SiH 4 monosilane
  • GeH 4 monogermane
  • silicon germanium can be selectively grown only in a region where silicon is exposed, that is, in the deep recess 113. Since impurity ions are not doped, the deep silicon mixed crystal layer 108a at this point is neither P-type nor N-type.
  • the protective film 111 made of a silicon oxide film on the gate electrode 102 is removed with hydrofluoric acid.
  • boron ions are implanted using the gate electrode 102, the offset sidewall 103, and the sidewall spacer 104 as a mask.
  • the conditions at this time are, for example, an implantation energy of 1.5 keV and a dose of 3 ⁇ 10 15 / cm 2 .
  • the impurities are activated, for example, by spike annealing at 1000 ° C. for 0 second.
  • the activation annealing activates the impurities implanted into the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108, respectively, and the extension impurity region 105 with a junction depth of 20 nm and the source / drain with a junction depth of 60 nm.
  • a drain impurity region 107 is formed.
  • the deep silicon mixed crystal layer 108 is P-type due to the impurity implantation. Note that impurities are also implanted into the gate electrode 102 in the step of FIG.
  • a silicide layer 109 is formed as shown in FIG.
  • NiPt having a film thickness of 6 nm is deposited so as to cover the deep silicon mixed crystal layer 108, the gate electrode 102, and the like.
  • a known method such as first annealing (280 ° C.), selective removal of unreacted NiPt by aqua regia, and second annealing (400 ° C.) is performed on the deep silicon mixed crystal layer 108 and A silicide layer 109 is formed on the gate electrode 102.
  • the substrate is etched and the silicon germanium is selectively grown before the extension implantation and the source / drain implantation, and the activation annealing is performed after the implantation.
  • the shallow silicon mixed crystal layer 106 that is a silicon germanium layer embedded in the extension impurity region 105. Can be manufactured.
  • a silicon cap layer may be formed on the deep silicon mixed crystal layer 108 in order to effectively perform the reaction between silicon and metal when the silicide layer 109 is formed.
  • the silicon germanium layer should be formed to a position higher than the bottom surface of the sidewall spacer 104.
  • the portion above the bottom portion does not need to be a silicon germanium layer.
  • silicon may be epitaxially grown instead of silicon germanium.
  • a silicon germanium layer having a germanium concentration of 25% is formed, but the concentration is not limited to this.
  • the germanium concentration is adjusted in the range of 10% to 60% for the shallow silicon mixed crystal layer 106a in FIG. 2 (d) and in the range of 10% to 40% for the deep silicon mixed crystal layer 108 in FIG. 3 (b). It is good to do.
  • the shallow silicon mixed crystal layer 106 has a higher germanium concentration than the deep silicon mixed crystal layer 108.
  • the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108 are both formed without doping, and are subsequently made P-type by ion implantation. However, it can also be made P-type by forming it while doping impurities.
  • a P-channel FET has been described above as an example.
  • an N-channel FET can be manufactured by a similar method, and high-speed and high-performance transistors can be realized while avoiding deterioration related to short channel characteristics and substrate leakage current.
  • a semiconductor material for example, silicon carbon
  • a lattice constant smaller than that of the semiconductor substrate 100 is used for the shallow silicon mixed crystal layer 106 and the deep silicon mixed crystal layer 108 in place of silicon germanium or the like.
  • a tensile stress in the gate length direction is applied to the channel formation region, so that the electron mobility is improved and the speed of the transistor can be increased.
  • the semiconductor device 151 including a P-channel FET has a configuration similar to that of the semiconductor device 150 of FIG. 1, as shown in FIG. Therefore, the same components are denoted by the same reference numerals as those in FIG.
  • the deep silicon mixed crystal layer 128 which is a silicon germanium layer embedded in the source / drain impurity region 107 and the shallow silicon formed to the gate electrode 102 side further than this.
  • a mixed crystal layer 126 Further, an extension impurity region 105 is provided at least between the shallow silicon mixed crystal layer 126 and the well region 110.
  • the deep silicon mixed crystal layer 108 is adjacent to the outside of the shallow silicon mixed crystal layer 106, whereas in the semiconductor device 151 of this embodiment, the deep silicon mixed crystal layer 108 is adjacent.
  • a shallow silicon mixed crystal layer 126 is stacked on the mixed crystal layer 128.
  • the first sidewall spacer 131 is formed in the semiconductor device 151 of the present embodiment. Further, in the semiconductor device 150, the sidewall spacer 104 is positioned on the shallow silicon mixed crystal layer 106, whereas in the semiconductor device 151 of the present embodiment, the first silicon mixed crystal layer 126 has the first The side wall spacer 131 is not located. As a result, the silicide layer 109 can be formed also on the silicon mixed crystal layer that functions as the extension region, and the effect of reducing the resistance by forming the silicide layer can be enhanced.
  • the dimensions and the like of each component can be the same as those in the first embodiment.
  • the first sidewall spacer 131 is made of, for example, a silicon nitride film, but is not limited thereto. Further, an offset sidewall may be interposed between the gate electrode 102 and the first sidewall spacer 131. Further, the first sidewall spacer 131 is not essential in the completed semiconductor device 151.
  • FIGS. 6A to 6E are cross-sectional views schematically showing these steps.
  • a P-channel FET is described as an example, an N-channel FET can be manufactured by a similar process.
  • the structure shown in FIG. 2A is formed using a general semiconductor manufacturing technique. That is, the N-type well region 110 is formed in the semiconductor substrate 100 by N-type impurity implantation or the like.
  • a gate insulating film 101 made of silicon oxynitride film having a thickness of 2 nm, a gate electrode 102 made of polysilicon having a thickness of 100 nm, and a silicon oxide film having a thickness of 5 nm for example, high-temperature low pressure CVD method
  • a protective film 111 made of HTO (High Temperature Oxide) film deposited by the above is laminated in this order from the bottom.
  • the gate length is, for example, 50 nm.
  • extension injection is performed as shown in FIG. Specifically, boron is ion-implanted into the well region 110 using the gate electrode 102 as a mask, and a P-type region 105 a is formed on the side of the gate electrode 102.
  • the implantation conditions are, for example, an implantation energy of 0.5 keV and a dose amount of 5 ⁇ 10 14 / cm 2 .
  • the P-type region 105a becomes the extension impurity region 105 by annealing in a later process.
  • a side wall spacer having a laminated structure is formed.
  • a silicon nitride film having a thickness of 10 nm is deposited on the well region 110 so as to cover the sidewall of the gate electrode 102 and the like.
  • the silicon nitride film is etched back to form a first sidewall spacer 131 having a width of 10 nm that covers the sidewall of the gate electrode 102.
  • a silicon oxide film having a thickness of 50 nm is formed so as to cover the side wall of the first sidewall spacer 131, and this is etched back to form a second sidewall spacer 132 having a width of 50 nm.
  • the first and second sidewall spacers may be collectively referred to as a laminated sidewall spacer 133.
  • the second sidewall spacer 132 since the second sidewall spacer 132 needs to be removed in a later step, it is formed so as to be easily removed.
  • a plasma oxide film deposited at a low temperature of about 250 ° C. is preferable as the second sidewall spacer 132 because the etching rate for hydrofluoric acid is about several tens of times higher than that of an HTO film.
  • boron ions are implanted using the gate electrode 102 and the stacked sidewall spacer 133 as a mask, and then activation annealing is performed.
  • a source / drain impurity region 107 having a junction depth of 60 nm is formed in the well region 110 on the side of the laminated sidewall spacer 133.
  • the impurities in the P-type region 105a are also activated, and the extension impurity region 105 having a junction depth of 20 nm is formed.
  • the boron ion implantation conditions are, for example, an implantation energy of 1.5 keV and a dose of 3 ⁇ 10 15 / cm 2 .
  • the activation annealing conditions are, for example, spike annealing at 1000 ° C. and 0 seconds.
  • dry etching is performed using the laminated sidewall spacer 133 and the gate electrode 102 as a mask to form a deep recess 134 having a depth of 50 nm on the side of the laminated sidewall spacer 133. To do.
  • a deep silicon mixed crystal layer 128 is formed by epitaxially growing silicon germanium having a germanium concentration of 25% so as to fill in the deep recess 134 formed by etching.
  • a CVD method is used for the epitaxial growth.
  • monosilane (SiH 4 ) is used as the silicon source gas
  • monogermane (GeH 4 ) is used as the germanium source gas.
  • SiH 4 monosilane
  • GeH 4 monogermane
  • silicon germanium can be selectively grown only in a region where silicon is exposed, that is, in the deep recess 134.
  • the surface of the deep silicon mixed crystal layer 128 be as high as the bottom surface of the stacked sidewall spacer 133.
  • a dopant of a P-type impurity such as diborane (B 2 H 6 ) during the growth of silicon germanium.
  • the second sidewall spacer 132 of the laminated sidewall spacer 133 is removed.
  • the silicon oxide film constituting the second sidewall spacer 132 has an extremely high etching rate for hydrofluoric acid as compared with the HTO film. Therefore, the second sidewall spacer 132 can be removed while suppressing the protective film 111 made of the silicon oxide film on the gate electrode 102 from being etched.
  • a shallow recess 135 is formed by etching. That is, dry etching is performed using the first sidewall spacer 131, the gate electrode 102, etc. as a mask, and a shallow recess 135 having a depth of about 15 nm is formed on the side of the first sidewall spacer 131.
  • a part of the deep silicon mixed crystal layer 128 made of silicon germanium is also removed by etching.
  • a shallow silicon mixed crystal layer 126 is formed by epitaxially growing silicon germanium having a germanium concentration of 25% so as to fill the shallow recess 135 formed by etching.
  • a CVD method is used for the epitaxial growth.
  • monosilane (SiH 4 ) is used as the silicon source gas
  • monogermane (GeH 4 ) is used as the germanium source gas.
  • SiH 4 monosilane
  • GeH 4 monogermane
  • these mixed gases are deposited under a hydrogen atmosphere or a nitrogen atmosphere at 650 ° C.
  • silicon germanium can be selectively grown only in a region where silicon and silicon germanium are exposed, that is, only in the shallow recess 135. it can.
  • a dopant of a P-type impurity such as diborane (B 2 H 6 ) during the growth of silicon germanium.
  • the protective film 111 on the gate electrode 102 is removed with hydrofluoric acid.
  • the etching rate is lower than that of the plasma oxide film deposited at a low temperature, the HTO film can also be removed with hydrofluoric acid.
  • a silicide layer 109 is formed.
  • NiPt having a film thickness of 6 nm is deposited so as to cover the shallow silicon mixed crystal layer 126, the gate electrode 102, and the like.
  • a known method such as first annealing (280 ° C.), selective removal of unreacted NiPt by aqua regia, and second annealing (400 ° C.) is performed on the shallow silicon mixed crystal layer 126 and A silicide layer 109 is formed on the gate electrode 102.
  • the stacked sidewall spacer 133 is used, and silicon germanium is embedded in the extension impurity region 105 and the source / drain impurity region 107 after the activation annealing.
  • a silicon germanium layer is formed as the shallow silicon mixed crystal layer 126 up to a position higher than the bottom surface of the first sidewall spacer 131.
  • the region above the bottom surface of the first sidewall spacer 131 does not need to be silicon germanium because it has little influence on the application of stress to the channel formation region.
  • a silicon cap layer may be formed in this region by epitaxially growing silicon.
  • a silicon germanium layer having a germanium concentration of 25% is formed.
  • the concentration is not limited to this.
  • the germanium concentration is adjusted in the range of 10% to 40% for the deep silicon mixed crystal layer 128 in FIG. 5 (f) and in the range of 10% to 60% for the shallow silicon mixed crystal layer 126 in FIG. 6 (c). It is good to do. Further, it is preferable that the shallow silicon mixed crystal layer 126 has a higher germanium concentration than the deep silicon mixed crystal layer 128.
  • the shallow silicon mixed crystal layer 126 and the deep silicon mixed crystal layer 128 are formed of a semiconductor material having a lattice constant smaller than that of the semiconductor substrate 100 such as silicon carbon.
  • phosphine (PH 3 ), arsine (ArH 3 ), and the like can be given as dopants for N-type impurities.
  • the semiconductor device of the present disclosure it is possible to increase the speed of the transistor while suppressing deterioration of the short channel characteristic, and it is useful also in a semiconductor device that has been miniaturized.

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Abstract

La présente invention a trait à un dispositif à semi-conducteurs (150) comprenant : un substrat semi-conducteur (100) ; une électrode de grille (102) formée sur ledit substrat semi-conducteur (100), un film d'isolation de grille (101) étant interposé entre eux ; et des couches de cristaux mixtes en silicium (106, 108) qui sont enfouies dans le substrat semi-conducteur (100) sur les deux côtés de l'électrode de grille (102) et qui présentent une constante du réseau cristallin différente de celle du substrat semi-conducteur (100). Les couches de cristaux mixtes en silicium se composent d'une couche mince de cristaux mixtes en silicium (106) et d'une couche épaisse de cristaux mixtes en silicium (108) disposée plus profondément dans le substrat semi-conducteur (100) que la couche mince de cristaux mixtes en silicium (106). Ladite couche mince de cristaux mixtes en silicium (106) se trouve plus près de l'électrode de grille (102) que ne l'est la couche épaisse de cristaux mixtes en silicium (108).
PCT/JP2010/002717 2009-10-26 2010-04-14 Dispositif à semi-conducteurs et son procédé de fabrication WO2011052108A1 (fr)

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US9412842B2 (en) 2013-07-03 2016-08-09 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device

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JP2006303501A (ja) * 2005-04-18 2006-11-02 Toshiba Corp ＰＦＥＴの移動度を強化したステップ埋め込みＳｉＧｅ構造
JP2008078347A (ja) * 2006-09-21 2008-04-03 Sony Corp 半導体装置の製造方法および半導体装置
JP2009182109A (ja) * 2008-01-30 2009-08-13 Toshiba Corp 半導体装置

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JP2006303501A (ja) * 2005-04-18 2006-11-02 Toshiba Corp ＰＦＥＴの移動度を強化したステップ埋め込みＳｉＧｅ構造
JP2008078347A (ja) * 2006-09-21 2008-04-03 Sony Corp 半導体装置の製造方法および半導体装置
JP2009182109A (ja) * 2008-01-30 2009-08-13 Toshiba Corp 半導体装置

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Publication number Priority date Publication date Assignee Title
CN106298526A (zh) * 2015-06-01 2017-01-04 中芯国际集成电路制造(上海)有限公司 准绝缘体上硅场效应晶体管器件的制作方法

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