WO2011048726A1

WO2011048726A1 - Solid state image capture element, solid state image capture device and method of driving solid state image capture element, and camera device

Info

Publication number: WO2011048726A1
Application number: PCT/JP2010/004223
Authority: WO
Inventors: 羽原紀史; 三宅智治; 山田哲生; 松尾卓也; 徳本順士
Original assignee: パナソニック株式会社
Priority date: 2009-10-21
Filing date: 2010-06-25
Publication date: 2011-04-28
Also published as: JP2011091562A

Abstract

Disclosed is a solid state image capture element (100), having a plurality of vertical driving electrodes (16), wherein each respective vertical driving electrode (16) is isolated from the vertical driving electrodes (16) in adjacent columns and rows, and is formed upon a VCCD (12) that is adjacent to each respective photodiode (11), a horizontal wiring part (15), which is disposed upon each row of the photodiodes (11), comprises a first and a second wiring part (13, 14) that are arranged horizontally, and each column of the vertical driving electrodes (16) has a first structure electrode column (161) and a second structure electrode column (162), which are connected to either the first or the second wiring part (13, 14) via a contact (17), wherein the pattern of the connections thereof differs therebetween.

Description

Solid-state imaging device, solid-state imaging device, driving method of solid-state imaging device, and camera device

The present invention relates to a solid-state imaging device for area imaging in which photoelectric conversion elements are arranged in a matrix, a driving method thereof, a solid-state imaging device, and a camera device equipped with the solid-state imaging device.

2. Description of the Related Art Area imaging solid-state imaging devices (hereinafter simply referred to as “solid-state imaging devices”) using CCDs (Charge Coupled Devices) are often used as imaging devices for camera devices such as digital still cameras and digital video cameras.

FIG. 50 is a schematic plan view showing a general configuration of a conventional solid-state imaging device 500.

As shown in the figure, the solid-state imaging device 500 includes a plurality of photodiodes 511, a plurality of vertical transfer units (hereinafter referred to as “VCCD”) 512, and a single horizontal transfer unit (hereinafter referred to as “HCCD”). ) 530 and an output portion 540 are formed on a semiconductor substrate.

The photodiodes 511 are arranged in a matrix to form the imaging unit 510. Each photodiode 511 constitutes a unit pixel having a photoelectric conversion function and a charge accumulation function, and accumulates signal charges corresponding to the amount of received light.

The VCCD 512 is arranged along each column of the photodiodes 511, and transfers the signal charges read from the individual photodiodes 511 in one direction in the vertical direction (in the direction of arrow v in the figure).

The HCCD 530 is provided in the horizontal direction adjacent to the final transfer stage of the VCCD 512, and transfers the signal charges transferred by each VCCD 512 in the horizontal direction (arrow h direction).

The output unit 540 converts the signal charge transferred by the HCCD 530 into a voltage and outputs it as a pixel signal, and includes a floating diffusion (FD) unit and an amplifier.

Although not shown, a Bayer-arranged RGB color filter is disposed above the light receiving surface of each photodiode 511 in the imaging unit 510, and the portion other than the light receiving surface is covered with a light shielding film. Incidence of light to regions other than the light receiving surface is blocked.

In such a solid-state imaging device 500, both the still image mode and the moving image mode are switched and used.

When imaging in still image mode, it is not necessary to read out signal charges from all pixels of the imaging unit 510 in an interlaced manner and reduce the number of output pixels. However, when imaging in moving image mode, a certain frame or more is required. In order to secure the rate (30 fps (frame / second) or 60 fps), the number of output pixel signals is reduced (hereinafter referred to as “output pixel reduction processing”).

For example, Patent Document 1 discloses a solid-state imaging device having an imaging unit 510 as shown in FIG.

As shown in the figure, this solid-state imaging device has three drive electrodes (first electrode 521, second electrode 522A (522A ′, 522B, 522B ′) (one hatched line in the figure) for one pixel in the VCCD 512. In the following description, the electrodes are collectively referred to as “second electrode group 522”.) And a third electrode 523) is disposed.

Among these, the second electrode group 522 also serves as an electrode (reading electrode) for transferring the signal charge accumulated in each photodiode 511 to the adjacent VCCD 512, and a drive pulse can be applied independently. It is configured as follows.

In the second electrode group 522, the

second electrodes

522A and 522A ′ are in charge of reading the odd columns, and the second electrodes 522B and 422B ′ are in charge of reading the even columns. It is bridge-connected by a wiring 524 to another readout electrode separated by one pixel in the direction.

Therefore, if a read voltage (read voltage) is applied to all of the second electrode group 522, the signal charges of all the pixels can be read, and the read voltage is applied only to some of the second electrodes. Only the signal charges of the pixels adjacent to the corresponding electrode are read out, and the output pixel reduction process is performed.

According to this configuration, for example, if a read voltage is applied only to the second electrode 522A, only the signal charge of the photodiode 511 marked with a double circle (◎) in the figure is read, and the number of output pixels is 4 It can be reduced by a factor.

JP 2000-152093 A

However, according to the configuration shown in Patent Document 1, the output pixel reduction rate is only a quarter, and it is difficult to obtain a further high reduction rate.

That is, in the above prior art, if it is intended to improve the output pixel reduction rate, it is necessary to increase the number of second drive electrodes that can be driven independently to increase the number of vertical drive phases, but with the increase in the number of vertical drive phases, it is necessary to move away in the vertical direction. It is necessary to increase the number of wirings to be bridge-connected to the pixels.

For example, in the example of FIG. 51, two bridge connection wirings are arranged in parallel in a vertical four-pixel period, but if the output pixel reduction rate is to be reduced to one third in the vertical direction, the vertical direction Therefore, it is necessary to perform bridge connection with pixels separated by three pixels for each column, and accordingly, three bridge connection wirings must be arranged in parallel within a vertical nine-pixel period. Further, in order to improve the output pixel reduction rate, the number of bridge connection wirings in the vertical direction on the VCCD must be four or more.

If the number of pixels is increased, the distance between the pixels becomes smaller (for example, about 1.5 μm), and it is practically difficult to arrange a large number of bridge connection wirings on the VCCD of such fine pixels. is there.

SUMMARY OF THE INVENTION The present invention solves the above-described problem. A solid-state imaging device capable of easily improving the output pixel reduction rate even when the number of pixels is increased, a driving method thereof, a solid-state imaging device, and a camera using the solid-state imaging device An object is to provide an apparatus.

In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device in which a plurality of photoelectric conversion elements are arranged in a matrix, and is arranged along each row of photoelectric conversion elements. By applying a plurality of drive pulses to the plurality of vertical drive electrodes, a plurality of vertical transfer units for reading out signal charges of the photoelectric conversion elements and transferring them in the vertical direction, and a plurality of arranged along each row of the photoelectric conversion elements And a horizontal transfer unit that transfers signal charges transferred from the plurality of vertical transfer units in the horizontal direction, and the vertical drive electrodes are individually provided corresponding to the individual photoelectric conversion elements. The horizontal wiring parts include first and second wirings extending in the horizontal direction, and the vertical driving electrodes are arranged in the same row as the vertical driving electrodes. Selective to one of the wiring When a vertical drive electrode group for one column connected to the first or second wiring of each horizontal wiring portion is defined as a structural electrode column, a predetermined first structural electrode column, One structure electrode column is characterized in that second structure electrode columns having different connection states with the first and second wirings of the horizontal wiring portion in each row are arranged in combination in the horizontal direction.

According to this configuration, the horizontal wiring portion is arranged along each row of the photoelectric conversion elements, and the plurality of drive electrodes arranged in the same row direction are connected to either the first wiring or the second wiring of the horizontal wiring portion. Since the first structure electrode row and the second structure electrode row are configured and these structure electrode rows are combined and arranged in the horizontal direction, different driving is performed for some of the drive electrodes arranged in the same row. A pulse can be applied. Accordingly, it is possible to perform horizontal thinning-out reading according to whether or not a read pulse is applied with respect to reading of signal charges of pixels having the same vertical address in the first structure electrode row and the second structure electrode row. In addition, since driving pulses can be applied independently to the first and second wirings in the horizontal wiring portion of each row, it is not necessary to arrange many bridge connection wirings on the VCCD in parallel, and vertical transfer is possible. The number of drive phases in the part can be easily increased. As a result, the degree of freedom of the combination of pixels for reading signal charges is increased, and the output pixel reduction rate is significantly improved. In addition, since it is not necessary to provide wiring for connecting the drive electrodes separated in the vertical direction to each other, it is possible to sufficiently cope with pixel miniaturization by increasing the number of pixels.

Further, the solid-state imaging device according to the present invention is configured in the horizontal direction with a structural electrode array group in which the first structural electrode array and the second structural electrode array are combined to be a total of P arrays (P ≧ 3) as an arrangement unit. It is characterized by being repeatedly arranged.

This configuration allows the number of output columns after horizontal thinning to be 1 / P of the number of horizontal pixels.

Furthermore, the solid-state imaging device according to the present invention is characterized in that the number of vertical drive phases of the first structure electrode array is different from the number of vertical drive phases of the second structure electrode array.

With this configuration, in addition to the effect of realizing horizontal thinning readout, two types of readout with different vertical thinning rates are performed in each of the first structure electrode row and the second structure electrode row, and the signal output of one structure electrode row is output. By adopting, multiple types of vertical thinning for different purposes can be set freely.

Furthermore, in the solid-state imaging device according to the present invention, the horizontal transfer unit is connected to each vertical transfer unit via the selection output unit, and the signal of the vertical transfer unit of the column selected by the selection output unit The charge is transferred to the horizontal transfer unit at a predetermined timing.

In this way, by controlling the timing of charge transfer from each vertical transfer unit to the horizontal transfer unit by the selection output unit, the signal charges in the plurality of vertical transfer units are stored in the same signal storage area of the horizontal transfer unit. Therefore, horizontal addition can be performed easily.

The selection output unit includes a first sub-selection output unit, a second sub-selection output unit, and a third sub-selection output unit to which drive pulses are applied independently, and the first, second, and third sub-selection output units. The selection output unit may be disposed between each vertical transfer unit and horizontal transfer unit.

Thereby, the timing of charge transfer from each vertical transfer unit to the horizontal transfer unit is determined by the drive pulse applied to each sub-selection output unit.

Further, in the solid-state imaging device according to the present invention, the horizontal transfer unit is arranged at a first sub-horizontal transfer unit arranged at one end of the vertical transfer unit and at the other end of the vertical transfer unit. The signal charge transferred from the first structure electrode array is transferred to the first horizontal transfer section, and the signal charge transferred from the second structure electrode array is transferred to the second horizontal transfer section. The signal charge transfer directions of the first and second structure electrode arrays are opposite to each other.

Thereby, since the horizontal transfer unit transferred for each of the first structure electrode row and the second structure electrode row is different, a different number of drive phases is set for each structure electrode row and simultaneously output to the corresponding horizontal transfer unit. Is possible. In addition, since two horizontal transfer units are provided, output can be made faster than processing by one horizontal transfer unit.

Furthermore, in the solid-state imaging device according to the present invention, the first sub-horizontal transfer unit is connected to a vertical transfer unit in which the first structure electrode array is arranged via a first selection output unit, and the second sub-horizontal transfer is performed. Is connected to the vertical transfer unit in which the second structure electrode column is arranged via the second selection output unit, and the signal charge of the vertical transfer unit of the column selected by the first and second selection output units is , The data is transferred to the corresponding first and second horizontal transfer units at a predetermined timing.

With this configuration, a plurality of vertical transfers are performed by controlling the timing at which the signal charges vertically transferred by the first and second structure electrode arrays are transferred to the first and second horizontal transfer units by the first and second selection output units. Since the signal charges in the unit can be stored in the same signal storage area of the corresponding first and second horizontal transfer units, horizontal addition can be easily performed.

Here, each of the first and second selection output units includes a first sub-selection output unit, a second sub-selection output unit, and a third sub-selection output unit to which drive pulses are applied independently, The first, second, and third sub-selection output units are respectively disposed between each vertical transfer unit and the first or second horizontal transfer unit that is the transfer destination.

Thereby, the timing of charge transfer from each vertical transfer unit to the first and second horizontal transfer units can be determined by the drive pulse applied to each sub-selection output unit.

In addition, the first selection output unit includes first and second sub selection output units, and the second selection output unit includes a third sub selection output unit, and the first and second sub selection output units. The driving pulses are independently applied to the second and third sub-selection output units, and each of the first and second sub-selection output units includes a vertical transfer unit and a first sub-horizontal transfer unit in which the first structure electrode array is arranged. The third sub-selection output unit may be disposed between the vertical transfer unit and the second sub-horizontal transfer unit in which the second structure electrode array is arranged.

With this configuration, since there is no common sub-selection output unit for transferring to the first and second horizontal transfer units, the signal charge of the pixel is read out by one of the first and second structure electrode columns, and the other Even when the non-signal readout column is used as the structure electrode column, the sub-selection output unit of the non-signal readout column can be kept out of operation, and the charge of the non-signal readout column that becomes a noise component is mixed into the output signal. Get the effect to prevent.

Furthermore, the solid-state imaging device according to the present invention is characterized in that a charge discharging unit to which a predetermined DC bias is applied is connected to an end of the vertical transfer unit on the side where the horizontal transfer unit is not connected.

With this configuration, it is possible to prevent the charge remaining in the non-readout column from being discarded in the charge discharging unit and to mix noise into the output signal.

Furthermore, a solid-state imaging device according to the present invention includes the above-described solid-state imaging device, a first drive pulse for driving the first structure electrode row of the solid-state imaging device, and a second drive for driving the second structure electrode row. Drive means for generating drive pulses and applying the drive pulses to the first and second structured electrode arrays, respectively.

Accordingly, different drive pulses are applied to the first structure electrode array and the second structure electrode array, and for example, only the signal charges of the photoelectric conversion element array corresponding to the first structure electrode array can be read out. Thinning can be performed easily. Further, vertical thinning can be easily performed by increasing the number of vertical drives in each column.

In the solid-state imaging device according to the present invention, when the driving unit drives either one of the first or second structure electrode rows and reads the signal charges from the corresponding photoelectric conversion element rows and vertically transfers them. The vertical transfer operation in the other structure electrode row that does not read out the signal charge is stopped, or the vertical transfer operation is executed in the direction opposite to the direction in which the signal charge is read out and transferred vertically. The drive pulse is generated.

This makes it possible to suppress unnecessary power consumption when the charge generated as a noise component in the non-read column is small, and to discharge the charge from the non-signal read column in the reverse direction when there is a large amount of charge, which is mixed into the output signal. Can be prevented.

In the solid-state imaging device according to the present invention, the driving unit drives the first structure electrode array in the first mode, drives the second structure electrode array in the second mode, and performs these modes. The first and second drive pulses are generated so as to be executed in parallel.

This makes it possible to simultaneously output imaging signals in two different drive modes.

Further, in the solid-state imaging device according to the present invention, the frame rate of the first mode in which the driving unit drives the first structure electrode row is K of the frame rate of the second mode in which the second structure electrode row is driven. The first and second drive pulses are generated so as to be double (K is an integer of 2 or more).

Thus, when two types of drive modes having different frame rates are executed in parallel, it is possible to facilitate the application pattern of drive pulses for reading of each drive mode and signal charge transfer.

Further, in the solid-state imaging device according to the present invention, the driving unit is configured so that the horizontal line output period of one mode of the first mode and the second mode is followed by the horizontal line output period of the other mode. The first and second drive pulses are generated.

Thus, even if the horizontal transfer unit has one channel, two types of drive modes can be driven in parallel.

In the solid-state imaging device according to the present invention, when the driving unit has a smaller pixel addition number in the first mode than the pixel addition number in the second mode, the signal charge in the first mode is The substrate potential of the solid-state imaging device at the time of reading is set to be the first potential, and the substrate potential of the solid-state imaging device at the time of reading the signal charge in the second mode is higher than the first potential. The substrate potential is set so that the substrate potential is maintained at a third potential that is equal to or lower than the first potential and the second potential during the exposure time by the photoelectric conversion element. It is characterized by controlling.

This makes it possible to set an optimum saturation capacity for both pixels to be read even when the two types of drive modes are driven simultaneously, even if the number of pixel additions differs between the two modes.

In the solid-state imaging device according to the present invention, the driving unit reads out the signal charges of the pixels in the Mth row of the (N−2) th column and the (N + 2) th column by the first structure electrode column, The signal charges of the pixels in the (M-2) th and (M + 2) th rows of the eye are read out by the second structure electrode column and vertically added, and the (N-2) th, Nth, and (N + 2) th columns are added. The first and second drive pulses are generated so that the signal charges of the columns are horizontally added to perform addition output for four pixels (N and M are integers of 3 or more).

Further, in the solid-state imaging device according to the present invention, the driving unit may obtain the signal charges of the pixels in the (M−2) th and (M + 2) th rows of the (N−2) th column and the (N + 2) th column. Read out by the first structure electrode column and vertically add, and read out signal charges of the pixels in the Mth row of the Nth column to the second structure electrode column, and read the (N−2) th, Nth and (N + 2) th columns. ) The first and second drive pulses are generated so that the signal charges in the columns are horizontally added and an addition output for five pixels is performed (N and M are integers of 3 or more).

This makes it possible to set complex addition target pixels in addition to the effect of horizontal thinning readout output.

In the solid-state imaging device according to the present invention, after the driving unit reads out the signal charges of the pixels in the Mth column of the Nth row by setting the substrate potential of the solid-state imaging device to the first potential, The substrate potential is set to a second potential higher than the first potential, and the (M−2) -th and (M + 2) -th rows of pixels in the (N−2) th column and the (N + 2) th column are set. After reading each signal charge, the substrate potential is reset to the first potential, and the signal charges in the (N−2) th, Nth, and (N + 2) th columns are horizontally added and output for exposure. During the time, the substrate potential is maintained at a third potential equal to or lower than the first potential.

Thereby, in addition to the effect of the horizontal thinning readout output, it is possible to set a complicated pixel to be added, and to output a pixel addition image in which saturation weighting is performed on the pixel located at the pixel centroid after the addition. .

Further, the present invention may be a camera device equipped with the solid-state imaging device.

It is a schematic plan view which shows the structure of the solid-state image sensor which concerns on Embodiment 1 of this invention. It is a top view which shows the pixel structure in the imaging part of the said solid-state image sensor. (A) and (b) are schematic diagrams for explaining the connection state between each drive electrode, the first wiring, and the second wiring in the AA ′ arrow cross-section and the BB ′ arrow cross-section of FIG. 2, respectively. (C) is a view in which a light-shielding film is further added in (b). It is a figure which shows the arrangement pattern (Bayer arrangement) of the color filter arrange | positioned at the light-receiving surface of a photodiode. 3 is an electrode arrangement diagram in the solid-state imaging element according to Embodiment 1. FIG. FIGS. 7A and 7B are diagrams (pixel addition diagrams) illustrating the arrangement of target pixels to be subjected to pixel addition processing in the driving of the solid-state imaging element according to the first embodiment and the pixel barycentric position after the addition. FIG. In the electrode arrangement diagram of FIG. 5, FIG. 6 is a diagram (read pixel arrangement diagram) in which numbers are added to readout target pixels when the pixel addition process according to FIG. FIG. 8 is a diagram (address allocation diagram) in which information on signal charges stored in the HCCD is added when an address is assigned to a pixel to be read in FIG. 7 and horizontal pixel addition processing is performed for only one horizontal line. FIG. 7 is a timing chart showing drive timings at the time of signal charge readout when performing pixel addition processing according to FIG. FIG. 7 is a timing chart showing drive timings in a horizontal blanking period when performing pixel addition processing according to FIG. 6 is a readout pixel arrangement diagram in which numbers are added to readout target pixels when the pixel addition processing according to FIG. 6B is performed in the electrode arrangement diagram of FIG. 5. FIG. 12 is an address assignment diagram in which an address is assigned to a pixel to be read in FIG. 11 and signal charge information stored in the HCCD is added when horizontal pixel addition driving is performed for only one horizontal line. 7 is a timing chart showing drive timing of a signal charge readout operation when performing pixel addition processing according to FIG. It is a figure which shows the relationship between electric potential distribution and a board | substrate potential in the thickness direction of the board | substrate of the photodiode of a solid-state image sensor. 1 is a block diagram illustrating an example of a configuration of a camera device equipped with a solid-state imaging device according to Embodiment 1. FIG. It is an electrode arrangement | positioning figure which shows the structure of the solid-state image sensor which concerns on Embodiment 2 of this invention. FIG. 6 is a pixel addition diagram when pixel addition processing is performed by the solid-state imaging device according to the second embodiment. FIG. 17 is a read pixel arrangement diagram in which numbers are added to the read target pixels in the electrode arrangement diagram of FIG. 16. FIG. 19 is an address assignment diagram in which an address is assigned to a pixel to be read in FIG. 18 and signal charge information stored in the HCCD is added when horizontal pixel addition driving is performed for only one horizontal line. FIG. 20 is a diagram in which information on signal charges stored in the HCCD when the horizontal pixel addition driving is performed for three horizontal lines in FIG. 19 is added. 10 is a timing chart showing drive timing of signal charge read operation in the second embodiment. 6 is a timing chart showing drive timing in a horizontal blanking period in the second embodiment. In Embodiment 2, it is an electric charge transfer figure which shows the mode of transfer from VCCD to HCCD in the 1st structure electrode row | line | column. In Embodiment 2, it is an electric charge transfer figure which shows the mode of transfer from VCCD to HCCD in the 2nd structure electrode row | line | column. It is an electrode arrangement | positioning figure which shows the structure of the solid-state image sensor which concerns on Embodiment 3 of this invention. FIG. 10 is a diagram illustrating a pixel to be read in Embodiment 3. FIG. 10 is a pixel addition diagram when pixel addition driving is performed using only the first structure electrode row in the solid-state imaging device according to the third embodiment. FIG. 10 is a pixel addition diagram when pixel addition driving is performed using only the second structure electrode row in the solid-state imaging device according to the third embodiment. FIG. 26 is a readout pixel layout diagram in which numbers are added to readout target pixels in the electrode layout diagram of FIG. 25. FIG. 26 is an address assignment diagram in which an address is assigned to a pixel to be read in FIG. 25 and signal charge information stored in the HCCD is added when horizontal pixel addition driving is performed for one horizontal line. 10 is a timing chart showing drive timing of signal charge read operation in the third embodiment. 10 is a timing chart showing drive timings in a horizontal blanking period in the third embodiment. FIG. 6 is a block diagram illustrating an example of a configuration of a camera device on which a solid-state imaging device according to a third embodiment is mounted. FIG. 10 is a timing chart showing a modification of the drive timing of the signal charge read operation when the substrate potential is changed in the third embodiment. It is an electrode arrangement | positioning figure which shows the structure of the solid-state image sensor which concerns on Embodiment 4 of this invention. FIG. 36 is a read pixel arrangement diagram in which numbers are added to the read target pixels in the schematic diagram of FIG. 35. FIG. 37 is an address assignment diagram in which an address is assigned to a readout target pixel in FIG. 36. 6 is a timing chart showing the drive timing of a signal charge read operation when the solid-state imaging device according to the fourth embodiment is driven in mode A. 10 is a timing chart showing drive timings in a horizontal blanking period when the solid-state imaging device is driven in mode A in the fourth embodiment. 10 is a timing chart showing the drive timing of a signal charge read operation when the solid-state imaging device is driven in mode B in the fourth embodiment. 10 is a timing chart showing drive timings in a horizontal blanking period when the solid-state imaging device is driven in mode B in the fourth embodiment. FIG. 10 is a diagram illustrating signal output switching timing in one frame time when driving in modes A and B is performed in parallel in the fourth embodiment. 10 is a timing chart showing drive timings related to a read drive pattern ChAB in a signal charge read operation by mode A and mode B parallel drive according to the fourth embodiment. 12 is a timing chart showing drive timings related to a read drive pattern ChB in a signal charge read operation in the mode A and mode B parallel drive according to the fourth embodiment. 14 is a timing chart showing drive timings related to the vertical drive pattern P1 in the horizontal blanking period in the mode A and mode B parallel drive according to the fourth embodiment. 10 is a timing chart showing drive timings related to a vertical drive pattern P2 in a horizontal blanking period in the mode A and mode B parallel drive according to the fourth embodiment. It is a pixel structure figure which shows the modification of the connection pattern with the 1st wiring of the horizontal wiring part of a 1st, 2nd structure electrode row | line, and a 2nd wiring. It is a pixel structure figure which shows the modification of the shape of a horizontal wiring part. (A) and (b) explain the state of contact between each drive electrode and the first wiring and the second wiring in each of the cross sections taken along the line EE ′ and the line FF ′ in FIG. (C) is a diagram in which a light shielding film is further added in (b). It is a schematic plan view which shows the structure of the conventional general solid-state image sensor. It is a figure which shows the structural example of the imaging part of the conventional solid-state imaging device.

Hereinafter, embodiments of the solid-state imaging device 100 according to the present invention will be described with reference to the drawings.

<Embodiment 1>
(1) Overall Configuration of Solid-State Image Sensor 100 FIG. 1 is a schematic plan view showing the structure of the solid-state image sensor 100 according to Embodiment 1 of the present invention. As shown in the figure, the solid-state imaging device 100 includes an imaging unit 10, a selection output unit 20, an HCCD 30, and an output unit 40.

The imaging unit 10 includes photodiodes 11 as photoelectric conversion elements arranged in a matrix, and a VCCD 12 that transfers signal charges read therefrom in the vertical direction along each photodiode column. .

The selection output unit 20 is arranged at the junction between the end of each VCCD 12 and the HCCD 30, and temporarily accumulates the signal charges transferred by the VCCD 12 and outputs them to the HCCD 30 at a predetermined timing. is there.

The HCCD 30 conveys the signal charge output from the selection output unit 20 in the horizontal direction and outputs it to the output unit 40.

The output unit 40 includes a floating diffusion unit that converts the signal charge transferred by the HCCD 30 into a voltage, and an amplifier that amplifies the converted voltage to a predetermined level.

(2) Configuration of Image Pickup Unit 10 FIG. 2 is an enlarged view showing an area of 5 × 5 pixels in order to explain the arrangement of the drive electrodes and the wiring structure thereof in the image pickup unit 10.

As shown in this enlarged view, VCCDs 12 are arranged in parallel adjacent to each column of photodiodes 11 arranged in a matrix, and signal charges read from the corresponding photodiode columns are transferred vertically. .

A drive electrode 16 is disposed on the upper surface of each VCCD 12, and a horizontal wiring portion 15 is disposed for each row of the photodiodes 11 in order to supply a drive pulse to the drive electrode 16.

Only one drive electrode 16 is provided on the VCCD 12 adjacent to one photodiode 11. The drive electrode 16 has a shape that does not contact the adjacent drive electrode 16 in both the column direction and the row direction, and is formed of one layer.

Each horizontal wiring portion 15 includes two wirings of a first wiring 13 and a second wiring 14 extending horizontally so as to sandwich the photodiodes 11 in the corresponding rows from above and below, and electrically connecting any one of these wirings and the drive electrode 16 to each other. A contact 17 is formed for connection.

In the present embodiment, all the driving electrodes 16 in the first column are connected to the first wiring 13 of the horizontal wiring portion 15 in each row, and all the driving electrodes 16 in the second column are connected to the horizontal wiring portion 15 in each row. It is connected to the second wiring 14.

The drive electrode 16 for one column connected only to the first wiring 13 as described above is hereinafter referred to as a “first structure electrode row 161”, and the drive electrode 16 for one row connected only to the second wiring 14. Hereinafter referred to as “second structure electrode column 162”, the first and second

structure electrode columns

161 and 162 are different from each other in the first wiring 13 and the second wiring 14 of the horizontal wiring portion 15 in each row. For example, if a read pulse is applied only to the first wiring 13 of each horizontal wiring section 15, the photodiode array adjacent to the VCCD 12 on which the first structure electrode array 161 is formed is applied. The signal charges are read out selectively, and horizontal thinning out can be easily performed.

3A shows a cross-sectional view taken along the line AA ′ of the VCCD 12 in the first row (first structure electrode row 161) in FIG. 2, and FIG. 3B shows the second row in FIG. FIG. 8 shows a cross-sectional view taken along line BB ′ of the column (second structure electrode column 162).

As shown in both figures, the VCCD 12 is formed in the semiconductor substrate 50, the driving electrode 16 made of polysilicon is formed thereon, and an insulating layer (oxide film) (not shown) is formed on the surface thereof. A hole is formed at a predetermined position of the insulating layer by a mask process or an etching process, and a contact 17 is formed by filling this part with a metal such as tungsten.

On the insulating layer, a first wiring 13 and a second wiring 14 that are electrically separated are formed corresponding to one drive electrode 16. The first and

second wirings

13 and 14 are made of, for example, tungsten. Each of the above layers is formed by vapor deposition, sputtering, or the like, but the manufacturing method itself is a known thin film manufacturing technique, and thus the description thereof is omitted.

Further, as shown in FIG. 3C, a light shielding film 19 is provided on the upper layer of the first wiring 13 and the second wiring 14 so as to cover the VCCD 12 portion. In addition to the upper part of the VCCD 12, the light shielding film 7 is also provided between the rows of the photodiodes 11 (the vertical separation part of the pixels) so as to shield light from being directly incident on portions other than the light receiving surface of the photodiodes 11. The sex is secured.

Referring back to FIG. 2, in the imaging unit 10, the combination of the first structure electrode row 161 and the second structure electrode row 162 is arranged so as to be periodically repeated in the row direction. In this example, “the first structure electrode row 161, the second structure electrode row 162, and the first structure electrode row 161” are repeatedly arranged in a three-row cycle.

A power supply bus line 18 connected to a drive unit 420 (see FIG. 15) is arranged around the imaging unit 10. The bus line 18 and the first wiring 13 and the second wiring 14 in each horizontal wiring unit 15. Are connected, and a predetermined drive pulse is applied to each drive electrode 16 via the contact 17.

In the present embodiment, drive pulses V1 to V10 having different phases are sequentially applied from the top to the five sets of the first wiring 13 and the second wiring 14 in each horizontal wiring section 15 in the first to fifth columns. The first structure electrode row 161 has drive pulses V1, V3, V5, V7, and V9, and the second structure electrode row 162 has drive pulses V2, V4, V6, V8, and V10. Each VCCD 12 is configured to be driven in five phases by applying a pulse.

In such a wiring structure, a read pulse is applied to the drive electrode 16 via the horizontal wiring portion 15 to change the internal potential of the VCCD 12 to form a potential well, and the signal charge of the adjacent photodiode 11 is transferred to the VCCD 12. Are transferred to the potential well (hereinafter simply referred to as “reading signal charges”), and then the potential well is moved by sequentially changing the five-phase drive pulses applied to the drive electrodes 16 to thereby transfer the signal in the VCCD 12. Charge is transferred in the vertical direction (vertical transfer).

(3) Selection output unit 20 and HCCD 30
Returning to FIG. 1, a selection output unit 20 is formed in the horizontal direction at the connection between the VCCD 12 and the HCCD 30.

The selection output unit 20 temporarily accumulates signal charges transferred vertically by the five-phase drive of the drive electrodes 16 of each VCCD 12 and transfers them to the HCCD 30 at a predetermined timing. Is formed for the purpose of adding.

The selection output unit 20 includes a storage unit 21 and a barrier unit 22, and is formed by forming a storage electrode 23 and a barrier electrode 24 on the upper surface of the end portion of the VCCD 12.

The main purpose of the storage unit 21 is to store the signal charge that has been vertically transferred from the VCCD 12 until the signal is selectively output to the HCCD 30.

The storage unit 21 is designed so that its charge storage capacity is larger than that of the VCCD 12 in the imaging region by making the horizontal width (channel width) of the VCCD 12 directly below the storage electrode 23 larger than the channel width in the imaging region. Thus, the signal charge obtained by adding the pixels in the vertical direction can be sufficiently accumulated.

On the other hand, the capacity of charge that can be stored in the VCCD 12 in the barrier unit 22, that is, in the VCCD 12 immediately below the barrier electrode 24, does not need to be particularly large. The main purpose is to form a barrier.

Wirings 231 to 233 are formed in the horizontal direction on the upper surface of the storage electrode 23 via an insulating layer (not shown), and each storage electrode 23, any of the wirings 231 to 233 and the contacts 25 are periodically connected. Connected with sex.

Similarly, wirings 241 to 243 are horizontally formed on the upper surface of the barrier electrode 24 via an insulating layer (not shown), and each barrier electrode 24 has one of the wirings 241 to 243 and the contact 25 connected thereto. Are connected with periodicity.

The connection between the storage electrode 23 and each wiring of the barrier electrode 24 has the same period in the horizontal direction, and in FIG. The column period is designed.

The storage electrode 23 is supplied with driving pulses S1, S2, and S3 via

wirings

231, 232, and 233, respectively, and the barrier electrode 24 is supplied with driving pulses B1, B2, B3 is supplied respectively.

The drive pulses S1 to S3 and B1 to B3 are independent signals separate from the drive electrodes 16 of the imaging unit 10 (hereinafter referred to as “selective output pulses”), and the timing of application thereof is from the VCCD 12 to the HCCD 30. Depends on how the output is controlled to perform pixel addition in the horizontal direction.

In the present embodiment, three sets of six types of selection output pulses of selection output pulses S 1 and B 1, S 2 and B 2, S 3 and B 3 are provided, and the output selection unit 20 outputs signal charges from the VCCD 12 to the HCCD 30. Charge transfer control can be arbitrarily performed by three types of VCCD 12 each having three types of configurations.

As described above, the storage electrode 23 and the barrier electrode 24 are intended to selectively control the output of the signal charges transferred vertically from the VCCD 12 to the HCCD 30 for each column.

Here, in each row, the electrodes having the respective roles for storage and barrier are formed as a set, and hereinafter, the unit is formed by forming the storage electrode 23 and the barrier electrode 24 as a set. In this case, it is referred to as “selective output electrode group” (in the claims of the present application, the portion of the VCCD in which each selective output electrode group is arranged is described as “sub-selection output unit”). .

The electrode groups to which the selective output pulses S1 and B1, S2 and B2, and S3 and B3 are applied are referred to as first, second, and third selective

output electrode groups

251, 252, and 253, respectively (see FIG. 5). .

In addition, in order to reduce signal lines such as bus lines, it is possible to partially share the selection output pulses of each set with the drive pulses of the imaging unit 10, but in this example, for easy understanding. A description will be given of a structure in which independent selective output pulses can be applied to the storage electrodes 23 and barrier electrodes 24 of all columns.

The HCCD 30 has a plurality of horizontal drive electrodes (not shown), and sequentially transfers signal charges by applying a predetermined horizontal drive pulse to the horizontal drive electrodes. For this reason, detailed description of the electrode configuration is omitted here, and an area for storing one signal (hereinafter referred to as “horizontal transfer packet”) is simply described by adding a partition.

In the present embodiment, as shown in FIG. 1, it is shown that the HCCD structure has a horizontal transfer packet for storing one signal for the three VCCD columns.

The light receiving surface of each photodiode 11 of the imaging unit 10 is covered with one of three color filters (not shown), an R (red) filter, a G (green) filter, and a B (green) filter. More specifically, the R, G, and B color filters are arranged in a Bayer arrangement as shown in FIG. 4, and rows in which G filters and B filters are alternately arranged in the horizontal direction, R filters, and G filters. Rows in which filters are alternately arranged in the horizontal direction are alternately arranged in the vertical direction (column direction).

The above is the basic configuration of the solid-state imaging device 100 according to the first embodiment.

Actually, a channel stop is formed between each VCCD 12 and the photodiode row on the opposite side to the photodiode row from which the signal is to be read, and the portions other than the light receiving surface of each photodiode 11 are covered with a light shielding film. However, these are all well-known configurations in the solid-state imaging device, and are not characteristic configurations of the present invention, so illustration and description are omitted (the same applies to all the following embodiments).

(4) Driving Method (4-1) Electrode Arrangement Diagram Hereinafter, a driving method of the solid-state imaging device 100 according to the first embodiment will be described. To facilitate the description, the solid-state imaging device 100 of FIG. The configuration is further simplified and illustrated.

5 shows information on the color filter above the photodiode 11 in FIG. 1, information on the drive pulse applied to each drive electrode 16, information on the drive pulse applied to each selective output electrode, and one signal in the HCCD 30. FIG. Is an abbreviated notation of an area (horizontal transfer packet) for storing, and is hereinafter referred to as an “electrode layout diagram”.

In this electrode arrangement diagram, the drive electrode 16 to which the drive pulse Vn (n = 1, 2, 3,..., 10) is applied is simply expressed as “Vn electrode” (for example, in the first structure electrode row 161, “ "V3" means an electrode to which the drive pulse V3 is applied among the drive electrodes 16, and is referred to as a V3 electrode). In the row of photodiodes 11, “R”, for example, means the photodiode 11 to which the “R” color filter is attached.

In the solid-state imaging device having such a basic electrode arrangement, a desired output pixel reduction process can be executed by controlling the timing of the drive pulse applied to the drive electrode 16.

(4-2) Pixel addition example FIGS. 6A and 6B are diagrams showing the arrangement of pixels to be subjected to addition processing and the pixel centroid position after addition in the output pixel reduction processing according to the present embodiment. (Hereinafter, referred to as “pixel addition diagram”), which respectively show first and second pixel addition examples executed by the solid-state imaging device 100 of the first embodiment.

First, the first pixel addition example shown in FIG. 6A is 4-pixel addition, and the readout target pixel is set at a distance of 2 pixels above, below, left, and right from the barycentric position (+ notation) after pixel addition. ing.

That is, the signal charges of the pixels in the Mth row of the (N-2) th column and the (N + 2) th column are read out by the first structure electrode column 161, and the (M-2) th row and the (M + 2) th row of the Nth column are read out. ) Each signal charge of the pixels in the row is read out by the second structure electrode column 162 and pixel addition in the vertical direction (hereinafter referred to as “vertical addition”) is executed, and the (N−2) th column, the Nth column, and the The signal charges in the (N + 2) columns are added in the horizontal direction (hereinafter referred to as “horizontal addition”), and an addition output for four pixels is performed (N and M are integers of 3 or more).

The distance between the pixel centroids after pixel addition has a distance of 3 pixels in the horizontal direction and 5 pixels in the vertical direction, and signals that are adjacent to each other in the horizontal direction after pixel addition are displayed in the horizontal direction. The overlapping arrangement is set (for example, R1 and G1). In addition, signals that are adjacent to each other in the vertical direction after pixel addition are set so that the pixels to be read are adjacent to each other without overlapping in the vertical direction (for example, R2 and G2).

In addition, the second pixel addition example shown in FIG. 6B is five-pixel addition, one pixel at the centroid position (+ notation) after pixel addition, and two pixels in the oblique four directions from the centroid position. The four pixels at the distance are set as readout target pixels.

That is, the signal charges of the pixels in the (M−2) th row and the (M + 2) th row in the (N−2) th column and the (N + 2) th column are read out by the first structure electrode column 161 and vertically added. The signal charges of the pixels in the Mth row of the Nth column are read out to the second structure electrode column 162, and the signal charges in the (N−2) th column, the Nth column and the (N + 2) th column are horizontally added to obtain 5 pixels. Minute addition output (N and M are integers of 3 or more).

The distance between the pixel centroids after pixel addition has a distance of 3 pixels in the horizontal direction and 5 pixels in the vertical direction, and signals that are adjacent to each other in the horizontal direction after pixel addition exceed each other in the horizontal direction. The wrapping arrangement is set (for example, R3 and G3).

Signals that are adjacent to each other in the vertical direction after pixel addition are set so that the pixels to be read are adjacent to each other without overlapping in the vertical direction (for example, R4 and G4).

In these pixel addition examples, when the structure is such that three vertical pixels are used as the electrode arrangement unit, the center of gravity after pixel addition in both the horizontal and vertical directions has a completely equal distance (for three pixels). The distribution can be good.

(4-3) Driving Method in First Pixel Addition Example First, a driving method for executing the first pixel addition example shown in FIG. 6A will be described.

(4-3-1) Read Pixel Arrangement Diagram and Address Allocation Diagram FIG. 7 shows columns corresponding to the first and second

structure electrode columns

161 and 162 for the pixels read out during the execution of the first pixel addition example. The numbers PDn (n = 1, 2, 3) are assigned to the respective pixels, and the pixels read out by the drive electrodes 16 to which the drive pulses of the same phase are applied are assigned the same numbers (hereinafter, “ Read pixel arrangement diagram ”).

In the photodiode row corresponding to the first structure electrode row 161, the signal charge of PD1 separated by 5 pixels in the vertical direction is read out.

In the photodiode row corresponding to the second structure electrode row 162, the signal charges of PD2 and PD3 separated by 4 pixels in the vertical direction are combined into the same vertical transfer packet (VCCD12) by combining read control and vertical transfer control, respectively. And a vertical addition is carried out in (a potential well unit for transferring one charge signal).

The timing of each drive pulse is such that PD1 reads signal charges with a read pulse to the V5 electrode, PD2 reads signal charges with a read pulse to the V2 electrode, and PD3 reads signal charges with a read pulse to the V10 electrode. Is set.

FIG. 8 shows information of vertical addresses (1, 2,... N,... 2n) and horizontal addresses (A, B,...) For pixels to be read when performing pixel addition driving according to this example. Is a diagram (hereinafter referred to as “address allocation diagram”) in which an example of a pixel addition signal stored in the HCCD 30 is described in the HCCD unit. Here, an example is disclosed in which signal charges of (C2 + E3 + E4 + G2) and (F2 + H3 + H4 + J2) are stored in each signal storage area as the addition pixel of the horizontal line output signal (the pixel of J2 is not shown).

(4-3-2) Signal Charge Reading Timing FIG. 9 is a timing chart showing drive timings at the time of signal charge reading executed in the vertical blanking period in order to execute the above pixel addition example.

Three types of voltage levels of drive pulses applied to each drive electrode 16 at the time of signal charge reading are set.

When signal charges are read from the photodiode 11 to the VCCD 12, a high level (hereinafter “VH”) voltage is applied, and the vertical charge transfer in the VCCD 12 is at a medium level (hereinafter “VM”) and low level. A driving pulse having a voltage (hereinafter, “VL”) is applied.

VM is a voltage level for forming a potential well in the VCCD 20 under the drive electrode 16 so that signal charge can be accumulated, and VL cannot accumulate the signal charge in the VCCD 20 under the drive electrode 16 (barrier state). This is the voltage level for

Generally, the VH level is about 13V, the VM level is about 0V, and the VL level is about -6V, but the VH level and the VL level have a width of about several V depending on the design.

In FIG. 9, VH, VM, and VL are simply abbreviated as “H”, “M”, and “L” (the same applies to the following timing charts).

First, in the A, C, D, F, G, and I rows where the first structure electrode row 161 is arranged, the V5 electrode is in the VH state at time t3, and the signal charge of the PD1 is read out.

After that, the V1 to V7 electrodes are sequentially changed from VM → VL and VL → VM to be transferred in the vertical direction by 5 pixels, and the signal charge is held in the vertical transfer packet formed immediately below the V3, V5, and V7 electrodes. To do.

In the B, E, and H rows in which the second structure electrode row 162 is arranged, the V2 electrode is in the VH state at time t2, and the signal charge of the PD2 is read, and then the V2 electrode, the V4 electrode, As the V6 electrode sequentially changes from VM to VL, it is transferred to a position immediately below the V6 electrode at time t4.

Since the V10 electrode changes to the VH state at this time t4, the signal charge of the corresponding PD3 is read and transferred to the VCCD 12, so that the signal charges of PD2 and PD3 are mixed in the same vertical transfer packet here. Thus, one signal is obtained, and thereby vertical addition is executed.

On the other hand, in the initial state at time t1, the charge storage electrodes S1 to S3 of the first to third selection output electrode groups 251 to 253 are both in the VL state, but the barrier electrodes B1 to B3 are sequentially in the VL → VM state. → Changes to VL. At this time, the signal charge read at the position closest to the HCCD 30 is transferred to the HCCD 30 without being added and output as an image signal. For example, the memory management described later is performed on the image signal. Control may be performed so that data is not written in the memory unit 470 by the unit 460 (FIG. 15).

(4-3-3) Vertical Transfer Timing FIG. 10 is a diagram showing the timing of vertical transfer executed in the horizontal blanking period after the signal charge reading operation, and is read out by the VCCD 12 in each column. After the signal charge is vertically transferred in the VCCD 12, the horizontal charge is output by outputting it to the HCCD 30 for one horizontal line.

That is, the signal charges read out to each VCCD 12 column are transferred by 5 pixels toward the HCCD 30 by vertical driving by the first structure electrode column 161 and the second structure electrode column 162 between times t1 and t12.

At this time, the signal charge in the vertical transfer packet closest to the HCCD 30 is selectively transferred to the HCCD 30 via the storage unit 21 and the barrier unit 22 of the selection output unit 20.

First, in the initial state at time t1, the electrodes S1 to S3 of the storage unit 21 and the electrodes B1 to B3 of the barrier unit 22 are in the VL state. Further, in the first structure electrode row 161 and the second structure electrode row 162, the drive electrodes (V9 electrode, V10 electrode) adjacent to the S1 to S3 electrodes are also in the VL state in the initial state.

At time t2, a VM level pulse is applied to the S1 to S3 electrodes, but the V9 and V10 electrodes remain in the VL state and the barrier is still formed, so that the signal charge held in the latest vertical transfer packet is accumulated as it is It cannot flow into the part 21.

After that, at time t3, the V9 electrode and the V10 electrode are in the VM state and the barrier disappears, so that the signal charge flows into the storage unit 21 of the corresponding column. However, since the barrier electrodes B1 to B3 remain in the VL state, And is not output to the HCCD 30. Thereafter, the movement of the signal charge to the storage unit 21 is completed by returning the V9 and V10 electrodes to the VL state at time t10.

At time t11, the electrode B1 is first brought into the VM state, the barrier is released, and the signal charge of the storage unit 21 in the same row starts to flow into the HCCD 30, and at times t12 and t13, the S1 electrode and the B1 electrode are sequentially changed to the VL state. Thus, the transfer of the signal charge to the HCCD 30 is completed (refer to the displacement of the drive state of the V9 electrode, the S1 electrode, and the B1 electrode at times t1 to t13 in the leftmost column in the charge transfer diagram of FIG. 23 described later). .

At time t15 and time t19, the other B3 and B2 electrodes are also in the VM state, and the transfer of signal charges to the HCCD 30 is completed by the same procedure as described above.

(4-3-4) Driving Principle of Selection Output Unit 20 When transferring the signal charge to the storage unit 21 of the selection output unit 20 as described above, first, a VM pulse is applied to the S1 to S3 electrodes. Then, the reason why the immediately preceding drive electrode 16 (the V9 and V10 electrodes in this example) is changed from VL to VM is as follows.

As described above, in this embodiment, in order to secure a sufficient accumulated charge capacity, the channel width of the VCCD of the accumulation unit 21 in the selection output unit 20 is made wider than the channel width of the VCCD width in the imaging region. Therefore, the narrow channel effect is weakened in this portion and the potential level is deepened, and the difference from the potential level with the portion where the channel width is not widened is increased.

Such a situation is a phenomenon that generally occurs at the boundary between the narrow channel width portion and the wide channel width portion of the VCCD. In this embodiment, the S1 to S3 electrodes and the B1 to B3 electrodes There are cases where the potential level in the VL state is V9 and the potential state of the V10 electrode relative to the potential level in the VM state cannot be secured sufficiently, and signal charges are generated at the barriers under the S1 to S3 electrodes and the B1 to B3 electrodes. There is a possibility that a part of the electric charge may get over to the HCCD 30 without being stopped.

In this embodiment, when the S1 to S3 electrodes are in the VM state and the B1 to B3 electrodes are in the VL state, the S1 to S3 electrodes are obtained so that a sufficient potential barrier can be obtained between the S1 to S3 electrodes and the B1 to B3 electrodes. Also, the VCCD 12 directly below the B1 to B3 electrodes is designed to have a small potential difference (that is, to have substantially the same VCCD width), and when the V9 electrode or the V10 electrode is brought into the VM state, the corresponding columns S1 to S3 By setting the electrodes in the VM state and the B1 to B3 electrodes in the VL state, overflow of signal charges is prevented.

When the V9 (V10) electrode is brought into the VM state and the barrier is released, the signal charge flows into the VCCD 12 immediately below the S1 to S3 electrodes in the VM state, but between the S1 to S3 in the VM state and the B1 to B3 in the VL state. Has a sufficiently high potential difference, the potential barrier formed by the B1 to B3 electrodes in the VL state can be surely blocked and leakage to the HCCD 30 can be prevented.

The process of selectively driving the signal charges in the VCCD 12 to the HCCD 30 by driving the S1 to S3 electrodes and the B1 to B3 electrodes in the selective output unit 20 in the order as described above also in other embodiments. Since the operations are performed in the same manner, for the sake of simplification of explanation, hereinafter, this will be simply referred to as “driving the selected output electrode group”.

(4-3-5) Horizontal Addition Processing Next, horizontal addition processing will be described.

As an example, a case where the signal charges C2, (E3 + E4), and G2 are horizontally added in FIG. 8 will be described. Since the signal charge G2 is output to the corresponding horizontal transfer packet of the HCCD 30 by driving the first selection output electrode group 251 of the G column at time t13 in FIG. 10, an appropriate horizontal drive pulse ( The HCCD 30 is driven by (not shown), the horizontal transfer packet is horizontally shifted by three columns in the left direction in FIG. 8 (t14), and the third selective output electrode group 253 of the E column is driven to vertically The added signal charges (E3 + E4) are transferred to the same horizontal transfer packet (t17), then the horizontal transfer packet in the HCCD 30 is further horizontally shifted by three columns to the left (t18), and finally the C-th column By driving the second selection output electrode group 252, the signal charge C2 is transferred to the same horizontal transfer packet (t21).

The same addition process is simultaneously executed in other columns, thereby completing the horizontal addition.

Thereafter, the HCCD 30 is driven to horizontally transfer all signal charges for one horizontal line and output from the output unit 40.

By repeatedly performing the above control, the output pixel reduction process by the 4-pixel addition output signal shown in FIG. 6A is executed for one frame.

(4-4) Driving Method in Second Pixel Addition Example Next, a driving method for executing the second pixel addition example shown in FIG. 6B will be described.

(4-4-1) Read Pixel Arrangement Diagram and Address Assignment Diagram FIG. 11 is a read pixel arrangement diagram in which numbers are assigned to the pixels read out during execution of the second pixel addition example.

As shown in the figure, in the photodiode rows A, C, D, F, and G corresponding to the first structure electrode row 161, PD1 and PD2 separated by 4 pixels in the vertical direction are read control and vertical transfer, respectively. The vertical addition is performed so as to read out a plurality of signal charges in the vertical transfer packet by combining the controls.

Further, in the photodiode rows B, E, and H corresponding to the second structure electrode row 162, the signal charge of the PD 3 separated by 5 pixels in the vertical direction is read out.

PD1 reads the signal charge with a read pulse to the V1 electrode of the first structure electrode row 161, PD2 reads the signal charge with a read pulse to the V9 electrode of the same electrode row, and PD3 reads the second structure electrode row 162. The timing of each drive pulse is set so that the signal charge is read by the read pulse to the V6 electrode.

FIG. 12 is an address assignment diagram in which vertical address and horizontal address information is assigned to the readout target pixel when executing this pixel addition example.

Here, there is disclosed an example in which (C3 + C4 + E2 + G3 + G4) and (F3 + F4 + H2 + J3 + J4) are stored as the added pixels of the horizontal line output signal (the pixels of J3 and J4 are not shown).

(4-4-2) Signal Charge Reading Timing and Vertical Transfer Timing FIG. 13 is a diagram showing signal charge reading timing executed in the vertical blanking period in order to execute the second pixel addition example. , “H” is attached only to the VH state, and other portions change between the VM state and the VL state.

In driving the first structure electrode row 161, the signal charge read out when the V1 electrode is in the VH state at time t5 is PD1 in FIG. 11, that is, the A, C, D, F, G, and I rows in FIG. The signal charges corresponding to the readout target pixels of the even-numbered addresses and the V9 electrode in the VH state at time t6 are read out in the PD2 of FIG. 11, that is, the columns A, C, D, F, G, and I in FIG. Correspond to the readout target pixels of the odd-numbered addresses in FIG.

In the column from which PD1 and PD2 are read, vertical addition is performed by mixing and reading the charges of PD1 and PD2 into the same vertical transfer packet (length of three vertical pixels) in the corresponding VCCD 12.

In driving the second structure electrode row 162, the signal charges read when the V6 electrode is in the VH state at time t2 correspond to the PD3 in FIG. 11, that is, the readout target pixels in the B, E, and H rows in FIG. .

In this read timing, modulation control of the substrate potential VSUB level is performed in the period from time t4 to time t7. This is because the saturation output of the vertical transfer packet is within a certain range regardless of whether or not the pixel is added. The purpose is to be. Details of this substrate potential modulation control will be described later.

After the signal charge reading process, vertical transfer driving of each signal charge is performed in the horizontal blanking period, and after being accumulated in the accumulation unit 21 of the corresponding selection output unit 20, the selection

output electrode groups

251, 253, The horizontal addition processing is executed by combining the driving of 252 and the horizontal shift of the horizontal transfer packet. Since the driving at this time is exactly the same as the vertical transfer timing shown in FIG. 10 except that the combination of signal charges to be added is different, description thereof will be omitted.

The pixel addition as shown in FIG. 6B can be executed by the driving method as described above. According to this pixel addition example, the target readout pixel at the V6 electrode becomes a pixel located at the centroid of the addition target pixel, and weighting is possible for the saturation output of the pixel located at the signal centroid after the addition.

(4-4-3) Substrate Potential Modulation Control At the signal charge readout timing in the second pixel addition example shown in FIG. 13, the substrate potential VSUB is modulated between times t3 and t4. By executing the modulation control, the charge capacity in the target pixel is switched according to the number of added pixels.

That is, when signal charges are added, signal charges are read in a state where the saturation charge capacity of each photodiode 11 is reduced in consideration of the capacity of the vertical transfer packet.

FIG. 14 is a diagram showing the relationship between the substrate potential of a general photodiode and the potential distribution. The horizontal axis in the distribution diagram indicates the position in the thickness direction in the solid-state imaging device, P indicates the light receiving surface side of the photodiode, and P ′ indicates the substrate side. The vertical axis indicates the substrate potential VSUB with the downward direction as a positive direction.

A potential structure called a vertical overflow drain (VOFD) exists at a position deeper than the layer where the photodiode is formed. By adjusting the substrate potential VSUB of the solid-state imaging device 100 and controlling the height of a potential barrier called a vertical overflow barrier between the photodiode and the substrate, all charges in the photodiode are discharged to the substrate side or photo The saturation charge capacity of the diode can be controlled.

By setting the substrate potential VSUB to the low level Va, the height of the potential barrier between the photodiode and VOFD can be increased to increase the capacitance of the photodiode. When the substrate potential VSUB is increased to the intermediate level Vb, The capacity of the diode can be reduced.

Furthermore, when the substrate potential VSUB is raised to the high level Vc, the potential barrier between the photodiode and VOFD disappears, and all the charges of the photodiode can be discharged to the substrate side, so that it is used as an electronic shutter described later.

At the signal charge readout timing shown in FIG. 13, by utilizing the photodiode potential structure as described above, at the time of signal readout of the column where pixel addition in the vertical direction is not performed at time t2, and in the vertical direction at time t5 and time t6. The charge capacity of the pixel to be read is switched by modulating the substrate potential VSUB level when reading the signal of the column where the pixel addition is performed.

That is, in the control of performing a vertical addition by reading a plurality of signal charges, the capacity of each pixel to be read is controlled so as not to overflow the charge capacity of the vertical transfer packet in the VCCD 12. When the number of added pixels is different, the substrate potential VSUB is increased by a predetermined voltage so that charge overflow does not occur in the column having the largest number of vertical added pixels (columns A, C, D, F, G, and I in FIG. 12). If they are set uniformly, the column with the smallest number of vertical addition pixels (columns B, E, and H in FIG. 12) is in a state where only a small amount of signal charge is accumulated with respect to the charge capacity of the vertical transfer packet. As a result, the charge capacity of the vertical transfer packet is not fully utilized.

Therefore, by controlling the substrate potential VSUB so that the saturation output of the pixel to be read at time t2 is about twice the saturation of the pixel to be read at time t5 and t6, By fully utilizing the charge capacity of the transfer packet, a saturated output is obtained by taking advantage of the performance of the device.

In order to increase the dynamic range, the substrate potential (third potential) during the exposure time of the photodiode 11 is the same as or equal to the substrate potential (first potential) when the number of added pixels is the smallest. Set to:

In order to apply this substrate potential modulation control also to the timing of the first pixel addition example shown in FIG. 6A, the signal charge read operation at time t3 in FIG. 9 is performed at times t2 and t4. The VSUB level is set to a low level so that the saturation capacity of the target pixel is increased, the readout pulse is applied to the V5 electrode, and the subsequent vertical addition is performed. In order to reduce the saturation capacity of the target pixel when reading out the signal charge at time t2 and t4, the timing of modulation of the substrate potential is set so as to set VSUB to a higher level, and the readout at times t2 and t4 is performed. After the completion, the VSUB level may be reset to a low level.

In addition, the actual substrate potential value is basically set in advance according to the characteristics indicating the relationship between the potential distribution and the substrate potential in the solid-state imaging device to be used, the number of added pixels, and the like.

(5) Camera Device FIG. 15 is a block diagram showing a structural example of a camera device 400 equipped with the solid-state imaging device 100 according to the present embodiment.

As shown in the figure, the camera device 400 includes a lens unit 410, a solid-state imaging device 100, a drive unit 420, a timing generation unit 430, a control unit 440, a signal processing unit 450, a memory management unit 460, a memory unit 470, and an analog front. An end 480, a display unit 490, an operation unit 495, and the like.

The lens unit 410 includes a condensing lens 401 and a lens driving unit 402 that moves the condensing lens 401 in the optical axis direction during focusing, and an image to be imaged is solid through the condensing lens 401. An image is formed on the imaging unit 10 (FIG. 1) of the imaging device 100.

The photoelectric conversion is performed by each photodiode 11 in the imaging unit 10, and a charge corresponding to the received light amount is accumulated as a signal charge. Each signal charge is read by the drive pulse supplied from the drive unit 420, converted into a voltage by the output unit 40 (see FIG. 1), and then output to the analog front end 480.

The analog front end 480 includes a correlated double sampling unit (CDS) 481 and an AD conversion unit 482, and the signal output from the solid-state imaging device 400 is correlated according to the set timing supplied from the timing generation unit 430. AD conversion is performed while double sampling is performed, and a digitalized image signal is output to the memory management unit 460.

The memory management unit 460 writes the image signals received from the analog front end 480 according to the control signal from the control unit 440 into the memory unit 470 according to the driving mode, rearranged in the correct address order as necessary, and An operation of transmitting an image signal from the memory unit 470 to the signal processing unit 450, an operation of writing a signal after image processing by the signal processing unit 450 to the memory unit 470, or an output signal from the analog front end 480 directly to the signal processing unit The operation sent to 450 is controlled.

Based on a user instruction received from the operation unit 495, the control unit 440 sets a signal transfer path to the memory management unit 460, the signal processing unit 450, and the timing generation unit 430 in order to execute a desired mode. Send instructions such as signal processing setting and drive timing setting.

The timing generation unit 430 outputs a predetermined drive pulse from the drive unit 420 to the solid-state imaging device 100 at a predetermined timing based on an instruction related to the drive timing setting received from the control unit 440, and the analog front end 480 Issue CDS control and AD conversion drive timing.

The drive unit 420 generates a predetermined drive pulse in accordance with the signal supplied from the timing generation unit 430 and supplies the drive pulse to the solid-state imaging device 100. In addition to the above-described driving such as signal charge reading, vertical transfer, and horizontal transfer, the substrate potential The electronic shutter that once discharges the charge in the photodiode is operated by setting VSUB to a high level. Further, the modulation of the substrate potential in the signal charge readout drive (FIG. 13) in the second pixel addition example is executed (Note that the “drive means” in the claims of this application is the drive unit 420, the timing in FIG. The concept is a combination of the generation unit 430 and the control unit 440, and the combination of the generation unit 430 and the control unit 440 is referred to as a “solid-state imaging device”.

Further, the control unit 440 transmits the image data subjected to the output pixel reduction process to the display unit 490 including a liquid crystal display panel and displays the image data at a predetermined frame rate.

(6) Effects of First Embodiment As described above, according to the first embodiment, the following effects can be obtained.

(A) A driving electrode 16 is provided for each photodiode 11, a horizontal wiring portion 15 is arranged along each row of the photodiode 11, and a plurality of driving electrodes 16 arranged in the row direction of the same vertical address are arranged in the horizontal wiring portion 15. The first structure electrode row 161 and the second structure electrode row 162 are connected to either the first wiring 13 or the second wiring 14 so that their connection states are different, and the drive electrodes 16 arranged in the same row are connected to each other. It is possible to apply different drive pulses for each column. This makes it possible to increase the degree of freedom of the combination for reading out signal charges and to easily improve the output pixel reduction rate, though it is an extremely simple configuration, and it is not necessary to provide a wiring for bridge connection.

That is, a single layer drive electrode with a simple configuration controls horizontal readout output by controlling signal readout from the photodiode to the VCCD, charge transfer from the VCCD to the HCCD, and charge transfer of the VCCD for each column. Since the structure electrode rows are arranged to enable different driving for each VCCD, various horizontal thinning readouts can be realized by combining the horizontal arrangement cycle, the HCCD arrangement, and the number of driving phases for each row. Can do. In addition, the number of vertical drive phases in each structure electrode array can be easily increased, and the vertical thinning rate can be improved.

(B) Since it is easy to increase the number of drive phases of each structure electrode array, one vertical transfer packet can be lengthened in the vertical direction to obtain a large VCCD saturation capacity. Therefore, solid-state imaging with fine pixels A camera device having a large dynamic range can be realized even in a camera device using an element.

(C) By making the number of vertical drive phases of each structural electrode row equal and making the drive pulses different, it is possible to realize a complicated pixel addition pattern using horizontal thinning readout. In particular, while maintaining the horizontal distribution of the signal centroid arrangement after pixel addition to be uniform and suppressing the number of added pixels, it is possible to suppress the influence of pixel saturation variation and obtain an output with high linear characteristics.

In other words, when trying to obtain a high output pixel reduction rate only by pixel decimation, resolution degradation tends to be conspicuous. On the other hand, if a high output pixel reduction rate is obtained only by pixel addition processing with an increased number of added pixels, The variation in saturation capacity in each pixel is also added, and an image lacking linear characteristics tends to be formed.

In order to prevent the charge overflow in the vertical transfer packet, it is necessary to adjust the readout charge amount so as not to exceed the charge capacity of the vertical transfer packet in consideration of the variation of the saturation capacity in each pixel. This is because when the number of pixels to be read and added to the vertical transfer packet increases, the capacity ratio secured as a consideration for the variation in saturation capacity of each pixel with respect to the charge capacity of the vertical transfer packet increases, and the capacity allocated to the linear characteristics decreases.

However, according to the present embodiment, the thinning process and the pixel addition process are appropriately used in combination to enable a high output pixel reduction rate, while maintaining a good balance in which deterioration in image quality and linear characteristics are suppressed as much as possible. A compressed image can be obtained.

(D) By executing the substrate potential modulation control at the time of reading the signal charge, the saturation capacity of the photodiode is adjusted according to the number of pixels to be vertically added, so that the signal output level of each mode can be optimized.

<Embodiment 2>
The solid-state imaging device 101 according to the second embodiment has the same basic structure as the solid-state imaging device 100 of the first embodiment, such as the first structure electrode row 161, the second structure electrode row 162, and the horizontal wiring portion 15. However, the first and second

structure electrode rows

161 and 162 are arranged in the horizontal direction, and the HCCD is divided into two channels.

(1) Electrode Arrangement Diagram FIG. 16 is an electrode arrangement diagram for illustrating the overall configuration of the solid-state imaging device 101 according to the present embodiment.

As shown in the figure, the solid-state imaging device 101 includes a first and second

structural electrode rows

161 and 162 arranged adjacent to the photodiodes 11 arranged in a matrix in the imaging unit 10. They are arranged so that they are switched for each column.

Further, at the end of each VCCD 12, the first to third selective output electrode groups 251 to 243 have a three-row cycle, and the arrangement positions for the first and second

structure electrode rows

161 and 162 are different from each other. It arrange | positions so that it may be located in an up-and-down edge part.

The horizontal transfer unit has a two-channel configuration, and the first HCCD 31 is arranged at the lower part of the imaging unit 10 and the second HCCD 32 is arranged at the upper part.

The first and

second output units

41 and 42 are arranged at the output side end portions of the first and second HCCDs 31 and 32, and the signal charges transferred by the first HCCD 31 are output from the first output unit 41. The signal charges converted into voltage values and transferred by the second HCCD 32 are converted into voltages by the output unit 42 and output as pixel signals, respectively.

As in the first embodiment, the drive pulses applied to the drive electrodes 16 of the first structure electrode row 161 are V1, V3, V5, V7, and V9, and are applied to the drive electrodes 16 of the second structure electrode row 162. The drive pulses are connected to the bus line 18 via the horizontal wiring portion 15 so as to be V2, V4, V6, V8, and V10.

Therefore, also in the present embodiment, each VCCD 12 is 5-phase drive with a period of 5 vertical pixels, and the first structure electrode rows 161 and the second structure electrode rows 162 are alternately arranged for each row in the horizontal direction. This is a period of two horizontal pixels, and the vertical 5 pixels × horizontal 2 pixels are arranged in the area of the imaging unit 10 as an arrangement unit.

Each of the

HCCDs

31 and 32 turned upside down of the imaging unit 10 has the number of drive phases and the timing of the drive pulses so as to provide a signal storage area (horizontal transfer packet) for storing one signal with respect to the width of two VCCD columns. It has been decided.

In addition, a first selection output unit 210 and a second selection output unit 220 are formed at the connecting portion between the first HCCD 31 and the second HCCD 32 and the first structure electrode row 161 and the second structure electrode row 162, and are transported from the VCCD 12. The received signal charges are selectively output to the first HCCD 31 or the second HCCD 32.

The first selection output unit 210 includes a storage unit 211 and a barrier unit 212, and the second selection output unit 220 includes a storage unit 221 and a barrier unit 222.

As in the first embodiment, these are formed by forming first to third selective output electrode groups 251 to 253 on the upper surface of the end portion of the VCCD 12, and are independent of the drive pulses V1 to V10 in the imaging region, respectively. A selective output pulse can be applied.

The first structure electrode row 161 can transfer charges only to the first HCCD 31 via the first to third selection output electrode groups 251 to 253, and the second structure electrode row 162 has the first to third selection electrode groups. Charges can be transferred only to the second HCCD 32 via the selective output electrode groups 251 to 253.

The first to third selection output electrode groups 251 to 253 have a structure assuming pixel addition for three columns in the horizontal direction (see FIG. 17), and the first and second structure electrode columns 161, The arrangement period is different from 162.

(2) Driving Method (2-1) Pixel Addition Example FIG. 17 is a pixel addition diagram showing the contents of the pixel addition process executed in the second embodiment.

In the same figure, pixel addition results of pixels having the same shape are added to obtain a pixel addition result of 2 vertical pixels × 3 horizontal pixels, and the signal centroid (+ position) distribution after the addition is evenly 3 in the horizontal direction. The distribution has a distance equivalent to 5 pixels in the vertical direction.

(2-2) Read Pixel Arrangement Diagram and Address Assignment Diagram FIG. 18 is a read in which numbers PDn (n = 1, 2, 3, 4) are assigned to the read pixels for each electrode in order to execute the pixel addition. It is a pixel arrangement diagram.

PD1 and PD2 and PD3 and PD4 separated by two pixels in the vertical direction are combined with read control and vertical transfer control, respectively, and read in the same vertical transfer packet to execute vertical addition.

The horizontal addition is executed by controlling the timing of transfer from each VCCD 12 to the first and second HCCDs 31 and 32 and the timing of horizontal transfer in each of the first and second HCCDs 31 and 32.

FIG. 19 shows an example of the pixel addition signal stored in the first HCCD 31 and the second HCCD 32 in each HCCD unit, with the information of the vertical address and the horizontal address assigned to the pixel to be read when performing pixel addition driving in FIG. It is an address allocation diagram.

Here, since the vertical addresses are assigned to the readout target pixels in the order of transfer to the first HCCD 31 and the second HCCD 32, the vertical address of the first structure electrode row 161 and the second structure electrode row 162 is assigned. The order is reversed.

FIG. 19 discloses an example in which (F3 + F4 + D3 + D4 + B3 + B4) is stored for the second structure electrode row 162 and (I3 + I4 + G3 + G4 + E3 + E4) is stored for the first structure electrode row 161 as the addition pixel of the horizontal line output signal. (I and G columns are not shown. The same applies to FIG. 20).

(2-3) Signal Charge Reading Timing The timing chart of FIG. 21 shows the operation timing in reading signal charges during the vertical blanking period.

Regarding the first structure electrode row 161, at time t2, a VH level drive pulse is applied to the V3 electrode to read the signal charge of the PD1.

After reading, time t3 when the signal charge of PD1 is transferred directly below the V7 electrode by performing vertical transfer by changing the drive pulse applied to each electrode of V1, V3, V5, V7, and V9 in the VM and VL states. In addition, a VH level drive pulse is applied to the V7 electrode to read out the signal charge of PD2, thereby reading out and vertically adding to the same vertical transfer packet as the signal charge of PD1 read out at time t2.

After adding the signal charges of PD1 and PD2, vertical transfer is performed until the storage unit 211 (FIG. 16) and the barrier unit 212 are the same as the initial state at time t1, and the transfer is stopped at time t6.

Regarding the second structure electrode row 162, the V4, V6, and V8 electrodes are set to the VM state at the time t1, and the V2 and V10 electrodes are set to the VL state at the time t2. A VH level driving pulse is applied to read the signal charge of PD3. Thereafter, the drive pulses applied to the electrodes V2, V6, V8, and V10 are changed in the VM and VL states so that the signal charge in the VCCD is perpendicular to the direction opposite to the first structure electrode row 161 (direction toward the second HCCD 32). At time t3, a drive pulse of VH level is applied to the V4 electrode to read the PD4 signal charge into the same vertical transfer packet that output the PD3 signal charge, and execute vertical addition. .

After adding the signal charges of PD3 and PD4, the vertical transfer is performed until the storage unit 221 and the barrier unit 222 become the same as the initial state at time t1, and the charge transfer is stopped at time t6.

During the vertical transfer of the signal charges, the operation of each of the

HCCDs

31 and 32 may be either stopped or transferred, but the HCCDs 31 and 32 are emptied in preparation for the output of a valid signal from the VCCD 12. In this embodiment, the

HCCDs

31 and 32 perform the transfer operation in the state at time t6 when the vertical transfer is finished, and the

output units

41 and 42 are used. Thus, the charge is wiped out (section tc).

(2-4) Vertical Transfer Timing The timing chart of FIG. 22 shows the drive timing at the time of vertical transfer of the signal charge in the VCCD during the horizontal blanking period after reading out the signal charge.

Also, FIG. 23 shows the inside of the VCCD 12 in the I, G, and E columns corresponding to the first to third selection output electrode groups 251 to 253, in which the first structure electrode row 161 at the time t1 to t21 in FIG. 2 is a diagram schematically showing the potential of HCCD 31 and the state of signal charges (hereinafter referred to as “charge transfer diagram”). FIG.

Similarly, in FIG. 24, the VCCD 12 in the F, D, and B columns corresponding to the first to third selection output electrode groups 251 to 253 are arranged, and the second structure electrode row 162 at time t1 to t21 in FIG. 6 is a charge transfer diagram in the inner and HCCD 32. FIG.

In the first structure electrode row 161, the signal charges read and vertically added in the signal charge reading process of FIG. 21 are accumulated in the vertical transfer packets formed immediately below the electrodes V3 to V5 (each of FIG. 23). At the time t1 to t10), the drive pulses applied to the electrodes V1, V3, V5, VV7, and 9 are sequentially changed in the VM and VL states and vertically transferred.

As a result, the signal charge in the vertical transfer packet that is closest to the first selection output unit 210 is accumulated in the accumulation unit 211 at time t10 (the electrodes S1 to S3 at time t10 in each column in FIG. 23). (See section).

Between time t11 and t13, the first selective output electrode group 251 is driven to transfer the accumulated charge in the I-column accumulation unit 211 into the horizontal transfer packet of the first HCCD 31 (TR11).

Thereafter, the horizontal transfer packet is horizontally shifted leftward by two columns of the VCCD 12 toward the output unit 41 (TR12), and the first selection electrode group 252 is driven between times t15 and t17, whereby the G column The accumulated charge in the accumulation unit 211 of the VCCD 12 is transferred to the horizontal transfer packet and added (TR13).

Thereafter, the horizontal transfer packet is further horizontally shifted to the left by two columns of the VCCD 12 (TR14), and the first selection electrode group 252 of the E column is driven between the times t19 and t21, so that the storage unit 211 of the VCCD 12 The accumulated charge is transferred to the horizontal transfer packet and added (TR15).

The addition processing in the horizontal direction is performed on the VCCDs 12 for the other odd-numbered columns in the same manner as described above.

On the other hand, the same control as described above is performed for the even-numbered columns of the VCCD 12 corresponding to the second structure electrode rows 162 (B, D, and F columns are illustrated in FIG. 24), and three signal charges existing in the horizontal direction are added. However, in these cases, since the second HCCD 32 is connected to the upper end, the vertical transfer direction is opposite to the case of the first structure electrode row 161.

Specifically, as shown in FIG. 22, regarding the drive control, the control is performed by replacing V1 of the first structure electrode array with V10, V3 with V8, V5 with V6, V7 with V4, and V9 with V2. By doing so, horizontal addition of signal charges can be realized.

In the above, when the signal charge reading of FIG. 21 and the vertical transfer of FIG. 22 are performed once, three columns of the VCCD 12 are horizontally added, and the state of the signal charges in the first and second HCCDs 31 and 32 is as follows: As shown in FIG. 19, signal charges are stored in only 1/3 of the signal storage areas of the first HCCD 31 and the second HCCD 32, and the other 2/3 signal storage areas are empty.

Accordingly, in the state of FIG. 19, the vertical drive of FIG. 22 is further performed twice while appropriately moving the horizontal transfer packet, so that the state of each of the first HCCD 31 and the second HCCD 32 is as shown in FIG. A signal charge having a predetermined horizontal line number can be transferred to all. In the example of FIG. 20, the horizontal line numbers stored in each signal storage area are given in the order of transfer to the first HCCD 31 and the second HCCD 32 in the transfer direction of each VCCD 12.

In this state, if the first HCCD 31 and the second HCCD 32 are horizontally transferred to perform signal output, a signal output for three horizontal lines can be obtained by one horizontal transfer output, and the processing speed can be increased.

In FIG. 19, signals (B1, B2, D1, D2, F1, F2) corresponding to the first horizontal line of the second structure electrode row 162 and the first horizontal line of the first structure electrode row 161 are shown. (A1, A2, C1, C2, E1, E2) are discharged to the second HCCD 32 and the first HCCD 31 at the end of the signal charge reading control in FIG. 21, and are obtained as effective output signals. However, this can be obtained as an effective output signal by appropriately adjusting the drive timing of FIG. 21 at the time of reading.

(3) Camera Device A camera device equipped with the solid-state imaging device 101 according to the present embodiment also has a configuration that is substantially the same as that shown in FIG. However, since the solid-state imaging device 101 has two

output units

41 and 42, two CDSs 481 and two AD conversion units 482 in the analog front end 480 are required in the camera device (see FIG. 33 described later). reference).

In addition, the horizontal line output order of the image signals in the HCCD structure of the upper and lower two channels sandwiching the imaging unit 10 is, for example, the first structure electrode row 161 from the lower part of the imaging unit, the second structure electrode row 162 from the upper part of the imaging unit, Since the output address of the imaging signal differs depending on the structure electrode array, the memory unit 470 needs to have a memory area for storing image signals for at least one screen, and the memory management unit 460 has an analog front end 480. Is written to the memory unit 470 at a correct address. Signal processing such as color adjustment is performed on the image signal written in the memory unit 470.

(4) Effects of Second Embodiment According to the invention according to the second embodiment, in addition to the main effects of the first embodiment, the charge transfer direction is designed in a different direction above and below the imaging region, and at each end. By providing the HCCD, the upper and lower 2-channel HCCD can be adapted to vertical multi-phase driving (5 or more phases), and the speed of outputting one frame is improved, so that the frame rate can be increased.

<Embodiment 3>
In the second embodiment, in the two-channel HCCD structure, the first structure electrode rows 161 and the second structure electrode rows 162 are alternately arranged, and both of them are driven in five phases. The arrangement period is different, and the number of phases for vertical driving is different between the first structure electrode row 161 and the second structure electrode row 162.

This is characterized in that the first structure electrode row 161 and the second structure electrode row 162 are driven in different modes and can be output independently from the first HCCD 31 and the second HCCD 32, respectively.

(1) Electrode Arrangement FIG. 25 is an electrode arrangement diagram of the solid-state imaging device 102 according to the third embodiment.

As shown in the figure, in the present embodiment, the first HCCD 31 disposed below is used as a signal charge transfer destination in the VCCD 12, and the second HCCD 32 disposed above is disposed in the VCCD. The second structure electrode row 162 as a signal charge transfer destination is an arrangement unit in which one cycle is composed of three rows each composed of two first structure electrode rows 161 and one second structure electrode row 162. Arranged in the imaging area.

Each of the first HCCD 31 and the second HCCD 32 has a signal storage area (horizontal transfer packet) having a length corresponding to three columns of the VCCD, and a first selective output electrode group between the first HCCD 31 and the first structure electrode row 161. 251 or the second selection output electrode group 252 is arranged, and the third selection output electrode group 253 is arranged between the second HCCD 32 and the second structure electrode row 162.

In the present embodiment, the drive pulse signals applied to the drive electrodes 16 in the imaging region of the first structure electrode row 161 are V1, V3, V5, V7, and V9, and in the imaging region of the second structure electrode row 162. The drive pulse signals applied to the drive electrodes 16 are V2, V4, V6, V8, V10, V12, V14, V16, and V18. The first structure electrode row 161 is the vertical five-phase drive and the second structure electrode row 162. Has a configuration of vertical nine-phase driving. For this reason, the number of bus lines 18 (see FIG. 2) is also added to the extent that the drive pulses V12, V14, V16, and V18 are supplied.

That is, in the present embodiment, the electrodes of 45 pixels vertical × 3 pixels horizontal are arranged in the imaging region as an arrangement unit.

(2) Reading Target Pixel and Pixel Addition Example FIG. 26 shows the arrangement of all the reading target pixels that do not distinguish the transfer destination HCCD. FIG. 27 shows the position of the pixel to be read out during execution of mode A output through the first HCCD 31 and an example of pixel addition thereof, and FIG. 28 shows the position of the pixel to be read out during execution of mode B via the second HCCD 32. And a pixel addition example thereof.

As shown in FIG. 27, in mode A in which pixel addition of 2 vertical pixels × 2 horizontal pixels is performed, the distribution of signal centroids (positions of +) after pixel addition is equivalent to 3 pixels in the horizontal direction and in the vertical direction. In the mode B in which the signal pixels of 2 vertical pixels × horizontal 1 pixel are added as shown in FIG. 28, the distribution has a uniform distance of 5 pixels. The distribution has a distance corresponding to pixels.

(3) Driving Method (3-1) Read Pixel Arrangement Diagram and Address Allocation Diagram FIG. 29 is a read pixel arrangement diagram in the present embodiment. In the photodiode column adjacent to the first structure electrode column 161, the vertical direction In the photodiode column adjacent to the second structure electrode column 162, PD1 and PD2 separated by two pixels in the same direction can be obtained by combining PD3 and PD4 separated by four pixels in the vertical direction by combining read control and vertical transfer control, respectively. Read in the vertical transfer packet and execute vertical addition.

As shown in FIG. 29, in the photodiode row adjacent to the first structure electrode row 161, PD1 reads the signal charge by the read pulse to the V3 electrode, and PD2 receives the signal charge by the read pulse to the V7 electrode. Read out.

In the photodiode row adjacent to the second structure electrode row 162, PD3 reads the signal charge with a read pulse to the V12 electrode, and PD4 reads the signal charge with a read pulse to the V4 electrode.

30 assigns the information of the vertical address and the horizontal address to the readout target pixel of FIG. 29, and the information of the pixel addition signal as the first horizontal line output stored in each of the first HCCD 31 and the second HCCD 32. FIG.

As in the second embodiment, the vertical addresses of the respective columns are assigned numbers in the vertical direction from the output first and second HCCDs 31 and 32, but the number of horizontal lines differs depending on the transfer destination.

In this example, since the readout pixels of the first structure electrode row 161 and the second structure electrode row 162 are added in the vertical direction, the number of horizontal lines output from the second HCCD 32 is (n / 2) lines, the first HCCD 31. The number of horizontal lines to be output is (x / 2) lines. (N, x: integer)
In FIG. 30, the first HCCD 31 has a first horizontal line output signal (A1 + A2 + C1 + C2) when the readout pixels of the A column and the C column, and the D column and the F column where the first structure electrode column 161 is arranged are added. ), (D1 + D2 + F1 + F2) are respectively stored, and the first horizontal line output signal (B1 + B2) when the read pixels of the B column and the E column in which the second structure electrode column 162 is arranged are added to the second HCCD 32, An example in which (E1 + E2) is stored is disclosed.

(3-2) Signal Charge Read Timing FIG. 31 shows a timing chart of each drive pulse at the time of signal charge read in the present embodiment.

First, in the drive pulse timing chart in the first structure electrode row 161, VH level drive pulses are applied to the V3 electrode and V7 electrode at time t3 and time t4, respectively, and the signal charges of PD1 and PD2 are read out.

At this time, the signal charges of PD1 and PD2 are read out so that the signal charges are mixed by the vertical transfer packet in the VCCD 12. Specifically, at time t3, the V3 electrode is set to the VH state, the signal charge of PD1 is read into the vertical transfer packet immediately below V3, and then the V1 to V9 electrodes are driven to bring the vertical transfer packet immediately below the V7 electrode. At time t4, the V7 electrode is set to the VH state, and the signal charge of PD2 is read and mixed in the same vertical transfer packet to execute the process of adding the signal charges of PD1 and PD2.

On the other hand, in the driving operation in the second structure electrode row 162, a VH level driving pulse is applied to the V4 electrode and the V12 electrode at time t2 and time t4, respectively, and the signal charges of PD3 and PD4 are read and vertically added. .

Specifically, at time t2, the V12 electrode is set to the VH state, the signal charge of PD3 is read into the vertical transfer packet of the VCCD 12 immediately below the V12 electrode, and then the V2 to V18 electrodes are driven to transfer the vertical transfer packet to the V4 electrode. A process of vertically adding the signal charges of PD3 and PD4 is executed by moving to just below, setting the V4 electrode to the VH state at time t4, and reading and mixing the signal charges of PD4 in the same transfer packet.

(3-3) Vertical Transfer Timing FIG. 32 is a timing chart showing the state of each drive pulse during vertical transfer executed in the horizontal blanking period after the vertical addition.

First, in the first structure electrode array 161, V1, V3, V5, V7, and V9 drive pulses are applied to the respective electrodes to vertically transfer signal charges, and the first selection output electrode group 251 and the second selection output. The electrode group 252 is driven to transfer charges from the VCCD 12 under the first structure electrode array to the first HCCD 31.

At this time, the signal charge transferred to the first HCCD 31 is the same as the signal charge output through the first selection output electrode 251 and the signal charge output through the second selection output electrode 252 in the same horizontal transfer packet of the first HCCD 31. Therefore, the signal charge output to the first HCCD 31 and the horizontal addition are executed simultaneously.

The signal charges output to the first HCCD 31 are transferred in the horizontal direction and output via the first output unit 41. As a result, the image data output from the first output unit 41 is output as a signal that has been subjected to 1/5 compression in the vertical direction and 1/3 compression in the horizontal direction as compared with the number of pixels of the element.

On the other hand, in the second structure electrode row 162, the signal charges vertically added by the vertical addition drive of FIG. 31 are applied with drive pulses of V2, V4, V6, V8, V10, V12, V14, V16, and V18 to each electrode. Then, vertical transfer in the VCCD is performed, the third selective output electrode group 253 is driven, and charge transfer from the VCCD 12 under the second structure electrode row 162 to the second HCCD 32 is performed.

The signal charges output to the second HCCD 32 are transferred in the horizontal direction and output via the second output unit 42. As a result, the image data output from the second output unit 42 is output as a signal that has been subjected to 1/9 compression in the vertical direction and 1/3 compression in the horizontal direction as compared with the number of pixels of the element.

Therefore, in the present embodiment, pixels are output from the first HCCD 31 at the output pixel reduction rate of 1/15 as the mode A, and the output pixels are reduced by 1/27 from the second HCCD 32 as the mode B. Pixels are output at a rate. In addition, since the first HCCD 31 and the second HCCD 32 can be driven independently, the mode A and the mode B can be executed simultaneously.

(4) Camera Device FIG. 33 shows a configuration example of the camera device 401 on which the solid-state imaging device 102 according to this embodiment is mounted. Although the basic configuration is almost the same as that of the camera device of

Embodiments

1 and 2, the timing generation unit 430 generates the timings related to a plurality of modes at the same time, so the first timing generation unit 431 and the second timing are the same. The generation unit 432 is included.

As a result, when a plurality of different modes are operated simultaneously, it is possible to simplify the transfer of timing setting data from the control unit 440, and the other mode is stopped while another mode is being executed or another drive is performed. It is possible to give flexibility to switch to a method.

Further, the control unit 440 controls the vertical synchronization period, the horizontal synchronization period, and the drive timing for a plurality of modes in accordance with the drive contents of each mode. For example, when the 30 fps mode and the 60 fps mode are operated simultaneously, the effective signal output period of the 30 fps mode and the signal read operation of the 60 fps mode may overlap, but at this time, noise caused by the read operation of the 60 fps mode may occur. In order to suppress the jumping in, it is desirable to temporarily stop the output of the effective signal in the 30 fps mode, or to perform control such as performing a read operation during a period in which the effective signal is not output to the outside.

Thus, in the image signal output from the first output unit 41 and the image data output from the second output unit 42, the number of pixels of the output signal is in a ratio of 9: 5. This is, for example, from the first output unit 41. It is possible to simultaneously control the mode A for driving the output image data to be output at a speed of 33 fps and the mode B for driving the image data output from the second output unit 42 at a speed of 60 fps. To do.

Furthermore, if the vertical blanking period is appropriately adjusted with respect to the timing of driving at a speed of 33 fps, the frame rate can be set to 30 fps, and 30 fps imaging output and 60 fps image data output can be obtained simultaneously. .

The current digital still camera (DSC) is generally equipped with a moving image recording function in order to increase its added value. The control unit 440 records, for example, high pixel image data while outputting at 30 fps, and uses low pixel image data at 60 fps for autofocus (AF) operation and exposure control (AE) operation. A known AF / AE process is performed to automatically control the focus and imaging conditions. This makes it possible to obtain an optimal moving image sequentially for a subject that changes every moment.

(5) Effects of Embodiment 3 As described above, according to this embodiment, in addition to the main effects described in

Embodiments

1 and 2, there are a plurality of structural electrode arrays in the solid-state imaging device. Read control and a plurality of vertical charge transfer controls, and a plurality of modes with different output pixel reduction rates can be driven simultaneously. The degree of freedom can be improved.

(6) Supplementary items (6-1) In this embodiment, the number of pixel additions constituting the output signal of mode A is 4 pixels, and the number of pixel additions constituting the output signal of mode B is 2 pixels. . As a result, the signal output level in mode B is about half that in mode A, so the dynamic range in mode B may be narrowed. This is illustrated in FIG. This can be dealt with by modulating the substrate potential VSUB in the same manner as described.

That is, as shown in FIG. 34, regarding the mode with a small number of pixel additions and the mode with a large number of pixel additions, the substrate potential VSUB is set to a high level after the readout target pixel in the mode with a small number of pixel additions is read first. Reading in a mode with a large number of pixel additions is performed.

Specifically, first, the substrate potential VSUB is set low, the mode B readout target pixel is read with the V12 electrode and the V4 electrode set to the VH state at times t2 and t4, and then the substrate potential VSUB is set after time t7. After that, the pixel to be read in mode A is read with the V3 and V7 electrodes in the VH state at times t5 and t6, respectively. After reading, VSUB is set low again at time t9.

Thus, by controlling the substrate potential VSUB according to the number of vertical additions, the signal output level in each mode can be optimized.

(6-2) Regarding a driving method for performing simultaneous control in a plurality of modes, the first HCCD 31, the second HCCD 32, the first output unit 41, and the second output unit 42 may share these driving periods, or either It is desirable to perform drive control so that one horizontal output period and one of the VCCD transfer operations do not overlap.

This is because shading occurs when the signal for driving the VCCD 12 changes when a signal is output from the first HCCD 31 and the second HCCD 32 via the first output unit 41 and the second output unit 42. It is because it is easy to do.

From this point of view, when driving a plurality of modes at the same time, it is desirable to share a period for outputting an external signal from the first HCCD 31 and the second HCCD 32 via the first output unit 41 and the second output unit 42, respectively. .

Structurally, by designing the number of signals that can be stored in the first and second HCCDs 31 and 32 to be substantially the same as in the present embodiment, the periods for outputting signals from the

HCCDs

31 and 32 are aligned. As a result, the timing design is less wasted.

(6-3) In the first to third selection output electrode groups 251 to 253 in the present embodiment, the corresponding first and second

structure electrode rows

161 and 162 are determined one-to-one. Even when the number of drive phases differs between the first and second structure electrode arrays, charge transfer is possible without any problem.

However, the first to third selection output electrode groups 251 to 253 and the first and second

structure electrode rows

161 and 162 are different from the above structure, for example, the specific selection output electrode group is the first and second structure electrodes. Even if it is used for both columns, devise such as setting a waiting time at one drive timing to absorb the difference in charge transfer method due to the difference in the number of VCCD drive phases of each structure electrode column It is possible to cope with.

(6-4) In this embodiment, the number of vertical drive phases in the first structure electrode row 161 is five phases, and that in the second structure electrode row 162 is nine phases, but this is another combination. But it ’s okay.

That is, the resolution of the signal read by the first structure electrode row 161 of the present embodiment is 1/5 in the vertical direction, and the resolution of the signal read by the second structure electrode row 162 is 1/9 in the vertical direction. However, for example, if the configuration of the first structure electrode row 161 is set to 7-phase drive instead of 5-phase drive, the resolution of the signal read out by the first structure electrode row 161 is a signal obtained by compressing 1/7 in the vertical direction. Can be output as

This is feasible because the driving of the vertical drive electrodes constituting the first structure electrode row 161 and the second structure electrode row 162 is independent of each other, and the output horizontal line is adapted to the demands and specifications of the product. The number of vertical drive phases of the first structure electrode row 161 and the second structure electrode row 162 may be determined so as to satisfy the number.

<Embodiment 4>
The fourth embodiment is characterized in that the HCCD is one channel in the third embodiment.

(1) Electrode Arrangement Diagram FIG. 35 is an electrode arrangement diagram in the solid-state imaging device 103 according to the fourth embodiment.

As shown in the figure, in the present embodiment, a unit in which one row is composed of three rows each having two first structure electrode rows 161 and one second structure electrode row 162 is arranged in the imaging region. A single HCCD 33 is arranged below them.

The HCCD 33 has a signal storage region (horizontal transfer packet) having a length corresponding to three columns, and a first selection output electrode group 251 and a second selection output electrode are disposed between the first structure electrode column 161 and the HCCD 33. A group 252 is arranged, and a third selective output electrode group 253 is arranged between the second structural electrode row 162.

Also in this embodiment, drive pulses are independently applied to S1 / S2 / S3 and B1 / B2 / B3 constituting each selective output electrode group.

The drive pulses applied to the drive electrodes 16 in the imaging region of the first structure electrode row 161 are V1, V3, V5, V7, and V9, and are applied to the drive electrodes 16 in the imaging region of the second structure electrode row 162. The drive pulse signals to be applied are V2, V4, V6, V8, V10, V12, V14, V16, and V18. The first structure electrode row 161 is driven by vertical five phases, and the second structure electrode row 162 is driven by vertical nine phases. In this configuration, electrodes of vertical 45 pixels × horizontal 3 pixels are arranged in the imaging region as an arrangement unit.

Also, a drain portion 45 for discharging excess charge of the VCCD 12 is provided at the end of the VCCD 12 opposite to the side connected to the HCCD 33, and a predetermined DC bias VDD is applied.

The drain part 45 forms a region in which ions are implanted on the semiconductor substrate so as to be in contact with all VCCD ends, and forms a contact with a wiring for supplying a DC bias VDD at the end of the implanted region.

The level of the DC bias VDD applied to this is a voltage of about several tens of volts, and the drive electrode (V1 or V2 electrode in FIG. 35) at the boundary between the VCCD 12 and the drain 45 is in the VM state. The potential level of the drain portion 45 is set to be deeper than the potential level, and noise charges are discharged to the drain portion 45 when noise charges are discharged by reverse VCCD transfer described later.

(2) Read Pixel Arrangement Diagram and Address Assignment Diagram FIG. 36 is a read pixel arrangement diagram in which numbers are assigned for each electrode to the pixels read when the solid-state image sensor 103 is subjected to pixel addition driving. Vertical addition is performed by transferring PD1 and PD2 separated by pixels and PD3 and PD4 separated by 4 pixels in the vertical direction in the same vertical transfer packet by combining signal charge readout control and vertical transfer control, respectively.

PD1 reads a signal charge with a read pulse to the V3 electrode, PD2 reads a signal charge with a read pulse to the V7 electrode, PD3 reads a signal charge with a read pulse to the V4 electrode, and PD4 The signal charge is read by a read pulse to the V12 electrode.

FIG. 37 is an address assignment diagram in which vertical address and horizontal address information is assigned to the readout target pixel in FIG.

In each column, a number in the vertical direction is assigned from the HCCD 33 side. When the readout pixels of the B column and the E column which are the second structure electrode column 162 are added and output to the HCCD 33, (B1 + B2) and (E1 + E2) are the respective signals as the first horizontal line output in each horizontal transfer packet. When the readout pixels of the A column and the C column, and the D column and the F column, which are the first structure electrode columns 161, are added and output in the storage area, each horizontal transfer packet has (A1 + A2 + C1 + C2) as the first horizontal line output. ) And (D1 + D2 + F1 + F2) are respectively stored.

(3) Driving method In the fourth embodiment, since the electrode arrangement in the imaging region is the same as that in the third embodiment, the same driving as in the modes A and B is possible, but the HCCD has one channel. Basically, each mode is executed separately. However, both modes can be executed in parallel by controlling the mode B frame rate K times that of mode A (K is an integer of 2 or more) in a time-sharing manner.

Hereafter, the explanation will be divided into the case where both modes are executed separately and the case where they are executed in parallel.

(3-1) When Driving Separately (3-1-1) Driving in Mode A FIGS. 38 and 39 show output pixels of 1/5 in the vertical direction and 1/3 in the horizontal direction in the solid-state image sensor 103. FIG. 28 is a timing chart showing drive timings when executing mode A (refer to the pixel addition diagram of FIG. 27) for performing reduction.

FIG. 38 shows the drive timing at the time of signal charge reading in the vertical blanking period, and FIG. 39 shows the drive timing of the vertical transfer of charges in the VCCD during the horizontal blanking period.

Here, only the first structure electrode row 161 performs signal readout and addition processing to execute mode A, and the second structure electrode row 162 carries the empty vertical transfer packet immediately below it toward the drain portion 45. A drive pulse is applied as described above.

Therefore, the drive timing in the first structure electrode row 161 is exactly the same as the drive timing in the first structure electrode row 161 described in FIG.

That is, regarding the operation of the first structure electrode row 161, a VH level drive pulse is applied to the V3 and V7 electrodes at time t3 and time t4, respectively, and the signal charges of PD1 and PD2 are transferred to the bottom of the first structure electrode row 161. Reading to VCCD.

At this time, the signal charges of PD1 and PD2 are read at a timing such that they are transferred and added to the same vertical transfer packet in the VCCD, and after reading, V1, V3, V5 are read according to the timing chart of FIG. , V7 and V9 are applied with drive pulses to perform vertical transfer in the VCCD to drive the first selection output electrode group 251 and the second selection output electrode group 252 respectively, and below the first structure electrode row 161. The charge transfer from the VCCD 12 to the HCCD 33 is performed. Accordingly, the signal charge output to the HCCD 33 and the horizontal addition are simultaneously performed on the signal charge output through the first selection output electrode group 251 and the signal charge output through the second selection output electrode group 252. .

Next, the drive timing of the second structure electrode row 162 will be described.

As shown in the timing chart corresponding to the second structure electrode row 162 in FIG. 38, the readout pulse is not applied to each of the V2 to V18 electrodes, and the charge in the VCCD is not read out without executing the readout of the signal charge. Is controlled so as to move toward the drain portion 45.

The VCCD 12 under the second structure electrode row 162 does not have a signal charge associated with signal charge reading and there is no need for charge transfer control, but the VCCD 12 is not operated for a long time transfer. In this case, since the vertical transfer packet overflows due to the dark current component generated in the VCCD 12, reverse charge sweeping in the VCCD is performed to prevent the dark current component from affecting the subsequent output image. .

Also, in the timing chart of FIG. 39, reverse transfer is performed for a distance corresponding to nine electrodes for each horizontal blanking period, but it is not always necessary to perform for each horizontal blanking period. The drive pulse applied to the second structure electrode row 162 may be in the VL state, and for example, one screen may be transferred in reverse for each of a plurality of vertical blanking periods. In this way, it is possible to save power for sweeping out charges.

However, taking into account that the amount of charge generated by smear under high-intensity imaging is more significant than dark current, it is possible to cope with various imaging situations by performing a constant reverse transfer every horizontal blanking period. It is.

(3-1-2) Driving in Mode B FIGS. 40 and 41 show images obtained by reducing the output pixels by 1/9 in the vertical direction and 1/3 in the horizontal direction in the solid-state imaging device 103 (pixel addition in FIG. FIG. 6 shows a timing chart when executing the mode B that outputs (see the figure).

FIG. 40 shows the drive timing at the time of signal charge reading in the vertical blanking period, and FIG. 41 shows the drive timing of vertical transfer in the horizontal blanking period.

As shown in the figure, in this mode B, signal readout and addition processing are performed only by the second structure electrode row 162, and the first structure electrode row 161 directs the empty transfer packet immediately below it to the drain unit 45. A driving pulse is applied so as to be conveyed.

Therefore, the drive timing of the second structure electrode row 162 is exactly the same as the drive timing of the second structure electrode row 162 in FIG.

That is, by combining the read control and the vertical transfer control, the signal charges of PD3 and PD4 are transferred in the same vertical transfer packet and the vertical addition is executed.

Thereafter, according to the timing chart of FIG. 41, drive pulses are applied to V2, V4, V6, V8, V10, V12, V14, V16, V18 to perform vertical transfer in the VCCD 12, and the third selection output electrode group 253 To transfer charges from the VCCD 12 under the second structure electrode row 162 to the HCCD 33. In the third embodiment, the second structure electrode row 162 is transferred to the second HCCD 32 at the upper end, but in this example, the transfer is made to the HCCD 33 at the lower end, so the drive timing of the second structure electrode row 162 is as shown in FIG. The operation is opposite to the drive timing of the second structure electrode row 162 in FIG.

As shown in FIG. 40, when the mode B is executed, the VH level drive pulse is not applied to the first structure electrode row 161 to read out the signal charge, and the first structure electrode row is not read. The movement of the signal charge by the vertical transfer packet in the VCCD 12 according to 161 is directed toward the drain part 45, and the charge of the dark current component generated in the VCCD 12 is swept out.

Also, in the timing chart of FIG. 41, reverse transfer is performed for a distance corresponding to five electrodes for each horizontal blanking period. However, as in the case of mode A, it is not always necessary to perform it for each horizontal blanking period. For example, a method may be used in which one screen is collectively transferred in reverse every a plurality of vertical blanking periods.

(3-2) In the case of parallel drive in modes A and B In the above description, the drive timing in the case of operating modes A and B separately has been described, but the drive timing should be devised even if there is only one HCCD. Thus, the two modes can be operated in parallel.

42 to 46 show timing charts when the mode A and the mode B are simultaneously operated in the solid-state imaging device 103. FIG.

As described above, the number of added pixels in mode A is 4 pixels in total, 2 pixels in the vertical direction and 2 pixels in the horizontal direction, and the number of added pixels in mode B is 2 pixels only in the vertical direction. Here, it is assumed that a high-resolution image output at a specific frame rate is performed in mode A while a low-resolution image at a high frame rate is output in mode B. The operation will be described on the assumption that data is output at a double frame rate.

(3-2-1) Timing of Switching Drive Pattern First, FIG. 42 shows the timing of switching the drive pattern at the frame time level. The vertical sync signal VSYNCA in mode A and the vertical sync signal VSYNCB in mode B are shown. , Horizontal synchronization signal HSYNC common to modes A and B, signal charge reading drive pattern of the solid-state imaging device 103 (hereinafter referred to as “reading drive pattern”) ChAB and ChB, vertical transfer drive pattern (hereinafter referred to as “vertical driving”). Pattern ") is a diagram describing the relationship between P1 and P2 and the horizontal line output in which mode the signal output in the interval between the vertical synchronizations.

For example, at time T2, the vertical drive pattern P1 is applied to output the 1st horizontal signal of mode A, and at time T5, the vertical drive pattern P2 is applied to output the 2nd horizontal signal of mode B. Yes.

In the case of a configuration in which a known optical black area is provided in the vertical direction and the signal (vertical OB signal) is also output, this may be included in the horizontal line output, but here the description is simplified. Therefore, it is described that the output starts from the 1st horizontal signal.

Further, the pulse position and width of each vertical synchronization signal need only be such that the synchronization pulse interval between VSYNCAs and between VSYNCBs has a uniform period. As described above, mode B has a frame rate twice that of mode A. Therefore, the VSYNCB issuance period is exactly twice as long as the VSYNCA issuance period.

The output signals Bn and Ax at times T6 and T11, that is, the nth horizontal line in mode B and the xth horizontal line in mode A correspond to FIG. 37, and the final horizontal line output in each of mode A and mode B It shows that there is. As described above, the present embodiment enables the parallel execution of different modes by executing the horizontal line output period of the other mode following the horizontal line output period of one mode.

Note that the number of output horizontal lines x in mode A and the number n of output horizontal lines in mode B are in a relationship of x> n. In the present embodiment, mode A is thinned vertically by 1/5, and mode B is vertically 1/9. Since it is thinning out, the ratio of each value is close to x: n≈9: 5.

Since the frame rate ratio of each mode is set to 1: 2 with respect to the output horizontal line number ratio x: n≈9: 5, after the final output (Ax) of mode A in one frame is made, Before the vertical synchronization signal VSYNCA and the vertical synchronization signal VSYNCB are generated, it is necessary to adjust the frame rate by inserting a mode A dummy output several times. FIG. 42 shows an example in which the vertical drive pattern P1 is executed at T13 between T11 and T14, and the dummy output D of mode A is executed only once. In practice, the difference between x and 2n is shown. In this embodiment, in the dummy output section, the vertical drive patterns P1 and P2 are basically exchanged in the same manner as in the other output portions. I will do it.

(3-2-2) Read drive pattern ChAB
FIG. 43 shows an example of the read drive pattern ChAB executed at times T1 and T14 in FIG.

The signal charge readout in mode A is executed by the first structure electrode row 161, and the signal charge read out by applying a read pulse to the V3 electrode at time t6 and the signal read out by applying the read pulse to the V7 electrode at time t7. Control for vertically adding charges and signal charge reading in mode B are executed by the second structure electrode row 162, and the signal charges read by applying a read pulse to the V4 electrode at time t2 and applied to the V12 electrode at time t3. Control is performed to vertically add signal charges read by applying a read pulse.

The level control of the substrate potential VSUB of the solid-state image sensor 103 is the same as that described with reference to FIG. 34 of the third embodiment, and the mode B signal charge in which the number of added pixels is small and the saturation capacitance per pixel is set high. The readout is performed prior to the readout in mode A, and then the VSUB level is raised after time t5 to lower the saturation capacity of one pixel, thereby lowering the saturation capacity per pixel when the number of added pixels is large. Mode A signal charge readout is performed.

After reading out of mode A, the VSUB level is reset again at time t8 and maintained at VSUB during the exposure of the next frame to increase the dynamic range of the photodiode 11.

(3-2-3) Read drive pattern ChB
FIG. 44 shows an example of the read drive pattern ChB of the solid-state image sensor 103 executed at time T8 in FIG.

Here, only the signal charge readout in the next frame of mode B in which the signal output for one frame has been completed is performed by driving the second structure electrode row 162. Of the read drive pattern ChB, the patterns of the electrodes related to mode A (V1, V3, V5, V7, V9, S1, S2, B1, and B2) are electrodes related to mode A in the vertical drive pattern P2 described later. This is the same as the drive pattern (see FIG. 46).

This is because the vertical drive patterns P1 and P2 are alternately executed as shown in FIG. 42, and the vertical drive patterns at times T7 and T9 sandwiching the read drive pattern ChB at time T8 are P1 patterns. This is to maintain the continuity of the vertical drive pattern related to mode A.

On the other hand, if the vertical drive pattern P2 is before and after the read drive pattern ChB at time T8 in FIG. 42, the electrode drive pattern related to mode A in the read drive pattern ChB is the vertical drive pattern P1. The electrode drive pattern related to mode A is applied (see FIG. 45). Since only mode B is driven, the VSUB level is kept low.

(3-2-4) Vertical drive pattern P1
FIG. 45 is a diagram of the vertical drive pattern P1 driven in the horizontal blanking period.

In the vertical drive pattern P1, the first structure electrode row 161 related to mode A does not transfer the signal charge in the imaging region, and drives the first selection output electrode group 251 and the second selection output electrode group 252. Then, the stored charge in the corresponding storage unit is transferred to the HCCD 48.

That is, without changing the drive patterns of the V1, V3, V5, V7, and V9 electrodes, only the drive patterns of the S1, S2, B1, and B2 electrodes are changed, and the signal accumulated immediately below the S1, S2 electrodes at time t1. The charge is transferred to the HCCD 33 at times t2 to t4.

With respect to mode B, vertical transfer of signal charges in the imaging region by driving the second structure electrode row 162 and signal charge accumulation immediately below the third selection output electrode group 253 are performed, but transfer from the VCCD 12 to the HCCD 33 is performed. Not performed (B3 electrode remains in VL state).

That is, the signal charges stored in the VCCD 12 immediately below the electrodes V10, V12, and V14 are transferred by a distance corresponding to nine electrodes from time t2 to t19, and are in front of the third selection output electrode group 253 at time t1. The signal charges are maintained in a state where charges are accumulated under the S3 electrode of the third selective output electrode group 253.

(3-2-5) Vertical drive pattern P2
FIG. 46 is a diagram showing the vertical drive pattern P2 in the horizontal blanking period.

In this vertical drive pattern P2, in contrast to the case of FIG. 45, with respect to mode A, signal charges are transferred and signal charges are stored in the imaging region, and no transfer is performed from VCCD 12 to HCCD 33.

That is, the signal charges accumulated in the VCCD 12 immediately below the V3, V5, and V7 electrodes of the first structure electrode row 161 are transferred by a distance corresponding to five electrodes from time t3 to t14, and the first, The signal charges existing before the second selection

output electrode groups

251 and 252 are stored immediately below the storage electrodes S1 and S2 of the first and second selection

output electrode groups

251 and 252, respectively.

In the electrode related to mode B, the signal charge in the imaging region is not transferred, and the charge stored immediately below the third selective output electrode group 253 is transferred from the VCCD 12 to the HCCD 33.

That is, without changing the drive patterns of the electrodes V2, V4, V6, V8, V10, V12, V14, V16, and V18, only the drive patterns of the S3 and B3 electrodes of the third selection output electrode group 253 are changed. The signal charge stored immediately below the S3 electrode at time t1 is transferred to the HCCD 33 at times t2 to t4.

As described above, the cycle of the vertical sync signal VSYNCB in mode B is set to twice the cycle of the vertical sync signal VSYNCA in mode A, and at the timing when the vertical sync signal VSYNCA and the vertical sync signal VSYNCB are generated simultaneously, The read drive pattern ChAB (FIG. 43) for simultaneously executing the B read drive is executed, and at the timing when only the vertical synchronization signal VSYNCB is generated, the read drive pattern ChB (FIG. 44) is executed to execute only the mode B read drive. Execute.

Then, between one vertical synchronizing signal and the next vertical synchronizing signal, the signal charge related to mode A is output to the HCCD 33 and the signal charge related to mode B is transferred vertically in the image area. P1 (FIG. 45) and the signal charge related to the mode B are output to the HCCD 33, and the vertical drive pattern P2 (FIG. 46) for performing the vertical transfer of the signal charge related to the mode A within the image area is alternately executed. By doing so, the two modes are executed in parallel.

(4) Camera Device A camera device equipped with the solid-state imaging device 103 according to the present embodiment is almost the same as the configuration shown in FIG. 33 except that the configuration of the front end unit 480 is the same as that shown in FIG. Although not particularly illustrated, the memory management unit 460 (FIG. 33) stores the output signal from the solid-state imaging device 103 in the memory unit 470 in accordance with the output timings of the mode A and the mode B in a distinguished manner. By controlling, image data of modes A and B can be obtained.

(5) Supplement Note that when driving the mode A and the mode B separately, at the operation timing of the vertical drive in the horizontal blanking period shown in FIGS. In FIG. 39, it is described that vertical reverse transfer of 9 electrodes (for 5 electrodes in FIG. 40) is performed, but this can be controlled by the temperature state and the imaging state.

That is, the generation amount of VCCD dark current increases at a high temperature, and noise charges mainly including smear increase in the presence of a subject with high illuminance. In these cases, the number of transfer stages is increased or What is necessary is just to discharge | emit by reverse transfer of a noise charge by performing reverse transfer frequently.

Also, the amount of generation of VCCD dark current decreases at low temperatures, and the noise charge when imaging under low illuminance conditions is dominated by VCCD dark current over the smear component. The reverse transfer may be performed only during a partial period within the frame time such as the vertical blanking period.

(6) Effects of Embodiment 4 According to the invention according to Embodiment 4, a plurality of different readout controls and a plurality of vertical charge transfer controls can be performed on each structure electrode array in the solid-state imaging device 103. Is possible.

In addition, it is possible to simultaneously output multiple images with different vertical thinning rates by changing the number of vertical drive phases in each structure electrode array, and further, saturation in each mode by controlling the substrate potential level in combination. Output optimization can also be realized.

Furthermore, when the image in one mode is not used, a good image in which both horizontal thinning and pixel addition are compatible can be obtained by reversely transferring the noise component in the non-signal readout column VCCD and discharging it to the drain side.

<Other supplementary matters>
(1) The color filter is a primary color Bayer array, but is not particularly limited.

In the above embodiment, an example is given in which a horizontal two-pixel period is arranged on the premise of the Bayer arrangement. However, if the first and second structure electrode arrays are arranged in accordance with the usage application and the arrangement period of the color filters, Good.

(2) The first structure electrode row 161 and the second structure electrode row 162 are not limited to the connection state as shown in FIG. 2. For example, the first structure electrode row 163 and the second structure electrode row as shown in FIG. A connection state such as 164 may be used. That is, the first and second structural electrode columns control the application of the driving pulse if the connection state between the driving electrode 16 and the first wiring 13 and the second wiring 14 of the horizontal wiring portion 15 is different in each row. As a result, horizontal thinning readout control and vertical transfer control are possible, and various other connection patterns can be considered.

(3) In addition, although the shapes of the first wiring 13 and the second wiring 14 in the horizontal wiring portion 15 of each row are vertically symmetric in FIG. 2, they are not necessarily required and may be asymmetric.

48 is a plan view showing the configuration of the imaging unit of the solid-state imaging device in this case, and FIGS. 49 (a) and 49 (b) are views taken along lines EE ′ and FF ′ of FIG. 47, respectively. A cross-sectional schematic diagram is shown.

As shown in FIG. 48, the first wiring 13 ′ and the second wiring 14 ′ are asymmetrical in the vertical direction. As shown in the schematic cross-sectional views of FIGS. The wiring on the side connected by the drive electrode 16 and the contact 17 has a large width, and the other wiring does not have a large width.

FIG. 49 (c) shows a cross-sectional view in the case where a light shielding film is further formed in the example of FIG. 49 (b). As shown in the figure, a step may occur in the shape of the light shielding film provided on the upper part of the VCCD and the wiring, and it may be difficult to ensure the flatness important for the image sensor.

Regarding the selection of the shapes of the first wiring 13 and the second wiring 14, if importance is attached to the uniformity of device formation related to flatness, the first wiring 13 and the second wiring 14 as shown in FIGS. For both of the wirings 14, the structure may be selected according to the purpose, for example, if the wiring width is expanded and the capacitance between the wirings is reduced in consideration of power consumption, the wiring width is not expanded.

(4) In the above embodiment, the first structure electrode row 161 and the second structure electrode row 162 are alternately arranged or combined as a group of structure electrode rows combined in a total of 3 rows, and this is repeated in the horizontal direction. Although arranged, more columns may be used as the arrangement unit. In this case, further diversification of drive modes becomes possible, and for example, a total of five structure electrode array groups each composed of one first structure electrode array 161 and four second structure electrode arrays 162 are provided. When the arrangement unit is used, the horizontal thinning rate can be reduced to 1/5, which contributes to the improvement of the output pixel reduction rate.

In the above embodiment, the selection output electrode group (sub-selection output unit) to which the independent drive pulse is applied is divided into three types of first selection output electrode group 251 to third selection output electrode group 253. However, four or more types may be used.

Further, the timing chart showing the drive timing shown in each embodiment is appropriately changed according to the number of the structured electrode row groups, the number of the selective output electrode groups, and the target drive mode (pixel addition example). .

(5) As described above, the horizontal wiring portion 15 of each row can be arranged with only the first wiring 13 and the second wiring 14, the arrangement of the first structure electrode row 161 and the second structure electrode row 162, and the selection output portion 20. By combining the two, a sufficient output pixel reduction effect can be obtained and a variety of drive modes can be ensured. However, the horizontal wiring portion 15 may include three or more wirings. In accordance with this, in addition to the first structure electrode row 161 and the second structure electrode row 162, a third structure electrode row, a fourth structure electrode row, and the like are formed, and these are arranged at a constant period, whereby the drive mode Can be further diversified.

In such a case, not all of the drive electrodes in each structural electrode column need to be partially connected to the drive electrodes of other structural electrode columns in the same row even if they are not different from the connection state with the horizontal wiring portion. For example, even if connected to the same first wiring 13, if the connection state is periodically different as a whole when viewed as the entire imaging unit, a certain output pixel reduction rate can be obtained and various types of driving can be performed. Mode execution may also be possible.

(6) In the above embodiment, the description has been given of the VCCD having five-phase driving or nine-phase driving. However, according to the present invention, driving of any number of three or more phases is possible. The optimum number of drive phases may be selected in consideration of the number of horizontal lines to be output and the saturation capacity of the VCCD.

However, considering the saturation capacity and barrier formation in the charge transfer in the VCCD, there are few merits in the three phases, and there are five or more phases in which the number of phases required for barrier region formation required for the transfer is less than half of the number of driving phases. It is considered appropriate.

Also, the pitch of the HCCD signal storage area (horizontal transfer packet) is set to 2 or 3 columns of VCCD, but the selection output electrode group is appropriately handled according to the pixel addition example and the type of drive mode. Therefore, other pitches can be handled.

(7) Supplement on substrate potential modulation control As described in the first, third, and fourth embodiments, by modulating the substrate potential VSUB according to the number of added pixels, an appropriate saturated output corresponding to the drive mode is obtained. However, a more optimal saturation output can be obtained by determining the substrate potential VSUB as follows.

In other words, the saturation capacity of a pixel in a solid-state image sensor generally varies from product to product, and an internal bias value management circuit is provided to adjust the saturation capacity of each pixel to a target level. It is possible to set an internal bias value according to.

This internal bias value management circuit has a plurality of series resistors and a plurality of fuse wirings connected in parallel to these resistors, and burns out the fuse wiring connected in parallel to the resistors according to the saturation characteristics of the solid-state imaging device, Thus, the optimum internal bias can be set for each product by controlling the voltage level generated by the internal bias value management circuit.

The actual substrate potential VSUB is defined as the above-mentioned internal bias added with the potential of the substrate potential adjustment signal φSUB applied from the drive unit 420 (see FIG. 15).

A substrate addition information management unit for pixel addition (hereinafter referred to as “potential information management unit”) is provided on the substrate of the solid-state imaging device. The potential information management unit stores a plurality of pieces of substrate potential information indicating the substrate potential optimized in advance for each product corresponding to the number of added pixels in each drive mode, and the control unit 440 (see FIG. 15). When the addition pixel substrate potential information switching signal (MSEL) indicating the addition pixel number switching is received, the substrate potential information (MO) corresponding to the addition pixel number is output from the solid-state imaging device to the drive unit 420.

The drive unit 420 determines the substrate potential adjustment signal φSUB based on the substrate potential information (MO) received from the potential information management unit and the values of the electronic shutter level and the non-electronic shutter level commonly set for all products. .

That is, the substrate potential adjustment signal φSUB is set to a preset electronic shutter level regardless of the driving mode of the solid-state imaging device when the electronic shutter is executed. In a period in which the electronic shutter is not applied, the non-electronic shutter level or a level obtained by adding a level defined by the substrate potential information (MO) to the non-electronic shutter level is set. Whether or not the level based on the substrate potential information (MO) is added to the non-electronic shutter level depends on the presence or absence of the substrate potential switching control signal (SUBC).

Therefore, first, the control unit 440 transmits a substrate potential information switching signal (MSEL) for addition pixels to the potential information management unit of the solid-state image sensor 100, and the substrate potential information (MO) corresponding to the number of added pixels is solid. When driving the pixel addition, the substrate potential switching control signal (SUBC) is transmitted to the driving unit 420 when switching the substrate potential VSUB, and the substrate electric information (MO) is transferred to the non-electronic shutter level. The substrate potential adjustment signal φSUB added with the level added by (1) is applied to the semiconductor substrate to be changed to a predetermined substrate potential VSUB.

Thereby, in the camera device, the substrate potential VSUB corresponding to the number of added pixels is set, and an optimum saturation output can be obtained.

(8) In each of the above embodiments, the drive pulses applied to each drive electrode, the selective output electrode group, and the like have been described on the premise that they are independent. It may be shared.

For example, in FIG. 21 and FIG. 22 showing the operation timing of the second embodiment, the drive pulse applied to the V1, V3, V5, V7, and V9 electrodes of the first structure electrode row 161 in the imaging region is the second structure. Since it is the same pattern as the V10, V8, V6, V4, and V2 electrodes in the electrode array 162, the number of drive pulse input terminals can be reduced by connecting the V1 and V10, V3 and V8, V5 and V6, and V9 and V2 electrodes. Can be reduced.

In addition, the drive electrodes in the first HCCD 31 and the second HCCD 32, the first SCD 1, the S 2 / B 2, and the S 3 / B 3 of the first, second, and third selection

output electrode groups

251, 252, and 253 outside the imaging region, The first output unit 41, the second output unit 42, and the like can be further reduced in size and cost by connecting the same operation timing and connecting the input terminals.

(9) In each of the above embodiments, only the driving timing when the output pixels are reduced has been described, but it is of course possible to output pixel signals of all pixels. For example, according to the configuration example of FIG. 5 according to the first embodiment, first, a read pulse is applied so as to perform vertical 5: 1 interlace with respect to all the drive electrodes 16 and read to the adjacent VCCD 12. For each vertical transfer, the first to third selection output electrode groups 251 to 253 may be driven in three steps for one horizontal line while being sequentially driven. By performing this for five fields, the pixel signals of all the pixels can be output without reducing the output pixels.

The present invention can efficiently reduce the number of output pixels while suppressing deterioration in image quality in a solid-state image sensor, and is particularly applicable to a solid-state image sensor having a large number of pixels and a camera device using the same.

10 Imaging unit 11 Photodiode 12 VCCD
13, 13 '1st wiring 14, 14' 2nd wiring 15 Horizontal wiring part 16 Drive electrode 17 Contact 18 Power

supply bus line

20, 210, 220 Selection output part 21 Storage part 22

Barrier part

30, 33 HCCD
31 1st HCCD
32 Second HCCD
40 output unit 41 first output unit 42 second output unit 50

semiconductor substrates

161 and 163 first

structure electrode row

162 and 164 second structure electrode row 251 first selection output electrode group 252 second selection output electrode group 253 second 3 selection

output electrode group

400, 401 camera device 410 lens unit 420 drive unit 430 timing generation unit 440 control unit 450 signal processing unit 460 memory management unit 470 memory unit 480 analog front end 490 display unit 495 operation unit

Claims

A plurality of photoelectric conversion elements are solid-state imaging elements arranged in a matrix,
A plurality of vertical transfer units that read out signal charges of the photoelectric conversion elements and transfer them in the vertical direction by applying a plurality of drive pulses to a plurality of vertical drive electrodes arranged along each column of the photoelectric conversion elements;
A plurality of horizontal wiring portions arranged along each row of photoelectric conversion elements;
A horizontal transfer unit that horizontally transfers the signal charges transferred from the plurality of vertical transfer units,
The vertical drive electrodes are individually provided corresponding to the individual photoelectric conversion elements, and each horizontal wiring portion includes first and second wirings extending in the horizontal direction. Selectively connected to either the first or second wiring of the horizontal wiring portion arranged in the same row as the vertical drive electrode;
When a group of vertical drive electrodes connected to the first or second wiring of each horizontal wiring portion is defined as a structure electrode array, a predetermined first structure electrode array, the first structure electrode array, A solid-state imaging device, wherein a second structure electrode column having a different connection state with the first and second wirings of the horizontal wiring portion in each row is arranged in combination in the horizontal direction.
The structure electrode array group in which the first structure electrode array and the second structure electrode array are combined to be a total of P arrays (P ≧ 3) is repeatedly arranged in the horizontal direction as an arrangement unit. The solid-state imaging device according to claim 1.
The solid-state imaging device according to claim 2, wherein the number of vertical drive phases of the first structure electrode array is different from the number of vertical drive phases of the second structure electrode array.
The horizontal transfer unit is connected to each vertical transfer unit via a selection output unit,
2. The solid-state imaging device according to claim 1, wherein the signal charges of the vertical transfer unit of the column selected by the selection output unit are transferred to the horizontal transfer unit at a predetermined timing.
The selection output unit includes a first sub selection output unit, a second sub selection output unit, and a third sub selection output unit to which drive pulses are applied independently,
5. The solid-state imaging device according to claim 4, wherein the first, second, and third sub-selection output units are respectively disposed between the vertical transfer units and the horizontal transfer units.
The horizontal transfer unit includes a first sub horizontal transfer unit disposed at one end of the vertical transfer unit and a second sub horizontal transfer unit disposed at the other end of the vertical transfer unit,
The signal charge transferred from the first structure electrode row is transferred to the first horizontal transfer unit,
The signal charge transferred from the second structure electrode array is transferred to the second horizontal transfer unit,
2. The solid-state imaging device according to claim 1, wherein the signal charge transfer directions of the first and second structure electrode arrays are opposite to each other.
The first sub-horizontal transfer unit is connected to a vertical transfer unit in which a first structure electrode array is arranged via a first selection output unit,
The second sub-horizontal transfer unit is connected to a vertical transfer unit in which a second structure electrode array is disposed via a second selection output unit,
The signal charge of the vertical transfer unit in the column selected by the first and second selection output units is transferred to the corresponding first and second horizontal transfer units at a predetermined timing, respectively. Item 7. The solid-state imaging device according to Item 6.
Each of the first and second selection output units includes a first sub selection output unit, a second sub selection output unit, and a third sub selection output unit to which driving pulses are applied independently.
The first, second, and third sub-selection output units are respectively disposed between each vertical transfer unit and the first or second horizontal transfer unit that is the transfer destination. The solid-state image sensor described in 1.
The first selection output unit includes first and second sub-selection output units, and the second selection output unit includes a third sub-selection output unit, and the first, second, and third A drive pulse is applied independently to the sub-selection output unit,
Each of the first and second sub-selection output units is disposed between a vertical transfer unit and a first sub-horizontal transfer unit in which the first structure electrode array is disposed,
The solid-state imaging device according to claim 7, wherein the third sub-selection output unit is disposed between a vertical transfer unit and a second sub-horizontal transfer unit in which the second structure electrode array is arranged. .
The solid-state imaging device according to claim 1, wherein a charge discharging unit to which a predetermined DC bias is applied is connected to an end of the vertical transfer unit on the side to which the horizontal transfer unit is not connected.
A solid-state imaging device according to claim 1;
A first drive pulse for driving the first structure electrode array of the solid-state imaging device and a second drive pulse for driving the second structure electrode array are generated, and the first and second structure electrode arrays are respectively generated. A solid-state imaging device comprising: a drive unit that applies the power.
The driving means includes
When driving one of the first or second structure electrode rows to read out signal charges from the corresponding photoelectric conversion element rows and vertically transfer them,
Stop the vertical transfer operation in the other structure electrode row that does not read out the signal charge, or read out the signal charge and execute the vertical transfer operation in the direction opposite to the vertical transfer direction. The solid-state imaging device according to claim 11, wherein a driving pulse is generated.
The driving means includes
The first and second drive pulses are driven so that the first structure electrode row is driven in the first mode, the second structure electrode row is driven in the second mode, and these modes are executed in parallel. It produces | generates. The solid-state imaging device of Claim 11 characterized by the above-mentioned.
The driving means includes
The first and second frame rates of the first mode for driving the first structure electrode row are K times (K is an integer of 2 or more) the frame rate of the second mode for driving the second structure electrode row. The solid-state imaging device according to claim 13, wherein the second driving pulse is generated.
The driving means includes
The first and second drive pulses are generated so that a horizontal line output period of one mode of the first and second modes is followed by a horizontal line output period of the other mode. Item 14. The solid-state imaging device according to Item 13.
The driving means includes
When the pixel addition number in the first mode is smaller than the pixel addition number in the second mode,
While setting the substrate potential of the solid-state imaging device at the time of reading the signal charge in the first mode to be the first potential,
Setting the substrate potential of the solid-state imaging device at the time of signal charge readout in the second mode to be a second potential higher than the first potential;
The substrate potential is controlled so that the substrate potential is maintained at a third potential which is lower than the first potential and the second potential during the exposure time by the photoelectric conversion element. Item 12. The solid-state imaging device according to Item 11.
The driving means includes
The signal charges of the pixels in the Mth row of the (N−2) th column and the (N + 2) th column are read out by the first structure electrode column, and the (M−2) th and (M + 2) th rows of the Nth column are read out. Each signal charge of the pixel is read out by the second structure electrode column and vertically added, and the signal charges of the (N−2) th column, the Nth column and the (N + 2) th column are horizontally added to obtain an addition output for four pixels. The solid-state imaging device according to claim 11, wherein the first and second drive pulses are generated so as to be performed (N and M are integers of 3 or more).
The driving means includes
The signal charges of the pixels in the (M−2) -th and (M + 2) -th rows of the (N−2) th column and the (N + 2) th column are read out by the first structure electrode column and vertically added, and the Nth column The signal charges of the pixels in the Mth row are read out to the second structure electrode column, and the signal charges in the (N−2) th column, the Nth column, and the (N + 2) th column are horizontally added and added for 5 pixels. The solid-state imaging device according to claim 11, wherein the first and second drive pulses are generated so as to perform (N and M are integers of 3 or more).
The driving means includes
After reading the signal charges of the pixels in the Mth column of the Nth row with the substrate potential of the solid-state imaging device set to the first potential, the substrate potential is set to a second potential higher than the first potential. Set,
After reading the signal charges of the pixels in the (M-2) th row and the (M + 2) th row in the (N-2) th column and the (N + 2) th column, the substrate potential is reset to the first potential,
The signal charges of the (N−2) th, Nth and (N + 2) th columns are horizontally added and output,
The solid-state imaging device according to claim 18, wherein the substrate potential is maintained at a third potential equal to or lower than the first potential during the exposure time.
A camera device comprising the solid-state imaging device according to any one of claims 11 to 19.