JPH0473347B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a frame transfer type image sensor suitable for photographing still images and an image pickup apparatus using the frame transfer type image sensor.

(Prior Art) Generally, in order to obtain a still screen suitable for a standard television system using a solid-state image sensor, it is necessary to obtain a so-called interlaced video signal for two fields.

However, frame transfer type CCD
(Charge Completed Device), such readout was previously thought to be impossible. That is, FIG. 1 shows the configuration of a conventional frame transfer type CCD, where 1 is an imaging section, 2 is a storage section, 3 is a horizontal transfer register, 4 is an output amplifier, and 5 is a signal output terminal.

Further, the PS is a cell, and a plurality of cells are arranged in rows and columns to constitute an imaging section 1 and a storage section 2, respectively. Each cell PS has a charge transfer function in the vertical direction in the figure, and the horizontal transfer register 3 has a horizontal transfer function.

Note that φ ₁ to _{φ 3} are transfer clocks for the imaging section, storage section, and horizontal transfer section, respectively.

Further, the area other than the imaging section, that is, the shaded area is shielded from light.

In the conventional CCD configured in this manner, image information incident on the imaging section is sampled by each cell and stored as charge information.

Thereafter, by supplying clocks φ ₁ to _{φ 3} , the charge information of the imaging section is transferred to the storage section at high speed and read out over an appropriate amount of time.

That is, after transferring the information in the storage section to the register 3 line by line, this line information is transferred to register ₃ by clock φ3.
Scanning line signals corresponding to the standard television signal are obtained sequentially by reading them over a horizontal scanning period, but since the standard television system uses 2:1 interlacing, the 1st and 2nd fields are The eyes scan different positions on the monitor screen for reproduction. Therefore, unless a two-field video signal interlaced with each other is obtained at the imaging stage, problems such as screen blurring and a decrease in resolution will occur during playback.

However, the conventional frame with the configuration shown in the first figure
With transfer type CCDs, it was considered impossible to read out the odd and even fields separately in the imaged screen.

In response to this, the present applicant proposed a new frame transfer type imaging device having a storage section in which the number of horizontal cells is more than twice the number of cells in the imaging section in Japanese Patent Application No. 181809/1982.

According to such an element, 1 formed in the imaging section
When vertically transferring the screen worth of playback to the storage unit, the above 1.
It becomes possible to separate and store information on odd-numbered lines and information on even-numbered lines of the information on the screen, and the above-mentioned problems can basically be solved.

(Purpose) The purpose of the first and third inventions of the present application is to further improve the frame transfer type CCD that the applicant had previously proposed in Japanese Patent Application No. 181809/1982.
To provide an inexpensive and reliable frame transfer type imaging device capable of capturing high-resolution still images by adopting a simple configuration capable of increasing yield, and an imaging device using the same. It is in.

Furthermore, the second object of the present invention is to read information from cells in the storage section using a frame transfer type that increases transfer efficiency regardless of the increase in the number of cells in the horizontal direction and facilitates signal sampling and holding. An object of the present invention is to provide an imaging device using an imaging device and a frame transfer type imaging device.

(Example) The configuration of an image sensor and an image pickup apparatus of the present invention for this purpose will be explained in detail based on an example.

FIG. 2 is a diagram for explaining the configuration of an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same elements. Note that the number of cells in the horizontal direction of the storage section 2 is the same as that of the imaging section 1.
The number of cells in the horizontal direction is twice as large as the number of cells in the horizontal direction. Furthermore, in this embodiment, the number of cells in the vertical direction of the storage section 2 is half the number of cells in the vertical direction of the imaging section 1, but generally the number of cells in the horizontal direction of the storage section is half the number of cells in the vertical direction of the imaging section 1.
It is good if it is at least twice as large, and 1/2 or more in the vertical direction.

In the illustrated embodiment, the imaging section 1 consists of pixels arranged in 8 rows and 4 columns, and the storage section 2 consists of pixels arranged in 4 rows and 8 columns, although in reality the number is much larger than this. 31 to 33 are first to third horizontal shift registers, respectively, and each horizontal shift register is controlled by a signal source 7, which will be described later, so as to read charges in a predetermined column of the storage section 2. Note that the number of horizontal shift registers may be two or four or more. T ₁ is a gate provided between the storage section 2 and the horizontal shift register 31, T ₂ is a gate provided between the registers 31 and 32, and T ₃ is a gate provided between the registers 32 and 33, respectively. 41 to 43 are horizontal shift registers 31 to 43, respectively.
This is an output amplifier for converting the charge signal read out from 33 into a voltage signal and reading it out. Further, 0 is a distribution section for appropriately distributing the charges in the cells of the storage section 2 to the horizontal shift registers. _φ1
is a shift pulse for vertically shifting the charge in the imaging section, and _φ20 is the first, fourth, and
5th and 8th columns (hereinafter these columns will be referred to as 201, 204,
The shift pulse φ ₂₁ is for vertically shifting the charges in the 2nd, 3rd, 6th, and 7th columns (referred to as 202, 208) from the right side in the figure (hereinafter these columns will be referred to as 202, 208).
3, 206, and 207), φ _T is a gate for controlling gates T ₁ to T ₃ and the distribution section, and φ ₃₁ to φ ₃₃ are horizontal shift registers 31 to 33, respectively. These are shift pulses for horizontally shifting the charges of 33, and these pulses are supplied from a signal source 7, which will be described later.

Note that, for example, a color separation filter as shown in the third figure is attached to the surface of the imaging section 1.

Here, R is a color filter that passes red, B is blue, and G is a color filter that passes green color light. Of course, the color pattern of the color separation filter is not limited to this.

FIG. 4 is a block diagram of an imaging, recording, and reproducing apparatus using the imaging element of the present invention. ) or movie (M), signals with timings as shown in FIG. 5, FIG. 6, or FIG. 7 are generated.

Further, the video signals Vout31 to Vout33 obtained through the output end of the image sensor are subjected to signal processing such as sample hold, γ correction, and aperture correction in the process circuit 10, and then sent to the recording circuit 11 which performs modulation, etc. Recording medium 1 via recording head 12
Recorded in 3. Further, the output of the process circuit 10 can be directly monitored on the television monitor 16.

Reference numeral 14 denotes a reproducing head, and the signal picked up by the head can be monitored on a monitor 16 after being appropriately demodulated in a reproducing circuit. Further, LS is an imaging optical system, which guides subject light to the imaging section 1 and forms an image.

FIG. 5 is a schematic diagram of the area around the boundary between the imaging section and the storage section of the second illustrated element, and shows an example of single-phase drive. CS
is a channel stopper, PS1 is a polysilicon electrode for supplying pulse _φ1 to the imaging section 1,
It covers the surfaces of regions A and B, which have different potential levels, in the semiconductor substrate.

Further, PS20 and PS21 cover the surfaces of regions A' and B' which have different potential levels in the storage section, and send pulses φ ₂₀ and φ ₂₁ to the storage section 2, respectively.
This is for applying to each column of .

In addition, the C area and D area of the imaging section and the storage section
The C' region and the D' region are virtual electrode regions each having a constant potential level and formed in the semiconductor substrate by ion implantation or the like.
Such a virtual electrode structure is, for example, disclosed in Japanese Patent Application Laid-Open No.
Something like the one seen in Publication No. 11394 is fine.

Note that the areas A, B, C, D or
One cell is formed by A', B', C', and D'.

Also, each area A, B, C, D, A', B', C',
Potential levels P(A), P seen from the electron of D′
(B), P(C), P(D), P(A'), P(B'), P(C')
,P
For example, (D') has the following relationship.

That is, if the voltage applied to each electrode is the same, P(A)=P(A'), P(B)=P(B'), P(C)=P(C'
),
P(D)=P(D') Also, when low level signals are applied to electrodes PS1, PS20, and PS21, P(A)>P(B)>P(C)>P(D) P(A ')>P(B')>P(C')>P(D') When high level signals are applied to one electrode PS1, PS20, PS21 P(C)>P(D)>P(A )>P(B) P(C')>P(D')>P(A')>P(B').

Further, in the embodiment of the present invention, each cell of the storage section 2 is wired so that a common voltage is applied to two predetermined adjacent cells. That is, electrode PS2
The electrodes PS20 and PS21 are respectively arranged for two predetermined adjacent cells, and the electrodes PS20 and PS21 are commonly connected by wiring.

Therefore, the electrodes for controlling the potential of each cell can be made large, which simplifies manufacturing. Furthermore, the wiring pattern is also simplified.

Furthermore, in this embodiment, some of the cells in the storage section are arranged vertically shifted from the remaining cells, so when wiring the electrodes PS20 and PS21 separately, the same electrodes can be connected horizontally. . Therefore, for example, the electrodes PS20 are connected by a horizontal comb-like wiring pattern in which the right side in the figure is commonly connected.
The PS21 can be connected by a comb-shaped wiring pattern in which the left side is connected in common by providing the PS21 in the gaps between the comb teeth, thereby simplifying the element manufacturing process.

Fig. 6 is a diagram schematically showing the -' cross section in Fig. 5 to explain the state of such potential level, where the solid line shows the voltage when a low level signal is applied to each electrode, and the broken line shows the voltage when a low level signal is applied to each electrode. This is the state when a high level signal is applied. Virtual electrode areas C, D, C′,
D′ is always maintained at a constant potential.

In addition, IL is an insulating layer such as SiO ₂ (silicon oxide),
SB is a semiconductor substrate such as Si (silicon), VE is a virtual electrode, Al20 and Al21 are electrodes PS20 and PS2, respectively.
This is an aluminum wiring for applying pulses φ ₂₀ and φ ₂₁ to 1.

Therefore, for example, when the clock _φ1 is once set to a high level and then lowered to a low level, the charges mainly stored in the area B at this fall are transferred to the area D as shown in the figure. That is, at the falling edge of the clock to each electrode, B→D or B'→D' is transferred.

Further, the charge in D or D' is transferred to region B or B' by setting each electrode to a high level. That is, at the rising edge of the clock, D→B or
Transfer from D′ to B′ is performed.

With this structure, if clocks _φ20 and _φ21 are alternately supplied in synchronization with clock _φ1 , the fifth
Information in each row of the image capturing section in the figure is distributed to a predetermined column of the storage section.

FIG. 7 is a diagram showing an example of an electrode pattern around the boundary between the storage section 2 and the horizontal shift registers 31 to 33 of the image pickup element in FIG. show.

Furthermore, areas A″, B′, C″, D″, A, B, C,
Potential level P for electrons of D
(A″), P(B″), P(C′), P(D″), P(A
), P
(B″), P(C), and P(D) are P(A)=P(A″)=P(A) P(B)=P(B″) when the voltage applied to each electrode is the same. =P(B) P(C)=P(C″)=P(C) P(D)=P(D″)=P(D) holds.Also, A″, B″, C″, D '' or the combinations of A, B, C, and D each form one cell.

Incidentally, as shown in FIG. 7, when the storage section and a plurality of horizontal shift registers are connected, a distribution section 0 is provided,
In this distribution section 0, the cells near the boundary between the storage section and the horizontal shift register are arranged vertically shifted, so when distributing the charge of each cell of the storage section to each horizontal shift register, the electrodes are arranged three-dimensionally. There is no need to cross the line, making it more resistant to noise and simplifying the manufacturing process. In other words, the distribution section 0 is composed of the bottom row of the storage section, the gate electrode _T1 , etc., and distributes the charges of multiple columns vertically transferred at the same timing within the storage section with a predetermined different delay for each predetermined column. By applying this signal, it is converted into a time-series signal, which is sequentially input into a horizontal shift register. In other words, this distribution section 0 is a parallel -
This is a serial conversion means.

Note that in this embodiment, the gate electrode T ₁ is
Parallel-to-serial conversion is performed by using the method, but the distribution section is formed by simply changing the length of each column of the storage section 2 little by little and configuring it so that information from multiple columns is guided to one column of cells. You may do so. The sixth invention of the present application also includes such a device.

Further, in this embodiment, some cells of the storage section are vertically shifted relative to other cells, but the structure of the distribution section is not limited to such a structure of the storage section. For example, even a storage section structure as shown in Fig. 7 of Japanese Patent Application No. 181809/1983 is applicable.

Next, the operation will be explained.

FIG. 8 is a diagram showing an example of the output timing of the signal source 7 in the configuration shown in the fourth figure. In the figure, the pulses φ ₁ , φ ₂₀ , φ ₂₁ , φ ₃₁ to _{φ 33} , and φ _T lower the potential level of each pixel in the image sensor relative to electrons when they are at a high level, and when they are at a low level, as described above. It is configured to increase the potential level.
When the imaging trigger switch 8 is activated, unnecessary charges are first discharged by supplying high-speed pulses φ ₁ , φ ₂₀ , φ ₂₁ , φ _T , φ ₃₁ to φ ₃₃ .

Next, when a predetermined accumulation time T _INT has elapsed [period (4-0)], the charge in the imaging unit 1 is shifted row by row at high speed downward in FIG. 2 by pulse φ ₁ in period (4-1). .

Also, among the information in each row that is shifted at this time, the information in odd rows is shifted to columns ₂₀₁ , 204,
205, 208, and the information in even rows is transferred to columns 202, 203, 206, 207 by pulse φ ₂₀ .
is transferred and stored. FIG. 2 shows the state in which one frame's worth of information from the imaging section is distributed and transferred to the storage section in this manner.

In addition, in this state, the charges in the bottom row of the storage section in the figure are in the wells 305, 325, 329, and 33 in FIG.
8,346,350 have been accumulated.

Also, the charges accumulated in each well are
Consider this in association with charges A4, B4, B3, A3, A2, and B2 in the figure.

That is, since the striped color separation filter shown in FIG. 3 is provided, charges A4 and B4 correspond to red, B3 and A3 correspond to green, and A2 and B
2 is a charge corresponding to blue.

Next, among the information stored in the storage unit 2 through the above process, examples 208, 205, 204, 201
Pulse φ ₂₁ , φ ₃₁ ~
Perform with φ ₃₅ and φ _T.

That is, first, in period (4-2), by supplying φ _T three times, the charges in wells 305, 338, and 346 are sequentially shifted vertically, and are finally stored in wells 317, 313, and 309, respectively. Ru.

Next, in period (4-3), high-speed pulses are supplied as pulses φ ₃₁ to _{φ 33} to the wells 317, 313, 30 while keeping pulse φ _T at low level.
9 is horizontally shifted to the left in FIG. The total of these periods (4-2) and (4-3) is set to, for example, one horizontal period (1H). Therefore, the first signal of the image accumulated in the imaging unit 1 during the period (4-0) is read out during the period (4-3).

Also, by applying one pulse φ ₂₁ during this period (4-3), the well 30 in FIG.
The charges in 1,334,342 are in well 30, respectively.
It is stored at 5,338,346.

Therefore, when 3 pulses of φ _T are supplied in period (4-4), wells 305 and 33 are
The charges in 8,346 are transferred to the horizontal shift register 33,
32 and 31.

In the following period (4-5), by repeating the same sequence, only the charges in the columns 208, 205, 204, etc., that is, the charges corresponding to the odd rows of the imaging section 1, are sequentially read out. These periods (4-1) ~
The sum of (4-5) is set to correspond to just one vertical period. Then one vertical period (4-
In step 6), charges in columns 207, 206, 203, 202, etc. are sequentially read out row by row in the same manner by pulses φ ₂₀ , φ _T , φ ₃₁ to _{φ 33} .

In this way, in the still mode of the present invention, signals for two fields simultaneously formed in the imaging section are combined into one.
Since each field can be sequentially interlaced and read out, a still image signal with high resolution and no blur can be obtained.

Next, FIG. 9 is a timing chart of the output pulses of the signal source when the switch 9 shown in FIG.
During this period, similarly to period (4-1) in FIG.
05, 208, information on even rows in columns 202, 20
3, 206, and 207, and in the period (9-2), first give one pulse φ ₂₀ to the wells 305, 325, 338, and 32.
Add the charges of 9,346 and 350. That is, the second
Charges A4 and B4 in the figure, B3 and A3, A2 and B2,
A1 and B1 are added, and then three pulses φ _T are applied to capture the charges into the registers 33 to 31.

Next, in period (9-3), this is horizontally transferred by pulses φ ₃₁ to _{φ 33} , and pulses φ ₂₀ and φ ₂₁ are transferred by 1, respectively.
By applying a pulse, charges C4 and D4 in Fig. 2,
Add D3 and C3, C2 and D2, D1 and C1,
Thereafter, this sequence is repeated to obtain one field signal. Note that the total of periods (9-1) to (9-3) is set to be one vertical period.

Thereafter, by transferring the information of the imaging unit to the storage unit again in the period (9-4), the period (9-2)
The charge signals formed in the imaging unit during the period from 9-3 to 9-3 are distributed and stored in the storage unit in the same manner as in the period (9-1).

After that, in the period (9-5), this accumulated information is added and read out, but at this time, the charge information to be added is shifted by one pulse between pulses φ ₂₀ and φ ₂₁ . The combination of these changes.

That is, unlike period (9-2), pulse φ ₂₀ is changed to φ ₂₁
Since one pulse is output in advance, (A1 to A4) of the imaging section are read out without being added, and (B1 to B4), (C1 to C4), and (D1 to
D4) and (E1-E4), (F1-F4) and (G1-G4) are added and read out as one line, and finally (H1-H4) is read out as one line.

Therefore, the signals read out in periods (9-2) and (9-3) and the signals read out in period (9-5) are interlaced with each other. Furthermore, since two rows are added, the sensitivity of the element is also improved.

Next, FIG. 10 is a diagram showing a second embodiment of signal readout timing in movie mode.

In this embodiment, when adding odd numbered rows and even numbered rows, this is done at the boundary between the imaging section and the storage section.

The charges accumulated in the imaging section during the period (10-1) are transferred to the storage section 2 by the pulses φ ₁ , φ ₂₀ , φ ₂₁ during the period (10-2), but at this time, for every two pulses of φ ₁ By applying one pulse of φ ₂₀ and φ ₂₁ at the same time, the added charges are almost equally transferred to each pair of columns of the storage section. Then, in the period (10-3), by first applying one pulse φ ₂₀ , columns 208 and 207 are applied to well 305 in FIG. 7, and column 2 is applied to well 338.
06 and 205, rows 204 and 203 in well 346
Collect and add the charges, then transfer these charges to the horizontal shift registers 31 to 33 by φ _T ,
Furthermore, it is read out in the horizontal direction by φ ₃₁ to _{φ 33} . After that
After applying one pulse φ ₂₀ and one pulse φ ₂₁ every 1H, similar reading is performed to sequentially read out the addition output.

Next, the charges accumulated in the imaging section during periods (10-3) and (10-4) are vertically transferred again during period (10-5), but at this time pulses φ ₁ , φ ₂₀ , φ ₂₁ By shifting the timing of the period (10-2) from that of the period (10-2), the combination of charges added near the boundary between the imaging section and the storage section is shifted by one row, so that an interlacing effect can be obtained.

After period (10-6), period (10-3), (10-
Reading similar to 4) is performed.

In this way, even if the capacitance of each cell in the storage section is small, the addition output is once divided and then stored in each cell, thereby preventing charge from overflowing.

(Effect) As explained above, according to the present invention, the frame
In the transfer type imaging device, the number of cells in the horizontal direction of the storage section is at least twice the number of cells in the horizontal direction of the imaging section, and in the first invention of the present application, the number of cells in the horizontal direction of the storage section is set to be at least twice the number of cells in the horizontal direction of the storage section. Since a plurality of independent electrodes are provided for applying a common voltage to each cell, the electrodes for controlling the cells in the storage section can be made relatively large, which facilitates manufacturing and improves yield.

In addition, since the number of some cells in the storage section is vertically shifted from the other cells, a connection pattern can be easily manufactured when each cell is controlled independently.

Furthermore, in the second invention of the present application, a plurality of horizontal shift registers are provided, and a distribution section is provided between the storage section and the horizontal shift register in order to distribute information in a predetermined column of the storage section to a predetermined corresponding horizontal shift register. Because of this, the horizontal readout frequency can be kept low, the transfer efficiency is high, and signal processing is facilitated.

Further, according to the third invention of the present application, by varying the transfer method after the signal obtained by the imaging section is accumulated in the storage section, the signal charge obtained by one exposure can be transferred to an integer. It is possible to obtain a signal for two raced fields, or a highly sensitive signal for one field.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional frame-transfer type image sensor, FIG. 2 is a schematic configuration diagram of a frame-transfer type image sensor of the present invention, FIG. 3 is a diagram of an embodiment of a color separation filter, and FIG. The figure is a schematic diagram of an imaging, recording, and reproducing apparatus using the image pickup element of the present invention, FIG. ′
A schematic diagram of the cross-sectional potential, FIG. 7 is a diagram of the electrode pattern near the boundary between the storage section and the horizontal shift register of the device shown in FIG. 2, FIG. 8 is a timing diagram of the device shown in FIG. 4 in still mode, and FIG. 9 is a diagram of the same movie. A first example diagram of the timing in the mode, and FIG. 10 are a second example diagram of the same. 0...Distribution section, 1...Imaging section, 2...Storage section, 3...Horizontal shift register, 4...Amplifier, 6...Gate,
PS20, PS21...electrode, 7...signal source.

Claims (1)

[Scope of Claims] 1. An imaging section having a plurality of charge transfer register rows; and a system for distributing and storing odd-numbered and even-numbered signals of each row of the imaging section into first and second columns, respectively. An accumulation section having a number of charge transfer register columns that is twice or more than the number of charge transfer register columns described above, and a storage section that sequentially stores the signals of the first column and second column accumulated in the charge transfer register columns of this accumulation section every field period. control means for forming interlaced video signals for each field period by selectively reading them, and the charge transfer register array of the storage section is configured to store the odd-numbered signals or the even-numbered signals. An imaging device characterized in that charge transfer columns are arranged adjacent to each other and a common transfer electrode is disposed in these mutually adjacent charge transfer columns. 2. The imaging device according to claim 1, wherein the transfer electrodes are arranged such that adjacent electrodes are shifted in the column direction. 3. An imaging section having a plurality of charge transfer register rows, and the number of charge transfer register rows for distributing and storing odd-numbered and even-numbered signals of each row of this imaging section in the first and second columns, respectively. A storage section having a number of charge transfer register rows that is more than twice as many as A control means for forming mutually interlaced video signals for each field period, a plurality of horizontal transfer registers for reading out the video signal, and a distribution section for distributing the video signal to each of the horizontal transfer registers. An imaging device characterized by: 4. An imaging section having a plurality of charge transfer register rows, and the number of charge transfer register rows for distributing and storing odd-numbered and even-numbered signals of each row of this imaging section in the first and second columns, respectively. an accumulation section having two or more charge transfer register rows, and in which transfer electrodes are provided independently in the first and second charge transfer register rows; By supplying a transfer signal to the storage section, the signals of the first column and the second column accumulated in the charge transfer register column are sequentially and selectively read out for each field period, thereby generating video signals interlaced with each other. control means for forming a video signal in each field period, or by simultaneously supplying a transfer signal to each of the transfer electrodes, to form a video signal obtained by adding the signals of the first column and the second column; An imaging device characterized by: