WO2011043613A2 - Procédé de fabrication d'un condensateur mim ayant une nanostructure - Google Patents

Procédé de fabrication d'un condensateur mim ayant une nanostructure Download PDF

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Publication number
WO2011043613A2
WO2011043613A2 PCT/KR2010/006875 KR2010006875W WO2011043613A2 WO 2011043613 A2 WO2011043613 A2 WO 2011043613A2 KR 2010006875 W KR2010006875 W KR 2010006875W WO 2011043613 A2 WO2011043613 A2 WO 2011043613A2
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WO
WIPO (PCT)
Prior art keywords
nanostructure
mim capacitor
substrate
interface
insulator
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Application number
PCT/KR2010/006875
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English (en)
Korean (ko)
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WO2011043613A3 (fr
Inventor
김삼동
이재서
설우석
오정훈
Original Assignee
동국대학교 산학협력단
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Publication of WO2011043613A2 publication Critical patent/WO2011043613A2/fr
Publication of WO2011043613A3 publication Critical patent/WO2011043613A3/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a method of manufacturing a high capacity MIM capacitor, and more particularly, to a MIM capacitor and a manufacturing method capable of large-scale, low-cost mass production without using expensive ALD equipment.
  • a high-capacity capacitor in which a carbon nanotube (CNT) structure called a super capacitor is coated with an oxide electrode, has started to appear, and much research is being conducted.
  • the supercapacitor uses a redox reaction, it is difficult to apply to a high-power electric vehicle due to its low power density.
  • a method of introducing a high dielectric constant k dielectric material into the dielectric layer may be considered.
  • a dielectric material having a high dielectric constant k is used, a high-capacity MIM capacitor having a charge storage capacity is secured by changing an electrode structure from a typical silicon-insulator-silicon (SIS) structure to a metal-insulator-metal (MIM) structure. Is to design.
  • SIS silicon-insulator-silicon
  • MIM metal-insulator-metal
  • an embodiment of the present invention has been made to solve the above problems, a large-capacity, low-capacity MIM capacitor having a large capacity capable of mass production of low cost without using the existing expensive ALD equipment and this It is intended to provide a method of preparation.
  • dielectric materials are deposited with a gapfill of 2 nm or less, and thus, due to the good nanoporosity of CNTs.
  • An MIM capacitor having a capacitance value and a method of manufacturing the same are provided.
  • An embodiment of the present invention is to provide a MIM capacitor having a nanostructure that can be used in a flexible substrate through a low temperature process and a method of manufacturing the same.
  • Method of manufacturing a MIM capacitor having a nanostructure comprises the steps of generating a catalyst layer on the substrate, growing a nanostructure on the catalyst layer, and a sol-gel on the substrate on which the nanostructure is grown coating Dielectric to a thickness capable of covering the grown nanostructure through a gel process, curing the interface of the nanostructure by baking the direct-coated substrate, and baking Washing the cured substrate with acetone and performing curing to form a lower electrode having an interface as an insulator on the upper surface, and a conductive polymer on the substrate having the lower electrode having the interface as an insulator on the upper surface.
  • conducting polymer) or a metal having a lower viscosity than AuSn or AgSn, and then patterning a portion of the electrode to form an upper electrode It includes.
  • the MIM capacitor having a nanostructure is a direct-coated on the substrate so that the nanostructure is covered with a substrate, the nanostructure is grown on top, the Sol-gel process (Sol-gel) process And a conductive electrode formed on the substrate on which the lower electrode formed by the baking of the direct-coated substrate is formed as an interface of an insulator nanostructure on an upper surface thereof, and a lower electrode formed on the upper surface of the substrate having an interface of an insulator formed thereon. polymer) or an upper electrode formed by coating a metal having a lower viscosity than AuSn or AgSn.
  • another feature according to an embodiment of the present invention is to increase the effective surface area of the dielectric layer by increasing the effective surface area of the bottom node of the capacitor in the MIM capacitor having a metal-insulator-metal (MIM) structure
  • MIM metal-insulator-metal
  • the MIM capacitor having the nanostructure and the manufacturing method according to the embodiment of the present invention have the following effects.
  • the MIM capacitor manufacturing process with high capacitance even if the MIM capacitor with high capacitance is grown due to good nanopores (nanoporosity) to grow the nanostructure of conventional nanotubes or CNTs without any straightness. There is a possible effect.
  • the effective surface area of the bottom node of the capacitor is increased to increase the effective surface area of the dielectric layer. Therefore, there is an effect having a high power density (power density) that can be applied to high-power electric vehicles.
  • MIM metal-insulator-metal
  • 1 to 5 are process diagrams for explaining a method for manufacturing a MIM capacitor having a nanostructure according to an embodiment of the present invention.
  • 1 to 5 are process diagrams for explaining a method for manufacturing a MIM capacitor having a nanostructure according to an embodiment of the present invention.
  • an arc plasma gun is used to generate a catalyst layer used as a lower electrode and a carbon nanotube (CNT) catalyst on a substrate 10, and then subjected to thermal CVD or remote plasma CVD on the catalyst layer. Thereby growing the CNT 20.
  • CNT carbon nanotube
  • the catalyst layer is a target of the arc plasma gun, and any one of Fe, Co, and Ni, or an alloy or compound containing at least one of these metals, or a mixture of at least two selected from these metals, alloys and compounds. It is formed using the target which consists of. And the CNT 20 grown on the substrate 10 is not possible to grow in a straight line, this straightness does not significantly affect in the present invention, there is no need for additional efforts to grow the straight line of the CNT 20 large There is a characteristic.
  • the CNT (20) is grown on the substrate 10, the upper part of the substrate through the Sol-gel (Sol-gel) process at a temperature of 20 °C ⁇ 25 °C is an inorganic (Sol-gel) Silisesquioxanes, Siloxanes, and Copolymers (MSQ or HSQ, PerHydorPolySilazane (PHPS)) are used to coat the dielectrics 20 of SiOx and SiOx to a thickness that the grown CNT 20 can cover.
  • Sol-gel process is possible by all-sol-gel method such as spin coating, spray coating, dip coating, wiping and roll coating. In the description of this specification, for the sake of clarity and simplicity, it is described that the direct coating is performed through the spin coating process in the sol-gel process, but it should be noted that this is only an example and is not intended to be limiting.
  • dielectric materials When SOD (Spin On Dielectric) is coated by spin coating during the sol-gel process, dielectric materials may be deposited with a gapfill of 2 nm or less even in the case of nanostructures that grow without linearity. have. In the case of the spin coating, it is preferable to coat with a spin of about 30 rpm.
  • the SOD 20 coated substrate 10 is placed on a heating element 40 such as a hot plate at about 90 ° C., and then baked for 30 minutes to 3 minutes. .
  • a heating element 40 such as a hot plate at about 90 ° C.
  • the interface 50 of the CNT 20 having good thermal conductivity of the SOD 20 coated substrate 10 is cured.
  • the interface 50 of the CNT 20 is cured to a thickness of 10 kPa or more and 90 kPa or less.
  • the interface 50 of the CNT 20 can be cured to about 30 mm thick.
  • the substrate 10 cured by baking is washed with acetone at an ambient temperature of 50 ° C. or lower, and the curing is performed, and a lower electrode, which is a CNT 20 having an interface 50 as an insulator, is formed on an upper surface thereof.
  • a lower electrode which is a CNT 20 having an interface 50 as an insulator
  • the curing is performed by using a furnace (furnace) equipment, or a solution containing OH radicals (water (H 2 O), hydrogen peroxide (H 2 O 2) water and ammonia water, KOH aqueous solution, NaOH aqueous solution, Ca (OH 2) solution, Ba (OH 2) solution) can be carried out by immersing the washed substrate 10 in a process.
  • a furnace furnace
  • a solution containing OH radicals water (H 2 O), hydrogen peroxide (H 2 O 2) water and ammonia water
  • KOH aqueous solution NaOH aqueous solution
  • Ca (OH 2) solution, Ba (OH 2) solution a solution containing OH radicals
  • a conductive polymer or a metal having a lower viscosity than AuSn or AgSn is coated on the substrate 10 on which the lower electrode 55 having the interface 50 as an insulator is formed on the upper surface.
  • the upper electrode 60 is formed by patterning a portion of the rear electrode to be formed. Accordingly, the lower electrode 55, the interface 50, and the upper electrode 60 are sequentially stacked on the substrate 10 to form a capacitor.
  • the upper electrode 60 when the upper electrode 60 is formed, a metal having a high viscosity such as AuSn or AgSn is melted and applied to the upper portion of the substrate 10 on which the lower electrode 55 is formed. Surface tension is less likely to be gapfilled. This is because the cross-sectional area of the upper electrode must be wider as the cross-sectional area of the lower electrode with the increased effective surface area can increase the effective surface area of the dielectric layer, so that the upper electrode 60 must be sufficiently gapfilled.
  • a metal having a high viscosity such as AuSn or AgSn
  • the upper electrode 60 formed on the substrate 10 on which the lower electrode 55 is formed by using a metal having a lower viscosity than the AuSn or AgSn or a conducting polymer is sufficiently filled with gap fill.
  • the embodiment of the present invention effectively increases the effective surface area of the bottom node of the capacitor in a MIM capacitor having a metal-insulator-metal (MIM) structure in which a high dielectric constant k dielectric material is introduced into the dielectric layer.
  • MIM metal-insulator-metal
  • Increasing the effective surface area of the dielectric layer enables the fabrication of high capacity MIM capacitors with a high power density that is applicable to high power electric vehicles.
  • Embodiments according to the present invention can be implemented in the form of program instructions that can be executed by various computer means can be recorded on a computer readable medium.
  • the computer readable medium may include program instructions, data files, data structures, and the like, alone or in combination.
  • Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts.
  • Examples of computer readable recording media include magnetic media such as hard disks, floppy disks and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks such as floppy disks.
  • Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like.
  • the hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Carbon And Carbon Compounds (AREA)

Abstract

L'invention concerne un condensateur MIM et un procédé de fabrication associé. Le procédé de fabrication comprend le dépôt de diélectriques dans un espace vide ayant une taille inférieure ou égale à 2 nm lors de la formation d'une nanostructure non linéaire de nanotubes ou de nanotubes de carbone, de sorte que la valeur de capacité du condensateur MIM soit élevée du fait de l'excellente nanoporosité des nanotubes de carbone.
PCT/KR2010/006875 2009-10-08 2010-10-07 Procédé de fabrication d'un condensateur mim ayant une nanostructure WO2011043613A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0095691 2009-10-08
KR1020090095691A KR101007057B1 (ko) 2009-10-08 2009-10-08 나노구조를 갖는 ｍｉｍ 캐패시터 제조방법

Publications (2)

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WO2011043613A2 true WO2011043613A2 (fr) 2011-04-14
WO2011043613A3 WO2011043613A3 (fr) 2011-07-14

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709112B1 (ko) * 2003-07-09 2007-04-18 고려대학교 산학협력단 나노선과 나노튜브 표면에 원자층 증착방법을 사용하여알루미나 박막을 코팅하는 방법
US20070166911A1 (en) * 2005-12-29 2007-07-19 Wen-Miao Lo Bottom electrode of metal-insulator-metal capacitor and method of fabricating the same
KR20090100257A (ko) * 2008-03-18 2009-09-23 후지쯔 가부시끼가이샤 시트 형상 구조체와 그 제조 방법, 및 전자 기기와 그 제조방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090088549A (ko) * 2008-02-15 2009-08-20 한국과학기술원 탄소나노튜브 수직성장법을 통한 ｃｏｂ타입 슈퍼 캐패시터형성 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709112B1 (ko) * 2003-07-09 2007-04-18 고려대학교 산학협력단 나노선과 나노튜브 표면에 원자층 증착방법을 사용하여알루미나 박막을 코팅하는 방법
US20070166911A1 (en) * 2005-12-29 2007-07-19 Wen-Miao Lo Bottom electrode of metal-insulator-metal capacitor and method of fabricating the same
KR20090100257A (ko) * 2008-03-18 2009-09-23 후지쯔 가부시끼가이샤 시트 형상 구조체와 그 제조 방법, 및 전자 기기와 그 제조방법

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KR101007057B1 (ko) 2011-01-12
WO2011043613A3 (fr) 2011-07-14

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