WO2011039793A1 - 基板処理装置 - Google Patents
基板処理装置 Download PDFInfo
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- WO2011039793A1 WO2011039793A1 PCT/JP2009/004960 JP2009004960W WO2011039793A1 WO 2011039793 A1 WO2011039793 A1 WO 2011039793A1 JP 2009004960 W JP2009004960 W JP 2009004960W WO 2011039793 A1 WO2011039793 A1 WO 2011039793A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 150000002500 ions Chemical class 0.000 description 35
- 230000008859 change Effects 0.000 description 12
- 230000002123 temporal effect Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32146—Amplitude modulation, includes pulsing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
Definitions
- the present invention relates to a substrate processing apparatus using plasma.
- a plasma is generated by applying RF (high frequency) to one of a pair of electrodes, and a substrate placed on the electrode to which RF is applied or on the other electrode by this plasma ( Wafer).
- An object of the present invention is to provide a substrate processing apparatus that enables efficient processing.
- a substrate processing apparatus includes a chamber, a first electrode disposed in the chamber, a second electrode disposed in the chamber so as to face the first electrode, and holding the substrate.
- An RF power source for applying an RF voltage having a frequency of 50 MHz or more to the second electrode, and a negative voltage pulse and 50 n from the negative voltage pulse superimposed on the RF voltage on the second electrode.
- a pulse power supply that repeatedly applies a voltage waveform including a positive voltage pulse with a delay time of less than a second.
- a substrate processing apparatus capable of efficient processing can be provided.
- FIG. 6 is a cross-sectional view illustrating a state where a wafer 15 is being processed.
- 3 is a graph showing an example of a temporal change in voltage on a wafer 15.
- 4 is a graph showing an example of a temporal change in an electron current flowing through a wafer 15. It is a graph showing an example of a combination pulse waveform.
- FIG. 3 is a graph showing an example of a temporal change in voltage on a wafer 15. It is the graph which expanded a part of FIG. 4 is a graph showing an example of a temporal change in an electron current flowing through a wafer 15. It is a graph showing an example of the time change of effective electric power Pe (t). 4 is a graph showing an example of a correspondence relationship between an active power amount Ee and a duty ratio D. It is a schematic diagram showing delay time. It is a graph showing an example of the time change of effective electric power Pe (t). It is a graph showing an example of the correspondence of active electric energy Ee and delay time td (delay time). It is a graph showing an example of the time change of effective electric power Pe (t). It is a graph showing an example of the correspondence between the amount of active power Ee and the number N of positive voltage pulses. It is a figure showing an example of a combination pulse waveform.
- FIG. 1 is a schematic configuration diagram of a substrate processing apparatus 1 according to one aspect of the present invention.
- the substrate processing apparatus 1 is a parallel plate type RIE (Reactive Ion Etching) apparatus.
- a wafer 15 is a processing target (substrate) of the substrate processing apparatus 1 according to this embodiment.
- the etching chamber 11 maintains an environment necessary for processing the wafer 15.
- the process gas introduction pipe 12 introduces a process gas necessary for processing the wafer 15.
- a process gas in addition to gases such as Ar, Kr, Xe, N 2 , O 2 , CO, and H 2 , SF 6 , CF 4 , C 2 F 6 , C 4 F 8 , C 5 F 8 , and C 4 are used as appropriate.
- F 6 , Cl 2 , HBr, SiH 4 , SiF 4 or the like can be used.
- the lower electrode 16 includes an electrostatic chuck for holding the wafer 15.
- the upper electrode 13 is provided to face the upper portion of the lower electrode 16, and one end thereof is set to the ground potential (ground potential).
- the upper electrode 13 and the lower electrode 16 constitute a parallel plate electrode.
- the plasma 14 is generated by RF applied to the lower electrode 16.
- the ions forming the plasma 14 enter the direction of the arrow in FIG.
- the wafer 15 is etched using the plasma 14.
- the exhaust port 17 is connected to a pressure adjustment valve and an exhaust pump (not shown).
- the gas in the etching chamber 11 is exhausted from the exhaust port 17, and the pressure in the etching chamber 11 is kept constant.
- the RF power source 19 generates an RF voltage to be applied to the lower electrode 16.
- the frequency of the RF voltage is 50 MHz or more. Details of this will be described later.
- the matching unit 18 matches the impedance between the RF power source 19 and the plasma 14.
- the pulse power supply 21 outputs, for example, the voltage waveform (combined pulse (Pulse) waveform) shown in FIG.
- the vertical axis and horizontal axis of the graph of FIG. 2 represent voltage (Voltage) and time ( ⁇ s), respectively.
- a waveform combining a negative voltage pulse and a positive voltage pulse is periodically repeated.
- Each of the negative voltage pulse and the positive voltage pulse is a rectangular waveform having a substantially constant voltage (peak voltage) within one pulse. Details of this will be described later.
- FIG. 3 is a schematic diagram showing an example of the internal configuration of the pulse power supply 21.
- the pulse power source 21 includes DC power sources 31 and 32, switches 33 to 35, and a gate pulser 36.
- the DC power supplies 31 and 32 are negative voltage and positive voltage power supplies.
- the DC power supply 31 functions as a first power supply having a first voltage corresponding to the peak voltage of the negative voltage pulse.
- the DC power source 32 functions as a second power source having a second voltage corresponding to the peak voltage of the positive voltage pulse.
- the switches 33 to 35 are controlled by the gate pulser 36 and are used to apply a negative voltage, a positive voltage, and a ground potential, respectively.
- the switch 33 functions as a first switch that switches the connection state of the first power source to the output terminal.
- the switch 34 functions as a second switch that switches the connection state of the second power source to the output terminal.
- the switch 35 functions as a third switch that switches the connection state of the ground potential to the output terminal.
- the gate pulser 36 controls the opening and closing of the switches 33 to 35, and functions as a control unit that controls the first to third switches.
- the gate pulser 36 controls the combination of the switches 33 to 35 in the order of (ON, OFF, OFF), (OFF, ON, OFF), (OFF, OFF, ON), so that negative voltage, positive voltage, and ground potential are pulsed. Applied to the output terminal of the power supply 21.
- FIG. 4 shows a state where the combined pulse waveform shown in FIG. 2 is decomposed into a negative voltage pulse waveform, a positive voltage pulse waveform, and a ground potential.
- a negative voltage pulse, a positive voltage pulse, and a ground potential are output from the pulse power source 21 at times t1 to t2, t2 to t3, and t3 to t4, respectively.
- a negative voltage pulse, a positive voltage pulse, and a ground potential are output from the pulse power supply 21 at times t4 to t5, t5 to t6, and t6 to t7.
- An LPF (Low Pass Filter) 20 prevents a high frequency from the RF power source 19 from entering the pulse power source 21 and outputs only a low frequency component from the voltage waveform input from the pulse power source 21 to the lower electrode 16. As a result, the high frequency from the RF power source 19 and the combined pulse waveform from the pulse power source 21 are superimposed and applied to the lower electrode 16.
- the wafer 15 is transferred by a transfer mechanism (not shown) into the etching chamber 11 that has been evacuated and reaches a predetermined pressure. Next, the wafer 15 is held on the lower electrode 16 by an electrostatic chuck provided in the lower electrode 16.
- the process gas introduced into the etching chamber 11 is exhausted from the exhaust port 17 at a predetermined speed by a pressure adjusting valve and an exhaust pump (not shown). As a result, the pressure in the etching chamber 11 is kept constant.
- RF is applied from the RF power source 19 to the lower electrode 16 through the matching unit 18. Further, the combined pulse waveform shown in FIG. 2 is applied from the pulse power source 21 to the lower electrode 16 so as to be superimposed on the RF.
- the plasma density is controlled by the RF power from the RF power source 19.
- the incident energy of ions incident on the wafer 15 is controlled by the voltage of the negative voltage pulse from the pulse power source 21.
- the wafer 15 is etched by ions having energy equal to or higher than the processing threshold value of the wafer 15.
- the frequency of the RF voltage As described above, the frequency of the RF power source 19 is 50 MHz or more. Hereinafter, the reason will be described. By setting the frequency of the RF power source 19 to 50 MHz or more, the following advantages (1) and (2) occur.
- the component Vdc1 decreases.
- the component Vdc1 is about 50 eV (a threshold value that does not affect the processing of the wafer 15) or less. Even at RF power exceeding 2.2 W / cm 2 , the RF power dependency of the component Vdc1 is extremely small.
- the average incident energy Vdc does not depend on the RF voltage but depends only on the negative voltage pulse.
- the incident energy Vdc can be controlled only by the negative voltage pulse.
- the reason why the RF voltage is applied to the lower electrode 16 is to generate plasma efficiently. Even when an insulating film is deposited on the wafer 15, the plasma can be efficiently generated and the wafer 15 can be processed.
- the distribution of ion energy in the plasma 14 has a low energy side peak P1 and a high energy side peak P2. This is because the plasma 14 is generated by the RF voltage.
- the energy width ⁇ E between the peaks P1 and P2 is several tens to several hundreds [eV] depending on the plasma generation conditions. Therefore, even when the average incident energy Vdc is adjusted to an optimum value for processing the wafer 15, ions that are too high in energy (high energy side peak) and ions that are too low (low energy side peak) for ions incident on the wafer 15. ) And exist.
- the processing accuracy may be insufficient.
- shoulder cutting shoulder drop
- the wafer 15 is processed with ions having a low energy peak, it may not contribute to the processing below the surface reaction threshold value, or the processing anisotropy may be deteriorated (the ion incident angle spreads with the heat speed).
- the energy width ⁇ Ei decreases. Therefore, by increasing the frequency of the RF voltage, particularly 50 MHz or more, the ion incident energy distribution is narrowed. As a result, the wafer 15 can be processed with ions having substantially a single energy peak. That is, RF with a frequency of 50 MHz or more does not substantially generate ions with too high energy.
- FIG. 5 is a cross-sectional view showing a state in which the wafer 15 is being processed.
- the wafer 15 is a laminated body of the substrate 41 and the insulator 42, and the groove 44 is formed using the mask 43.
- Si, SiOC, or Si 3 N 4 silicon nitride
- Si, SiOC, or Si 3 N 4 can be used for the substrate 41, the insulator 42, and the mask 43, respectively.
- Electrons e ⁇ and positive ions I + are unevenly distributed on the side wall near the entrance and near the bottom of the groove 44, and are negatively and positively charged.
- the reason why charge-up is likely to occur on the inner surface of the groove 44 is that the positive ions I + are anisotropic and the electrons e ⁇ are isotropic.
- the positive ions I + are accelerated in the direction of the substrate 41 by the negative voltage pulse, and the directions are aligned (is anisotropic).
- the electrons e ⁇ are not accelerated in the direction of the substrate 41, and the directions are scattered (isotropic).
- the isotropic electron e ⁇ does not easily enter the depth of the narrow groove, and the side wall near the entrance of the groove 44 is negatively charged up.
- the positive charge-up generated at the bottom of the groove 44 reduces the number of positive ions I + reaching the bottom of the groove 44, and the trajectory of the positive ions I + is bent. For this reason, processing stop (etching stop) and processing shape abnormality (for example, notching: abnormal etching occurring on the bottom side surface of the groove 44) occur, and desired processing becomes difficult.
- processing stop etching stop
- processing shape abnormality for example, notching: abnormal etching occurring on the bottom side surface of the groove 44
- FIG. 6 is a graph showing an example of the temporal change of the voltage on the wafer 15.
- the voltage is expressed with reference to the potential at the upper electrode 13.
- FIG. 7 is a graph showing temporal changes in the electron current flowing through the wafer 15. 6 and 7, graphs G ⁇ b> 10 and G ⁇ b> 20 correspond to the case where only the RF voltage and the negative voltage pulse are applied to the lower electrode 16. Graphs G11 and G21 correspond to the case where an RF voltage and a combined pulse waveform (negative voltage pulse and positive voltage pulse) are applied to the lower electrode 16.
- the positive voltage pulse has a peak voltage of 500V and a pulse width of 1% of the combined pulse period (1% duty ratio).
- the integrated value of the electron current is the same in the graphs G20 and G21 can be explained as follows.
- the pulse waveform is repeatedly applied on the surface of the insulating film, the ion current and the electron current on the wafer 15 are balanced and equal in one cycle. That is, in a steady state where the amount of charge (charge up amount) on the wafer 15 is stable, the direct current component in one cycle becomes zero.
- the graphs G20 and G21 there is no substantial difference in the amount of incident ions (the state of the plasma 14 is virtually dominated by RF and hardly influenced by the positive voltage pulse).
- the integrated value is also almost the same.
- the presence or absence of anisotropy between ions and electrons is different when a positive voltage pulse is not applied. For this reason, at the bottom of a high aspect ratio groove or hole, ions are incident, while electrons are difficult to be incident, and therefore charge up to the positive side. In order to relax the balanced charge-up distribution in this state, it is necessary to reduce the ion current to the bottom of the groove (hole) or increase the electron current to the bottom of the groove (hole). The former is not preferable because the process rate decreases, so the latter is adopted.
- an index for evaluating the contribution to the reduction in charge-up at the bottom of the groove or hole is provided. Necessary. This index is defined as an active power amount Ee.
- the effective power amount Ee is defined by the following formula (1).
- the active power amount Ee is an integral value of the active power Pe (product of the voltage V (t) and the electronic current Ie (t)). It is considered that the electron current during the period in which a positive potential is applied to the wafer 15 has anisotropy and contributes to relaxation of charge-up in the groove (positive charge-up of the groove bottom). Hereinafter, the relaxation of charge-up will be evaluated using the active energy Ee.
- Duty ratio of positive voltage pulse Consider the influence of pulse width (duty ratio) of positive voltage pulse.
- the positive voltage pulse has a peak voltage of 500 V
- FIG. 8 is a graph showing the combined pulse waveform at this time.
- 9 and 10 are graphs showing temporal changes in the voltage (voltage V (t)) on the wafer 15 at this time.
- FIG. 10 shows an enlarged part of FIG.
- FIG. 11 is a graph showing a temporal change in the electron current (electron current Ie (t)) flowing through the wafer 15 at this time.
- the case where the duty ratio is 0.1% is excluded for the sake of easy understanding.
- FIG. 12 is a graph showing temporal changes in the active power Pe (t) at this time.
- the active power Pe (t) is calculated by multiplying the voltage V (t) and the electronic current Ie (t) shown in FIGS.
- FIG. 13 is a graph showing the correspondence between the active power amount Ee and the duty ratio D.
- the active power amount Ee varies greatly depending on whether or not a positive voltage pulse is applied.
- the active power Ee is about 0.6 ⁇ 10 ⁇ 2 [J].
- the active power amount Ee is about 2.0 ⁇ 10 ⁇ 2 [J]. That is, the active power amount Ee increases about three times depending on whether or not a positive voltage pulse is applied.
- the duty ratio is 5% and 10%
- the active energy Ee is about 6.0 ⁇ 10 ⁇ 2 [J], which is about 10 times that when no positive voltage pulse is applied (duty ratio 0%). Has increased to.
- the duty ratio becomes larger than a certain level, the active power amount Ee tends to decrease.
- a duty ratio of 0.1% to 20% can be employed.
- a more preferable duty ratio is approximately 1% to 18%, and a further preferable duty ratio is approximately 3% to 13%.
- FIG. 14 is a schematic diagram showing the delay time. The time from when the application of the negative voltage pulse is completed and the lower electrode 16 becomes the ground potential until the application of the positive voltage pulse is started is a delay time td.
- the delay time was changed to 0, 50, 150, and 250 ns.
- the duty ratio was 1%, the period T0 was 1 [ ⁇ sec], and the negative pulse application time was 700 [ns].
- FIG. 15 is a graph showing a temporal change of the active power Pe (t) at this time.
- the effective power Pe (t) is calculated by multiplying the voltage V (t) and the electron current Ie (t).
- FIG. 16 is a graph showing a correspondence relationship between the active power amount Ee and the delay time td (delay time).
- a delay time of 50 ns or less, particularly immediately after application of a negative voltage pulse is good.
- the effective electric energy Ee is about twice as large as when the application is greatly delayed (delay time 250 ns).
- the total amount (integration amount) of the electron current is determined, and immediately after the negative voltage pulse is applied, the peak of the electron current occurs even if the positive voltage pulse is not applied. Electrons that flow when no positive voltage pulse is applied are basically isotropic. Therefore, when application of the positive voltage pulse is delayed, the proportion of the anisotropic electron current in the total amount of electron current decreases.
- the combination pulse can be a combination of a negative voltage pulse and a plurality of positive voltage pulses.
- the number N of positive voltage pulses is changed from 0 to 6.
- FIG. 17 is a graph showing a temporal change in the active power Pe (t) at this time. As described above, the effective power Pe (t) is calculated by multiplying the voltage V (t) and the electron current Ie (t).
- FIG. 18 is a graph showing a correspondence relationship between the active power amount Ee and the number N of positive voltage pulses.
- the active electric energy Ee is increased by dividing one positive voltage pulse into a plurality of positive voltage pulses.
- the total duty ratio Dt was 0.5% and 1%, respectively, the number of positive voltage pulses N was 3 and 2, and the active energy Ee was maximized.
- the division of the positive voltage pulse is effective because the effect of suppressing the charge-up due to the positive voltage pulse is reduced in time (because the voltage on the wafer 15 is reduced, that is, the anisotropy of electrons is reduced). it is conceivable that.
- the charge-up suppressing effect can be recovered in a pause period between the plurality of positive voltage pulses.
- the combined pulse can be a combination of a plurality of negative voltage pulses and a single positive voltage pulse.
- FIG. 19 shows an example of this. A negative voltage pulse is continuously applied, and a positive voltage pulse is applied during the pause. This figure shows a state in which the RF voltage is also superimposed. It is also possible to repeat a combination of a negative voltage pulse and a positive voltage pulse instead of a continuous negative voltage pulse.
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Abstract
Description
図1は、本発明の1態様に係る基板処理装置1の概略構成図である。この基板処理装置1は、平行平板型のRIE(Reactive Ion Etching)装置である。
真空引きされ所定の圧力に達したエッチングチャンバ11内に、図示しない搬送機構によりウエハ15が搬送される。次に、下部電極16が具備する静電チャックにより、下部電極16上にウエハ15が保持される。
既述のように、RF電源19の周波数は50MHz以上である。以下、この理由を説明する。RF電源19の周波数を50MHz以上とすることで、次の(1)、(2)の利点が生じる。
既述のように、下部電極16には、RF電圧と組み合わせ電圧パルスとが重畳して印加される。RF電圧によって、下部電極16及び上部電極13間にプラズマ14が生成される。このプラズマ14中の正イオンがウエハ15に入射し、ウエハ15が処理される。このとき、入射する正イオンの平均入射エネルギーVdcは、RF電圧に起因する成分Vdc1と負電圧パルスに起因する成分Vdc2に区分できる。
以下に示すように、RF電圧の周波数を増大させることで、実質的に単一のエネルギーピークのイオンにより、効率的かつ高精度でウエハ15を加工できる。
以下、正電圧パルスの印加の効果を説明する。先に、正電圧パルスを印加せず、負電圧パルスのみを印加する場合を説明する。
本実施形態では、負電圧パルスに加えて、正電圧パルスを印加することで、短時間でチャージアップを低減することが可能となる。
T:組み合わせパルスの周期
Ie(t):電子電流
V(t):ウエハ15に印加される電圧
Pe(t):有効電力
正電圧パルスのパルス幅(デューティ比)の影響を考える。ここでは、正電圧パルスは、500Vのピーク電圧とし、デューティ比D(組み合わせパルスの周期Tに占めるパルス幅ΔTの割合(D=ΔT/T))を0、0.1、1、5、10、20%と変化させた(それぞれ、図8~図12でのグラフD0、D0.1、D1、D5、D10、D20に対応)。ディーティ比D=0%は、正電圧パルスを印加しないことを意味する。
次に負電圧パルスを印加してから正電圧パルスを印加するまでの遅れ時間td(delay time)の影響を考える。図14は、遅れ時間を表す模式図である。負電圧パルスの印加が終了し、下部電極16がグランド電位となってから、正電圧パルスの印加を開始するまでの時間が遅れ時間(delay time)tdである。
組み合わせパルスを負電圧パルスと、複数の正電圧パルスの組み合わせとすることも可能である。ここでは、正電圧パルスの個数Nを0~6まで変化させる。なお、個数N=0は、正電圧パルスを印加しないことを意味する。このとき、正電圧パルス全体でのデューティ比(全デューティ比)Dtを一定とした(0.5%、1%)。即ち、正電圧パルス1つ当たりのデューティ比Dは、正電圧パルスの個数Nに応じて減少する(D=Dt/N)。
組み合わせパルスを複数の負電圧パルスと、単一の正電圧パルスの組み合わせとすることも可能である。図19にこの1例を示す。連続して負電圧パルスが印加され、その休止中に、正電圧パルスが印加されている。この図ではRF電圧も重畳した状態を表している。なお、連続する負電圧パルスに替えて、負電圧パルスと正電圧パルスの組み合わせを繰り返すことも可能である。
なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。例えば、基板処理装置として、RIEの他、プラズマCVD(Chemical Vapor Deposition)装置などにも適用することができる。
Claims (5)
- チャンバと、
前記チャンバ内に配置される第1の電極と、
前記チャンバ内に前記第1の電極と対向して配置され、基板を保持する第2の電極と、
前記第2の電極に、50MHz以上の周波数のRF電圧を印加するRF電源と、
前記第2の電極に、前記RF電圧と重畳して、負電圧パルスおよびこの負電圧パルスから50n秒以下の遅れ時間の正電圧パルスを含む電圧波形を繰り返し印加するパルス電源と、
を具備する基板処理装置。 - 前記正電圧パルスのデューティ比が、0.1%以上、20%以下である
請求項1に記載の基板処理装置。 - 前記電圧波形が、複数の正電圧パルスまたは複数の負電圧パルスを含む、
請求項2に記載の基板処理装置。 - 前記パルス電源が、
前記負電圧パルスのピーク電圧に対応する第1の電圧を有する第1の電源と、
前記正電圧パルスのピーク電圧に対応する第2の電圧を有する第2の電源と、
前記第1、第2の電源、およびグランド電位の何れかが印加される出力端と、
前記出力端への前記第1の電源の接続状態を切り替える第1のスイッチと、
前記出力端への前記第2の電源の接続状態を切り替える第2のスイッチと、
前記出力端への前記グランド電位の接続状態を切り替える第3のスイッチと、
前記第1~第3のスイッチを制御する制御部と、を有する、
請求項2に記載の基板処理装置。 - 前記制御部が、
前記第1のスイッチを閉状態とし、前記第2、第3のスイッチを開状態として、前記出力端に前記負電圧パルスを出力させる第1の制御部と、
前記第2のスイッチを閉状態とし、前記第1、第3のスイッチを開状態として、前記出力端に前記正電圧パルスを出力させる第2の制御部と、
前記第3のスイッチを閉状態とし、前記第1、第2のスイッチを開状態として、前記出力端に前記グランド電位を出力させる第3の制御部と、を有する、
請求項4に記載の基板処理装置。
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JP2018006664A (ja) * | 2016-07-07 | 2018-01-11 | 東芝メモリ株式会社 | プラズマ処理装置およびプラズマ処理方法 |
CN109216146A (zh) * | 2017-07-07 | 2019-01-15 | Asm Ip控股有限公司 | 基板处理装置、存储介质和基板处理方法 |
JP2022103235A (ja) * | 2018-11-05 | 2022-07-07 | 東京エレクトロン株式会社 | プラズマ処理装置及びプラズマ処理方法 |
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JP6542053B2 (ja) * | 2015-07-15 | 2019-07-10 | 株式会社東芝 | プラズマ電極構造、およびプラズマ誘起流発生装置 |
US10312048B2 (en) * | 2016-12-12 | 2019-06-04 | Applied Materials, Inc. | Creating ion energy distribution functions (IEDF) |
JP7045152B2 (ja) * | 2017-08-18 | 2022-03-31 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
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