WO2011007699A1 - Semiconductor device manufacturing method and semiconductor integrated circuit device - Google Patents

Semiconductor device manufacturing method and semiconductor integrated circuit device Download PDF

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Publication number
WO2011007699A1
WO2011007699A1 PCT/JP2010/061480 JP2010061480W WO2011007699A1 WO 2011007699 A1 WO2011007699 A1 WO 2011007699A1 JP 2010061480 W JP2010061480 W JP 2010061480W WO 2011007699 A1 WO2011007699 A1 WO 2011007699A1
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region
oxide film
semiconductor substrate
locos oxide
manufacturing
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PCT/JP2010/061480
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French (fr)
Japanese (ja)
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正樹 笠原
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ミツミ電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor device in which a LOCOS oxide film is formed in a predetermined region on the surface of a semiconductor substrate, and a semiconductor having the semiconductor device manufactured by such a method.
  • the present invention relates to an integrated circuit device.
  • a LOCOS oxide film is formed on the surface of a semiconductor substrate by a LOCOS (Local Oxidation of Silicon) method, and a resist is used to implant ions using the LOCOS oxide film and the resist as a mask to form a device.
  • LOCOS Local Oxidation of Silicon
  • Device manufacturing methods are known.
  • FIGS. 1A to 1F are views showing an example of a conventional method for manufacturing a semiconductor device. 1A to 1F, an example of a method for manufacturing an npn transistor will be described.
  • FIGS. 1A to 1F show a plan view and a cross-sectional view, respectively.
  • FIG. 1A is a diagram showing a LOCOS oxide film forming step.
  • a LOCOS oxide film 170 is formed by a LOCOS method on the surface of the semiconductor substrate 140 on which the n-type layer 120 is formed on the silicon substrate 110.
  • a region for forming a device such as a transistor on the surface of the semiconductor substrate 140 is surrounded by a LOCOS oxide film 170.
  • FIG. 1B is a diagram showing a base region forming process.
  • a portion of the semiconductor substrate 140 where the impurity region is not formed is covered with the resist 200, and a portion where the impurity region is formed is not covered with the resist 200 and is exposed.
  • ions are implanted into the semiconductor substrate 140, and impurities are implanted.
  • impurities For example, boron or the like is used as the ion. Ions are implanted with high energy, and a portion of the LOCOS oxide film 170 is transmitted through the LOCOS oxide film 170 and implanted. In the portion where the LOCOS oxide film 170 is not present, ions are directly implanted into the n-type layer 120.
  • a portion of the semiconductor substrate 140 where ions are implanted becomes a base region 150 into which impurities are implanted.
  • the portion where the LOCOS oxide film 170 is not present and the n-type layer 120 of the semiconductor substrate 140 is exposed becomes the high concentration base region 151, and the portion below the LOCOS oxide film 170 becomes the low concentration base region 152. .
  • FIG. 1C is a diagram showing a heat treatment process.
  • the resist 200 is removed and the semiconductor substrate 140 is subjected to heat treatment.
  • thermal diffusion of the base region 150 is performed, and the implanted impurities are diffused in the base region 150, and the concentration distribution of the impurity concentration goes in the direction of averaging, and the base region 150 expands laterally and downward. To do.
  • FIG. 1D is a diagram showing a gate oxide film forming step.
  • a gate oxide film 180 is formed in a portion where the high-concentration base region 151 is exposed.
  • the surface of the high concentration base region 151 is covered with the gate oxide film 180.
  • the gate oxide film 180 means a thin oxide film similar to the gate oxide film 180 in the process of manufacturing a MOS transistor, and does not necessarily mean that a gate is formed in that region.
  • FIG. 1E is a diagram showing an emitter region forming step.
  • the portion of the semiconductor substrate 140 where ions are not implanted is covered with the resist 202.
  • the organic resist 202 is scraped and mixed into the emitter region 160 when ions are implanted, the characteristics of the emitter region 160 are adversely affected. Therefore, the end of the emitter region 160 is ion-doped with the LOCOS oxide film 170 as a mask. Driving is done. For example, phosphorus may be used as the ion.
  • the ion implantation is performed in the region where the gate oxide film 180 is formed using the LOCOS oxide film 170 as a mask, the ion implantation is performed with low energy so as to pass through the gate oxide film 180 and not through the LOCOS oxide film 170. Done.
  • an emitter region 160 that is also an impurity region is formed on the surface of the base region 150 that is an impurity region.
  • FIG. 1F is a diagram showing a heat treatment process.
  • the semiconductor substrate 140 is subjected to heat treatment, and thermal diffusion of the emitter region 160 is performed.
  • the impurity concentration of the emitter region 160 is averaged, and the emitter region 160 expands laterally and downward.
  • the n-type layer 120 functions as a collector region and can form an npn-type bipolar transistor.
  • the n-type layer 120 may be formed on a P-type silicon substrate by, for example, epitaxial growth.
  • Patent Document 1 discloses a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) integrated circuit device in which a MOS (Metal-Oxide-Semiconductor) transistor and a bipolar transistor are mixedly mounted on the same semiconductor substrate.
  • the bipolar transistor has a base extraction electrode having an insulator side wall connected to the base layer, and an emitter electrode extraction opening and an emitter layer formed in a self-aligned manner using the insulator side wall. Is described.
  • the side wall of the insulator of the BiCMOS integrated circuit device is formed by forming a TEOS on the entire semiconductor substrate including the step of forming an insulating film on the base lead electrode and the side surface of the base lead electrode and the emitter forming region surrounded by the base lead electrode.
  • the size of the emitter region 160 is affected by the processing accuracy and film thickness of the LOCOS oxide film 170, and the adjacent device is affected by the variation of the emitter region 160. There was a problem that the characteristics of the film became non-uniform. Further, when the size of the emitter region 160 is increased, the size of the high-concentration base region 151 of the base region 150 is reduced, so that a parasitic operation in the lateral direction occurs even though the bipolar transistor is desired to operate in the vertical direction. As a result, there is a problem that transistor characteristics deteriorate and variations occur.
  • FIG. 2 is an enlarged view of portion A in FIG. 1F (b).
  • the lateral position of the LOCOS oxide film 170 may vary depending on the processing accuracy.
  • the end portion of the LOCOS oxide film 170 has a cross-sectional shape with a sharp tip such as the apex of a triangle in which the film thickness decreases toward the outside. With such a shape, the film thickness slightly changes depending on the position of the end portion of the LOCOS oxide film 170 in the lateral direction, and the lateral size of the emitter region 160 is affected and fluctuates accordingly.
  • the high-concentration base region 151 into which impurities are implanted by permeation of the LOCOS oxide film 170 is located below the portion of the LOCOS oxide film 170 where the triangular film thickness changes, so that the processing accuracy of the LOCOS oxide film 170 and The film thickness affects the impurity concentration.
  • the impurity concentration of the high concentration base region 151 affects the diffusion length of the minority carriers injected from the emitter region 160 during the operation of the transistor.
  • the low concentration base region 152 is implanted through the thick film portion of the LOCOS oxide film 170, the impurity concentration is lower than that of the high concentration base region 151. Further, since the low concentration base region 152 has a low impurity concentration, the diffusion length of the minority carriers is long.
  • an object of the present invention is to provide a method for manufacturing a semiconductor device capable of uniformizing device characteristics and a semiconductor integrated circuit device having the semiconductor device manufactured by such a method by a simple process.
  • a method of manufacturing a semiconductor device includes a step of forming a LOCOS oxide film in a predetermined region of a surface of a semiconductor substrate, and covering a boundary between the LOCOS oxide film and the surface of the semiconductor substrate.
  • a semiconductor device or a semiconductor integrated circuit device having excellent characteristics and uniformity is provided.
  • FIG. 1A and 1B are views showing a LOCOS oxide film forming process according to an embodiment of the present invention, in which FIG. 1A is a plan view of a semiconductor substrate on which a semiconductor device is manufactured, and FIG. 4A and 4B are diagrams showing a high energy ion implantation process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate. It is the figure which showed the heat processing process by one Example of this invention, (a) is a top view of a bipolar transistor formation area, (b) is sectional drawing of a semiconductor substrate.
  • FIG. 4A and 4B are diagrams illustrating a gate oxide film forming process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate.
  • FIG. 5A and 4B are diagrams illustrating a polysilicon film forming process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate. It is the figure which showed the ion implantation process by one Example of this invention, (a) is a top view of a bipolar transistor formation area, (b) is sectional drawing of a semiconductor substrate.
  • 3A to 3G are diagrams showing a series of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 3A is a diagram showing a LOCOS oxide film forming step.
  • 3A is a plan view of the semiconductor substrate 40 on which the semiconductor device is manufactured
  • FIG. 3B is a cross-sectional view of the semiconductor substrate 40.
  • the semiconductor substrate 40 includes a silicon substrate 10, an n-type layer 20, and a p-type layer 30.
  • a LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40.
  • the silicon substrate 10 may be a substrate made of another semiconductor material, but in this embodiment, an example using the silicon substrate 10 will be described.
  • the n-type layer 20 may be formed by epitaxial growth.
  • the surface of the semiconductor substrate 40 has a bipolar transistor formation region 41 and a MOS transistor formation region 42.
  • the semiconductor device manufacturing method according to the present embodiment can manufacture a semiconductor device in which an impurity region is formed with high accuracy while utilizing a MOS transistor manufacturing process. Therefore, FIGS. 3A to 3G show an example in which an npn bipolar transistor is manufactured by the method of manufacturing a semiconductor device according to this embodiment and an n-channel MOS transistor is formed on the same semiconductor substrate 40.
  • the semiconductor device manufacturing method according to the present embodiment can be used not only for the process of simultaneously manufacturing the MOS transistors but also for the device manufacturing alone, the MOS transistors need not always be manufactured at the same time. .
  • a LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40 by the LOCOS method.
  • the LOCOS oxide film 70 is formed at a position for isolating the bipolar transistor formation region 41 and the n-channel MOS transistor 42 from each other. Further, since the LOCOS oxide film 70 is also used as a mask at the time of ion implantation, it is provided in the bipolar transistor formation region 41 at a position where a high concentration impurity region is not formed.
  • a p-type layer 30 is provided between the bipolar transistor formation region 41 and the MOS transistor formation region 42 in the vertical direction (depth direction) of the semiconductor substrate 40 in order to perform element isolation.
  • the LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40, and the LOCOS oxide film 70 functions as an element isolation oxide film or a mask.
  • the LOCOS oxide film 70 functions as an element isolation oxide film or a mask.
  • FIGS. 3B to 3G only the bipolar transistor formation region 41 is shown in the plan view of FIG. 3A. Indicates.
  • the semiconductor substrate 40 can be configured as a substrate made of various semiconductor materials as long as it is a semiconductor material.
  • the semiconductor substrate 40 may be configured as a silicon substrate.
  • the case where the semiconductor substrate 40 is an n-type conductivity will be described as an example.
  • FIG. 3B is a diagram showing a high energy ion implantation process. 3B, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
  • a film-like resist 100 is applied to the surface (surface layer) of the semiconductor substrate 40, and ions are implanted.
  • ions as impurities are implanted with high energy into the surface (surface layer) of the semiconductor substrate 40 to form the base region 50 and the p-type well layer 55.
  • boron may be used as the ion.
  • the base region 50 and the p-type well layer 55 which are p-type impurity regions are formed on the surface of the n-type semiconductor substrate 40.
  • the resist 100 is selectively formed by patterning so as to cover portions of the semiconductor substrate 40 where the p-type impurity regions 50 and 55 are not formed.
  • ions are implanted into the semiconductor substrate 40 with high energy to form the base region 50 and the p-type well layer 55. Since the ions are implanted with high energy, the ions pass through the LOCOS oxide film 70, A base region 50 and a p-type well layer 55 are also formed under the LOCOS oxide film 70.
  • the high energy mentioned here means energy that allows ions implanted into the semiconductor substrate 40 to pass through the LOCOS oxide film 70 and form an impurity region under the LOCOS oxide film 70. The energy value can vary depending on the semiconductor substrate 40, the ion material, and the like.
  • a resist 100 is formed in a frame shape, a LOCOS oxide film 70 functioning as a mask, and a base region in the opening 101 of the resist 100. 50 is exposed.
  • FIG. 3C is a diagram showing a heat treatment process. 3C, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
  • the semiconductor substrate 40 is subjected to a heat treatment to diffuse the impurities in the base region 50 and the p-type well layer 55, so that the impurity concentration distribution is uniform. Is achieved. Further, in the heat treatment step, the sizes of the base region 50 and the p-type well layer 55 are expanded laterally and downward.
  • the base region 50 and the P-type well layer 55 are expanded laterally and downward in the semiconductor substrate 40.
  • the high-concentration base region 51 and the high-concentration p-type well layer 56 are enlarged in the portion where the semiconductor substrate 40 is exposed, and the low-concentration base region 52 is located under the LOCOS oxide film 70.
  • the low concentration p-type well layer 57 is enlarged.
  • FIG. 3C (a) transparently shows a plan view of the bipolar transistor formation region 41.
  • reference numerals in parentheses indicate regions that are transparently represented.
  • the low-concentration base region 52 whose reference symbol is shown in parentheses is a transparently represented region.
  • the exposed portion of the LOCOS oxide film 70 and the semiconductor substrate 40 is shown in the portion covered with the resist 100 in FIG.
  • FIG. 3B (a) in the portion corresponding to the opening 101 of the resist 100, the portion where the LOCOS oxide film 70 is not formed becomes the high-concentration base region 51, and the LOCOS oxide film 70 is formed.
  • the portion is a low concentration base region 52.
  • the formation region of the base region 50 and the p-type well layer 55 is controlled by the presence or absence of the resist 100, and the impurity concentration in the base region 50 and the p-type well layer 55 is controlled by the presence or absence of the LOCOS oxide film 70.
  • FIG. 3D is a diagram showing a gate oxide film forming step. 3D, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
  • a gate oxide film 80 is formed on the exposed portions of the surfaces of the base region 50 and the p-type well layer 55.
  • the gate oxide film 80 is a thin oxide film formed in the gate formation region in the MOS transistor manufacturing process.
  • the thin gate oxide film 80 is formed not only in the MOS transistor formation region 42 but also in the bipolar transistor formation region 41.
  • the gate oxide film may be composed of various materials, but may be composed of, for example, a SiO 2 film.
  • the region where the gate oxide film 80 is formed is a portion where the surface of the semiconductor substrate 40 is exposed where the LOCOS oxide film 70 does not exist, the surface of the n-type layer 20, the high-concentration base region 51, or the high-concentration P-type. It becomes one of the well layers 56.
  • FIG. 3D (a) shows a transparent plan view of the bipolar transistor formation region 41, which is substantially the same as FIG. 3C (a).
  • the portion of the high-concentration base region 51 and the portion where the n-type layer 20 of the semiconductor substrate 40 is exposed are thin gate oxide films. Although it is covered with 80, if a figure is drawn transparently, it will become the same plane composition as (a) of Drawing 3C.
  • the gate oxide film forming step shown in FIG. 3D may be omitted, for example, when the semiconductor device manufacturing method of this embodiment is used to manufacture a device alone without forming a MOS transistor at the same time.
  • FIG. 3E is a diagram showing a polysilicon film forming process. 3E, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
  • a polysilicon film 90 is formed so as to cover the boundary.
  • the polysilicon film 90 is used when forming a gate in the MOS transistor manufacturing process. Therefore, in the MOS transistor formation region 42, the polysilicon film 90 is formed as a gate.
  • the polysilicon film 90 may be formed so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40 in the bipolar transistor formation region 41. .
  • the polysilicon film 90 is formed to be used as a mask.
  • the end portion of the LOCOS oxide film 70 has a shape in which the tip becomes thinner and the thickness becomes thinner as it approaches the tip, and the processing accuracy cannot be made high. Therefore, in the method of manufacturing the semiconductor device according to the present embodiment, the mask is formed with high accuracy using the polysilicon film 90 with high processing accuracy. Therefore, the end portion of the mask is not the LOCOS oxide film 70 but the polysilicon film 90, and the position of the mask end portion can be determined with high accuracy.
  • Polysilicon is originally a material used as the gate of a MOS transistor, and the gate length and gate width of the MOS transistor are controlled with high precision, so that the polysilicon film 90 is formed with high precision processing. It becomes possible enough.
  • the polysilicon film 90 covers the inclined portion of the LOCOS oxide film 70 and the gate oxide so as to cover the boundary between the LOCOS oxide film 70 and the gate oxide film 80 on the surface of the semiconductor substrate 40 where the emitter region 60 is to be formed. It is formed so as to straddle the film 80.
  • the LOCOS oxide film 70 is used as it is in the central portion where the LOCOS oxide film 70 is sufficiently thick, and the inclined portion of the tip where the processing accuracy is lowered is covered with the polysilicon film 90, the minimum polysilicon is obtained.
  • a functionally sufficient mask effect can be obtained by forming the film 90.
  • the polysilicon film forming process is a process performed in a normal MOS transistor manufacturing process, there is no need to add an extra process to the MOS transistor manufacturing process in order to manufacture a bipolar transistor.
  • a highly accurate mask can be formed with the same number of steps as in the manufacturing process.
  • FIG. 3E shows a plan view of the bipolar transistor formation region 41.
  • the planar configuration is such that the polysilicon film 90 surrounds the periphery of the high concentration base region 51.
  • the other parts are the same as (a) of FIG.
  • FIG. 3F is a diagram showing an ion implantation process. 3F, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
  • a resist 102 is selectively formed and patterned on the surface of the structure shown in FIG. 3E.
  • An emitter region 60 that is an impurity region is formed on the surface of the high-concentration base region 51 of the base region 50.
  • a drain region 62 and a source region 63 are formed on the surface of the p-type well layer 55.
  • ions are implanted on the surface of the base region 50, and an impurity region (emitter region 60) is further formed.
  • a collector contact region 61 is formed on the surface of the portion of the n-type layer 20 covered with the gate oxide film 80. If the formation of the gate oxide film 80 is omitted, the collector contact region 61 may be formed on the surface of the exposed portion of the n-type layer 20 in the bipolar transistor formation region 41.
  • the resist 102 is patterned, and a portion where no impurity region is formed is covered with the resist 102.
  • ions are implanted using the resist 102, the LOCOS oxide film 70, and the polysilicon film 90 as a mask.
  • the LOCOS oxide film 70 is used as a part of the mask, ions are implanted with low energy that does not pass through the LOCOS oxide film 70.
  • the portion of the semiconductor substrate 40 that is not covered with the LOCOS oxide film 70 is covered with a thin gate oxide film 80, so that the gate oxide film 80 has low energy to transmit and ions are implanted. It is.
  • phosphorus may be used as the ions to be implanted.
  • the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are formed with the n-type conductivity type on the surfaces of the base region 50 and the p-type well layer 55. Note that since the drain region 62 and the source region 63 are the same impurity region, the arrangement may be reversed.
  • the shape and size of the emitter region 60 are determined with high accuracy by the polysilicon film 90 functioning as a mask, and the emitter region 60 can be formed with high accuracy. Thereby, in the base region 50, the width of the high concentration base region 51 between the emitter region 60 and the low concentration base region 52 can be appropriately ensured.
  • FIG. 3F shows a plan view of the bipolar transistor formation region 41.
  • FIG. 3G is a diagram showing a heat treatment process.
  • (a) is a plan view of the bipolar transistor formation region 41
  • (b) is a cross-sectional view of the semiconductor substrate 40.
  • the semiconductor substrate 40 is heat-treated after removing the resist 102.
  • the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 formed on the surface of the semiconductor substrate 40 expand laterally and downward.
  • the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are formed thin on the surface of the semiconductor substrate 40 by low energy ion implantation, and compared with the base region 50 and the p-type well layer 55, The layer is considerably thin. Therefore, the lateral expansion amount due to the thermal diffusion is considerably smaller than that during the thermal diffusion of the base region 50, and the emitter region 60 does not dig into the high-concentration base region 51, and the end of the emitter region 60 is sufficiently covered. Can be controlled.
  • the polysilicon film 90 in the bipolar transistor formation region 41 remains on the semiconductor substrate 40 as in the LOCOS oxide film 70, but the emitter region 60 and the base region 50 are separated by the gate oxide film 80. Since it is electrically disconnected and no voltage is applied, the operation of the bipolar transistor is not adversely affected.
  • the polysilicon film 90 is formed and functions as a gate.
  • FIG. 3G (a) transparently shows a plan view of the bipolar transistor formation region 41.
  • the emitter region 60 whose surface is covered with the gate oxide film 80 is surrounded by the polysilicon film 90.
  • a low concentration base region 52 is formed under the LOCOS oxide film 70.
  • the portion where the high-concentration base region 51 is not covered with the polysilicon film 90 but only with the gate oxide film 80 is a base contact region. From here, current input to the base is performed.
  • an npn bipolar transistor can be manufactured through a series of steps shown in FIGS. 3A to 3G.
  • FIG. 4 is an enlarged view of portion B in FIG. 3G (b).
  • a boundary portion between the emitter region 60 and the base region 50 of the completed bipolar transistor is shown.
  • the mask is formed by the polysilicon film 90, so that the emitter region 60 is not affected by the LOCOS oxide film 70. It can be formed with high accuracy. Thereby, it is possible to avoid the end of the emitter region 60 from biting into the high-concentration base region 51, and to ensure a sufficient size in the lateral direction of the high-concentration base region 51.
  • FIG. 5 is a diagram for explaining an operation example of the npn-type bipolar transistor according to the present embodiment.
  • the npn-type bipolar transistor preferably has a normal operation in which the electrons of the minority carriers injected into the emitter region 60 move vertically and pass through the base region 50 and flow into the n-type layer 20 which is the collector region. Is the action.
  • the width of the high-concentration base region 51 that surrounds the emitter region 60 from the side is small, the fractional carriers flow in the horizontal direction instead of the vertical direction.
  • the high concentration base region 51 and the low concentration base region 52 have an impurity concentration gradient, the fractional carriers injected into the high concentration base region 51 are efficiently transferred to the low concentration base region 52. That is, a parasitic operation occurs.
  • the width of the high concentration base region 51 is sufficiently long, it is possible to suppress the fractional carriers injected into the emitter region 60 from passing through the high concentration base region 51 and further moving to the low concentration base region 52. Parasitic operation can be prevented.
  • the polysilicon film 90 with high processing accuracy covers the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40, and an ion implantation process is performed using this as a mask, so that the end portion of the emitter region 60 is obtained. Is formed so as to face the end portions of the polysilicon film 90 and the LOCOS oxide film 70. Further, by defining the area of the emitter region 60 on the surface of the semiconductor substrate 40 with a mask of the polysilicon film 90 with high processing accuracy, the variation in the area of the emitter region 60 can be suppressed.
  • the bipolar transistor can be operated vertically.
  • a bipolar transistor having designed characteristics can be obtained.
  • the bipolar transistor can be manufactured using the same process as that of the MOS transistor. Even when the bipolar transistor and the MOS transistor are manufactured on the same semiconductor substrate 40, the semiconductor device can be manufactured efficiently. it can.
  • the semiconductor device manufactured by the method for manufacturing a semiconductor device according to this embodiment can be used for various electronic circuits, and can be configured as a reference voltage generation circuit, for example. Then, by housing the semiconductor device in a package, it can be configured as a semiconductor integrated circuit device. As a result, the semiconductor integrated circuit device having excellent characteristics in which the impurity regions are formed as designed and there is no variation can be obtained.
  • CMOS complementary metal-oxide-semiconductor
  • a polysilicon film with high processing accuracy can be used as a mask, and an impurity region can be formed with high accuracy by a simple manufacturing process.
  • a semiconductor device manufacturing method is also used for a semiconductor device manufacturing process in which another impurity region is formed on the surface of an impurity region formed by high-energy ion implantation.
  • another impurity region is formed on the surface of an impurity region formed by high-energy ion implantation.
  • an active region of a transistor can be formed with high accuracy, and a transistor with favorable characteristics and less variation can be manufactured.
  • a bipolar transistor with good characteristics and little variation can be manufactured.
  • the present invention can be applied to a manufacturing process of a semiconductor device including a bipolar transistor and the like, and a semiconductor integrated circuit device using such a semiconductor device.

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Abstract

Disclosed is a semiconductor device manufacturing method that involves a step for forming a LOCOS oxide film on a prescribed area of a surface of a semiconductor substrate, a step for forming a polysilicon film to cover the boundaries between the aforementioned surface of the semiconductor substrate and said LOCOS oxide film, and a step for forming an impurity region on the aforementioned surface of the semiconductor substrate by bombarding the aforementioned surface of the semiconductor substrate with ions using said polysilicon film as a mask.

Description

半導体装置の製造方法及び半導体集積回路装置Semiconductor device manufacturing method and semiconductor integrated circuit device
　本発明は、半導体装置の製造方法及び半導体集積回路装置に関し、特に、半導体基板の表面の所定領域に、ＬＯＣＯＳ酸化膜を形成する半導体装置の製造方法及びかかる方法により製造された半導体装置を有する半導体集積回路装置に関する。 The present invention relates to a method for manufacturing a semiconductor device and a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor device in which a LOCOS oxide film is formed in a predetermined region on the surface of a semiconductor substrate, and a semiconductor having the semiconductor device manufactured by such a method. The present invention relates to an integrated circuit device.
　従来から、半導体基板の表面に、ＬＯＣＯＳ（Local Oxidation of Silicon）法によりＬＯＣＯＳ酸化膜を形成し、更にレジストを用いて、ＬＯＣＯＳ酸化膜とレジストをマスクとしてイオンの打ち込みを行い、デバイスを形成する半導体装置の製造方法が知られている。 Conventionally, a LOCOS oxide film is formed on the surface of a semiconductor substrate by a LOCOS (Local Oxidation of Silicon) method, and a resist is used to implant ions using the LOCOS oxide film and the resist as a mask to form a device. Device manufacturing methods are known.
　図１Ａ乃至図１Ｆは、従来の半導体装置の製造方法の一例を示した図である。図１Ａ乃至図１Ｆにおいては、ｎｐｎトランジスタの製造方法の一例を説明する。図１Ａ乃至図１Ｆのそれぞれにおいて（ａ）、（ｂ）はそれぞれ平面図、断面図を示す。図１Ａは、ＬＯＣＯＳ酸化膜形成工程を示した図である。ＬＯＣＯＳ酸化膜形成工程において、シリコン基板１１０上にｎ型層１２０が形成された半導体基板１４０の表面に、ＬＯＣＯＳ法によりＬＯＣＯＳ酸化膜１７０が形成される。（ａ）の平面図に示すように、半導体基板１４０の表面のトランジスタ等のデバイスを形成する領域が、ＬＯＣＯＳ酸化膜１７０で周囲を囲まれる。 1A to 1F are views showing an example of a conventional method for manufacturing a semiconductor device. 1A to 1F, an example of a method for manufacturing an npn transistor will be described. In each of FIGS. 1A to 1F, (a) and (b) show a plan view and a cross-sectional view, respectively. FIG. 1A is a diagram showing a LOCOS oxide film forming step. In the LOCOS oxide film formation step, a LOCOS oxide film 170 is formed by a LOCOS method on the surface of the semiconductor substrate 140 on which the n-type layer 120 is formed on the silicon substrate 110. As shown in the plan view of FIG. 5A, a region for forming a device such as a transistor on the surface of the semiconductor substrate 140 is surrounded by a LOCOS oxide film 170.
　図１Ｂは、ベース領域形成工程を示した図である。半導体基板１４０の不純物領域を形成しない部分は、レジスト２００で覆われ、不純物領域を形成する部分は、レジスト２００で覆われないで露出された状態となる。この、レジスト２００がパターニングされた状態で、半導体基板１４０にイオンが打ち込まれ、不純物の注入が行われる。イオンは、例えば、ボロン等が用いられる。イオンは、高エネルギーで打ち込みが行われ、ＬＯＣＯＳ酸化膜１７０のある部分は、ＬＯＣＯＳ酸化膜１７０を透過してイオンが打ち込まれる。ＬＯＣＯＳ酸化膜１７０の無い部分は、直接ｎ型層１２０にイオンが打ち込まれる。半導体基板１４０のイオンが打ち込まれた箇所は、不純物が注入されたベース領域１５０となる。ベース領域１５０中、ＬＯＣＯＳ酸化膜１７０が無く、半導体基板１４０のｎ型層１２０が露出した箇所は、高濃度ベース領域１５１となり、ＬＯＣＯＳ酸化膜１７０の下の箇所は、低濃度ベース領域１５２となる。 FIG. 1B is a diagram showing a base region forming process. A portion of the semiconductor substrate 140 where the impurity region is not formed is covered with the resist 200, and a portion where the impurity region is formed is not covered with the resist 200 and is exposed. With the resist 200 patterned, ions are implanted into the semiconductor substrate 140, and impurities are implanted. For example, boron or the like is used as the ion. Ions are implanted with high energy, and a portion of the LOCOS oxide film 170 is transmitted through the LOCOS oxide film 170 and implanted. In the portion where the LOCOS oxide film 170 is not present, ions are directly implanted into the n-type layer 120. A portion of the semiconductor substrate 140 where ions are implanted becomes a base region 150 into which impurities are implanted. In the base region 150, the portion where the LOCOS oxide film 170 is not present and the n-type layer 120 of the semiconductor substrate 140 is exposed becomes the high concentration base region 151, and the portion below the LOCOS oxide film 170 becomes the low concentration base region 152. .
　図１Ｃは、熱処理工程を示した図である。図１Ｂにおいて、高エネルギーイオンの打ち込みが行われた後は、レジスト２００が除去され、半導体基板１４０の加熱処理が行われる。これにより、ベース領域１５０の熱拡散が行われ、注入された不純物がベース領域１５０中を拡散し、不純物濃度の濃度分布が平均化の方向に向かうとともに、ベース領域１５０が側方及び下方に拡大する。 FIG. 1C is a diagram showing a heat treatment process. In FIG. 1B, after high-energy ion implantation is performed, the resist 200 is removed and the semiconductor substrate 140 is subjected to heat treatment. As a result, thermal diffusion of the base region 150 is performed, and the implanted impurities are diffused in the base region 150, and the concentration distribution of the impurity concentration goes in the direction of averaging, and the base region 150 expands laterally and downward. To do.
　図１Ｄは、ゲート酸化膜形成工程を示した図である。ゲート酸化膜形成工程においては、高濃度ベース領域１５１が露出した部分に、ゲート酸化膜１８０が形成される。これにより、高濃度ベース領域１５１の表面は、ゲート酸化膜１８０に覆われる。なお、ゲート酸化膜１８０は、ＭＯＳトランジスタを製造するプロセスにおける、ゲート酸化膜１８０と同様の薄膜状の酸化膜という意味であり、必ずしもその領域にゲートを形成するという意味ではない。 FIG. 1D is a diagram showing a gate oxide film forming step. In the gate oxide film forming step, a gate oxide film 180 is formed in a portion where the high-concentration base region 151 is exposed. As a result, the surface of the high concentration base region 151 is covered with the gate oxide film 180. The gate oxide film 180 means a thin oxide film similar to the gate oxide film 180 in the process of manufacturing a MOS transistor, and does not necessarily mean that a gate is formed in that region.
　図１Ｅは、エミッタ領域形成工程を示した図である。エミッタ領域形成工程においては、半導体基板１４０のイオンの打ち込みを行わない箇所がレジスト２０２で覆われる。一方、イオンの打ち込みの際、有機物のレジスト２０２が削れてエミッタ領域１６０に混入すると、エミッタ領域１６０の特性に悪影響を与えるため、エミッタ領域１６０の端部は、ＬＯＣＯＳ酸化膜１７０をマスクとしてイオンの打ち込みが行われる。イオンは、例えば、リンが用いられてよい。また、イオンの打ち込みは、ゲート酸化膜１８０の形成された領域に、ＬＯＣＯＳ酸化膜１７０をマスクとして行われるため、ゲート酸化膜１８０を透過し、かつＬＯＣＯＳ酸化膜１７０を透過しない程度の低エネルギーで行われる。低エネルギーイオンの打ち込みにより、不純物領域であるベース領域１５０の表面に、やはり不純物領域であるエミッタ領域１６０が形成される。 FIG. 1E is a diagram showing an emitter region forming step. In the emitter region forming step, the portion of the semiconductor substrate 140 where ions are not implanted is covered with the resist 202. On the other hand, if the organic resist 202 is scraped and mixed into the emitter region 160 when ions are implanted, the characteristics of the emitter region 160 are adversely affected. Therefore, the end of the emitter region 160 is ion-doped with the LOCOS oxide film 170 as a mask. Driving is done. For example, phosphorus may be used as the ion. In addition, since the ion implantation is performed in the region where the gate oxide film 180 is formed using the LOCOS oxide film 170 as a mask, the ion implantation is performed with low energy so as to pass through the gate oxide film 180 and not through the LOCOS oxide film 170. Done. By implantation of low energy ions, an emitter region 160 that is also an impurity region is formed on the surface of the base region 150 that is an impurity region.
　図１Ｆは、熱処理工程を示した図である。熱処理工程においては、半導体基板１４０が加熱処理され、エミッタ領域１６０の熱拡散が行われる。これにより、エミッタ領域１６０の不純物濃度が平均化するとともに、エミッタ領域１６０が側方及び下方に拡大する。なお、ｎ型層１２０は、コレクタ領域として機能し、ｎｐｎ型バイポーラトランジスタを形成することができる。なお、ｎ型層１２０は、例えば、エピタキシャル成長により、Ｐ型のシリコン基板の上に形成されてもよい。 FIG. 1F is a diagram showing a heat treatment process. In the heat treatment step, the semiconductor substrate 140 is subjected to heat treatment, and thermal diffusion of the emitter region 160 is performed. As a result, the impurity concentration of the emitter region 160 is averaged, and the emitter region 160 expands laterally and downward. Note that the n-type layer 120 functions as a collector region and can form an npn-type bipolar transistor. The n-type layer 120 may be formed on a P-type silicon substrate by, for example, epitaxial growth.
　また、例えば、特許文献１には、ＭＯＳ（Metal-Oxide-Semiconductor）トランジスタとバイポーラトランジスタが同一の半導体基板上に混載されているＢｉＣＭＯＳ（Bipolar Complementary Metal-Oxide-Semiconductor）集積回路装置であって、バイポーラトランジスタは、ベース層に接続された、側面に絶縁体の側壁を有するベース引出電極を有し、当該絶縁体の側壁を用いて、エミッタ電極引出開口及びエミッタ層を自己整合的に形成したものが記載されている。 Further, for example, Patent Document 1 discloses a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) integrated circuit device in which a MOS (Metal-Oxide-Semiconductor) transistor and a bipolar transistor are mixedly mounted on the same semiconductor substrate. The bipolar transistor has a base extraction electrode having an insulator side wall connected to the base layer, and an emitter electrode extraction opening and an emitter layer formed in a self-aligned manner using the insulator side wall. Is described.
　かかるＢｉＣＭＯＳ集積回路装置の絶縁体の側壁の形成は、ベース引出電極上に絶縁膜を形成する工程と、ベース引出電極の側面及びベース引出電極に取り囲まれたエミッタ形成領域を含む半導体基板全体にＴＥＯＳ膜の絶縁膜を成長させる工程と、ＴＥＯＳ膜の絶縁膜を異方性エッチングして、エミッタ形成領域上のベース引出電極側面に側壁を残す工程と、を含んでいる。 The side wall of the insulator of the BiCMOS integrated circuit device is formed by forming a TEOS on the entire semiconductor substrate including the step of forming an insulating film on the base lead electrode and the side surface of the base lead electrode and the emitter forming region surrounded by the base lead electrode. A step of growing an insulating film of the film, and a step of anisotropically etching the insulating film of the TEOS film to leave a side wall on the side surface of the base extraction electrode on the emitter formation region.
特開平１１－１１１８７３号公報Japanese Patent Laid-Open No. 11-111873
　しかしながら、上述の図１Ａ乃至図１Ｆの従来技術の構成では、エミッタ領域１６０のサイズが、ＬＯＣＯＳ酸化膜１７０の加工精度及び膜厚に影響を受けてしまい、エミッタ領域１６０の変動により、隣接するデバイスの特性が不均一となるという問題があった。また、エミッタ領域１６０のサイズが大きくなると、ベース領域１５０の高濃度ベース領域１５１のサイズが小さくなり、バイポーラトランジスタを縦方向に動作させたいにも関わらず、横方向の寄生動作が発生するようになり、トランジスタ特性が悪化するとともにバラつきが生じてしまうという問題があった。 However, in the configuration of the prior art of FIGS. 1A to 1F described above, the size of the emitter region 160 is affected by the processing accuracy and film thickness of the LOCOS oxide film 170, and the adjacent device is affected by the variation of the emitter region 160. There was a problem that the characteristics of the film became non-uniform. Further, when the size of the emitter region 160 is increased, the size of the high-concentration base region 151 of the base region 150 is reduced, so that a parasitic operation in the lateral direction occurs even though the bipolar transistor is desired to operate in the vertical direction. As a result, there is a problem that transistor characteristics deteriorate and variations occur.
　図２は、図１Ｆの（ｂ）のＡ部分の拡大図である。図２に示すように、ＬＯＣＯＳ酸化膜１７０の横方向の位置は、加工精度により変動するおそれがある。また、ＬＯＣＯＳ酸化膜１７０の端部は、外側に向かうにつれて膜厚が減少する、三角形の頂点のような先端が尖った断面形状となっている。このような形状であると、ＬＯＣＯＳ酸化膜１７０の端部の横方向の位置により、膜厚も微妙に変化し、エミッタ領域１６０の横方向の大きさもそれによって影響を受けて変動する。同様に、ＬＯＣＯＳ酸化膜１７０の透過により不純物が注入される高濃度ベース領域１５１は、ＬＯＣＯＳ酸化膜１７０の三角形状の膜厚が変化する部分の下方にあるため、ＬＯＣＯＳ酸化膜１７０の加工精度及び膜厚が、その不純物濃度に影響を与える。 FIG. 2 is an enlarged view of portion A in FIG. 1F (b). As shown in FIG. 2, the lateral position of the LOCOS oxide film 170 may vary depending on the processing accuracy. In addition, the end portion of the LOCOS oxide film 170 has a cross-sectional shape with a sharp tip such as the apex of a triangle in which the film thickness decreases toward the outside. With such a shape, the film thickness slightly changes depending on the position of the end portion of the LOCOS oxide film 170 in the lateral direction, and the lateral size of the emitter region 160 is affected and fluctuates accordingly. Similarly, the high-concentration base region 151 into which impurities are implanted by permeation of the LOCOS oxide film 170 is located below the portion of the LOCOS oxide film 170 where the triangular film thickness changes, so that the processing accuracy of the LOCOS oxide film 170 and The film thickness affects the impurity concentration.
　また、高濃度ベース領域１５１の不純物濃度は、トランジスタの動作中、エミッタ領域１６０から注入された小数キャリアの拡散長に影響を及ぼす。一方、低濃度ベース領域１５２は、ＬＯＣＯＳ酸化膜１７０の厚膜部分を通して打ち込まれているので、高濃度ベース領域１５１よりも、不純物濃度が低い。また、低濃度ベース領域１５２は、不純物濃度が低いので、小数キャリアの拡散長が長い。このように、高濃度ベース領域１５１から低濃度ベース領域１５２にかけて、不純物の濃度勾配があるので、高濃度ベース領域１５１に注入された小数キャリアは、効率よく低濃度ベース領域１５２に移送され、トランジスタの横方向の寄生動作が大きくなってしまうという問題があった。 Also, the impurity concentration of the high concentration base region 151 affects the diffusion length of the minority carriers injected from the emitter region 160 during the operation of the transistor. On the other hand, since the low concentration base region 152 is implanted through the thick film portion of the LOCOS oxide film 170, the impurity concentration is lower than that of the high concentration base region 151. Further, since the low concentration base region 152 has a low impurity concentration, the diffusion length of the minority carriers is long. Thus, since there is an impurity concentration gradient from the high concentration base region 151 to the low concentration base region 152, the fractional carriers injected into the high concentration base region 151 are efficiently transferred to the low concentration base region 152, and the transistor There is a problem that the parasitic operation in the lateral direction becomes large.
　更に、特許文献１に記載の構成では、エミッタ領域を酸化膜の側壁で精度よく形成することは可能であるが、上述のように、複雑な工程を必要とし、製造工程が複雑化し、コスト増にも繋がるという問題があった。また、通常のＭＯＳトランジスタの製造工程とは異なる工程が多く、バイポーラトランジスタを、ＭＯＳトランジスタの工程と同じ工程で製造することができず、工程数の増加に繋がるという問題があった。 Furthermore, in the configuration described in Patent Document 1, it is possible to form the emitter region with the sidewall of the oxide film with high accuracy. However, as described above, a complicated process is required, the manufacturing process is complicated, and the cost is increased. There was a problem of being connected. In addition, there are many processes different from the manufacturing process of a normal MOS transistor, and the bipolar transistor cannot be manufactured in the same process as the MOS transistor process, leading to an increase in the number of processes.
　そこで、本発明は、簡素な工程で、デバイスの特性を均一化することができる半導体装置の製造方法及びかかる方法により製造された半導体装置を有する半導体集積回路装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of uniformizing device characteristics and a semiconductor integrated circuit device having the semiconductor device manufactured by such a method by a simple process.
　本発明の一側面によれば、半導体装置の製造方法は、半導体基板の表面の所定領域に、ＬＯＣＯＳ酸化膜を形成する工程と、該ＬＯＣＯＳ酸化膜と前記半導体基板の表面の境界を覆うように、ポリシリコン膜を形成する工程と、該ポリシリコン膜をマスクとして、前記半導体基板の表面にイオンの打ち込みを行い、前記半導体基板の表面に、不純物領域を形成する工程と、を含む。 According to one aspect of the present invention, a method of manufacturing a semiconductor device includes a step of forming a LOCOS oxide film in a predetermined region of a surface of a semiconductor substrate, and covering a boundary between the LOCOS oxide film and the surface of the semiconductor substrate. A step of forming a polysilicon film, and a step of implanting ions on the surface of the semiconductor substrate using the polysilicon film as a mask to form an impurity region on the surface of the semiconductor substrate.
　本発明の一側面によれば、特性が良好で均一な半導体装置又は半導体集積回路装置が提供される。 According to one aspect of the present invention, a semiconductor device or a semiconductor integrated circuit device having excellent characteristics and uniformity is provided.
　本発明の他の目的、特徴及び利点は添付の図面を参照し以下の詳細な説明を読むことにより、一層明瞭となるであろう。
従来の半導体装置の製造方法の一例におけるＬＯＣＯＳ酸化膜形成工程を示した図である。 従来の半導体装置の製造方法の一例におけるベース領域形成工程を示した図である。 従来の半導体装置の製造方法の一例における熱処理工程を示した図である。 従来の半導体装置の製造方法の一例におけるゲート酸化膜形成工程を示した図である。 従来の半導体装置の製造方法の一例におけるエミッタ領域形成工程を示した図である。 従来の半導体装置の製造方法の一例における熱処理工程を示した図である。 図１Ｆの（ｂ）のＡ部分の拡大図である。 本発明の一実施例によるＬＯＣＯＳ酸化膜形成工程を示した図であり、（ａ）は半導体装置が製造される半導体基板の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例による高エネルギーイオン打ち込み工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例による熱処理工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例によるゲート酸化膜形成工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例によるポリシリコン膜形成工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例によるイオン打ち込み工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例による熱処理工程を示した図であり、（ａ）はバイポーラトランジスタ形成領域の平面図、（ｂ）は半導体基板の断面図である。 本発明の一実施例による図３Ｇの（ｂ）のBの部分を拡大した図である。 本発明の一実施例に係るｎｐｎ型バイポーラトランジスタの動作例を説明する図である。 Other objects, features and advantages of the present invention will become more apparent upon reading the following detailed description with reference to the accompanying drawings.
It is the figure which showed the LOCOS oxide film formation process in an example of the manufacturing method of the conventional semiconductor device. It is the figure which showed the base area | region formation process in an example of the manufacturing method of the conventional semiconductor device. It is the figure which showed the heat treatment process in an example of the manufacturing method of the conventional semiconductor device. It is the figure which showed the gate oxide film formation process in an example of the manufacturing method of the conventional semiconductor device. It is the figure which showed the emitter region formation process in an example of the manufacturing method of the conventional semiconductor device. It is the figure which showed the heat treatment process in an example of the manufacturing method of the conventional semiconductor device. It is an enlarged view of the A part of (b) of FIG. 1F. 1A and 1B are views showing a LOCOS oxide film forming process according to an embodiment of the present invention, in which FIG. 1A is a plan view of a semiconductor substrate on which a semiconductor device is manufactured, and FIG. 4A and 4B are diagrams showing a high energy ion implantation process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate. It is the figure which showed the heat processing process by one Example of this invention, (a) is a top view of a bipolar transistor formation area, (b) is sectional drawing of a semiconductor substrate. 4A and 4B are diagrams illustrating a gate oxide film forming process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate. 4A and 4B are diagrams illustrating a polysilicon film forming process according to an embodiment of the present invention, in which FIG. 5A is a plan view of a bipolar transistor formation region, and FIG. 5B is a cross-sectional view of a semiconductor substrate. It is the figure which showed the ion implantation process by one Example of this invention, (a) is a top view of a bipolar transistor formation area, (b) is sectional drawing of a semiconductor substrate. It is the figure which showed the heat processing process by one Example of this invention, (a) is a top view of a bipolar transistor formation area, (b) is sectional drawing of a semiconductor substrate. It is the figure which expanded the B section of (b) of Drawing 3G by one example of the present invention. It is a figure explaining the operation example of the npn-type bipolar transistor which concerns on one Example of this invention.
　以下、添付の図面を参照して、本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
　図３Ａ乃至図３Ｇは、本発明の実施例に係る半導体装置の製造方法の一連の工程を示した図である。 3A to 3G are diagrams showing a series of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
　図３Ａは、ＬＯＣＯＳ酸化膜形成工程を示した図である。図３Ａにおいて、（ａ）は半導体装置が製造される半導体基板４０の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3A is a diagram showing a LOCOS oxide film forming step. 3A is a plan view of the semiconductor substrate 40 on which the semiconductor device is manufactured, and FIG. 3B is a cross-sectional view of the semiconductor substrate 40.
　図３Ａの（ｂ）を参照すれば、半導体基板４０は、シリコン基板１０と、ｎ型層２０と、ｐ型層３０とを有する。また、半導体基板４０の表面に、ＬＯＣＯＳ酸化膜７０が形成されている。シリコン基板１０は、他の半導体材料からなる基板であってもよいが、本実施例においては、シリコン基板１０を用いた例を挙げて説明する。ｎ型層２０は、例えば、エピタキシャル成長によって形成されてもよい。 Referring to (b) of FIG. 3A, the semiconductor substrate 40 includes a silicon substrate 10, an n-type layer 20, and a p-type layer 30. A LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40. The silicon substrate 10 may be a substrate made of another semiconductor material, but in this embodiment, an example using the silicon substrate 10 will be described. For example, the n-type layer 20 may be formed by epitaxial growth.
　半導体基板４０の表面は、バイポーラトランジスタ形成領域４１と、ＭＯＳトランジスタ形成領域４２とを有している。本実施例に係る半導体装置の製造方法は、ＭＯＳトランジスタの製造工程を利用しつつ、高精度に不純物領域が形成された半導体装置を製造することができる。よって、図３Ａ乃至図３Ｇにおいては、本実施例に係る半導体装置の製造方法によりｎｐｎ型バイポーラトランジスタを製造するとともに、ｎチャネルＭＯＳトランジスタを同じ半導体基板４０上に形成する例を示すこととする。但し、本実施例に係る半導体装置の製造方法は、ＭＯＳトランジスタを同時に製造する工程だけでなく、単独でデバイスの製造に用いることができるので、ＭＯＳトランジスタの製造は、必ずしも同時に行われる必要は無い。 The surface of the semiconductor substrate 40 has a bipolar transistor formation region 41 and a MOS transistor formation region 42. The semiconductor device manufacturing method according to the present embodiment can manufacture a semiconductor device in which an impurity region is formed with high accuracy while utilizing a MOS transistor manufacturing process. Therefore, FIGS. 3A to 3G show an example in which an npn bipolar transistor is manufactured by the method of manufacturing a semiconductor device according to this embodiment and an n-channel MOS transistor is formed on the same semiconductor substrate 40. However, since the semiconductor device manufacturing method according to the present embodiment can be used not only for the process of simultaneously manufacturing the MOS transistors but also for the device manufacturing alone, the MOS transistors need not always be manufactured at the same time. .
　図３Ａの（ｂ）に示すように、ＬＯＣＯＳ酸化膜形成工程においては、ＬＯＣＯＳ法により、半導体基板４０の表面に、ＬＯＣＯＳ酸化膜７０が形成される。ＬＯＣＯＳ酸化膜７０は、バイポーラトランジスタ形成領域４１と、ｎチャネルＭＯＳトランジスタ４２とを素子分離する位置に形成される。また、ＬＯＣＯＳ酸化膜７０は、イオン打ち込み時のマスクとしても用いられるため、バイポーラトランジスタ形成領域４１内においては、高濃度の不純物領域を形成しない位置にも設けられている。なお、バイポーラトランジスタ形成領域４１と、ＭＯＳトランジスタ形成領域４２との間には、素子分離を行うべく、半導体基板４０の縦方向（深さ方向）にｐ型層３０が設けられている。 As shown in FIG. 3A (b), in the LOCOS oxide film forming step, a LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40 by the LOCOS method. The LOCOS oxide film 70 is formed at a position for isolating the bipolar transistor formation region 41 and the n-channel MOS transistor 42 from each other. Further, since the LOCOS oxide film 70 is also used as a mask at the time of ion implantation, it is provided in the bipolar transistor formation region 41 at a position where a high concentration impurity region is not formed. A p-type layer 30 is provided between the bipolar transistor formation region 41 and the MOS transistor formation region 42 in the vertical direction (depth direction) of the semiconductor substrate 40 in order to perform element isolation.
　図３Ａの（ａ）を参照すれば、半導体基板４０の表面の大半がＬＯＣＯＳ酸化膜７０で覆われ、ＬＯＣＯＳ酸化膜７０で覆われていない領域に、半導体基板４０のｎ型層２０が露出している。このように、ＬＯＣＯＳ酸化膜形成工程においては、ＬＯＣＯＳ酸化膜７０が半導体基板４０の表面に形成され、ＬＯＣＯＳ酸化膜７０が、素子分離酸化膜又はマスクとして機能する。なお、図３Ａの（ａ）においては、バイポーラトランジスタ形成領域４１の表面のみが示されており、図３Ｂ乃至図３Ｇにおいても同様に、（ａ）の平面図については、バイポーラトランジスタ形成領域４１のみを示す。 3A, most of the surface of the semiconductor substrate 40 is covered with the LOCOS oxide film 70, and the n-type layer 20 of the semiconductor substrate 40 is exposed in a region not covered with the LOCOS oxide film 70. ing. Thus, in the LOCOS oxide film formation step, the LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40, and the LOCOS oxide film 70 functions as an element isolation oxide film or a mask. 3A, only the surface of the bipolar transistor formation region 41 is shown. Similarly, in FIGS. 3B to 3G, only the bipolar transistor formation region 41 is shown in the plan view of FIG. 3A. Indicates.
　また、半導体基板４０は、半導体材料であれば、種々の半導体材料からなる基板として構成することができる。例えば、半導体基板４０は、シリコン基板として構成されてもよい。また、本実施例に係る半導体装置の製造方法においては、半導体基板４０が、ｎ型の導電型である場合を例に挙げて説明することとする。 The semiconductor substrate 40 can be configured as a substrate made of various semiconductor materials as long as it is a semiconductor material. For example, the semiconductor substrate 40 may be configured as a silicon substrate. Further, in the method for manufacturing a semiconductor device according to the present embodiment, the case where the semiconductor substrate 40 is an n-type conductivity will be described as an example.
　図３Ｂは、高エネルギーイオン打ち込み工程を示した図である。図３Ｂにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3B is a diagram showing a high energy ion implantation process. 3B, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　図３Ｂの（ｂ）を参照すれば、半導体基板４０の表面（表層）に、膜状のレジスト１００が塗布され、イオンが打ち込まれている。高エネルギーイオン打ち込み工程においては、半導体基板４０の表面（表層）に、不純物であるイオンが高エネルギーで打ち込まれ、ベース領域５０及びｐ型ウェル層５５が形成される。イオンは、例えば、ボロンが用いられてもよい。この場合、ｎ型の半導体基板４０の表面に、ｐ型不純物領域であるベース領域５０及びｐ型ウェル層５５が形成されることになる。レジスト１００は、半導体基板４０上のｐ型不純物領域５０、５５を形成しない部分を覆うように、パターニングされて選択的に形成される。 Referring to FIG. 3B (b), a film-like resist 100 is applied to the surface (surface layer) of the semiconductor substrate 40, and ions are implanted. In the high energy ion implantation process, ions as impurities are implanted with high energy into the surface (surface layer) of the semiconductor substrate 40 to form the base region 50 and the p-type well layer 55. For example, boron may be used as the ion. In this case, the base region 50 and the p-type well layer 55 which are p-type impurity regions are formed on the surface of the n-type semiconductor substrate 40. The resist 100 is selectively formed by patterning so as to cover portions of the semiconductor substrate 40 where the p- type impurity regions 50 and 55 are not formed.
　レジスト１００の形成後は、半導体基板４０にイオンを高エネルギーで打ち込み、ベース領域５０及びｐ型ウェル層５５を形成するが、イオンは高エネルギーで打ち込まれるため、ＬＯＣＯＳ酸化膜７０を透過して、ＬＯＣＯＳ酸化膜７０の下にもベース領域５０及びｐ型ウェル層５５が形成される。なお、ここで言う高エネルギーは、半導体基板４０に打ち込まれたイオンが、ＬＯＣＯＳ酸化膜７０を透過してＬＯＣＯＳ酸化膜７０の下に不純物領域を形成できる程のエネルギーという意味であり、具体的なエネルギー値は、半導体基板４０やイオンの材質等により変化し得る。 After the formation of the resist 100, ions are implanted into the semiconductor substrate 40 with high energy to form the base region 50 and the p-type well layer 55. Since the ions are implanted with high energy, the ions pass through the LOCOS oxide film 70, A base region 50 and a p-type well layer 55 are also formed under the LOCOS oxide film 70. The high energy mentioned here means energy that allows ions implanted into the semiconductor substrate 40 to pass through the LOCOS oxide film 70 and form an impurity region under the LOCOS oxide film 70. The energy value can vary depending on the semiconductor substrate 40, the ion material, and the like.
　ベース領域５０内において、ＬＯＣＯＳ酸化膜７０で覆われていない、半導体基板４０の表面が露出した部分は、不純物の濃度が高い高濃度ベース領域５１となる。また、ＬＯＣＯＳ酸化膜７０に覆われたＬＯＣＯＳ酸化膜７０の下方の部分は、低濃度ベース領域５２となる。ＭＯＳトランジスタ形成領域４２にも同様に、高濃度ｐ型ウェル層５６及び低濃度ｐ型ウェル層５７がｐ型ウェル層５５内に形成される。 In the base region 50, the portion where the surface of the semiconductor substrate 40 is exposed, which is not covered with the LOCOS oxide film 70, becomes a high concentration base region 51 having a high impurity concentration. Further, the lower portion of the LOCOS oxide film 70 covered with the LOCOS oxide film 70 becomes a low-concentration base region 52. Similarly, in the MOS transistor formation region 42, a high concentration p-type well layer 56 and a low concentration p-type well layer 57 are formed in the p-type well layer 55.
　図３Ｂの（ａ）に示されるバイポーラトランジスタ形成領域４１の平面図を参照すれば、枠状にレジスト１００が形成され、レジスト１００の開口１０１に、マスクとして機能するＬＯＣＯＳ酸化膜７０と、ベース領域５０が露出している。 Referring to the plan view of the bipolar transistor formation region 41 shown in FIG. 3B, a resist 100 is formed in a frame shape, a LOCOS oxide film 70 functioning as a mask, and a base region in the opening 101 of the resist 100. 50 is exposed.
　図３Ｃは、熱処理工程を示した図である。図３Ｃにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3C is a diagram showing a heat treatment process. 3C, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　熱処理工程においては、高エネルギーイオン打ち込み工程で用いたレジスト１００が除去された後、半導体基板４０が加熱処理され、ベース領域５０及びｐ型ウェル層５５内の不純物を拡散させ、不純物濃度分布の均一化が図られる。また、熱処理工程において、ベース領域５０及びｐ型ウェル層５５の大きさが、側方及び下方に拡大される。 In the heat treatment process, after the resist 100 used in the high energy ion implantation process is removed, the semiconductor substrate 40 is subjected to a heat treatment to diffuse the impurities in the base region 50 and the p-type well layer 55, so that the impurity concentration distribution is uniform. Is achieved. Further, in the heat treatment step, the sizes of the base region 50 and the p-type well layer 55 are expanded laterally and downward.
　図３Ｃの（ｂ）を参照すれば、図３Ｂの（ｂ）と比較して、半導体基板４０において、ベース領域５０及びＰ型ウェル層５５が横方向及び下方向に拡大している。図３Ｃの（ｂ）に示すように、半導体基板４０が露出した部分は、高濃度ベース領域５１及び高濃度ｐ型ウェル層５６が拡大し、ＬＯＣＯＳ酸化膜７０の下方は、低濃度ベース領域５２及び低濃度ｐ型ウェル層５７が拡大している。 Referring to (b) of FIG. 3C, compared to (b) of FIG. 3B, the base region 50 and the P-type well layer 55 are expanded laterally and downward in the semiconductor substrate 40. As shown in FIG. 3C (b), the high-concentration base region 51 and the high-concentration p-type well layer 56 are enlarged in the portion where the semiconductor substrate 40 is exposed, and the low-concentration base region 52 is located under the LOCOS oxide film 70. And the low concentration p-type well layer 57 is enlarged.
　図３Ｃの（ａ）は、バイポーラトランジスタ形成領域４１の平面図を透過的に示している。なお、図面において括弧内の参照符号が、透過的に表された領域を示している。図３Ｃの（ａ）では、参照符号が括弧内に示される低濃度ベース領域５２が、透過的に表された領域である。バイポーラトランジスタ形成領域４１のうち、図３Ｂの（ａ）において、レジスト１００で覆われていた部分には、ＬＯＣＯＳ酸化膜７０及び半導体基板４０の露出部分が示されている。一方、図３Ｂの（ａ）において、レジスト１００の開口１０１に該当した部分については、ＬＯＣＯＳ酸化膜７０が形成されていない部分は、高濃度ベース領域５１となり、ＬＯＣＯＳ酸化膜７０が形成されていた部分は、低濃度ベース領域５２となっている。 FIG. 3C (a) transparently shows a plan view of the bipolar transistor formation region 41. In the drawings, reference numerals in parentheses indicate regions that are transparently represented. In FIG. 3C (a), the low-concentration base region 52 whose reference symbol is shown in parentheses is a transparently represented region. In the bipolar transistor formation region 41, the exposed portion of the LOCOS oxide film 70 and the semiconductor substrate 40 is shown in the portion covered with the resist 100 in FIG. On the other hand, in FIG. 3B (a), in the portion corresponding to the opening 101 of the resist 100, the portion where the LOCOS oxide film 70 is not formed becomes the high-concentration base region 51, and the LOCOS oxide film 70 is formed. The portion is a low concentration base region 52.
　このように、レジスト１００の有無により、ベース領域５０及びｐ型ウェル層５５の形成領域が制御され、ＬＯＣＯＳ酸化膜７０の有無により、ベース領域５０及びｐ型ウェル層５５内の不純物濃度が制御される。 Thus, the formation region of the base region 50 and the p-type well layer 55 is controlled by the presence or absence of the resist 100, and the impurity concentration in the base region 50 and the p-type well layer 55 is controlled by the presence or absence of the LOCOS oxide film 70. The
　図３Ｄは、ゲート酸化膜形成工程を示した図である。図３Ｄにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3D is a diagram showing a gate oxide film forming step. 3D, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　ゲート酸化膜形成工程においては、ベース領域５０及びｐ型ウェル層５５の表面の露出部分に、ゲート酸化膜８０が形成される。ゲート酸化膜８０は、ＭＯＳトランジスタ製造工程において、ゲート形成領域に形成する薄膜状の酸化膜である。この、薄膜状のゲート酸化膜８０を、ＭＯＳトランジスタ形成領域４２だけでなく、バイポーラトランジスタ形成領域４１にも形成する。なお、ゲート酸化膜は、種々の材料で構成されてよいが、例えば、ＳｉＯ２膜で構成されてもよい。 In the gate oxide film forming step, a gate oxide film 80 is formed on the exposed portions of the surfaces of the base region 50 and the p-type well layer 55. The gate oxide film 80 is a thin oxide film formed in the gate formation region in the MOS transistor manufacturing process. The thin gate oxide film 80 is formed not only in the MOS transistor formation region 42 but also in the bipolar transistor formation region 41. The gate oxide film may be composed of various materials, but may be composed of, for example, a SiO 2 film.
　また、ゲート酸化膜８０を形成する領域は、ＬＯＣＯＳ酸化膜７０の存在しない、半導体基板４０の表面が露出した部分であるので、ｎ型層２０の表面、高濃度ベース領域５１又は高濃度Ｐ型ウェル層５６のいずれかになる。 Further, since the region where the gate oxide film 80 is formed is a portion where the surface of the semiconductor substrate 40 is exposed where the LOCOS oxide film 70 does not exist, the surface of the n-type layer 20, the high-concentration base region 51, or the high-concentration P-type. It becomes one of the well layers 56.
　図３Ｄの（ａ）は、バイポーラトランジスタ形成領域４１の透過的な平面図を示しているが、図３Ｃの（ａ）と略同様の図となる。図３Ｄの（ａ）を参照すれば、バイポーラトランジスタ形成領域４１のうち、高濃度ベース領域５１の部分と、半導体基板４０のｎ型層２０が露出した部分は、表面が薄膜状のゲート酸化膜８０で覆われるが、透過的に図を描くと、図３Ｃの（ａ）と同様の平面構成となる。 FIG. 3D (a) shows a transparent plan view of the bipolar transistor formation region 41, which is substantially the same as FIG. 3C (a). Referring to FIG. 3D, in the bipolar transistor formation region 41, the portion of the high-concentration base region 51 and the portion where the n-type layer 20 of the semiconductor substrate 40 is exposed are thin gate oxide films. Although it is covered with 80, if a figure is drawn transparently, it will become the same plane composition as (a) of Drawing 3C.
　なお、図３Ｄに示すゲート酸化膜形成工程は、例えば、本実施例の半導体装置の製造方法をＭＯＳトランジスタを同時に形成せずデバイスを単独で製造するのに用いる場合には省略しても良い。 The gate oxide film forming step shown in FIG. 3D may be omitted, for example, when the semiconductor device manufacturing method of this embodiment is used to manufacture a device alone without forming a MOS transistor at the same time.
　図３Ｅは、ポリシリコン膜形成工程を示した図である。図３Ｅにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3E is a diagram showing a polysilicon film forming process. 3E, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　図３Ｅの（ｂ）を参照すれば、バイポーラトランジスタ形成領域４１において、ＬＯＣＯＳ酸化膜７０と半導体基板４０のうちエミッタ領域６０（図３Ｆを参照し後述）を形成する部分の表面のゲート酸化膜８０との境界を覆うように、ポリシリコン膜９０が形成されている。ポリシリコン膜９０は、ＭＯＳトランジスタ製造工程において、ゲートを形成する際に用いる。よって、ＭＯＳトランジスタ形成領域４２においては、ゲートとしてポリシリコン膜９０が形成されている。 Referring to (b) of FIG. 3E, in the bipolar transistor formation region 41, the gate oxide film 80 on the surface of the portion of the LOCOS oxide film 70 and the semiconductor substrate 40 where the emitter region 60 (described later with reference to FIG. 3F) is to be formed. A polysilicon film 90 is formed so as to cover the boundary. The polysilicon film 90 is used when forming a gate in the MOS transistor manufacturing process. Therefore, in the MOS transistor formation region 42, the polysilicon film 90 is formed as a gate.
　なお、ゲート酸化膜８０の形成を省略する場合には、上記ポリシリコン膜９０は、バイポーラトランジスタ形成領域４１において、ＬＯＣＯＳ酸化膜７０と半導体基板４０の表面との境界を覆うように形成されて良い。 When the formation of the gate oxide film 80 is omitted, the polysilicon film 90 may be formed so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40 in the bipolar transistor formation region 41. .
　一方、バイポーラトランジスタ形成領域４１においては、ポリシリコン膜９０は、マスクとして利用されるために形成される。図２を参照し説明したように、ＬＯＣＯＳ酸化膜７０の端部は、先端に接近するにつれて先が細くなって厚さが薄くなる形状であり、加工精度を高精度にすることができない。そこで、本実施例に係る半導体装置の製造方法においては、加工精度の高いポリシリコン膜９０を用いて、高精度にマスクを形成している。よって、マスクの端部は、ＬＯＣＯＳ酸化膜７０ではなく、ポリシリコン膜９０となり、マスク端部の位置を高精度に定めることができる。ポリシリコンは、本来的には、ＭＯＳトランジスタのゲートとして用いられる材料であり、ＭＯＳトランジスタのゲート長及びゲート幅は高精度に管理されているので、高精度な加工でポリシリコン膜９０を形成することが、十分に可能となる。 On the other hand, in the bipolar transistor formation region 41, the polysilicon film 90 is formed to be used as a mask. As described with reference to FIG. 2, the end portion of the LOCOS oxide film 70 has a shape in which the tip becomes thinner and the thickness becomes thinner as it approaches the tip, and the processing accuracy cannot be made high. Therefore, in the method of manufacturing the semiconductor device according to the present embodiment, the mask is formed with high accuracy using the polysilicon film 90 with high processing accuracy. Therefore, the end portion of the mask is not the LOCOS oxide film 70 but the polysilicon film 90, and the position of the mask end portion can be determined with high accuracy. Polysilicon is originally a material used as the gate of a MOS transistor, and the gate length and gate width of the MOS transistor are controlled with high precision, so that the polysilicon film 90 is formed with high precision processing. It becomes possible enough.
　このように、マスクの端部を、マスクとしての加工精度に問題があるＬＯＣＯＳ酸化膜７０の端部の代わりに加工精度の高いポリシリコン膜９０を用いて形成することにより、高精度にマスク形状を加工することができる。よって、ポリシリコン膜９０は、ＬＯＣＯＳ酸化膜７０と半導体基板４０のうちエミッタ領域６０を形成する部分の表面のゲート酸化膜８０との境界を覆うように、ＬＯＣＯＳ酸化膜７０の傾斜部分とゲート酸化膜８０とに跨るように形成する。これにより、ＬＯＣＯＳ酸化膜７０の厚さが十分ある中央部分はそのままＬＯＣＯＳ酸化膜７０を活かし、加工精度が低下する先端の傾斜部分をポリシリコン膜９０で覆うようにすれば、最小限のポリシリコン膜９０の形成で機能的に十分なマスク効果を得ることができる。 In this way, by forming the edge of the mask using the polysilicon film 90 having high processing accuracy instead of the end of the LOCOS oxide film 70 having a problem in processing accuracy as a mask, the mask shape can be formed with high accuracy. Can be processed. Therefore, the polysilicon film 90 covers the inclined portion of the LOCOS oxide film 70 and the gate oxide so as to cover the boundary between the LOCOS oxide film 70 and the gate oxide film 80 on the surface of the semiconductor substrate 40 where the emitter region 60 is to be formed. It is formed so as to straddle the film 80. As a result, if the LOCOS oxide film 70 is used as it is in the central portion where the LOCOS oxide film 70 is sufficiently thick, and the inclined portion of the tip where the processing accuracy is lowered is covered with the polysilicon film 90, the minimum polysilicon is obtained. A functionally sufficient mask effect can be obtained by forming the film 90.
　また、ポリシリコン膜形成工程は、通常のＭＯＳトランジスタの製造プロセスで行われる工程であるから、バイポーラトランジスタを製造するために、ＭＯＳトランジスタの製造工程に余分な工程を追加する必要がなく、ＭＯＳトランジスタの製造プロセスと同じ工程数で高精度なマスクを形成することができる。 In addition, since the polysilicon film forming process is a process performed in a normal MOS transistor manufacturing process, there is no need to add an extra process to the MOS transistor manufacturing process in order to manufacture a bipolar transistor. A highly accurate mask can be formed with the same number of steps as in the manufacturing process.
　図３Ｅの（ａ）は、バイポーラトランジスタ形成領域４１の平面図を示している。高濃度ベース領域５１の周囲を、ポリシリコン膜９０が囲むような平面構成となっている。その他の部分は、図３Ｄの（ａ）と同様であるので、説明を省略する。 FIG. 3E shows a plan view of the bipolar transistor formation region 41. The planar configuration is such that the polysilicon film 90 surrounds the periphery of the high concentration base region 51. The other parts are the same as (a) of FIG.
　図３Ｆは、イオン打ち込み工程を示した図である。図３Ｆにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3F is a diagram showing an ion implantation process. 3F, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　図３Ｆの（ｂ）を参照すれば、図３Ｅに示す構造体の表面に、レジスト１０２が選択的に形成されてパターニングされている。また、ベース領域５０の高濃度ベース領域５１の表面に、不純物領域であるエミッタ領域６０が形成されている。同様に、ｐ型ウェル層５５の表面には、ドレイン領域６２及びソース領域６３が形成されている。
　イオン打ち込み工程においては、ベース領域５０の表面に、イオンの打ち込みが行われ、更に不純物領域（エミッタ領域６０）が形成される。また、バイポーラトランジスタ形成領域４１において、ｎ型層２０のゲート酸化膜８０に覆われた部分の表面には、コレクタコンタクト領域６１が形成される。なお、ゲート酸化膜８０の形成を省略する場合には、コレクタコンタクト領域６１は、バイポーラトランジスタ形成領域４１において、ｎ型層２０の露出した部分の表面に形成されて良い。 Referring to (b) of FIG. 3F, a resist 102 is selectively formed and patterned on the surface of the structure shown in FIG. 3E. An emitter region 60 that is an impurity region is formed on the surface of the high-concentration base region 51 of the base region 50. Similarly, a drain region 62 and a source region 63 are formed on the surface of the p-type well layer 55.
In the ion implantation process, ions are implanted on the surface of the base region 50, and an impurity region (emitter region 60) is further formed. In the bipolar transistor formation region 41, a collector contact region 61 is formed on the surface of the portion of the n-type layer 20 covered with the gate oxide film 80. If the formation of the gate oxide film 80 is omitted, the collector contact region 61 may be formed on the surface of the exposed portion of the n-type layer 20 in the bipolar transistor formation region 41.
　イオン打ち込み工程においては、まず、レジスト１０２のパターニングが行われ、不純物領域を形成しない部分がレジスト１０２で覆われる。次いで、レジスト１０２と、ＬＯＣＯＳ酸化膜７０と、ポリシリコン膜９０とをマスクとして、イオンの打ち込みが行われる。この場合、ＬＯＣＯＳ酸化膜７０をマスクの一部として用いるので、イオンは、ＬＯＣＯＳ酸化膜７０を透過しない程度の低エネルギーで打ち込まれる。また、半導体基板４０のうち、ＬＯＣＯＳ酸化膜７０で覆われていない部分は、薄膜状のゲート酸化膜８０で覆われているので、ゲート酸化膜８０は透過するレベルの低エネルギーで、イオンは打ち込まれる。打ち込まれるイオンは、例えば、リンが用いられてもよい。これにより、エミッタ領域６０、コレクタコンタクト領域６１、ドレイン領域６２及びソース領域６３が、ベース領域５０及びｐ型ウェル層５５の表面にｎ型の導電型で形成されることになる。なお、ドレイン領域６２とソース領域６３は、同じ不純物領域であるので、配置が逆であってもよい。 In the ion implantation process, first, the resist 102 is patterned, and a portion where no impurity region is formed is covered with the resist 102. Next, ions are implanted using the resist 102, the LOCOS oxide film 70, and the polysilicon film 90 as a mask. In this case, since the LOCOS oxide film 70 is used as a part of the mask, ions are implanted with low energy that does not pass through the LOCOS oxide film 70. Further, the portion of the semiconductor substrate 40 that is not covered with the LOCOS oxide film 70 is covered with a thin gate oxide film 80, so that the gate oxide film 80 has low energy to transmit and ions are implanted. It is. For example, phosphorus may be used as the ions to be implanted. As a result, the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are formed with the n-type conductivity type on the surfaces of the base region 50 and the p-type well layer 55. Note that since the drain region 62 and the source region 63 are the same impurity region, the arrangement may be reversed.
　エミッタ領域６０の形状及び大きさは、マスクとして機能するポリシリコン膜９０により高精度に定められ、エミッタ領域６０を高精度に形成することができる。これにより、ベース領域５０において、エミッタ領域６０と低濃度ベース領域５２の間の、高濃度ベース領域５１の横幅の大きさを適切に確保することができる。 The shape and size of the emitter region 60 are determined with high accuracy by the polysilicon film 90 functioning as a mask, and the emitter region 60 can be formed with high accuracy. Thereby, in the base region 50, the width of the high concentration base region 51 between the emitter region 60 and the low concentration base region 52 can be appropriately ensured.
　図３Ｆの（ａ）は、バイポーラトランジスタ形成領域４１の平面図を示しているが、レジスト１０２と、ＬＯＣＯＳ酸化膜７０と、ポリシリコン膜９０により形成されるマスクを用いイオンの打ち込みを行うことにより、エミッタ領域６０が形成されている。 FIG. 3F shows a plan view of the bipolar transistor formation region 41. By performing ion implantation using a mask formed of the resist 102, the LOCOS oxide film 70, and the polysilicon film 90, FIG. An emitter region 60 is formed.
　図３Ｇは、熱処理工程を示した図である。図３Ｇにおいて、（ａ）はバイポーラトランジスタ形成領域４１の平面図であり、（ｂ）は半導体基板４０の断面図である。 FIG. 3G is a diagram showing a heat treatment process. 3G, (a) is a plan view of the bipolar transistor formation region 41, and (b) is a cross-sectional view of the semiconductor substrate 40. FIG.
　熱処理工程においては、レジスト１０２を除去した後、半導体基板４０が加熱処理される。これにより、図３Ｇの（ｂ）に示すように、半導体基板４０の表面に形成されたエミッタ領域６０、コレクタコンタクト領域６１、ドレイン領域６２及びソース領域６３が側方及び下方に拡大する。 In the heat treatment step, the semiconductor substrate 40 is heat-treated after removing the resist 102. As a result, as shown in FIG. 3G (b), the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 formed on the surface of the semiconductor substrate 40 expand laterally and downward.
　なお、エミッタ領域６０、コレクタコンタクト領域６１、ドレイン領域６２及びソース領域６３は、低エネルギーのイオン打ち込みにより半導体基板４０の表面に薄く形成され、ベース領域５０及びｐ型ウェル層５５と比較して、厚さが相当に薄い層である。よって、熱拡散による側方への拡大量は、ベース領域５０の熱拡散時に比較して相当に小さくなり、エミッタ領域６０は高濃度ベース領域５１に大きく食い込まず、エミッタ領域６０の端部を十分に制御することができる。 The emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are formed thin on the surface of the semiconductor substrate 40 by low energy ion implantation, and compared with the base region 50 and the p-type well layer 55, The layer is considerably thin. Therefore, the lateral expansion amount due to the thermal diffusion is considerably smaller than that during the thermal diffusion of the base region 50, and the emitter region 60 does not dig into the high-concentration base region 51, and the end of the emitter region 60 is sufficiently covered. Can be controlled.
　また、バイポーラトランジス形成領域４１のポリシリコン膜９０は、ＬＯＣＯＳ酸化膜７０と同様に、半導体基板４０上に残されたままとなるが、ゲート酸化膜８０によりエミッタ領域６０及びベース領域５０とは、電気的に断線されており、電圧が印加される訳ではないので、何らバイポーラトランジスタの動作に悪影響は及ぼさない。また、ＭＯＳトランジスタ形成領域４２においては、ポリシリコン膜９０は、ゲートとして形成され、機能することになる。 Further, the polysilicon film 90 in the bipolar transistor formation region 41 remains on the semiconductor substrate 40 as in the LOCOS oxide film 70, but the emitter region 60 and the base region 50 are separated by the gate oxide film 80. Since it is electrically disconnected and no voltage is applied, the operation of the bipolar transistor is not adversely affected. In the MOS transistor formation region 42, the polysilicon film 90 is formed and functions as a gate.
　図３Ｇの（ａ）は、バイポーラトランジスタ形成領域４１の平面図を透過的に示している。図３Ｇの（ａ）を参照すれば、ゲート酸化膜８０で表面を覆われたエミッタ領域６０が、ポリシリコン膜９０に周囲が囲まれている。また、ＬＯＣＯＳ酸化膜７０の下には、低濃度ベース領域５２が形成されている。なお、高濃度ベース領域５１が、ポリシリコン膜９０に覆われず、ゲート酸化膜８０にのみ覆われた部分は、ベースコンタクト領域である。ここから、ベースへの電流入力を行うことになる。 FIG. 3G (a) transparently shows a plan view of the bipolar transistor formation region 41. Referring to FIG. 3G, the emitter region 60 whose surface is covered with the gate oxide film 80 is surrounded by the polysilicon film 90. A low concentration base region 52 is formed under the LOCOS oxide film 70. The portion where the high-concentration base region 51 is not covered with the polysilicon film 90 but only with the gate oxide film 80 is a base contact region. From here, current input to the base is performed.
　このように、本実施例に係る半導体装置の製造方法においては、図３Ａ乃至図３Ｇに示した一連の工程を経て、ｎｐｎ型バイポーラトランジスタを製造することができる。 Thus, in the method for manufacturing a semiconductor device according to the present embodiment, an npn bipolar transistor can be manufactured through a series of steps shown in FIGS. 3A to 3G.
　図４は、図３Ｇの（ｂ）のBの部分を拡大した図である。図４において、完成したバイポーラトランジスタのエミッタ領域６０と、ベース領域５０の境界部分が示されている。図４に示すように、ＬＯＣＯＳ酸化膜７０の横方向の位置が変動しても、ポリシリコン膜９０によりマスクが形成されているので、ＬＯＣＯＳ酸化膜７０の影響を受けず、エミッタ領域６０を高精度に形成することができる。これにより、エミッタ領域６０の端部が高濃度ベース領域５１に食い込むことを回避することができ、高濃度ベース領域５１の横方向の大きさを十分に確保することができる。 FIG. 4 is an enlarged view of portion B in FIG. 3G (b). In FIG. 4, a boundary portion between the emitter region 60 and the base region 50 of the completed bipolar transistor is shown. As shown in FIG. 4, even if the lateral position of the LOCOS oxide film 70 changes, the mask is formed by the polysilicon film 90, so that the emitter region 60 is not affected by the LOCOS oxide film 70. It can be formed with high accuracy. Thereby, it is possible to avoid the end of the emitter region 60 from biting into the high-concentration base region 51, and to ensure a sufficient size in the lateral direction of the high-concentration base region 51.
　図５は、本実施例に係るｎｐｎ型バイポーラトランジスタの動作例を説明するための図である。図５において、ｎｐｎ型バイポーラトランジスタは、エミッタ領域６０に注入された小数キャリアの電子が、縦に移動してベース領域５０を通過し、コレクタ領域であるｎ型層２０に流れ込む動作が好ましい正常な動作である。しかしながら、エミッタ領域６０を側方から囲んでいる高濃度ベース領域５１の幅が小さいと、小数キャリアが縦方向ではなく、横方向に流れてしまう。また、高濃度ベース領域５１と、低濃度ベース領域５２は、不純物の濃度勾配があるので、高濃度ベース領域５１に注入された小数キャリアは、効率良く低濃度ベース領域５２に移送される。つまり、寄生動作をしてしまう。 FIG. 5 is a diagram for explaining an operation example of the npn-type bipolar transistor according to the present embodiment. In FIG. 5, the npn-type bipolar transistor preferably has a normal operation in which the electrons of the minority carriers injected into the emitter region 60 move vertically and pass through the base region 50 and flow into the n-type layer 20 which is the collector region. Is the action. However, if the width of the high-concentration base region 51 that surrounds the emitter region 60 from the side is small, the fractional carriers flow in the horizontal direction instead of the vertical direction. Further, since the high concentration base region 51 and the low concentration base region 52 have an impurity concentration gradient, the fractional carriers injected into the high concentration base region 51 are efficiently transferred to the low concentration base region 52. That is, a parasitic operation occurs.
　一方、高濃度ベース領域５１の幅が十分に長ければ、エミッタ領域６０に注入された小数キャリアが高濃度ベース領域５１を通過し、更に低濃度ベース領域５２に移動することを抑制することができ、寄生動作を防止することができる。 On the other hand, if the width of the high concentration base region 51 is sufficiently long, it is possible to suppress the fractional carriers injected into the emitter region 60 from passing through the high concentration base region 51 and further moving to the low concentration base region 52. Parasitic operation can be prevented.
　図４に戻る。図４に示すように、加工精度の高いポリシリコン膜９０で、ＬＯＣＯＳ酸化膜７０と半導体基板４０の表面の境界を覆い、これをマスクとしてイオン打ち込み工程を行うことにより、エミッタ領域６０の端部が、ポリシリコン膜９０及びＬＯＣＯＳ酸化膜７０の端部に対向するように形成される。また、加工精度の高いポリシリコン膜９０のマスクで半導体基板４０の表面におけるエミッタ領域６０の面積を規定することにより、エミッタ領域６０の面積のバラツキを抑えることができる。また、エミッタ領域６０の端部を設計通りに規定して加工することにより、エミッタ領域６０を側方から囲んでいる高濃度ベース領域５１の横方向の長さ（寸法）を大きくし、バイポーラトランジスタを縦方向に動作させることができる。これにより、設計通りの特性を有するバイポーラトランジスタとすることができる。更に、バイポーラトランジスタは、ＭＯＳトランジスタと同様の工程を用いて製造することができ、同一の半導体基板４０上にバイポーラトランジスタとＭＯＳトランジスタを製造する場合にも、効率的に半導体装置を製造することができる。 Return to FIG. As shown in FIG. 4, the polysilicon film 90 with high processing accuracy covers the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40, and an ion implantation process is performed using this as a mask, so that the end portion of the emitter region 60 is obtained. Is formed so as to face the end portions of the polysilicon film 90 and the LOCOS oxide film 70. Further, by defining the area of the emitter region 60 on the surface of the semiconductor substrate 40 with a mask of the polysilicon film 90 with high processing accuracy, the variation in the area of the emitter region 60 can be suppressed. In addition, by defining and processing the end of the emitter region 60 as designed, the lateral length (dimension) of the high-concentration base region 51 surrounding the emitter region 60 from the side is increased, and the bipolar transistor Can be operated vertically. Thereby, a bipolar transistor having designed characteristics can be obtained. Furthermore, the bipolar transistor can be manufactured using the same process as that of the MOS transistor. Even when the bipolar transistor and the MOS transistor are manufactured on the same semiconductor substrate 40, the semiconductor device can be manufactured efficiently. it can.
　なお、本実施例に係る半導体装置の製造方法により製造された半導体装置は、種々の電子回路に利用することができ、例えば、基準電圧生成回路として構成することができる。そして、半導体装置をパッケージに収容することにより、半導体集積回路装置として構成することができる。これにより、不純物領域が設計通りに形成され、バラツキの無い優れた特性を有する半導体集積回路装置とすることができる。 The semiconductor device manufactured by the method for manufacturing a semiconductor device according to this embodiment can be used for various electronic circuits, and can be configured as a reference voltage generation circuit, for example. Then, by housing the semiconductor device in a package, it can be configured as a semiconductor integrated circuit device. As a result, the semiconductor integrated circuit device having excellent characteristics in which the impurity regions are formed as designed and there is no variation can be obtained.
　また、本実施例においては、半導体装置として、ｎｐｎ型バイポーラトランジスタを製造する例を挙げて説明したが、ＬＯＣＯＳ酸化膜７０をマスクとしてイオン打ち込み工程を実行する半導体製造工程であれば、種々の半導体装置の製造工程に適用することができる。また、ＭＯＳトランジスタ形成領域４２には、ＣＭＯＳを製造するようにしてもよい。ＣＭＯＳの製造工程も、ＭＯＳトランジスタの製造工程と同様であるので、本実施例を同様に適用することができる。 In this embodiment, an example of manufacturing an npn bipolar transistor as a semiconductor device has been described. However, various semiconductors can be used as long as the semiconductor manufacturing process executes an ion implantation process using the LOCOS oxide film 70 as a mask. It can be applied to the manufacturing process of the device. Further, a CMOS may be manufactured in the MOS transistor formation region 42. Since the CMOS manufacturing process is the same as the MOS transistor manufacturing process, the present embodiment can be similarly applied.
　本発明の一側面によれば、加工精度の高いポリシリコン膜をマスクとして利用することができ、簡素な製造工程で高精度に不純物領域を形成することができる。 According to one aspect of the present invention, a polysilicon film with high processing accuracy can be used as a mask, and an impurity region can be formed with high accuracy by a simple manufacturing process.
　本発明の一側面によれば、一実施例による半導体装置の製造方法を、高エネルギーイオン打ち込みにより形成された不純物領域の表面に、更に別の不純物領域を形成する半導体装置の製造工程にも利用することができ、種々の半導体装置について高精度な不純物領域の形成を行うことができる。 According to one aspect of the present invention, a semiconductor device manufacturing method according to an embodiment is also used for a semiconductor device manufacturing process in which another impurity region is formed on the surface of an impurity region formed by high-energy ion implantation. Thus, highly accurate impurity regions can be formed for various semiconductor devices.
　本発明の一側面によれば、トランジスタの活性領域を高精度に形成することができ、特性が良好でバラツキの少ないトランジスタを製造することができる。 According to one aspect of the present invention, an active region of a transistor can be formed with high accuracy, and a transistor with favorable characteristics and less variation can be manufactured.
　本発明の一側面によれば、特性が良好でバラツキの少ないバイポーラトランジスタを製造することができる。 According to one aspect of the present invention, a bipolar transistor with good characteristics and little variation can be manufactured.
　本発明の一側面によれば、ＭＯＳトランジスタを製造するプロセスを利用しつつ、余分な工程を増やすことなく、特性が良好でバラツキの少ない半導体装置を製造することができる。 According to one aspect of the present invention, it is possible to manufacture a semiconductor device with good characteristics and little variation without using an extra process while using a process for manufacturing a MOS transistor.
　本発明の一側面によれば、特性が良好でバラツキの少ない半導体集積回路装置を提供することができる。 According to one aspect of the present invention, it is possible to provide a semiconductor integrated circuit device having favorable characteristics and less variation.
　本発明は具体的に開示された実施例に限定されることなく、本発明の範囲を逸脱することなく様々な変形例、改良例がなされるであろう。 The present invention is not limited to the specifically disclosed embodiments, and various modifications and improvements may be made without departing from the scope of the present invention.
　本願は２００９年７月１３日に出願した日本国特許出願第２００９－１６５０８４号に基づきその優先権を主張するものであり、同日本国出願の全内容を参照することにより本願に援用する。 This application claims priority based on Japanese Patent Application No. 2009-165084 filed on July 13, 2009, and is incorporated herein by reference in its entirety.
　本発明は、バイポーラトランジスタ等を含む半導体装置の製造工程や、かかる半導体装置を用いる半導体集積回路装置に適用することができる。 The present invention can be applied to a manufacturing process of a semiconductor device including a bipolar transistor and the like, and a semiconductor integrated circuit device using such a semiconductor device.
　１０、１１０　　シリコン基板
　２０、１２０　　ｎ型層
　３０　　ｐ型層
　４０、１４０　　半導体基板
　４１　　バイポーラトランジスタ形成領域
　４２　　ＭＯＳトランジスタ形成領域
　５０、１５０　　ベース領域
　５１、１５１　　高濃度ベース領域
　５２、１５２　　低濃度ベース領域
　６０、１６０　　エミッタ領域
　６１　　コレクタコンタクト領域
　６２　　ドレイン領域
　６３　　ソース領域
　７０、１７０　　ＬＯＣＯＳ酸化膜
　８０、１８０　　ゲート酸化膜
　９０　　ポリシリコン膜
　１００、１０２、２００、２０２　　レジスト 10, 110 Silicon substrate 20, 120 n-type layer 30 p- type layer 40, 140 Semiconductor substrate 41 Bipolar transistor formation region 42 MOS transistor formation region 50, 150 Base region 51, 151 High- concentration base region 52, 152 Low- concentration base region 60 , 160 Emitter region 61 Collector contact region 62 Drain region 63 Source region 70, 170 LOCOS oxide film 80, 180 Gate oxide film 90 Polysilicon film 100, 102, 200, 202 Resist

Claims (9)

  1. 　半導体基板の表面の所定領域に、ＬＯＣＯＳ酸化膜を形成する工程と、
    　該ＬＯＣＯＳ酸化膜と前記半導体基板の表面の境界を覆うように、ポリシリコン膜を形成する工程と、
    　該ポリシリコン膜をマスクとして、前記半導体基板の表面にイオンの打ち込みを行い、前記半導体基板の表面に、不純物領域を形成する工程と、を含む半導体装置の製造方法。     Forming a LOCOS oxide film in a predetermined region of the surface of the semiconductor substrate;
    Forming a polysilicon film so as to cover a boundary between the LOCOS oxide film and the surface of the semiconductor substrate;
    Using the polysilicon film as a mask, implanting ions on the surface of the semiconductor substrate, and forming an impurity region on the surface of the semiconductor substrate.
  2. 　前記ＬＯＣＯＳ酸化膜形成工程と前記ポリシリコン形成工程との間に、イオンが前記ＬＯＣＯＳ酸化膜を透過するエネルギーによりイオン打ち込みを行う工程を含む請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing ion implantation with energy that allows ions to pass through the LOCOS oxide film between the LOCOS oxide film forming step and the polysilicon forming step.
  3. 　前記不純物領域は、トランジスタの活性領域である請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity region is an active region of a transistor.
  4. 　前記トランジスタは、バイポーラトランジスタである請求項３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3, wherein the transistor is a bipolar transistor.
  5. 　前記バイポーラトランジスタは、ｎｐｎ型トランジスタであって、
    　前記活性領域は、エミッタ領域である請求項４に記載の半導体装置の製造方法。     The bipolar transistor is an npn type transistor,
    The method for manufacturing a semiconductor device according to claim 4, wherein the active region is an emitter region.
  6. 　前記エミッタ領域の端部は、前記ＬＯＣＯＳ酸化膜の端部と対向している請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein an end portion of the emitter region is opposed to an end portion of the LOCOS oxide film.
  7. 　前記半導体基板の表面の前記所定領域外に、前記ＬＯＣＯＳ酸化膜を形成する工程において、ＭＯＳトランジスタの形成領域を定めるＬＯＣＯＳ酸化膜を更に形成し、
    　前記ポリシリコン膜を形成する工程において、前記ＭＯＳトランジスタのゲートを形成し、
    　前記不純物領域を形成する工程において、前記ＭＯＳトランジスタのドレイン領域及びソース領域を形成し、前記所定領域外にＭＯＳトランジスタを同時に形成する請求項１に記載の半導体装置の製造方法。     In the step of forming the LOCOS oxide film outside the predetermined region on the surface of the semiconductor substrate, a LOCOS oxide film that defines a formation region of the MOS transistor is further formed,
    In the step of forming the polysilicon film, forming a gate of the MOS transistor,
    2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the impurity region, a drain region and a source region of the MOS transistor are formed, and a MOS transistor is simultaneously formed outside the predetermined region.
  8. 　前記ＭＯＳトランジスタは、ＣＭＯＳである請求項７に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 7, wherein the MOS transistor is a CMOS.
  9. 　請求項３に記載のトランジスタを用いて構成した基準電圧生成回路を含む半導体集積回路装置。 A semiconductor integrated circuit device including a reference voltage generation circuit configured using the transistor according to claim 3.
PCT/JP2010/061480 2009-07-13 2010-07-06 Semiconductor device manufacturing method and semiconductor integrated circuit device WO2011007699A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229648A (en) * 1990-07-30 1992-08-19 Nippon Motoroola Kk Transistor provided with prescribed emitter region; its manufacture
JP2001144189A (en) * 1999-11-17 2001-05-25 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device and manufacturing method therefor
JP2003174100A (en) * 2001-12-05 2003-06-20 Hitachi Ltd Semiconductor device and method of manufacturing the same
WO2005062150A1 (en) * 2003-12-24 2005-07-07 Renesas Technology Corp. Voltage generating circuit and semiconductor integrated circuit device
JP2005533372A (en) * 2002-07-09 2005-11-04 インピンジ インコーポレイテッド Floating gate semiconductor structure
JP2006059841A (en) * 2004-08-17 2006-03-02 Nec Electronics Corp Semiconductor device and its manufacturing method
JP2006222329A (en) * 2005-02-14 2006-08-24 Elpida Memory Inc Semiconductor device
JP2009088189A (en) * 2007-09-28 2009-04-23 Sanyo Electric Co Ltd Dmos transistor and manufacturing method therefor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229648A (en) * 1990-07-30 1992-08-19 Nippon Motoroola Kk Transistor provided with prescribed emitter region; its manufacture
JP2001144189A (en) * 1999-11-17 2001-05-25 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device and manufacturing method therefor
JP2003174100A (en) * 2001-12-05 2003-06-20 Hitachi Ltd Semiconductor device and method of manufacturing the same
JP2005533372A (en) * 2002-07-09 2005-11-04 インピンジ インコーポレイテッド Floating gate semiconductor structure
WO2005062150A1 (en) * 2003-12-24 2005-07-07 Renesas Technology Corp. Voltage generating circuit and semiconductor integrated circuit device
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JP2009088189A (en) * 2007-09-28 2009-04-23 Sanyo Electric Co Ltd Dmos transistor and manufacturing method therefor

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